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Colin Cross7056d422010-04-22 20:30:13 -07001/*
Colin Cross7056d422010-04-22 20:30:13 -07002 * Copyright (C) 2010 Google, Inc.
3 *
4 * Author:
5 * Colin Cross <ccross@google.com>
6 * Based on arch/arm/plat-omap/cpu-omap.c, (C) 2005 Nokia Corporation
7 *
8 * This software is licensed under the terms of the GNU General Public
9 * License version 2, as published by the Free Software Foundation, and
10 * may be copied, distributed, and modified under those terms.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 */
18
19#include <linux/kernel.h>
20#include <linux/module.h>
21#include <linux/types.h>
22#include <linux/sched.h>
23#include <linux/cpufreq.h>
24#include <linux/delay.h>
25#include <linux/init.h>
26#include <linux/err.h>
27#include <linux/clk.h>
28#include <linux/io.h>
Colin Cross1eb2ecf2010-08-05 17:40:39 -070029#include <linux/suspend.h>
Colin Cross7056d422010-04-22 20:30:13 -070030
Colin Cross7056d422010-04-22 20:30:13 -070031static struct cpufreq_frequency_table freq_table[] = {
Viresh Kumar5d690302013-05-14 19:08:50 +053032 { .frequency = 216000 },
33 { .frequency = 312000 },
34 { .frequency = 456000 },
35 { .frequency = 608000 },
36 { .frequency = 760000 },
37 { .frequency = 816000 },
38 { .frequency = 912000 },
39 { .frequency = 1000000 },
40 { .frequency = CPUFREQ_TABLE_END },
Colin Cross7056d422010-04-22 20:30:13 -070041};
42
43#define NUM_CPUS 2
44
45static struct clk *cpu_clk;
Stephen Warrence32dda2012-09-10 17:05:01 -060046static struct clk *pll_x_clk;
47static struct clk *pll_p_clk;
Colin Cross7a281282010-11-22 18:54:36 -080048static struct clk *emc_clk;
Colin Cross7056d422010-04-22 20:30:13 -070049
50static unsigned long target_cpu_speed[NUM_CPUS];
Colin Cross1eb2ecf2010-08-05 17:40:39 -070051static DEFINE_MUTEX(tegra_cpu_lock);
52static bool is_suspended;
Colin Cross7056d422010-04-22 20:30:13 -070053
Olof Johansson6686c732011-10-09 21:57:04 -070054static int tegra_verify_speed(struct cpufreq_policy *policy)
Colin Cross7056d422010-04-22 20:30:13 -070055{
56 return cpufreq_frequency_table_verify(policy, freq_table);
57}
58
Olof Johansson6686c732011-10-09 21:57:04 -070059static unsigned int tegra_getspeed(unsigned int cpu)
Colin Cross7056d422010-04-22 20:30:13 -070060{
61 unsigned long rate;
62
63 if (cpu >= NUM_CPUS)
64 return 0;
65
66 rate = clk_get_rate(cpu_clk) / 1000;
67 return rate;
68}
69
Stephen Warrence32dda2012-09-10 17:05:01 -060070static int tegra_cpu_clk_set_rate(unsigned long rate)
71{
72 int ret;
73
74 /*
75 * Take an extra reference to the main pll so it doesn't turn
76 * off when we move the cpu off of it
77 */
78 clk_prepare_enable(pll_x_clk);
79
80 ret = clk_set_parent(cpu_clk, pll_p_clk);
81 if (ret) {
82 pr_err("Failed to switch cpu to clock pll_p\n");
83 goto out;
84 }
85
86 if (rate == clk_get_rate(pll_p_clk))
87 goto out;
88
89 ret = clk_set_rate(pll_x_clk, rate);
90 if (ret) {
91 pr_err("Failed to change pll_x to %lu\n", rate);
92 goto out;
93 }
94
95 ret = clk_set_parent(cpu_clk, pll_x_clk);
96 if (ret) {
97 pr_err("Failed to switch cpu to clock pll_x\n");
98 goto out;
99 }
100
101out:
102 clk_disable_unprepare(pll_x_clk);
103 return ret;
104}
105
Viresh Kumarb43a7ff2013-03-24 11:56:43 +0530106static int tegra_update_cpu_speed(struct cpufreq_policy *policy,
107 unsigned long rate)
Colin Cross7056d422010-04-22 20:30:13 -0700108{
Colin Cross7056d422010-04-22 20:30:13 -0700109 int ret = 0;
110 struct cpufreq_freqs freqs;
111
Colin Cross7056d422010-04-22 20:30:13 -0700112 freqs.old = tegra_getspeed(0);
113 freqs.new = rate;
114
115 if (freqs.old == freqs.new)
116 return ret;
117
Colin Cross7a281282010-11-22 18:54:36 -0800118 /*
119 * Vote on memory bus frequency based on cpu frequency
120 * This sets the minimum frequency, display or avp may request higher
121 */
122 if (rate >= 816000)
123 clk_set_rate(emc_clk, 600000000); /* cpu 816 MHz, emc max */
124 else if (rate >= 456000)
125 clk_set_rate(emc_clk, 300000000); /* cpu 456 MHz, emc 150Mhz */
126 else
127 clk_set_rate(emc_clk, 100000000); /* emc 50Mhz */
128
Viresh Kumarb43a7ff2013-03-24 11:56:43 +0530129 cpufreq_notify_transition(policy, &freqs, CPUFREQ_PRECHANGE);
Colin Cross7056d422010-04-22 20:30:13 -0700130
131#ifdef CONFIG_CPU_FREQ_DEBUG
132 printk(KERN_DEBUG "cpufreq-tegra: transition: %u --> %u\n",
133 freqs.old, freqs.new);
134#endif
135
Stephen Warrence32dda2012-09-10 17:05:01 -0600136 ret = tegra_cpu_clk_set_rate(freqs.new * 1000);
Colin Cross7056d422010-04-22 20:30:13 -0700137 if (ret) {
138 pr_err("cpu-tegra: Failed to set cpu frequency to %d kHz\n",
139 freqs.new);
Viresh Kumarf56cc992013-06-19 11:18:20 +0530140 freqs.new = freqs.old;
Colin Cross7056d422010-04-22 20:30:13 -0700141 }
142
Viresh Kumarb43a7ff2013-03-24 11:56:43 +0530143 cpufreq_notify_transition(policy, &freqs, CPUFREQ_POSTCHANGE);
Colin Cross7056d422010-04-22 20:30:13 -0700144
Viresh Kumarf56cc992013-06-19 11:18:20 +0530145 return ret;
Colin Cross7056d422010-04-22 20:30:13 -0700146}
147
Colin Cross1eb2ecf2010-08-05 17:40:39 -0700148static unsigned long tegra_cpu_highest_speed(void)
149{
150 unsigned long rate = 0;
151 int i;
152
153 for_each_online_cpu(i)
154 rate = max(rate, target_cpu_speed[i]);
155 return rate;
156}
157
Colin Cross7056d422010-04-22 20:30:13 -0700158static int tegra_target(struct cpufreq_policy *policy,
159 unsigned int target_freq,
160 unsigned int relation)
161{
Olof Johanssonfdb684a2011-10-09 21:31:23 -0700162 unsigned int idx;
Colin Cross7056d422010-04-22 20:30:13 -0700163 unsigned int freq;
Colin Cross1eb2ecf2010-08-05 17:40:39 -0700164 int ret = 0;
165
166 mutex_lock(&tegra_cpu_lock);
167
168 if (is_suspended) {
169 ret = -EBUSY;
170 goto out;
171 }
Colin Cross7056d422010-04-22 20:30:13 -0700172
173 cpufreq_frequency_table_target(policy, freq_table, target_freq,
174 relation, &idx);
175
176 freq = freq_table[idx].frequency;
177
178 target_cpu_speed[policy->cpu] = freq;
179
Viresh Kumarb43a7ff2013-03-24 11:56:43 +0530180 ret = tegra_update_cpu_speed(policy, tegra_cpu_highest_speed());
Colin Cross1eb2ecf2010-08-05 17:40:39 -0700181
182out:
183 mutex_unlock(&tegra_cpu_lock);
184 return ret;
Colin Cross7056d422010-04-22 20:30:13 -0700185}
186
Colin Cross1eb2ecf2010-08-05 17:40:39 -0700187static int tegra_pm_notify(struct notifier_block *nb, unsigned long event,
188 void *dummy)
189{
190 mutex_lock(&tegra_cpu_lock);
191 if (event == PM_SUSPEND_PREPARE) {
Viresh Kumarb43a7ff2013-03-24 11:56:43 +0530192 struct cpufreq_policy *policy = cpufreq_cpu_get(0);
Colin Cross1eb2ecf2010-08-05 17:40:39 -0700193 is_suspended = true;
194 pr_info("Tegra cpufreq suspend: setting frequency to %d kHz\n",
195 freq_table[0].frequency);
Viresh Kumarb43a7ff2013-03-24 11:56:43 +0530196 tegra_update_cpu_speed(policy, freq_table[0].frequency);
197 cpufreq_cpu_put(policy);
Colin Cross1eb2ecf2010-08-05 17:40:39 -0700198 } else if (event == PM_POST_SUSPEND) {
199 is_suspended = false;
200 }
201 mutex_unlock(&tegra_cpu_lock);
202
203 return NOTIFY_OK;
204}
205
206static struct notifier_block tegra_cpu_pm_notifier = {
207 .notifier_call = tegra_pm_notify,
208};
209
Colin Cross7056d422010-04-22 20:30:13 -0700210static int tegra_cpu_init(struct cpufreq_policy *policy)
211{
212 if (policy->cpu >= NUM_CPUS)
213 return -EINVAL;
214
Prashant Gaikwad6a5278d2012-06-05 09:59:35 +0530215 clk_prepare_enable(emc_clk);
216 clk_prepare_enable(cpu_clk);
Colin Cross89a5fb82010-10-20 17:47:59 -0700217
Colin Cross7056d422010-04-22 20:30:13 -0700218 cpufreq_frequency_table_cpuinfo(policy, freq_table);
219 cpufreq_frequency_table_get_attr(freq_table, policy->cpu);
220 policy->cur = tegra_getspeed(policy->cpu);
221 target_cpu_speed[policy->cpu] = policy->cur;
222
223 /* FIXME: what's the actual transition time? */
224 policy->cpuinfo.transition_latency = 300 * 1000;
225
Viresh Kumar16a44f82013-02-01 06:40:00 +0000226 cpumask_copy(policy->cpus, cpu_possible_mask);
Colin Cross7056d422010-04-22 20:30:13 -0700227
Colin Cross1eb2ecf2010-08-05 17:40:39 -0700228 if (policy->cpu == 0)
229 register_pm_notifier(&tegra_cpu_pm_notifier);
230
Colin Cross7056d422010-04-22 20:30:13 -0700231 return 0;
232}
233
234static int tegra_cpu_exit(struct cpufreq_policy *policy)
235{
236 cpufreq_frequency_table_cpuinfo(policy, freq_table);
Prashant Gaikwad6a5278d2012-06-05 09:59:35 +0530237 clk_disable_unprepare(emc_clk);
Colin Cross7056d422010-04-22 20:30:13 -0700238 return 0;
239}
240
241static struct freq_attr *tegra_cpufreq_attr[] = {
242 &cpufreq_freq_attr_scaling_available_freqs,
243 NULL,
244};
245
246static struct cpufreq_driver tegra_cpufreq_driver = {
247 .verify = tegra_verify_speed,
248 .target = tegra_target,
249 .get = tegra_getspeed,
250 .init = tegra_cpu_init,
251 .exit = tegra_cpu_exit,
252 .name = "tegra",
253 .attr = tegra_cpufreq_attr,
254};
255
256static int __init tegra_cpufreq_init(void)
257{
Joseph Lob192b912013-08-23 09:43:58 +0800258 cpu_clk = clk_get_sys(NULL, "cclk");
Richard Zhaoc26cefd2012-12-21 00:09:55 +0000259 if (IS_ERR(cpu_clk))
260 return PTR_ERR(cpu_clk);
261
262 pll_x_clk = clk_get_sys(NULL, "pll_x");
263 if (IS_ERR(pll_x_clk))
264 return PTR_ERR(pll_x_clk);
265
Joseph Lob192b912013-08-23 09:43:58 +0800266 pll_p_clk = clk_get_sys(NULL, "pll_p");
Richard Zhaoc26cefd2012-12-21 00:09:55 +0000267 if (IS_ERR(pll_p_clk))
268 return PTR_ERR(pll_p_clk);
269
270 emc_clk = clk_get_sys("cpu", "emc");
271 if (IS_ERR(emc_clk)) {
272 clk_put(cpu_clk);
273 return PTR_ERR(emc_clk);
274 }
275
Colin Cross7056d422010-04-22 20:30:13 -0700276 return cpufreq_register_driver(&tegra_cpufreq_driver);
277}
278
279static void __exit tegra_cpufreq_exit(void)
280{
281 cpufreq_unregister_driver(&tegra_cpufreq_driver);
Richard Zhaoc26cefd2012-12-21 00:09:55 +0000282 clk_put(emc_clk);
283 clk_put(cpu_clk);
Colin Cross7056d422010-04-22 20:30:13 -0700284}
285
286
287MODULE_AUTHOR("Colin Cross <ccross@android.com>");
288MODULE_DESCRIPTION("cpufreq driver for Nvidia Tegra2");
289MODULE_LICENSE("GPL");
290module_init(tegra_cpufreq_init);
291module_exit(tegra_cpufreq_exit);