Vladimir Barinov | 3e062b0 | 2007-06-05 16:36:55 +0100 | [diff] [blame] | 1 | /* |
| 2 | * TI DaVinci clock definitions |
| 3 | * |
Kevin Hilman | c5b736d | 2009-03-20 17:29:01 -0700 | [diff] [blame] | 4 | * Copyright (C) 2006-2007 Texas Instruments. |
| 5 | * Copyright (C) 2008-2009 Deep Root Systems, LLC |
Vladimir Barinov | 3e062b0 | 2007-06-05 16:36:55 +0100 | [diff] [blame] | 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License version 2 as |
| 9 | * published by the Free Software Foundation. |
| 10 | */ |
| 11 | |
| 12 | #ifndef __ARCH_ARM_DAVINCI_CLOCK_H |
| 13 | #define __ARCH_ARM_DAVINCI_CLOCK_H |
| 14 | |
Kevin Hilman | c5b736d | 2009-03-20 17:29:01 -0700 | [diff] [blame] | 15 | #include <linux/list.h> |
| 16 | #include <asm/clkdev.h> |
| 17 | |
| 18 | #define DAVINCI_PLL1_BASE 0x01c40800 |
| 19 | #define DAVINCI_PLL2_BASE 0x01c40c00 |
| 20 | #define MAX_PLL 2 |
| 21 | |
| 22 | /* PLL/Reset register offsets */ |
| 23 | #define PLLCTL 0x100 |
| 24 | #define PLLCTL_PLLEN BIT(0) |
Sekhar Nori | d6a6156 | 2009-08-31 15:48:03 +0530 | [diff] [blame] | 25 | #define PLLCTL_PLLPWRDN BIT(1) |
| 26 | #define PLLCTL_PLLRST BIT(3) |
| 27 | #define PLLCTL_PLLDIS BIT(4) |
| 28 | #define PLLCTL_PLLENSRC BIT(5) |
Kevin Hilman | c5b736d | 2009-03-20 17:29:01 -0700 | [diff] [blame] | 29 | #define PLLCTL_CLKMODE BIT(8) |
| 30 | |
| 31 | #define PLLM 0x110 |
| 32 | #define PLLM_PLLM_MASK 0xff |
| 33 | |
| 34 | #define PREDIV 0x114 |
| 35 | #define PLLDIV1 0x118 |
| 36 | #define PLLDIV2 0x11c |
| 37 | #define PLLDIV3 0x120 |
| 38 | #define POSTDIV 0x128 |
| 39 | #define BPDIV 0x12c |
| 40 | #define PLLCMD 0x138 |
| 41 | #define PLLSTAT 0x13c |
| 42 | #define PLLALNCTL 0x140 |
| 43 | #define PLLDCHANGE 0x144 |
| 44 | #define PLLCKEN 0x148 |
| 45 | #define PLLCKSTAT 0x14c |
| 46 | #define PLLSYSTAT 0x150 |
| 47 | #define PLLDIV4 0x160 |
| 48 | #define PLLDIV5 0x164 |
| 49 | #define PLLDIV6 0x168 |
| 50 | #define PLLDIV7 0x16c |
| 51 | #define PLLDIV8 0x170 |
| 52 | #define PLLDIV9 0x174 |
| 53 | #define PLLDIV_EN BIT(15) |
| 54 | #define PLLDIV_RATIO_MASK 0x1f |
| 55 | |
Sekhar Nori | 9a219a9 | 2009-11-16 17:21:33 +0530 | [diff] [blame^] | 56 | /* |
| 57 | * OMAP-L138 system reference guide recommends a wait for 4 OSCIN/CLKIN |
| 58 | * cycles to ensure that the PLLC has switched to bypass mode. Delay of 1us |
| 59 | * ensures we are good for all > 4MHz OSCIN/CLKIN inputs. Typically the input |
| 60 | * is ~25MHz. Units are micro seconds. |
| 61 | */ |
| 62 | #define PLL_BYPASS_TIME 1 |
| 63 | /* From OMAP-L138 datasheet table 6-4. Units are micro seconds */ |
| 64 | #define PLL_RESET_TIME 1 |
| 65 | /* |
| 66 | * From OMAP-L138 datasheet table 6-4; assuming prediv = 1, sqrt(pllm) = 4 |
| 67 | * Units are micro seconds. |
| 68 | */ |
| 69 | #define PLL_LOCK_TIME 20 |
| 70 | |
Kevin Hilman | c5b736d | 2009-03-20 17:29:01 -0700 | [diff] [blame] | 71 | struct pll_data { |
| 72 | u32 phys_base; |
| 73 | void __iomem *base; |
| 74 | u32 num; |
| 75 | u32 flags; |
| 76 | u32 input_rate; |
| 77 | }; |
| 78 | #define PLL_HAS_PREDIV 0x01 |
| 79 | #define PLL_HAS_POSTDIV 0x02 |
| 80 | |
Vladimir Barinov | 3e062b0 | 2007-06-05 16:36:55 +0100 | [diff] [blame] | 81 | struct clk { |
| 82 | struct list_head node; |
| 83 | struct module *owner; |
| 84 | const char *name; |
Kevin Hilman | c5b736d | 2009-03-20 17:29:01 -0700 | [diff] [blame] | 85 | unsigned long rate; |
| 86 | u8 usecount; |
Kevin Hilman | c5b736d | 2009-03-20 17:29:01 -0700 | [diff] [blame] | 87 | u8 lpsc; |
Sergei Shtylyov | 789a785 | 2009-09-30 19:48:03 +0400 | [diff] [blame] | 88 | u8 gpsc; |
Sekhar Nori | 5d36a33 | 2009-08-31 15:48:05 +0530 | [diff] [blame] | 89 | u32 flags; |
Kevin Hilman | c5b736d | 2009-03-20 17:29:01 -0700 | [diff] [blame] | 90 | struct clk *parent; |
Sekhar Nori | f02bf3b | 2009-08-31 15:48:01 +0530 | [diff] [blame] | 91 | struct list_head children; /* list of children */ |
| 92 | struct list_head childnode; /* parent's child list node */ |
Kevin Hilman | c5b736d | 2009-03-20 17:29:01 -0700 | [diff] [blame] | 93 | struct pll_data *pll_data; |
| 94 | u32 div_reg; |
Sekhar Nori | de381a9 | 2009-08-31 15:48:02 +0530 | [diff] [blame] | 95 | unsigned long (*recalc) (struct clk *); |
Sekhar Nori | d6a6156 | 2009-08-31 15:48:03 +0530 | [diff] [blame] | 96 | int (*set_rate) (struct clk *clk, unsigned long rate); |
| 97 | int (*round_rate) (struct clk *clk, unsigned long rate); |
Vladimir Barinov | 3e062b0 | 2007-06-05 16:36:55 +0100 | [diff] [blame] | 98 | }; |
| 99 | |
Sekhar Nori | 5d36a33 | 2009-08-31 15:48:05 +0530 | [diff] [blame] | 100 | /* Clock flags: SoC-specific flags start at BIT(16) */ |
Kevin Hilman | c5b736d | 2009-03-20 17:29:01 -0700 | [diff] [blame] | 101 | #define ALWAYS_ENABLED BIT(1) |
| 102 | #define CLK_PSC BIT(2) |
| 103 | #define PSC_DSP BIT(3) /* PSC uses DSP domain, not ARM */ |
| 104 | #define CLK_PLL BIT(4) /* PLL-derived clock */ |
| 105 | #define PRE_PLL BIT(5) /* source is before PLL mult/div */ |
Vladimir Barinov | 3e062b0 | 2007-06-05 16:36:55 +0100 | [diff] [blame] | 106 | |
Kevin Hilman | c5b736d | 2009-03-20 17:29:01 -0700 | [diff] [blame] | 107 | struct davinci_clk { |
| 108 | struct clk_lookup lk; |
| 109 | }; |
| 110 | |
| 111 | #define CLK(dev, con, ck) \ |
| 112 | { \ |
| 113 | .lk = { \ |
| 114 | .dev_id = dev, \ |
| 115 | .con_id = con, \ |
| 116 | .clk = ck, \ |
| 117 | }, \ |
| 118 | } |
| 119 | |
| 120 | int davinci_clk_init(struct davinci_clk *clocks); |
Sekhar Nori | d6a6156 | 2009-08-31 15:48:03 +0530 | [diff] [blame] | 121 | int davinci_set_pllrate(struct pll_data *pll, unsigned int prediv, |
| 122 | unsigned int mult, unsigned int postdiv); |
Kevin Hilman | fb63138 | 2009-04-29 16:23:59 -0700 | [diff] [blame] | 123 | |
| 124 | extern struct platform_device davinci_wdt_device; |
| 125 | |
Vladimir Barinov | 3e062b0 | 2007-06-05 16:36:55 +0100 | [diff] [blame] | 126 | #endif |