Guennadi Liakhovetski | 9a7b8e0 | 2012-05-09 17:09:13 +0200 | [diff] [blame^] | 1 | /* |
| 2 | * Dmaengine driver base library for DMA controllers, found on SH-based SoCs |
| 3 | * |
| 4 | * extracted from shdma.c |
| 5 | * |
| 6 | * Copyright (C) 2011-2012 Guennadi Liakhovetski <g.liakhovetski@gmx.de> |
| 7 | * Copyright (C) 2009 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> |
| 8 | * Copyright (C) 2009 Renesas Solutions, Inc. All rights reserved. |
| 9 | * Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved. |
| 10 | * |
| 11 | * This is free software; you can redistribute it and/or modify |
| 12 | * it under the terms of version 2 of the GNU General Public License as |
| 13 | * published by the Free Software Foundation. |
| 14 | */ |
| 15 | |
| 16 | #include <linux/delay.h> |
| 17 | #include <linux/shdma-base.h> |
| 18 | #include <linux/dmaengine.h> |
| 19 | #include <linux/init.h> |
| 20 | #include <linux/interrupt.h> |
| 21 | #include <linux/module.h> |
| 22 | #include <linux/pm_runtime.h> |
| 23 | #include <linux/slab.h> |
| 24 | #include <linux/spinlock.h> |
| 25 | |
| 26 | #include "../dmaengine.h" |
| 27 | |
| 28 | /* DMA descriptor control */ |
| 29 | enum shdma_desc_status { |
| 30 | DESC_IDLE, |
| 31 | DESC_PREPARED, |
| 32 | DESC_SUBMITTED, |
| 33 | DESC_COMPLETED, /* completed, have to call callback */ |
| 34 | DESC_WAITING, /* callback called, waiting for ack / re-submit */ |
| 35 | }; |
| 36 | |
| 37 | #define NR_DESCS_PER_CHANNEL 32 |
| 38 | |
| 39 | #define to_shdma_chan(c) container_of(c, struct shdma_chan, dma_chan) |
| 40 | #define to_shdma_dev(d) container_of(d, struct shdma_dev, dma_dev) |
| 41 | |
| 42 | /* |
| 43 | * For slave DMA we assume, that there is a finite number of DMA slaves in the |
| 44 | * system, and that each such slave can only use a finite number of channels. |
| 45 | * We use slave channel IDs to make sure, that no such slave channel ID is |
| 46 | * allocated more than once. |
| 47 | */ |
| 48 | static unsigned int slave_num = 256; |
| 49 | module_param(slave_num, uint, 0444); |
| 50 | |
| 51 | /* A bitmask with slave_num bits */ |
| 52 | static unsigned long *shdma_slave_used; |
| 53 | |
| 54 | /* Called under spin_lock_irq(&schan->chan_lock") */ |
| 55 | static void shdma_chan_xfer_ld_queue(struct shdma_chan *schan) |
| 56 | { |
| 57 | struct shdma_dev *sdev = to_shdma_dev(schan->dma_chan.device); |
| 58 | const struct shdma_ops *ops = sdev->ops; |
| 59 | struct shdma_desc *sdesc; |
| 60 | |
| 61 | /* DMA work check */ |
| 62 | if (ops->channel_busy(schan)) |
| 63 | return; |
| 64 | |
| 65 | /* Find the first not transferred descriptor */ |
| 66 | list_for_each_entry(sdesc, &schan->ld_queue, node) |
| 67 | if (sdesc->mark == DESC_SUBMITTED) { |
| 68 | ops->start_xfer(schan, sdesc); |
| 69 | break; |
| 70 | } |
| 71 | } |
| 72 | |
| 73 | static dma_cookie_t shdma_tx_submit(struct dma_async_tx_descriptor *tx) |
| 74 | { |
| 75 | struct shdma_desc *chunk, *c, *desc = |
| 76 | container_of(tx, struct shdma_desc, async_tx), |
| 77 | *last = desc; |
| 78 | struct shdma_chan *schan = to_shdma_chan(tx->chan); |
| 79 | struct shdma_slave *slave = tx->chan->private; |
| 80 | dma_async_tx_callback callback = tx->callback; |
| 81 | dma_cookie_t cookie; |
| 82 | bool power_up; |
| 83 | |
| 84 | spin_lock_irq(&schan->chan_lock); |
| 85 | |
| 86 | power_up = list_empty(&schan->ld_queue); |
| 87 | |
| 88 | cookie = dma_cookie_assign(tx); |
| 89 | |
| 90 | /* Mark all chunks of this descriptor as submitted, move to the queue */ |
| 91 | list_for_each_entry_safe(chunk, c, desc->node.prev, node) { |
| 92 | /* |
| 93 | * All chunks are on the global ld_free, so, we have to find |
| 94 | * the end of the chain ourselves |
| 95 | */ |
| 96 | if (chunk != desc && (chunk->mark == DESC_IDLE || |
| 97 | chunk->async_tx.cookie > 0 || |
| 98 | chunk->async_tx.cookie == -EBUSY || |
| 99 | &chunk->node == &schan->ld_free)) |
| 100 | break; |
| 101 | chunk->mark = DESC_SUBMITTED; |
| 102 | /* Callback goes to the last chunk */ |
| 103 | chunk->async_tx.callback = NULL; |
| 104 | chunk->cookie = cookie; |
| 105 | list_move_tail(&chunk->node, &schan->ld_queue); |
| 106 | last = chunk; |
| 107 | |
| 108 | dev_dbg(schan->dev, "submit #%d@%p on %d\n", |
| 109 | tx->cookie, &last->async_tx, schan->id); |
| 110 | } |
| 111 | |
| 112 | last->async_tx.callback = callback; |
| 113 | last->async_tx.callback_param = tx->callback_param; |
| 114 | |
| 115 | if (power_up) { |
| 116 | int ret; |
| 117 | schan->pm_state = SHDMA_PM_BUSY; |
| 118 | |
| 119 | ret = pm_runtime_get(schan->dev); |
| 120 | |
| 121 | spin_unlock_irq(&schan->chan_lock); |
| 122 | if (ret < 0) |
| 123 | dev_err(schan->dev, "%s(): GET = %d\n", __func__, ret); |
| 124 | |
| 125 | pm_runtime_barrier(schan->dev); |
| 126 | |
| 127 | spin_lock_irq(&schan->chan_lock); |
| 128 | |
| 129 | /* Have we been reset, while waiting? */ |
| 130 | if (schan->pm_state != SHDMA_PM_ESTABLISHED) { |
| 131 | struct shdma_dev *sdev = |
| 132 | to_shdma_dev(schan->dma_chan.device); |
| 133 | const struct shdma_ops *ops = sdev->ops; |
| 134 | dev_dbg(schan->dev, "Bring up channel %d\n", |
| 135 | schan->id); |
| 136 | /* |
| 137 | * TODO: .xfer_setup() might fail on some platforms. |
| 138 | * Make it int then, on error remove chunks from the |
| 139 | * queue again |
| 140 | */ |
| 141 | ops->setup_xfer(schan, slave); |
| 142 | |
| 143 | if (schan->pm_state == SHDMA_PM_PENDING) |
| 144 | shdma_chan_xfer_ld_queue(schan); |
| 145 | schan->pm_state = SHDMA_PM_ESTABLISHED; |
| 146 | } |
| 147 | } else { |
| 148 | /* |
| 149 | * Tell .device_issue_pending() not to run the queue, interrupts |
| 150 | * will do it anyway |
| 151 | */ |
| 152 | schan->pm_state = SHDMA_PM_PENDING; |
| 153 | } |
| 154 | |
| 155 | spin_unlock_irq(&schan->chan_lock); |
| 156 | |
| 157 | return cookie; |
| 158 | } |
| 159 | |
| 160 | /* Called with desc_lock held */ |
| 161 | static struct shdma_desc *shdma_get_desc(struct shdma_chan *schan) |
| 162 | { |
| 163 | struct shdma_desc *sdesc; |
| 164 | |
| 165 | list_for_each_entry(sdesc, &schan->ld_free, node) |
| 166 | if (sdesc->mark != DESC_PREPARED) { |
| 167 | BUG_ON(sdesc->mark != DESC_IDLE); |
| 168 | list_del(&sdesc->node); |
| 169 | return sdesc; |
| 170 | } |
| 171 | |
| 172 | return NULL; |
| 173 | } |
| 174 | |
| 175 | static int shdma_alloc_chan_resources(struct dma_chan *chan) |
| 176 | { |
| 177 | struct shdma_chan *schan = to_shdma_chan(chan); |
| 178 | struct shdma_dev *sdev = to_shdma_dev(schan->dma_chan.device); |
| 179 | const struct shdma_ops *ops = sdev->ops; |
| 180 | struct shdma_desc *desc; |
| 181 | struct shdma_slave *slave = chan->private; |
| 182 | int ret, i; |
| 183 | |
| 184 | /* |
| 185 | * This relies on the guarantee from dmaengine that alloc_chan_resources |
| 186 | * never runs concurrently with itself or free_chan_resources. |
| 187 | */ |
| 188 | if (slave) { |
| 189 | if (slave->slave_id >= slave_num) { |
| 190 | ret = -EINVAL; |
| 191 | goto evalid; |
| 192 | } |
| 193 | |
| 194 | if (test_and_set_bit(slave->slave_id, shdma_slave_used)) { |
| 195 | ret = -EBUSY; |
| 196 | goto etestused; |
| 197 | } |
| 198 | |
| 199 | ret = ops->set_slave(schan, slave); |
| 200 | if (ret < 0) |
| 201 | goto esetslave; |
| 202 | } |
| 203 | |
| 204 | schan->desc = kcalloc(NR_DESCS_PER_CHANNEL, |
| 205 | sdev->desc_size, GFP_KERNEL); |
| 206 | if (!schan->desc) { |
| 207 | ret = -ENOMEM; |
| 208 | goto edescalloc; |
| 209 | } |
| 210 | schan->desc_num = NR_DESCS_PER_CHANNEL; |
| 211 | |
| 212 | for (i = 0; i < NR_DESCS_PER_CHANNEL; i++) { |
| 213 | desc = ops->embedded_desc(schan->desc, i); |
| 214 | dma_async_tx_descriptor_init(&desc->async_tx, |
| 215 | &schan->dma_chan); |
| 216 | desc->async_tx.tx_submit = shdma_tx_submit; |
| 217 | desc->mark = DESC_IDLE; |
| 218 | |
| 219 | list_add(&desc->node, &schan->ld_free); |
| 220 | } |
| 221 | |
| 222 | return NR_DESCS_PER_CHANNEL; |
| 223 | |
| 224 | edescalloc: |
| 225 | if (slave) |
| 226 | esetslave: |
| 227 | clear_bit(slave->slave_id, shdma_slave_used); |
| 228 | etestused: |
| 229 | evalid: |
| 230 | chan->private = NULL; |
| 231 | return ret; |
| 232 | } |
| 233 | |
| 234 | static dma_async_tx_callback __ld_cleanup(struct shdma_chan *schan, bool all) |
| 235 | { |
| 236 | struct shdma_desc *desc, *_desc; |
| 237 | /* Is the "exposed" head of a chain acked? */ |
| 238 | bool head_acked = false; |
| 239 | dma_cookie_t cookie = 0; |
| 240 | dma_async_tx_callback callback = NULL; |
| 241 | void *param = NULL; |
| 242 | unsigned long flags; |
| 243 | |
| 244 | spin_lock_irqsave(&schan->chan_lock, flags); |
| 245 | list_for_each_entry_safe(desc, _desc, &schan->ld_queue, node) { |
| 246 | struct dma_async_tx_descriptor *tx = &desc->async_tx; |
| 247 | |
| 248 | BUG_ON(tx->cookie > 0 && tx->cookie != desc->cookie); |
| 249 | BUG_ON(desc->mark != DESC_SUBMITTED && |
| 250 | desc->mark != DESC_COMPLETED && |
| 251 | desc->mark != DESC_WAITING); |
| 252 | |
| 253 | /* |
| 254 | * queue is ordered, and we use this loop to (1) clean up all |
| 255 | * completed descriptors, and to (2) update descriptor flags of |
| 256 | * any chunks in a (partially) completed chain |
| 257 | */ |
| 258 | if (!all && desc->mark == DESC_SUBMITTED && |
| 259 | desc->cookie != cookie) |
| 260 | break; |
| 261 | |
| 262 | if (tx->cookie > 0) |
| 263 | cookie = tx->cookie; |
| 264 | |
| 265 | if (desc->mark == DESC_COMPLETED && desc->chunks == 1) { |
| 266 | if (schan->dma_chan.completed_cookie != desc->cookie - 1) |
| 267 | dev_dbg(schan->dev, |
| 268 | "Completing cookie %d, expected %d\n", |
| 269 | desc->cookie, |
| 270 | schan->dma_chan.completed_cookie + 1); |
| 271 | schan->dma_chan.completed_cookie = desc->cookie; |
| 272 | } |
| 273 | |
| 274 | /* Call callback on the last chunk */ |
| 275 | if (desc->mark == DESC_COMPLETED && tx->callback) { |
| 276 | desc->mark = DESC_WAITING; |
| 277 | callback = tx->callback; |
| 278 | param = tx->callback_param; |
| 279 | dev_dbg(schan->dev, "descriptor #%d@%p on %d callback\n", |
| 280 | tx->cookie, tx, schan->id); |
| 281 | BUG_ON(desc->chunks != 1); |
| 282 | break; |
| 283 | } |
| 284 | |
| 285 | if (tx->cookie > 0 || tx->cookie == -EBUSY) { |
| 286 | if (desc->mark == DESC_COMPLETED) { |
| 287 | BUG_ON(tx->cookie < 0); |
| 288 | desc->mark = DESC_WAITING; |
| 289 | } |
| 290 | head_acked = async_tx_test_ack(tx); |
| 291 | } else { |
| 292 | switch (desc->mark) { |
| 293 | case DESC_COMPLETED: |
| 294 | desc->mark = DESC_WAITING; |
| 295 | /* Fall through */ |
| 296 | case DESC_WAITING: |
| 297 | if (head_acked) |
| 298 | async_tx_ack(&desc->async_tx); |
| 299 | } |
| 300 | } |
| 301 | |
| 302 | dev_dbg(schan->dev, "descriptor %p #%d completed.\n", |
| 303 | tx, tx->cookie); |
| 304 | |
| 305 | if (((desc->mark == DESC_COMPLETED || |
| 306 | desc->mark == DESC_WAITING) && |
| 307 | async_tx_test_ack(&desc->async_tx)) || all) { |
| 308 | /* Remove from ld_queue list */ |
| 309 | desc->mark = DESC_IDLE; |
| 310 | |
| 311 | list_move(&desc->node, &schan->ld_free); |
| 312 | |
| 313 | if (list_empty(&schan->ld_queue)) { |
| 314 | dev_dbg(schan->dev, "Bring down channel %d\n", schan->id); |
| 315 | pm_runtime_put(schan->dev); |
| 316 | schan->pm_state = SHDMA_PM_ESTABLISHED; |
| 317 | } |
| 318 | } |
| 319 | } |
| 320 | |
| 321 | if (all && !callback) |
| 322 | /* |
| 323 | * Terminating and the loop completed normally: forgive |
| 324 | * uncompleted cookies |
| 325 | */ |
| 326 | schan->dma_chan.completed_cookie = schan->dma_chan.cookie; |
| 327 | |
| 328 | spin_unlock_irqrestore(&schan->chan_lock, flags); |
| 329 | |
| 330 | if (callback) |
| 331 | callback(param); |
| 332 | |
| 333 | return callback; |
| 334 | } |
| 335 | |
| 336 | /* |
| 337 | * shdma_chan_ld_cleanup - Clean up link descriptors |
| 338 | * |
| 339 | * Clean up the ld_queue of DMA channel. |
| 340 | */ |
| 341 | static void shdma_chan_ld_cleanup(struct shdma_chan *schan, bool all) |
| 342 | { |
| 343 | while (__ld_cleanup(schan, all)) |
| 344 | ; |
| 345 | } |
| 346 | |
| 347 | /* |
| 348 | * shdma_free_chan_resources - Free all resources of the channel. |
| 349 | */ |
| 350 | static void shdma_free_chan_resources(struct dma_chan *chan) |
| 351 | { |
| 352 | struct shdma_chan *schan = to_shdma_chan(chan); |
| 353 | struct shdma_dev *sdev = to_shdma_dev(chan->device); |
| 354 | const struct shdma_ops *ops = sdev->ops; |
| 355 | LIST_HEAD(list); |
| 356 | |
| 357 | /* Protect against ISR */ |
| 358 | spin_lock_irq(&schan->chan_lock); |
| 359 | ops->halt_channel(schan); |
| 360 | spin_unlock_irq(&schan->chan_lock); |
| 361 | |
| 362 | /* Now no new interrupts will occur */ |
| 363 | |
| 364 | /* Prepared and not submitted descriptors can still be on the queue */ |
| 365 | if (!list_empty(&schan->ld_queue)) |
| 366 | shdma_chan_ld_cleanup(schan, true); |
| 367 | |
| 368 | if (chan->private) { |
| 369 | /* The caller is holding dma_list_mutex */ |
| 370 | struct shdma_slave *slave = chan->private; |
| 371 | clear_bit(slave->slave_id, shdma_slave_used); |
| 372 | chan->private = NULL; |
| 373 | } |
| 374 | |
| 375 | spin_lock_irq(&schan->chan_lock); |
| 376 | |
| 377 | list_splice_init(&schan->ld_free, &list); |
| 378 | schan->desc_num = 0; |
| 379 | |
| 380 | spin_unlock_irq(&schan->chan_lock); |
| 381 | |
| 382 | kfree(schan->desc); |
| 383 | } |
| 384 | |
| 385 | /** |
| 386 | * shdma_add_desc - get, set up and return one transfer descriptor |
| 387 | * @schan: DMA channel |
| 388 | * @flags: DMA transfer flags |
| 389 | * @dst: destination DMA address, incremented when direction equals |
| 390 | * DMA_DEV_TO_MEM or DMA_MEM_TO_MEM |
| 391 | * @src: source DMA address, incremented when direction equals |
| 392 | * DMA_MEM_TO_DEV or DMA_MEM_TO_MEM |
| 393 | * @len: DMA transfer length |
| 394 | * @first: if NULL, set to the current descriptor and cookie set to -EBUSY |
| 395 | * @direction: needed for slave DMA to decide which address to keep constant, |
| 396 | * equals DMA_MEM_TO_MEM for MEMCPY |
| 397 | * Returns 0 or an error |
| 398 | * Locks: called with desc_lock held |
| 399 | */ |
| 400 | static struct shdma_desc *shdma_add_desc(struct shdma_chan *schan, |
| 401 | unsigned long flags, dma_addr_t *dst, dma_addr_t *src, size_t *len, |
| 402 | struct shdma_desc **first, enum dma_transfer_direction direction) |
| 403 | { |
| 404 | struct shdma_dev *sdev = to_shdma_dev(schan->dma_chan.device); |
| 405 | const struct shdma_ops *ops = sdev->ops; |
| 406 | struct shdma_desc *new; |
| 407 | size_t copy_size = *len; |
| 408 | |
| 409 | if (!copy_size) |
| 410 | return NULL; |
| 411 | |
| 412 | /* Allocate the link descriptor from the free list */ |
| 413 | new = shdma_get_desc(schan); |
| 414 | if (!new) { |
| 415 | dev_err(schan->dev, "No free link descriptor available\n"); |
| 416 | return NULL; |
| 417 | } |
| 418 | |
| 419 | ops->desc_setup(schan, new, *src, *dst, ©_size); |
| 420 | |
| 421 | if (!*first) { |
| 422 | /* First desc */ |
| 423 | new->async_tx.cookie = -EBUSY; |
| 424 | *first = new; |
| 425 | } else { |
| 426 | /* Other desc - invisible to the user */ |
| 427 | new->async_tx.cookie = -EINVAL; |
| 428 | } |
| 429 | |
| 430 | dev_dbg(schan->dev, |
| 431 | "chaining (%u/%u)@%x -> %x with %p, cookie %d\n", |
| 432 | copy_size, *len, *src, *dst, &new->async_tx, |
| 433 | new->async_tx.cookie); |
| 434 | |
| 435 | new->mark = DESC_PREPARED; |
| 436 | new->async_tx.flags = flags; |
| 437 | new->direction = direction; |
| 438 | |
| 439 | *len -= copy_size; |
| 440 | if (direction == DMA_MEM_TO_MEM || direction == DMA_MEM_TO_DEV) |
| 441 | *src += copy_size; |
| 442 | if (direction == DMA_MEM_TO_MEM || direction == DMA_DEV_TO_MEM) |
| 443 | *dst += copy_size; |
| 444 | |
| 445 | return new; |
| 446 | } |
| 447 | |
| 448 | /* |
| 449 | * shdma_prep_sg - prepare transfer descriptors from an SG list |
| 450 | * |
| 451 | * Common routine for public (MEMCPY) and slave DMA. The MEMCPY case is also |
| 452 | * converted to scatter-gather to guarantee consistent locking and a correct |
| 453 | * list manipulation. For slave DMA direction carries the usual meaning, and, |
| 454 | * logically, the SG list is RAM and the addr variable contains slave address, |
| 455 | * e.g., the FIFO I/O register. For MEMCPY direction equals DMA_MEM_TO_MEM |
| 456 | * and the SG list contains only one element and points at the source buffer. |
| 457 | */ |
| 458 | static struct dma_async_tx_descriptor *shdma_prep_sg(struct shdma_chan *schan, |
| 459 | struct scatterlist *sgl, unsigned int sg_len, dma_addr_t *addr, |
| 460 | enum dma_transfer_direction direction, unsigned long flags) |
| 461 | { |
| 462 | struct scatterlist *sg; |
| 463 | struct shdma_desc *first = NULL, *new = NULL /* compiler... */; |
| 464 | LIST_HEAD(tx_list); |
| 465 | int chunks = 0; |
| 466 | unsigned long irq_flags; |
| 467 | int i; |
| 468 | |
| 469 | for_each_sg(sgl, sg, sg_len, i) |
| 470 | chunks += DIV_ROUND_UP(sg_dma_len(sg), schan->max_xfer_len); |
| 471 | |
| 472 | /* Have to lock the whole loop to protect against concurrent release */ |
| 473 | spin_lock_irqsave(&schan->chan_lock, irq_flags); |
| 474 | |
| 475 | /* |
| 476 | * Chaining: |
| 477 | * first descriptor is what user is dealing with in all API calls, its |
| 478 | * cookie is at first set to -EBUSY, at tx-submit to a positive |
| 479 | * number |
| 480 | * if more than one chunk is needed further chunks have cookie = -EINVAL |
| 481 | * the last chunk, if not equal to the first, has cookie = -ENOSPC |
| 482 | * all chunks are linked onto the tx_list head with their .node heads |
| 483 | * only during this function, then they are immediately spliced |
| 484 | * back onto the free list in form of a chain |
| 485 | */ |
| 486 | for_each_sg(sgl, sg, sg_len, i) { |
| 487 | dma_addr_t sg_addr = sg_dma_address(sg); |
| 488 | size_t len = sg_dma_len(sg); |
| 489 | |
| 490 | if (!len) |
| 491 | goto err_get_desc; |
| 492 | |
| 493 | do { |
| 494 | dev_dbg(schan->dev, "Add SG #%d@%p[%d], dma %llx\n", |
| 495 | i, sg, len, (unsigned long long)sg_addr); |
| 496 | |
| 497 | if (direction == DMA_DEV_TO_MEM) |
| 498 | new = shdma_add_desc(schan, flags, |
| 499 | &sg_addr, addr, &len, &first, |
| 500 | direction); |
| 501 | else |
| 502 | new = shdma_add_desc(schan, flags, |
| 503 | addr, &sg_addr, &len, &first, |
| 504 | direction); |
| 505 | if (!new) |
| 506 | goto err_get_desc; |
| 507 | |
| 508 | new->chunks = chunks--; |
| 509 | list_add_tail(&new->node, &tx_list); |
| 510 | } while (len); |
| 511 | } |
| 512 | |
| 513 | if (new != first) |
| 514 | new->async_tx.cookie = -ENOSPC; |
| 515 | |
| 516 | /* Put them back on the free list, so, they don't get lost */ |
| 517 | list_splice_tail(&tx_list, &schan->ld_free); |
| 518 | |
| 519 | spin_unlock_irqrestore(&schan->chan_lock, irq_flags); |
| 520 | |
| 521 | return &first->async_tx; |
| 522 | |
| 523 | err_get_desc: |
| 524 | list_for_each_entry(new, &tx_list, node) |
| 525 | new->mark = DESC_IDLE; |
| 526 | list_splice(&tx_list, &schan->ld_free); |
| 527 | |
| 528 | spin_unlock_irqrestore(&schan->chan_lock, irq_flags); |
| 529 | |
| 530 | return NULL; |
| 531 | } |
| 532 | |
| 533 | static struct dma_async_tx_descriptor *shdma_prep_memcpy( |
| 534 | struct dma_chan *chan, dma_addr_t dma_dest, dma_addr_t dma_src, |
| 535 | size_t len, unsigned long flags) |
| 536 | { |
| 537 | struct shdma_chan *schan = to_shdma_chan(chan); |
| 538 | struct scatterlist sg; |
| 539 | |
| 540 | if (!chan || !len) |
| 541 | return NULL; |
| 542 | |
| 543 | BUG_ON(!schan->desc_num); |
| 544 | |
| 545 | sg_init_table(&sg, 1); |
| 546 | sg_set_page(&sg, pfn_to_page(PFN_DOWN(dma_src)), len, |
| 547 | offset_in_page(dma_src)); |
| 548 | sg_dma_address(&sg) = dma_src; |
| 549 | sg_dma_len(&sg) = len; |
| 550 | |
| 551 | return shdma_prep_sg(schan, &sg, 1, &dma_dest, DMA_MEM_TO_MEM, flags); |
| 552 | } |
| 553 | |
| 554 | static struct dma_async_tx_descriptor *shdma_prep_slave_sg( |
| 555 | struct dma_chan *chan, struct scatterlist *sgl, unsigned int sg_len, |
| 556 | enum dma_transfer_direction direction, unsigned long flags, void *context) |
| 557 | { |
| 558 | struct shdma_chan *schan = to_shdma_chan(chan); |
| 559 | struct shdma_dev *sdev = to_shdma_dev(schan->dma_chan.device); |
| 560 | const struct shdma_ops *ops = sdev->ops; |
| 561 | struct shdma_slave *slave = chan->private; |
| 562 | dma_addr_t slave_addr; |
| 563 | |
| 564 | if (!chan) |
| 565 | return NULL; |
| 566 | |
| 567 | BUG_ON(!schan->desc_num); |
| 568 | |
| 569 | /* Someone calling slave DMA on a generic channel? */ |
| 570 | if (!slave || !sg_len) { |
| 571 | dev_warn(schan->dev, "%s: bad parameter: %p, %d, %d\n", |
| 572 | __func__, slave, sg_len, slave ? slave->slave_id : -1); |
| 573 | return NULL; |
| 574 | } |
| 575 | |
| 576 | slave_addr = ops->slave_addr(schan); |
| 577 | |
| 578 | return shdma_prep_sg(schan, sgl, sg_len, &slave_addr, |
| 579 | direction, flags); |
| 580 | } |
| 581 | |
| 582 | static int shdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, |
| 583 | unsigned long arg) |
| 584 | { |
| 585 | struct shdma_chan *schan = to_shdma_chan(chan); |
| 586 | struct shdma_dev *sdev = to_shdma_dev(chan->device); |
| 587 | const struct shdma_ops *ops = sdev->ops; |
| 588 | unsigned long flags; |
| 589 | |
| 590 | /* Only supports DMA_TERMINATE_ALL */ |
| 591 | if (cmd != DMA_TERMINATE_ALL) |
| 592 | return -ENXIO; |
| 593 | |
| 594 | if (!chan) |
| 595 | return -EINVAL; |
| 596 | |
| 597 | spin_lock_irqsave(&schan->chan_lock, flags); |
| 598 | |
| 599 | ops->halt_channel(schan); |
| 600 | |
| 601 | spin_unlock_irqrestore(&schan->chan_lock, flags); |
| 602 | |
| 603 | shdma_chan_ld_cleanup(schan, true); |
| 604 | |
| 605 | return 0; |
| 606 | } |
| 607 | |
| 608 | static void shdma_issue_pending(struct dma_chan *chan) |
| 609 | { |
| 610 | struct shdma_chan *schan = to_shdma_chan(chan); |
| 611 | |
| 612 | spin_lock_irq(&schan->chan_lock); |
| 613 | if (schan->pm_state == SHDMA_PM_ESTABLISHED) |
| 614 | shdma_chan_xfer_ld_queue(schan); |
| 615 | else |
| 616 | schan->pm_state = SHDMA_PM_PENDING; |
| 617 | spin_unlock_irq(&schan->chan_lock); |
| 618 | } |
| 619 | |
| 620 | static enum dma_status shdma_tx_status(struct dma_chan *chan, |
| 621 | dma_cookie_t cookie, |
| 622 | struct dma_tx_state *txstate) |
| 623 | { |
| 624 | struct shdma_chan *schan = to_shdma_chan(chan); |
| 625 | enum dma_status status; |
| 626 | unsigned long flags; |
| 627 | |
| 628 | shdma_chan_ld_cleanup(schan, false); |
| 629 | |
| 630 | spin_lock_irqsave(&schan->chan_lock, flags); |
| 631 | |
| 632 | status = dma_cookie_status(chan, cookie, txstate); |
| 633 | |
| 634 | /* |
| 635 | * If we don't find cookie on the queue, it has been aborted and we have |
| 636 | * to report error |
| 637 | */ |
| 638 | if (status != DMA_SUCCESS) { |
| 639 | struct shdma_desc *sdesc; |
| 640 | status = DMA_ERROR; |
| 641 | list_for_each_entry(sdesc, &schan->ld_queue, node) |
| 642 | if (sdesc->cookie == cookie) { |
| 643 | status = DMA_IN_PROGRESS; |
| 644 | break; |
| 645 | } |
| 646 | } |
| 647 | |
| 648 | spin_unlock_irqrestore(&schan->chan_lock, flags); |
| 649 | |
| 650 | return status; |
| 651 | } |
| 652 | |
| 653 | /* Called from error IRQ or NMI */ |
| 654 | bool shdma_reset(struct shdma_dev *sdev) |
| 655 | { |
| 656 | const struct shdma_ops *ops = sdev->ops; |
| 657 | struct shdma_chan *schan; |
| 658 | unsigned int handled = 0; |
| 659 | int i; |
| 660 | |
| 661 | /* Reset all channels */ |
| 662 | shdma_for_each_chan(schan, sdev, i) { |
| 663 | struct shdma_desc *sdesc; |
| 664 | LIST_HEAD(dl); |
| 665 | |
| 666 | if (!schan) |
| 667 | continue; |
| 668 | |
| 669 | spin_lock(&schan->chan_lock); |
| 670 | |
| 671 | /* Stop the channel */ |
| 672 | ops->halt_channel(schan); |
| 673 | |
| 674 | list_splice_init(&schan->ld_queue, &dl); |
| 675 | |
| 676 | if (!list_empty(&dl)) { |
| 677 | dev_dbg(schan->dev, "Bring down channel %d\n", schan->id); |
| 678 | pm_runtime_put(schan->dev); |
| 679 | } |
| 680 | schan->pm_state = SHDMA_PM_ESTABLISHED; |
| 681 | |
| 682 | spin_unlock(&schan->chan_lock); |
| 683 | |
| 684 | /* Complete all */ |
| 685 | list_for_each_entry(sdesc, &dl, node) { |
| 686 | struct dma_async_tx_descriptor *tx = &sdesc->async_tx; |
| 687 | sdesc->mark = DESC_IDLE; |
| 688 | if (tx->callback) |
| 689 | tx->callback(tx->callback_param); |
| 690 | } |
| 691 | |
| 692 | spin_lock(&schan->chan_lock); |
| 693 | list_splice(&dl, &schan->ld_free); |
| 694 | spin_unlock(&schan->chan_lock); |
| 695 | |
| 696 | handled++; |
| 697 | } |
| 698 | |
| 699 | return !!handled; |
| 700 | } |
| 701 | EXPORT_SYMBOL(shdma_reset); |
| 702 | |
| 703 | static irqreturn_t chan_irq(int irq, void *dev) |
| 704 | { |
| 705 | struct shdma_chan *schan = dev; |
| 706 | const struct shdma_ops *ops = |
| 707 | to_shdma_dev(schan->dma_chan.device)->ops; |
| 708 | irqreturn_t ret; |
| 709 | |
| 710 | spin_lock(&schan->chan_lock); |
| 711 | |
| 712 | ret = ops->chan_irq(schan, irq) ? IRQ_WAKE_THREAD : IRQ_NONE; |
| 713 | |
| 714 | spin_unlock(&schan->chan_lock); |
| 715 | |
| 716 | return ret; |
| 717 | } |
| 718 | |
| 719 | static irqreturn_t chan_irqt(int irq, void *dev) |
| 720 | { |
| 721 | struct shdma_chan *schan = dev; |
| 722 | const struct shdma_ops *ops = |
| 723 | to_shdma_dev(schan->dma_chan.device)->ops; |
| 724 | struct shdma_desc *sdesc; |
| 725 | |
| 726 | spin_lock_irq(&schan->chan_lock); |
| 727 | list_for_each_entry(sdesc, &schan->ld_queue, node) { |
| 728 | if (sdesc->mark == DESC_SUBMITTED && |
| 729 | ops->desc_completed(schan, sdesc)) { |
| 730 | dev_dbg(schan->dev, "done #%d@%p\n", |
| 731 | sdesc->async_tx.cookie, &sdesc->async_tx); |
| 732 | sdesc->mark = DESC_COMPLETED; |
| 733 | break; |
| 734 | } |
| 735 | } |
| 736 | /* Next desc */ |
| 737 | shdma_chan_xfer_ld_queue(schan); |
| 738 | spin_unlock_irq(&schan->chan_lock); |
| 739 | |
| 740 | shdma_chan_ld_cleanup(schan, false); |
| 741 | |
| 742 | return IRQ_HANDLED; |
| 743 | } |
| 744 | |
| 745 | int shdma_request_irq(struct shdma_chan *schan, int irq, |
| 746 | unsigned long flags, const char *name) |
| 747 | { |
| 748 | int ret = request_threaded_irq(irq, chan_irq, chan_irqt, |
| 749 | flags, name, schan); |
| 750 | |
| 751 | schan->irq = ret < 0 ? ret : irq; |
| 752 | |
| 753 | return ret; |
| 754 | } |
| 755 | EXPORT_SYMBOL(shdma_request_irq); |
| 756 | |
| 757 | void shdma_free_irq(struct shdma_chan *schan) |
| 758 | { |
| 759 | if (schan->irq >= 0) |
| 760 | free_irq(schan->irq, schan); |
| 761 | } |
| 762 | EXPORT_SYMBOL(shdma_free_irq); |
| 763 | |
| 764 | void shdma_chan_probe(struct shdma_dev *sdev, |
| 765 | struct shdma_chan *schan, int id) |
| 766 | { |
| 767 | schan->pm_state = SHDMA_PM_ESTABLISHED; |
| 768 | |
| 769 | /* reference struct dma_device */ |
| 770 | schan->dma_chan.device = &sdev->dma_dev; |
| 771 | dma_cookie_init(&schan->dma_chan); |
| 772 | |
| 773 | schan->dev = sdev->dma_dev.dev; |
| 774 | schan->id = id; |
| 775 | |
| 776 | if (!schan->max_xfer_len) |
| 777 | schan->max_xfer_len = PAGE_SIZE; |
| 778 | |
| 779 | spin_lock_init(&schan->chan_lock); |
| 780 | |
| 781 | /* Init descripter manage list */ |
| 782 | INIT_LIST_HEAD(&schan->ld_queue); |
| 783 | INIT_LIST_HEAD(&schan->ld_free); |
| 784 | |
| 785 | /* Add the channel to DMA device channel list */ |
| 786 | list_add_tail(&schan->dma_chan.device_node, |
| 787 | &sdev->dma_dev.channels); |
| 788 | sdev->schan[sdev->dma_dev.chancnt++] = schan; |
| 789 | } |
| 790 | EXPORT_SYMBOL(shdma_chan_probe); |
| 791 | |
| 792 | void shdma_chan_remove(struct shdma_chan *schan) |
| 793 | { |
| 794 | list_del(&schan->dma_chan.device_node); |
| 795 | } |
| 796 | EXPORT_SYMBOL(shdma_chan_remove); |
| 797 | |
| 798 | int shdma_init(struct device *dev, struct shdma_dev *sdev, |
| 799 | int chan_num) |
| 800 | { |
| 801 | struct dma_device *dma_dev = &sdev->dma_dev; |
| 802 | |
| 803 | /* |
| 804 | * Require all call-backs for now, they can trivially be made optional |
| 805 | * later as required |
| 806 | */ |
| 807 | if (!sdev->ops || |
| 808 | !sdev->desc_size || |
| 809 | !sdev->ops->embedded_desc || |
| 810 | !sdev->ops->start_xfer || |
| 811 | !sdev->ops->setup_xfer || |
| 812 | !sdev->ops->set_slave || |
| 813 | !sdev->ops->desc_setup || |
| 814 | !sdev->ops->slave_addr || |
| 815 | !sdev->ops->channel_busy || |
| 816 | !sdev->ops->halt_channel || |
| 817 | !sdev->ops->desc_completed) |
| 818 | return -EINVAL; |
| 819 | |
| 820 | sdev->schan = kcalloc(chan_num, sizeof(*sdev->schan), GFP_KERNEL); |
| 821 | if (!sdev->schan) |
| 822 | return -ENOMEM; |
| 823 | |
| 824 | INIT_LIST_HEAD(&dma_dev->channels); |
| 825 | |
| 826 | /* Common and MEMCPY operations */ |
| 827 | dma_dev->device_alloc_chan_resources |
| 828 | = shdma_alloc_chan_resources; |
| 829 | dma_dev->device_free_chan_resources = shdma_free_chan_resources; |
| 830 | dma_dev->device_prep_dma_memcpy = shdma_prep_memcpy; |
| 831 | dma_dev->device_tx_status = shdma_tx_status; |
| 832 | dma_dev->device_issue_pending = shdma_issue_pending; |
| 833 | |
| 834 | /* Compulsory for DMA_SLAVE fields */ |
| 835 | dma_dev->device_prep_slave_sg = shdma_prep_slave_sg; |
| 836 | dma_dev->device_control = shdma_control; |
| 837 | |
| 838 | dma_dev->dev = dev; |
| 839 | |
| 840 | return 0; |
| 841 | } |
| 842 | EXPORT_SYMBOL(shdma_init); |
| 843 | |
| 844 | void shdma_cleanup(struct shdma_dev *sdev) |
| 845 | { |
| 846 | kfree(sdev->schan); |
| 847 | } |
| 848 | EXPORT_SYMBOL(shdma_cleanup); |
| 849 | |
| 850 | static int __init shdma_enter(void) |
| 851 | { |
| 852 | shdma_slave_used = kzalloc(DIV_ROUND_UP(slave_num, BITS_PER_LONG) * |
| 853 | sizeof(long), GFP_KERNEL); |
| 854 | if (!shdma_slave_used) |
| 855 | return -ENOMEM; |
| 856 | return 0; |
| 857 | } |
| 858 | module_init(shdma_enter); |
| 859 | |
| 860 | static void __exit shdma_exit(void) |
| 861 | { |
| 862 | kfree(shdma_slave_used); |
| 863 | } |
| 864 | module_exit(shdma_exit); |
| 865 | |
| 866 | MODULE_LICENSE("GPL v2"); |
| 867 | MODULE_DESCRIPTION("SH-DMA driver base library"); |
| 868 | MODULE_AUTHOR("Guennadi Liakhovetski <g.liakhovetski@gmx.de>"); |