Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1 | /* |
| 2 | *Copyright (C) 2010 OKI SEMICONDUCTOR CO., LTD. |
| 3 | * |
| 4 | *This program is free software; you can redistribute it and/or modify |
| 5 | *it under the terms of the GNU General Public License as published by |
| 6 | *the Free Software Foundation; version 2 of the License. |
| 7 | * |
| 8 | *This program is distributed in the hope that it will be useful, |
| 9 | *but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 10 | *MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 11 | *GNU General Public License for more details. |
| 12 | * |
| 13 | *You should have received a copy of the GNU General Public License |
| 14 | *along with this program; if not, write to the Free Software |
| 15 | *Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. |
| 16 | */ |
| 17 | #include <linux/serial_reg.h> |
| 18 | #include <linux/pci.h> |
| 19 | #include <linux/module.h> |
| 20 | #include <linux/pci.h> |
| 21 | #include <linux/serial_core.h> |
| 22 | #include <linux/interrupt.h> |
| 23 | #include <linux/io.h> |
| 24 | |
| 25 | #include <linux/dmaengine.h> |
| 26 | #include <linux/pch_dma.h> |
| 27 | |
| 28 | enum { |
| 29 | PCH_UART_HANDLED_RX_INT_SHIFT, |
| 30 | PCH_UART_HANDLED_TX_INT_SHIFT, |
| 31 | PCH_UART_HANDLED_RX_ERR_INT_SHIFT, |
| 32 | PCH_UART_HANDLED_RX_TRG_INT_SHIFT, |
| 33 | PCH_UART_HANDLED_MS_INT_SHIFT, |
| 34 | }; |
| 35 | |
| 36 | enum { |
| 37 | PCH_UART_8LINE, |
| 38 | PCH_UART_2LINE, |
| 39 | }; |
| 40 | |
| 41 | #define PCH_UART_DRIVER_DEVICE "ttyPCH" |
| 42 | |
Tomoya MORINAGA | 4564e1e | 2011-01-28 18:00:01 +0900 | [diff] [blame] | 43 | /* Set the max number of UART port |
| 44 | * Intel EG20T PCH: 4 port |
| 45 | * OKI SEMICONDUCTOR ML7213 IOH: 3 port |
| 46 | */ |
| 47 | #define PCH_UART_NR 4 |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 48 | |
| 49 | #define PCH_UART_HANDLED_RX_INT (1<<((PCH_UART_HANDLED_RX_INT_SHIFT)<<1)) |
| 50 | #define PCH_UART_HANDLED_TX_INT (1<<((PCH_UART_HANDLED_TX_INT_SHIFT)<<1)) |
| 51 | #define PCH_UART_HANDLED_RX_ERR_INT (1<<((\ |
| 52 | PCH_UART_HANDLED_RX_ERR_INT_SHIFT)<<1)) |
| 53 | #define PCH_UART_HANDLED_RX_TRG_INT (1<<((\ |
| 54 | PCH_UART_HANDLED_RX_TRG_INT_SHIFT)<<1)) |
| 55 | #define PCH_UART_HANDLED_MS_INT (1<<((PCH_UART_HANDLED_MS_INT_SHIFT)<<1)) |
| 56 | |
| 57 | #define PCH_UART_RBR 0x00 |
| 58 | #define PCH_UART_THR 0x00 |
| 59 | |
| 60 | #define PCH_UART_IER_MASK (PCH_UART_IER_ERBFI|PCH_UART_IER_ETBEI|\ |
| 61 | PCH_UART_IER_ELSI|PCH_UART_IER_EDSSI) |
| 62 | #define PCH_UART_IER_ERBFI 0x00000001 |
| 63 | #define PCH_UART_IER_ETBEI 0x00000002 |
| 64 | #define PCH_UART_IER_ELSI 0x00000004 |
| 65 | #define PCH_UART_IER_EDSSI 0x00000008 |
| 66 | |
| 67 | #define PCH_UART_IIR_IP 0x00000001 |
| 68 | #define PCH_UART_IIR_IID 0x00000006 |
| 69 | #define PCH_UART_IIR_MSI 0x00000000 |
| 70 | #define PCH_UART_IIR_TRI 0x00000002 |
| 71 | #define PCH_UART_IIR_RRI 0x00000004 |
| 72 | #define PCH_UART_IIR_REI 0x00000006 |
| 73 | #define PCH_UART_IIR_TOI 0x00000008 |
| 74 | #define PCH_UART_IIR_FIFO256 0x00000020 |
| 75 | #define PCH_UART_IIR_FIFO64 PCH_UART_IIR_FIFO256 |
| 76 | #define PCH_UART_IIR_FE 0x000000C0 |
| 77 | |
| 78 | #define PCH_UART_FCR_FIFOE 0x00000001 |
| 79 | #define PCH_UART_FCR_RFR 0x00000002 |
| 80 | #define PCH_UART_FCR_TFR 0x00000004 |
| 81 | #define PCH_UART_FCR_DMS 0x00000008 |
| 82 | #define PCH_UART_FCR_FIFO256 0x00000020 |
| 83 | #define PCH_UART_FCR_RFTL 0x000000C0 |
| 84 | |
| 85 | #define PCH_UART_FCR_RFTL1 0x00000000 |
| 86 | #define PCH_UART_FCR_RFTL64 0x00000040 |
| 87 | #define PCH_UART_FCR_RFTL128 0x00000080 |
| 88 | #define PCH_UART_FCR_RFTL224 0x000000C0 |
| 89 | #define PCH_UART_FCR_RFTL16 PCH_UART_FCR_RFTL64 |
| 90 | #define PCH_UART_FCR_RFTL32 PCH_UART_FCR_RFTL128 |
| 91 | #define PCH_UART_FCR_RFTL56 PCH_UART_FCR_RFTL224 |
| 92 | #define PCH_UART_FCR_RFTL4 PCH_UART_FCR_RFTL64 |
| 93 | #define PCH_UART_FCR_RFTL8 PCH_UART_FCR_RFTL128 |
| 94 | #define PCH_UART_FCR_RFTL14 PCH_UART_FCR_RFTL224 |
| 95 | #define PCH_UART_FCR_RFTL_SHIFT 6 |
| 96 | |
| 97 | #define PCH_UART_LCR_WLS 0x00000003 |
| 98 | #define PCH_UART_LCR_STB 0x00000004 |
| 99 | #define PCH_UART_LCR_PEN 0x00000008 |
| 100 | #define PCH_UART_LCR_EPS 0x00000010 |
| 101 | #define PCH_UART_LCR_SP 0x00000020 |
| 102 | #define PCH_UART_LCR_SB 0x00000040 |
| 103 | #define PCH_UART_LCR_DLAB 0x00000080 |
| 104 | #define PCH_UART_LCR_NP 0x00000000 |
| 105 | #define PCH_UART_LCR_OP PCH_UART_LCR_PEN |
| 106 | #define PCH_UART_LCR_EP (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS) |
| 107 | #define PCH_UART_LCR_1P (PCH_UART_LCR_PEN | PCH_UART_LCR_SP) |
| 108 | #define PCH_UART_LCR_0P (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS |\ |
| 109 | PCH_UART_LCR_SP) |
| 110 | |
| 111 | #define PCH_UART_LCR_5BIT 0x00000000 |
| 112 | #define PCH_UART_LCR_6BIT 0x00000001 |
| 113 | #define PCH_UART_LCR_7BIT 0x00000002 |
| 114 | #define PCH_UART_LCR_8BIT 0x00000003 |
| 115 | |
| 116 | #define PCH_UART_MCR_DTR 0x00000001 |
| 117 | #define PCH_UART_MCR_RTS 0x00000002 |
| 118 | #define PCH_UART_MCR_OUT 0x0000000C |
| 119 | #define PCH_UART_MCR_LOOP 0x00000010 |
| 120 | #define PCH_UART_MCR_AFE 0x00000020 |
| 121 | |
| 122 | #define PCH_UART_LSR_DR 0x00000001 |
| 123 | #define PCH_UART_LSR_ERR (1<<7) |
| 124 | |
| 125 | #define PCH_UART_MSR_DCTS 0x00000001 |
| 126 | #define PCH_UART_MSR_DDSR 0x00000002 |
| 127 | #define PCH_UART_MSR_TERI 0x00000004 |
| 128 | #define PCH_UART_MSR_DDCD 0x00000008 |
| 129 | #define PCH_UART_MSR_CTS 0x00000010 |
| 130 | #define PCH_UART_MSR_DSR 0x00000020 |
| 131 | #define PCH_UART_MSR_RI 0x00000040 |
| 132 | #define PCH_UART_MSR_DCD 0x00000080 |
| 133 | #define PCH_UART_MSR_DELTA (PCH_UART_MSR_DCTS | PCH_UART_MSR_DDSR |\ |
| 134 | PCH_UART_MSR_TERI | PCH_UART_MSR_DDCD) |
| 135 | |
| 136 | #define PCH_UART_DLL 0x00 |
| 137 | #define PCH_UART_DLM 0x01 |
| 138 | |
| 139 | #define DIV_ROUND(a, b) (((a) + ((b)/2)) / (b)) |
| 140 | |
| 141 | #define PCH_UART_IID_RLS (PCH_UART_IIR_REI) |
| 142 | #define PCH_UART_IID_RDR (PCH_UART_IIR_RRI) |
| 143 | #define PCH_UART_IID_RDR_TO (PCH_UART_IIR_RRI | PCH_UART_IIR_TOI) |
| 144 | #define PCH_UART_IID_THRE (PCH_UART_IIR_TRI) |
| 145 | #define PCH_UART_IID_MS (PCH_UART_IIR_MSI) |
| 146 | |
| 147 | #define PCH_UART_HAL_PARITY_NONE (PCH_UART_LCR_NP) |
| 148 | #define PCH_UART_HAL_PARITY_ODD (PCH_UART_LCR_OP) |
| 149 | #define PCH_UART_HAL_PARITY_EVEN (PCH_UART_LCR_EP) |
| 150 | #define PCH_UART_HAL_PARITY_FIX1 (PCH_UART_LCR_1P) |
| 151 | #define PCH_UART_HAL_PARITY_FIX0 (PCH_UART_LCR_0P) |
| 152 | #define PCH_UART_HAL_5BIT (PCH_UART_LCR_5BIT) |
| 153 | #define PCH_UART_HAL_6BIT (PCH_UART_LCR_6BIT) |
| 154 | #define PCH_UART_HAL_7BIT (PCH_UART_LCR_7BIT) |
| 155 | #define PCH_UART_HAL_8BIT (PCH_UART_LCR_8BIT) |
| 156 | #define PCH_UART_HAL_STB1 0 |
| 157 | #define PCH_UART_HAL_STB2 (PCH_UART_LCR_STB) |
| 158 | |
| 159 | #define PCH_UART_HAL_CLR_TX_FIFO (PCH_UART_FCR_TFR) |
| 160 | #define PCH_UART_HAL_CLR_RX_FIFO (PCH_UART_FCR_RFR) |
| 161 | #define PCH_UART_HAL_CLR_ALL_FIFO (PCH_UART_HAL_CLR_TX_FIFO | \ |
| 162 | PCH_UART_HAL_CLR_RX_FIFO) |
| 163 | |
| 164 | #define PCH_UART_HAL_DMA_MODE0 0 |
| 165 | #define PCH_UART_HAL_FIFO_DIS 0 |
| 166 | #define PCH_UART_HAL_FIFO16 (PCH_UART_FCR_FIFOE) |
| 167 | #define PCH_UART_HAL_FIFO256 (PCH_UART_FCR_FIFOE | \ |
| 168 | PCH_UART_FCR_FIFO256) |
| 169 | #define PCH_UART_HAL_FIFO64 (PCH_UART_HAL_FIFO256) |
| 170 | #define PCH_UART_HAL_TRIGGER1 (PCH_UART_FCR_RFTL1) |
| 171 | #define PCH_UART_HAL_TRIGGER64 (PCH_UART_FCR_RFTL64) |
| 172 | #define PCH_UART_HAL_TRIGGER128 (PCH_UART_FCR_RFTL128) |
| 173 | #define PCH_UART_HAL_TRIGGER224 (PCH_UART_FCR_RFTL224) |
| 174 | #define PCH_UART_HAL_TRIGGER16 (PCH_UART_FCR_RFTL16) |
| 175 | #define PCH_UART_HAL_TRIGGER32 (PCH_UART_FCR_RFTL32) |
| 176 | #define PCH_UART_HAL_TRIGGER56 (PCH_UART_FCR_RFTL56) |
| 177 | #define PCH_UART_HAL_TRIGGER4 (PCH_UART_FCR_RFTL4) |
| 178 | #define PCH_UART_HAL_TRIGGER8 (PCH_UART_FCR_RFTL8) |
| 179 | #define PCH_UART_HAL_TRIGGER14 (PCH_UART_FCR_RFTL14) |
| 180 | #define PCH_UART_HAL_TRIGGER_L (PCH_UART_FCR_RFTL64) |
| 181 | #define PCH_UART_HAL_TRIGGER_M (PCH_UART_FCR_RFTL128) |
| 182 | #define PCH_UART_HAL_TRIGGER_H (PCH_UART_FCR_RFTL224) |
| 183 | |
| 184 | #define PCH_UART_HAL_RX_INT (PCH_UART_IER_ERBFI) |
| 185 | #define PCH_UART_HAL_TX_INT (PCH_UART_IER_ETBEI) |
| 186 | #define PCH_UART_HAL_RX_ERR_INT (PCH_UART_IER_ELSI) |
| 187 | #define PCH_UART_HAL_MS_INT (PCH_UART_IER_EDSSI) |
| 188 | #define PCH_UART_HAL_ALL_INT (PCH_UART_IER_MASK) |
| 189 | |
| 190 | #define PCH_UART_HAL_DTR (PCH_UART_MCR_DTR) |
| 191 | #define PCH_UART_HAL_RTS (PCH_UART_MCR_RTS) |
| 192 | #define PCH_UART_HAL_OUT (PCH_UART_MCR_OUT) |
| 193 | #define PCH_UART_HAL_LOOP (PCH_UART_MCR_LOOP) |
| 194 | #define PCH_UART_HAL_AFE (PCH_UART_MCR_AFE) |
| 195 | |
Tomoya MORINAGA | 4564e1e | 2011-01-28 18:00:01 +0900 | [diff] [blame] | 196 | #define PCI_VENDOR_ID_ROHM 0x10DB |
| 197 | |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 198 | struct pch_uart_buffer { |
| 199 | unsigned char *buf; |
| 200 | int size; |
| 201 | }; |
| 202 | |
| 203 | struct eg20t_port { |
| 204 | struct uart_port port; |
| 205 | int port_type; |
| 206 | void __iomem *membase; |
| 207 | resource_size_t mapbase; |
| 208 | unsigned int iobase; |
| 209 | struct pci_dev *pdev; |
| 210 | int fifo_size; |
| 211 | int base_baud; |
| 212 | int start_tx; |
| 213 | int start_rx; |
| 214 | int tx_empty; |
| 215 | int int_dis_flag; |
| 216 | int trigger; |
| 217 | int trigger_level; |
| 218 | struct pch_uart_buffer rxbuf; |
| 219 | unsigned int dmsr; |
| 220 | unsigned int fcr; |
Tomoya MORINAGA | 9af7155 | 2011-02-23 10:03:17 +0900 | [diff] [blame^] | 221 | unsigned int mcr; |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 222 | unsigned int use_dma; |
| 223 | unsigned int use_dma_flag; |
| 224 | struct dma_async_tx_descriptor *desc_tx; |
| 225 | struct dma_async_tx_descriptor *desc_rx; |
| 226 | struct pch_dma_slave param_tx; |
| 227 | struct pch_dma_slave param_rx; |
| 228 | struct dma_chan *chan_tx; |
| 229 | struct dma_chan *chan_rx; |
Tomoya MORINAGA | da3564e | 2011-02-23 10:03:12 +0900 | [diff] [blame] | 230 | struct scatterlist *sg_tx_p; |
| 231 | int nent; |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 232 | struct scatterlist sg_rx; |
| 233 | int tx_dma_use; |
| 234 | void *rx_buf_virt; |
| 235 | dma_addr_t rx_buf_dma; |
| 236 | }; |
| 237 | |
| 238 | static unsigned int default_baud = 9600; |
| 239 | static const int trigger_level_256[4] = { 1, 64, 128, 224 }; |
| 240 | static const int trigger_level_64[4] = { 1, 16, 32, 56 }; |
| 241 | static const int trigger_level_16[4] = { 1, 4, 8, 14 }; |
| 242 | static const int trigger_level_1[4] = { 1, 1, 1, 1 }; |
| 243 | |
| 244 | static void pch_uart_hal_request(struct pci_dev *pdev, int fifosize, |
| 245 | int base_baud) |
| 246 | { |
| 247 | struct eg20t_port *priv = pci_get_drvdata(pdev); |
| 248 | |
| 249 | priv->trigger_level = 1; |
| 250 | priv->fcr = 0; |
| 251 | } |
| 252 | |
| 253 | static unsigned int get_msr(struct eg20t_port *priv, void __iomem *base) |
| 254 | { |
| 255 | unsigned int msr = ioread8(base + UART_MSR); |
| 256 | priv->dmsr |= msr & PCH_UART_MSR_DELTA; |
| 257 | |
| 258 | return msr; |
| 259 | } |
| 260 | |
| 261 | static void pch_uart_hal_enable_interrupt(struct eg20t_port *priv, |
| 262 | unsigned int flag) |
| 263 | { |
| 264 | u8 ier = ioread8(priv->membase + UART_IER); |
| 265 | ier |= flag & PCH_UART_IER_MASK; |
| 266 | iowrite8(ier, priv->membase + UART_IER); |
| 267 | } |
| 268 | |
| 269 | static void pch_uart_hal_disable_interrupt(struct eg20t_port *priv, |
| 270 | unsigned int flag) |
| 271 | { |
| 272 | u8 ier = ioread8(priv->membase + UART_IER); |
| 273 | ier &= ~(flag & PCH_UART_IER_MASK); |
| 274 | iowrite8(ier, priv->membase + UART_IER); |
| 275 | } |
| 276 | |
| 277 | static int pch_uart_hal_set_line(struct eg20t_port *priv, int baud, |
| 278 | unsigned int parity, unsigned int bits, |
| 279 | unsigned int stb) |
| 280 | { |
| 281 | unsigned int dll, dlm, lcr; |
| 282 | int div; |
| 283 | |
| 284 | div = DIV_ROUND(priv->base_baud / 16, baud); |
| 285 | if (div < 0 || USHRT_MAX <= div) { |
Tomoya MORINAGA | 23877fd | 2011-02-23 10:03:15 +0900 | [diff] [blame] | 286 | dev_err(priv->port.dev, "Invalid Baud(div=0x%x)\n", div); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 287 | return -EINVAL; |
| 288 | } |
| 289 | |
| 290 | dll = (unsigned int)div & 0x00FFU; |
| 291 | dlm = ((unsigned int)div >> 8) & 0x00FFU; |
| 292 | |
| 293 | if (parity & ~(PCH_UART_LCR_PEN | PCH_UART_LCR_EPS | PCH_UART_LCR_SP)) { |
Tomoya MORINAGA | 23877fd | 2011-02-23 10:03:15 +0900 | [diff] [blame] | 294 | dev_err(priv->port.dev, "Invalid parity(0x%x)\n", parity); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 295 | return -EINVAL; |
| 296 | } |
| 297 | |
| 298 | if (bits & ~PCH_UART_LCR_WLS) { |
Tomoya MORINAGA | 23877fd | 2011-02-23 10:03:15 +0900 | [diff] [blame] | 299 | dev_err(priv->port.dev, "Invalid bits(0x%x)\n", bits); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 300 | return -EINVAL; |
| 301 | } |
| 302 | |
| 303 | if (stb & ~PCH_UART_LCR_STB) { |
Tomoya MORINAGA | 23877fd | 2011-02-23 10:03:15 +0900 | [diff] [blame] | 304 | dev_err(priv->port.dev, "Invalid STB(0x%x)\n", stb); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 305 | return -EINVAL; |
| 306 | } |
| 307 | |
| 308 | lcr = parity; |
| 309 | lcr |= bits; |
| 310 | lcr |= stb; |
| 311 | |
Tomoya MORINAGA | 23877fd | 2011-02-23 10:03:15 +0900 | [diff] [blame] | 312 | dev_dbg(priv->port.dev, "%s:baud = %d, div = %04x, lcr = %02x (%lu)\n", |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 313 | __func__, baud, div, lcr, jiffies); |
| 314 | iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR); |
| 315 | iowrite8(dll, priv->membase + PCH_UART_DLL); |
| 316 | iowrite8(dlm, priv->membase + PCH_UART_DLM); |
| 317 | iowrite8(lcr, priv->membase + UART_LCR); |
| 318 | |
| 319 | return 0; |
| 320 | } |
| 321 | |
| 322 | static int pch_uart_hal_fifo_reset(struct eg20t_port *priv, |
| 323 | unsigned int flag) |
| 324 | { |
| 325 | if (flag & ~(PCH_UART_FCR_TFR | PCH_UART_FCR_RFR)) { |
Tomoya MORINAGA | 23877fd | 2011-02-23 10:03:15 +0900 | [diff] [blame] | 326 | dev_err(priv->port.dev, "%s:Invalid flag(0x%x)\n", |
| 327 | __func__, flag); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 328 | return -EINVAL; |
| 329 | } |
| 330 | |
| 331 | iowrite8(PCH_UART_FCR_FIFOE | priv->fcr, priv->membase + UART_FCR); |
| 332 | iowrite8(PCH_UART_FCR_FIFOE | priv->fcr | flag, |
| 333 | priv->membase + UART_FCR); |
| 334 | iowrite8(priv->fcr, priv->membase + UART_FCR); |
| 335 | |
| 336 | return 0; |
| 337 | } |
| 338 | |
| 339 | static int pch_uart_hal_set_fifo(struct eg20t_port *priv, |
| 340 | unsigned int dmamode, |
| 341 | unsigned int fifo_size, unsigned int trigger) |
| 342 | { |
| 343 | u8 fcr; |
| 344 | |
| 345 | if (dmamode & ~PCH_UART_FCR_DMS) { |
Tomoya MORINAGA | 23877fd | 2011-02-23 10:03:15 +0900 | [diff] [blame] | 346 | dev_err(priv->port.dev, "%s:Invalid DMA Mode(0x%x)\n", |
| 347 | __func__, dmamode); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 348 | return -EINVAL; |
| 349 | } |
| 350 | |
| 351 | if (fifo_size & ~(PCH_UART_FCR_FIFOE | PCH_UART_FCR_FIFO256)) { |
Tomoya MORINAGA | 23877fd | 2011-02-23 10:03:15 +0900 | [diff] [blame] | 352 | dev_err(priv->port.dev, "%s:Invalid FIFO SIZE(0x%x)\n", |
| 353 | __func__, fifo_size); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 354 | return -EINVAL; |
| 355 | } |
| 356 | |
| 357 | if (trigger & ~PCH_UART_FCR_RFTL) { |
Tomoya MORINAGA | 23877fd | 2011-02-23 10:03:15 +0900 | [diff] [blame] | 358 | dev_err(priv->port.dev, "%s:Invalid TRIGGER(0x%x)\n", |
| 359 | __func__, trigger); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 360 | return -EINVAL; |
| 361 | } |
| 362 | |
| 363 | switch (priv->fifo_size) { |
| 364 | case 256: |
| 365 | priv->trigger_level = |
| 366 | trigger_level_256[trigger >> PCH_UART_FCR_RFTL_SHIFT]; |
| 367 | break; |
| 368 | case 64: |
| 369 | priv->trigger_level = |
| 370 | trigger_level_64[trigger >> PCH_UART_FCR_RFTL_SHIFT]; |
| 371 | break; |
| 372 | case 16: |
| 373 | priv->trigger_level = |
| 374 | trigger_level_16[trigger >> PCH_UART_FCR_RFTL_SHIFT]; |
| 375 | break; |
| 376 | default: |
| 377 | priv->trigger_level = |
| 378 | trigger_level_1[trigger >> PCH_UART_FCR_RFTL_SHIFT]; |
| 379 | break; |
| 380 | } |
| 381 | fcr = |
| 382 | dmamode | fifo_size | trigger | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR; |
| 383 | iowrite8(PCH_UART_FCR_FIFOE, priv->membase + UART_FCR); |
| 384 | iowrite8(PCH_UART_FCR_FIFOE | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR, |
| 385 | priv->membase + UART_FCR); |
| 386 | iowrite8(fcr, priv->membase + UART_FCR); |
| 387 | priv->fcr = fcr; |
| 388 | |
| 389 | return 0; |
| 390 | } |
| 391 | |
| 392 | static u8 pch_uart_hal_get_modem(struct eg20t_port *priv) |
| 393 | { |
| 394 | priv->dmsr = 0; |
| 395 | return get_msr(priv, priv->membase); |
| 396 | } |
| 397 | |
Tomoya MORINAGA | 1822076 | 2011-02-23 10:03:14 +0900 | [diff] [blame] | 398 | static void pch_uart_hal_write(struct eg20t_port *priv, |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 399 | const unsigned char *buf, int tx_size) |
| 400 | { |
| 401 | int i; |
| 402 | unsigned int thr; |
| 403 | |
| 404 | for (i = 0; i < tx_size;) { |
| 405 | thr = buf[i++]; |
| 406 | iowrite8(thr, priv->membase + PCH_UART_THR); |
| 407 | } |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 408 | } |
| 409 | |
| 410 | static int pch_uart_hal_read(struct eg20t_port *priv, unsigned char *buf, |
| 411 | int rx_size) |
| 412 | { |
| 413 | int i; |
| 414 | u8 rbr, lsr; |
| 415 | |
| 416 | lsr = ioread8(priv->membase + UART_LSR); |
| 417 | for (i = 0, lsr = ioread8(priv->membase + UART_LSR); |
| 418 | i < rx_size && lsr & UART_LSR_DR; |
| 419 | lsr = ioread8(priv->membase + UART_LSR)) { |
| 420 | rbr = ioread8(priv->membase + PCH_UART_RBR); |
| 421 | buf[i++] = rbr; |
| 422 | } |
| 423 | return i; |
| 424 | } |
| 425 | |
| 426 | static unsigned int pch_uart_hal_get_iid(struct eg20t_port *priv) |
| 427 | { |
| 428 | unsigned int iir; |
| 429 | int ret; |
| 430 | |
| 431 | iir = ioread8(priv->membase + UART_IIR); |
| 432 | ret = (iir & (PCH_UART_IIR_IID | PCH_UART_IIR_TOI | PCH_UART_IIR_IP)); |
| 433 | return ret; |
| 434 | } |
| 435 | |
| 436 | static u8 pch_uart_hal_get_line_status(struct eg20t_port *priv) |
| 437 | { |
| 438 | return ioread8(priv->membase + UART_LSR); |
| 439 | } |
| 440 | |
| 441 | static void pch_uart_hal_set_break(struct eg20t_port *priv, int on) |
| 442 | { |
| 443 | unsigned int lcr; |
| 444 | |
| 445 | lcr = ioread8(priv->membase + UART_LCR); |
| 446 | if (on) |
| 447 | lcr |= PCH_UART_LCR_SB; |
| 448 | else |
| 449 | lcr &= ~PCH_UART_LCR_SB; |
| 450 | |
| 451 | iowrite8(lcr, priv->membase + UART_LCR); |
| 452 | } |
| 453 | |
| 454 | static int push_rx(struct eg20t_port *priv, const unsigned char *buf, |
| 455 | int size) |
| 456 | { |
| 457 | struct uart_port *port; |
| 458 | struct tty_struct *tty; |
| 459 | |
| 460 | port = &priv->port; |
| 461 | tty = tty_port_tty_get(&port->state->port); |
| 462 | if (!tty) { |
Tomoya MORINAGA | 23877fd | 2011-02-23 10:03:15 +0900 | [diff] [blame] | 463 | dev_dbg(priv->port.dev, "%s:tty is busy now", __func__); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 464 | return -EBUSY; |
| 465 | } |
| 466 | |
| 467 | tty_insert_flip_string(tty, buf, size); |
| 468 | tty_flip_buffer_push(tty); |
| 469 | tty_kref_put(tty); |
| 470 | |
| 471 | return 0; |
| 472 | } |
| 473 | |
| 474 | static int pop_tx_x(struct eg20t_port *priv, unsigned char *buf) |
| 475 | { |
| 476 | int ret; |
| 477 | struct uart_port *port = &priv->port; |
| 478 | |
| 479 | if (port->x_char) { |
Tomoya MORINAGA | 23877fd | 2011-02-23 10:03:15 +0900 | [diff] [blame] | 480 | dev_dbg(priv->port.dev, "%s:X character send %02x (%lu)\n", |
| 481 | __func__, port->x_char, jiffies); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 482 | buf[0] = port->x_char; |
| 483 | port->x_char = 0; |
| 484 | ret = 1; |
| 485 | } else { |
| 486 | ret = 0; |
| 487 | } |
| 488 | |
| 489 | return ret; |
| 490 | } |
| 491 | |
| 492 | static int dma_push_rx(struct eg20t_port *priv, int size) |
| 493 | { |
| 494 | struct tty_struct *tty; |
| 495 | int room; |
| 496 | struct uart_port *port = &priv->port; |
| 497 | |
| 498 | port = &priv->port; |
| 499 | tty = tty_port_tty_get(&port->state->port); |
| 500 | if (!tty) { |
Tomoya MORINAGA | 23877fd | 2011-02-23 10:03:15 +0900 | [diff] [blame] | 501 | dev_dbg(priv->port.dev, "%s:tty is busy now", __func__); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 502 | return 0; |
| 503 | } |
| 504 | |
| 505 | room = tty_buffer_request_room(tty, size); |
| 506 | |
| 507 | if (room < size) |
| 508 | dev_warn(port->dev, "Rx overrun: dropping %u bytes\n", |
| 509 | size - room); |
| 510 | if (!room) |
| 511 | return room; |
| 512 | |
| 513 | tty_insert_flip_string(tty, sg_virt(&priv->sg_rx), size); |
| 514 | |
| 515 | port->icount.rx += room; |
| 516 | tty_kref_put(tty); |
| 517 | |
| 518 | return room; |
| 519 | } |
| 520 | |
| 521 | static void pch_free_dma(struct uart_port *port) |
| 522 | { |
| 523 | struct eg20t_port *priv; |
| 524 | priv = container_of(port, struct eg20t_port, port); |
| 525 | |
| 526 | if (priv->chan_tx) { |
| 527 | dma_release_channel(priv->chan_tx); |
| 528 | priv->chan_tx = NULL; |
| 529 | } |
| 530 | if (priv->chan_rx) { |
| 531 | dma_release_channel(priv->chan_rx); |
| 532 | priv->chan_rx = NULL; |
| 533 | } |
| 534 | if (sg_dma_address(&priv->sg_rx)) |
| 535 | dma_free_coherent(port->dev, port->fifosize, |
| 536 | sg_virt(&priv->sg_rx), |
| 537 | sg_dma_address(&priv->sg_rx)); |
| 538 | |
| 539 | return; |
| 540 | } |
| 541 | |
| 542 | static bool filter(struct dma_chan *chan, void *slave) |
| 543 | { |
| 544 | struct pch_dma_slave *param = slave; |
| 545 | |
| 546 | if ((chan->chan_id == param->chan_id) && (param->dma_dev == |
| 547 | chan->device->dev)) { |
| 548 | chan->private = param; |
| 549 | return true; |
| 550 | } else { |
| 551 | return false; |
| 552 | } |
| 553 | } |
| 554 | |
| 555 | static void pch_request_dma(struct uart_port *port) |
| 556 | { |
| 557 | dma_cap_mask_t mask; |
| 558 | struct dma_chan *chan; |
| 559 | struct pci_dev *dma_dev; |
| 560 | struct pch_dma_slave *param; |
| 561 | struct eg20t_port *priv = |
| 562 | container_of(port, struct eg20t_port, port); |
| 563 | dma_cap_zero(mask); |
| 564 | dma_cap_set(DMA_SLAVE, mask); |
| 565 | |
| 566 | dma_dev = pci_get_bus_and_slot(2, PCI_DEVFN(0xa, 0)); /* Get DMA's dev |
| 567 | information */ |
| 568 | /* Set Tx DMA */ |
| 569 | param = &priv->param_tx; |
| 570 | param->dma_dev = &dma_dev->dev; |
| 571 | param->chan_id = priv->port.line; |
| 572 | param->tx_reg = port->mapbase + UART_TX; |
| 573 | chan = dma_request_channel(mask, filter, param); |
| 574 | if (!chan) { |
Tomoya MORINAGA | 23877fd | 2011-02-23 10:03:15 +0900 | [diff] [blame] | 575 | dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Tx)\n", |
| 576 | __func__); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 577 | return; |
| 578 | } |
| 579 | priv->chan_tx = chan; |
| 580 | |
| 581 | /* Set Rx DMA */ |
| 582 | param = &priv->param_rx; |
| 583 | param->dma_dev = &dma_dev->dev; |
| 584 | param->chan_id = priv->port.line + 1; /* Rx = Tx + 1 */ |
| 585 | param->rx_reg = port->mapbase + UART_RX; |
| 586 | chan = dma_request_channel(mask, filter, param); |
| 587 | if (!chan) { |
Tomoya MORINAGA | 23877fd | 2011-02-23 10:03:15 +0900 | [diff] [blame] | 588 | dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Rx)\n", |
| 589 | __func__); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 590 | dma_release_channel(priv->chan_tx); |
| 591 | return; |
| 592 | } |
| 593 | |
| 594 | /* Get Consistent memory for DMA */ |
| 595 | priv->rx_buf_virt = dma_alloc_coherent(port->dev, port->fifosize, |
| 596 | &priv->rx_buf_dma, GFP_KERNEL); |
| 597 | priv->chan_rx = chan; |
| 598 | } |
| 599 | |
| 600 | static void pch_dma_rx_complete(void *arg) |
| 601 | { |
| 602 | struct eg20t_port *priv = arg; |
| 603 | struct uart_port *port = &priv->port; |
| 604 | struct tty_struct *tty = tty_port_tty_get(&port->state->port); |
Tomoya MORINAGA | da3564e | 2011-02-23 10:03:12 +0900 | [diff] [blame] | 605 | int count; |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 606 | |
| 607 | if (!tty) { |
Tomoya MORINAGA | 23877fd | 2011-02-23 10:03:15 +0900 | [diff] [blame] | 608 | dev_dbg(priv->port.dev, "%s:tty is busy now", __func__); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 609 | return; |
| 610 | } |
| 611 | |
Tomoya MORINAGA | da3564e | 2011-02-23 10:03:12 +0900 | [diff] [blame] | 612 | dma_sync_sg_for_cpu(port->dev, &priv->sg_rx, 1, DMA_FROM_DEVICE); |
| 613 | count = dma_push_rx(priv, priv->trigger_level); |
| 614 | if (count) |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 615 | tty_flip_buffer_push(tty); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 616 | tty_kref_put(tty); |
Tomoya MORINAGA | da3564e | 2011-02-23 10:03:12 +0900 | [diff] [blame] | 617 | async_tx_ack(priv->desc_rx); |
| 618 | pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 619 | } |
| 620 | |
| 621 | static void pch_dma_tx_complete(void *arg) |
| 622 | { |
| 623 | struct eg20t_port *priv = arg; |
| 624 | struct uart_port *port = &priv->port; |
| 625 | struct circ_buf *xmit = &port->state->xmit; |
Tomoya MORINAGA | da3564e | 2011-02-23 10:03:12 +0900 | [diff] [blame] | 626 | struct scatterlist *sg = priv->sg_tx_p; |
| 627 | int i; |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 628 | |
Tomoya MORINAGA | da3564e | 2011-02-23 10:03:12 +0900 | [diff] [blame] | 629 | for (i = 0; i < priv->nent; i++, sg++) { |
| 630 | xmit->tail += sg_dma_len(sg); |
| 631 | port->icount.tx += sg_dma_len(sg); |
| 632 | } |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 633 | xmit->tail &= UART_XMIT_SIZE - 1; |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 634 | async_tx_ack(priv->desc_tx); |
Tomoya MORINAGA | da3564e | 2011-02-23 10:03:12 +0900 | [diff] [blame] | 635 | dma_unmap_sg(port->dev, sg, priv->nent, DMA_TO_DEVICE); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 636 | priv->tx_dma_use = 0; |
Tomoya MORINAGA | da3564e | 2011-02-23 10:03:12 +0900 | [diff] [blame] | 637 | priv->nent = 0; |
| 638 | kfree(priv->sg_tx_p); |
| 639 | if (uart_circ_chars_pending(xmit)) |
| 640 | pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 641 | } |
| 642 | |
Tomoya MORINAGA | 1822076 | 2011-02-23 10:03:14 +0900 | [diff] [blame] | 643 | static int pop_tx(struct eg20t_port *priv, int size) |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 644 | { |
| 645 | int count = 0; |
| 646 | struct uart_port *port = &priv->port; |
| 647 | struct circ_buf *xmit = &port->state->xmit; |
| 648 | |
| 649 | if (uart_tx_stopped(port) || uart_circ_empty(xmit) || count >= size) |
| 650 | goto pop_tx_end; |
| 651 | |
| 652 | do { |
| 653 | int cnt_to_end = |
| 654 | CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE); |
| 655 | int sz = min(size - count, cnt_to_end); |
Tomoya MORINAGA | 1822076 | 2011-02-23 10:03:14 +0900 | [diff] [blame] | 656 | pch_uart_hal_write(priv, &xmit->buf[xmit->tail], sz); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 657 | xmit->tail = (xmit->tail + sz) & (UART_XMIT_SIZE - 1); |
| 658 | count += sz; |
| 659 | } while (!uart_circ_empty(xmit) && count < size); |
| 660 | |
| 661 | pop_tx_end: |
Tomoya MORINAGA | 23877fd | 2011-02-23 10:03:15 +0900 | [diff] [blame] | 662 | dev_dbg(priv->port.dev, "%d characters. Remained %d characters.(%lu)\n", |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 663 | count, size - count, jiffies); |
| 664 | |
| 665 | return count; |
| 666 | } |
| 667 | |
| 668 | static int handle_rx_to(struct eg20t_port *priv) |
| 669 | { |
| 670 | struct pch_uart_buffer *buf; |
| 671 | int rx_size; |
| 672 | int ret; |
| 673 | if (!priv->start_rx) { |
| 674 | pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT); |
| 675 | return 0; |
| 676 | } |
| 677 | buf = &priv->rxbuf; |
| 678 | do { |
| 679 | rx_size = pch_uart_hal_read(priv, buf->buf, buf->size); |
| 680 | ret = push_rx(priv, buf->buf, rx_size); |
| 681 | if (ret) |
| 682 | return 0; |
| 683 | } while (rx_size == buf->size); |
| 684 | |
| 685 | return PCH_UART_HANDLED_RX_INT; |
| 686 | } |
| 687 | |
| 688 | static int handle_rx(struct eg20t_port *priv) |
| 689 | { |
| 690 | return handle_rx_to(priv); |
| 691 | } |
| 692 | |
| 693 | static int dma_handle_rx(struct eg20t_port *priv) |
| 694 | { |
| 695 | struct uart_port *port = &priv->port; |
| 696 | struct dma_async_tx_descriptor *desc; |
| 697 | struct scatterlist *sg; |
| 698 | |
| 699 | priv = container_of(port, struct eg20t_port, port); |
| 700 | sg = &priv->sg_rx; |
| 701 | |
| 702 | sg_init_table(&priv->sg_rx, 1); /* Initialize SG table */ |
| 703 | |
Tomoya MORINAGA | da3564e | 2011-02-23 10:03:12 +0900 | [diff] [blame] | 704 | sg_dma_len(sg) = priv->trigger_level; |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 705 | |
| 706 | sg_set_page(&priv->sg_rx, virt_to_page(priv->rx_buf_virt), |
Tomoya MORINAGA | 1c51899 | 2010-12-16 16:13:29 +0900 | [diff] [blame] | 707 | sg_dma_len(sg), (unsigned long)priv->rx_buf_virt & |
| 708 | ~PAGE_MASK); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 709 | |
| 710 | sg_dma_address(sg) = priv->rx_buf_dma; |
| 711 | |
| 712 | desc = priv->chan_rx->device->device_prep_slave_sg(priv->chan_rx, |
| 713 | sg, 1, DMA_FROM_DEVICE, |
Tomoya MORINAGA | da3564e | 2011-02-23 10:03:12 +0900 | [diff] [blame] | 714 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
| 715 | |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 716 | if (!desc) |
| 717 | return 0; |
| 718 | |
| 719 | priv->desc_rx = desc; |
| 720 | desc->callback = pch_dma_rx_complete; |
| 721 | desc->callback_param = priv; |
| 722 | desc->tx_submit(desc); |
| 723 | dma_async_issue_pending(priv->chan_rx); |
| 724 | |
| 725 | return PCH_UART_HANDLED_RX_INT; |
| 726 | } |
| 727 | |
| 728 | static unsigned int handle_tx(struct eg20t_port *priv) |
| 729 | { |
| 730 | struct uart_port *port = &priv->port; |
| 731 | struct circ_buf *xmit = &port->state->xmit; |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 732 | int fifo_size; |
| 733 | int tx_size; |
| 734 | int size; |
| 735 | int tx_empty; |
| 736 | |
| 737 | if (!priv->start_tx) { |
Tomoya MORINAGA | 23877fd | 2011-02-23 10:03:15 +0900 | [diff] [blame] | 738 | dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n", |
| 739 | __func__, jiffies); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 740 | pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT); |
| 741 | priv->tx_empty = 1; |
| 742 | return 0; |
| 743 | } |
| 744 | |
| 745 | fifo_size = max(priv->fifo_size, 1); |
| 746 | tx_empty = 1; |
| 747 | if (pop_tx_x(priv, xmit->buf)) { |
| 748 | pch_uart_hal_write(priv, xmit->buf, 1); |
| 749 | port->icount.tx++; |
| 750 | tx_empty = 0; |
| 751 | fifo_size--; |
| 752 | } |
| 753 | size = min(xmit->head - xmit->tail, fifo_size); |
Tomoya MORINAGA | da3564e | 2011-02-23 10:03:12 +0900 | [diff] [blame] | 754 | if (size < 0) |
| 755 | size = fifo_size; |
| 756 | |
Tomoya MORINAGA | 1822076 | 2011-02-23 10:03:14 +0900 | [diff] [blame] | 757 | tx_size = pop_tx(priv, size); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 758 | if (tx_size > 0) { |
Tomoya MORINAGA | 1822076 | 2011-02-23 10:03:14 +0900 | [diff] [blame] | 759 | port->icount.tx += tx_size; |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 760 | tx_empty = 0; |
| 761 | } |
| 762 | |
| 763 | priv->tx_empty = tx_empty; |
| 764 | |
Tomoya MORINAGA | da3564e | 2011-02-23 10:03:12 +0900 | [diff] [blame] | 765 | if (tx_empty) { |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 766 | pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT); |
Tomoya MORINAGA | da3564e | 2011-02-23 10:03:12 +0900 | [diff] [blame] | 767 | uart_write_wakeup(port); |
| 768 | } |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 769 | |
| 770 | return PCH_UART_HANDLED_TX_INT; |
| 771 | } |
| 772 | |
| 773 | static unsigned int dma_handle_tx(struct eg20t_port *priv) |
| 774 | { |
| 775 | struct uart_port *port = &priv->port; |
| 776 | struct circ_buf *xmit = &port->state->xmit; |
Tomoya MORINAGA | da3564e | 2011-02-23 10:03:12 +0900 | [diff] [blame] | 777 | struct scatterlist *sg; |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 778 | int nent; |
| 779 | int fifo_size; |
| 780 | int tx_empty; |
| 781 | struct dma_async_tx_descriptor *desc; |
Tomoya MORINAGA | da3564e | 2011-02-23 10:03:12 +0900 | [diff] [blame] | 782 | int num; |
| 783 | int i; |
| 784 | int bytes; |
| 785 | int size; |
| 786 | int rem; |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 787 | |
| 788 | if (!priv->start_tx) { |
Tomoya MORINAGA | 23877fd | 2011-02-23 10:03:15 +0900 | [diff] [blame] | 789 | dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n", |
| 790 | __func__, jiffies); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 791 | pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT); |
| 792 | priv->tx_empty = 1; |
| 793 | return 0; |
| 794 | } |
| 795 | |
| 796 | fifo_size = max(priv->fifo_size, 1); |
| 797 | tx_empty = 1; |
| 798 | if (pop_tx_x(priv, xmit->buf)) { |
| 799 | pch_uart_hal_write(priv, xmit->buf, 1); |
| 800 | port->icount.tx++; |
| 801 | tx_empty = 0; |
| 802 | fifo_size--; |
| 803 | } |
| 804 | |
Tomoya MORINAGA | da3564e | 2011-02-23 10:03:12 +0900 | [diff] [blame] | 805 | bytes = min((int)CIRC_CNT(xmit->head, xmit->tail, |
| 806 | UART_XMIT_SIZE), CIRC_CNT_TO_END(xmit->head, |
| 807 | xmit->tail, UART_XMIT_SIZE)); |
| 808 | if (!bytes) { |
Tomoya MORINAGA | 23877fd | 2011-02-23 10:03:15 +0900 | [diff] [blame] | 809 | dev_dbg(priv->port.dev, "%s 0 bytes return\n", __func__); |
Tomoya MORINAGA | da3564e | 2011-02-23 10:03:12 +0900 | [diff] [blame] | 810 | pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT); |
| 811 | uart_write_wakeup(port); |
| 812 | return 0; |
| 813 | } |
| 814 | |
| 815 | if (bytes > fifo_size) { |
| 816 | num = bytes / fifo_size + 1; |
| 817 | size = fifo_size; |
| 818 | rem = bytes % fifo_size; |
| 819 | } else { |
| 820 | num = 1; |
| 821 | size = bytes; |
| 822 | rem = bytes; |
| 823 | } |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 824 | |
Tomoya MORINAGA | 23877fd | 2011-02-23 10:03:15 +0900 | [diff] [blame] | 825 | dev_dbg(priv->port.dev, "%s num=%d size=%d rem=%d\n", |
| 826 | __func__, num, size, rem); |
| 827 | |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 828 | priv->tx_dma_use = 1; |
| 829 | |
Tomoya MORINAGA | da3564e | 2011-02-23 10:03:12 +0900 | [diff] [blame] | 830 | priv->sg_tx_p = kzalloc(sizeof(struct scatterlist)*num, GFP_ATOMIC); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 831 | |
Tomoya MORINAGA | da3564e | 2011-02-23 10:03:12 +0900 | [diff] [blame] | 832 | sg_init_table(priv->sg_tx_p, num); /* Initialize SG table */ |
| 833 | sg = priv->sg_tx_p; |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 834 | |
Tomoya MORINAGA | da3564e | 2011-02-23 10:03:12 +0900 | [diff] [blame] | 835 | for (i = 0; i < num; i++, sg++) { |
| 836 | if (i == (num - 1)) |
| 837 | sg_set_page(sg, virt_to_page(xmit->buf), |
| 838 | rem, fifo_size * i); |
| 839 | else |
| 840 | sg_set_page(sg, virt_to_page(xmit->buf), |
| 841 | size, fifo_size * i); |
| 842 | } |
| 843 | |
| 844 | sg = priv->sg_tx_p; |
| 845 | nent = dma_map_sg(port->dev, sg, num, DMA_TO_DEVICE); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 846 | if (!nent) { |
Tomoya MORINAGA | 23877fd | 2011-02-23 10:03:15 +0900 | [diff] [blame] | 847 | dev_err(priv->port.dev, "%s:dma_map_sg Failed\n", __func__); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 848 | return 0; |
| 849 | } |
Tomoya MORINAGA | da3564e | 2011-02-23 10:03:12 +0900 | [diff] [blame] | 850 | priv->nent = nent; |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 851 | |
Tomoya MORINAGA | da3564e | 2011-02-23 10:03:12 +0900 | [diff] [blame] | 852 | for (i = 0; i < nent; i++, sg++) { |
| 853 | sg->offset = (xmit->tail & (UART_XMIT_SIZE - 1)) + |
| 854 | fifo_size * i; |
| 855 | sg_dma_address(sg) = (sg_dma_address(sg) & |
| 856 | ~(UART_XMIT_SIZE - 1)) + sg->offset; |
| 857 | if (i == (nent - 1)) |
| 858 | sg_dma_len(sg) = rem; |
| 859 | else |
| 860 | sg_dma_len(sg) = size; |
| 861 | } |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 862 | |
| 863 | desc = priv->chan_tx->device->device_prep_slave_sg(priv->chan_tx, |
Tomoya MORINAGA | da3564e | 2011-02-23 10:03:12 +0900 | [diff] [blame] | 864 | priv->sg_tx_p, nent, DMA_TO_DEVICE, |
| 865 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 866 | if (!desc) { |
Tomoya MORINAGA | 23877fd | 2011-02-23 10:03:15 +0900 | [diff] [blame] | 867 | dev_err(priv->port.dev, "%s:device_prep_slave_sg Failed\n", |
| 868 | __func__); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 869 | return 0; |
| 870 | } |
Tomoya MORINAGA | da3564e | 2011-02-23 10:03:12 +0900 | [diff] [blame] | 871 | dma_sync_sg_for_device(port->dev, priv->sg_tx_p, nent, DMA_TO_DEVICE); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 872 | priv->desc_tx = desc; |
| 873 | desc->callback = pch_dma_tx_complete; |
| 874 | desc->callback_param = priv; |
| 875 | |
| 876 | desc->tx_submit(desc); |
| 877 | |
| 878 | dma_async_issue_pending(priv->chan_tx); |
| 879 | |
| 880 | return PCH_UART_HANDLED_TX_INT; |
| 881 | } |
| 882 | |
| 883 | static void pch_uart_err_ir(struct eg20t_port *priv, unsigned int lsr) |
| 884 | { |
| 885 | u8 fcr = ioread8(priv->membase + UART_FCR); |
| 886 | |
| 887 | /* Reset FIFO */ |
| 888 | fcr |= UART_FCR_CLEAR_RCVR; |
| 889 | iowrite8(fcr, priv->membase + UART_FCR); |
| 890 | |
| 891 | if (lsr & PCH_UART_LSR_ERR) |
| 892 | dev_err(&priv->pdev->dev, "Error data in FIFO\n"); |
| 893 | |
| 894 | if (lsr & UART_LSR_FE) |
| 895 | dev_err(&priv->pdev->dev, "Framing Error\n"); |
| 896 | |
| 897 | if (lsr & UART_LSR_PE) |
| 898 | dev_err(&priv->pdev->dev, "Parity Error\n"); |
| 899 | |
| 900 | if (lsr & UART_LSR_OE) |
| 901 | dev_err(&priv->pdev->dev, "Overrun Error\n"); |
| 902 | } |
| 903 | |
| 904 | static irqreturn_t pch_uart_interrupt(int irq, void *dev_id) |
| 905 | { |
| 906 | struct eg20t_port *priv = dev_id; |
| 907 | unsigned int handled; |
| 908 | u8 lsr; |
| 909 | int ret = 0; |
| 910 | unsigned int iid; |
| 911 | unsigned long flags; |
| 912 | |
| 913 | spin_lock_irqsave(&priv->port.lock, flags); |
| 914 | handled = 0; |
| 915 | while ((iid = pch_uart_hal_get_iid(priv)) > 1) { |
| 916 | switch (iid) { |
| 917 | case PCH_UART_IID_RLS: /* Receiver Line Status */ |
| 918 | lsr = pch_uart_hal_get_line_status(priv); |
| 919 | if (lsr & (PCH_UART_LSR_ERR | UART_LSR_FE | |
| 920 | UART_LSR_PE | UART_LSR_OE)) { |
| 921 | pch_uart_err_ir(priv, lsr); |
| 922 | ret = PCH_UART_HANDLED_RX_ERR_INT; |
| 923 | } |
| 924 | break; |
| 925 | case PCH_UART_IID_RDR: /* Received Data Ready */ |
Tomoya MORINAGA | da3564e | 2011-02-23 10:03:12 +0900 | [diff] [blame] | 926 | if (priv->use_dma) { |
| 927 | pch_uart_hal_disable_interrupt(priv, |
| 928 | PCH_UART_HAL_RX_INT); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 929 | ret = dma_handle_rx(priv); |
Tomoya MORINAGA | da3564e | 2011-02-23 10:03:12 +0900 | [diff] [blame] | 930 | if (!ret) |
| 931 | pch_uart_hal_enable_interrupt(priv, |
| 932 | PCH_UART_HAL_RX_INT); |
| 933 | } else { |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 934 | ret = handle_rx(priv); |
Tomoya MORINAGA | da3564e | 2011-02-23 10:03:12 +0900 | [diff] [blame] | 935 | } |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 936 | break; |
| 937 | case PCH_UART_IID_RDR_TO: /* Received Data Ready |
| 938 | (FIFO Timeout) */ |
| 939 | ret = handle_rx_to(priv); |
| 940 | break; |
| 941 | case PCH_UART_IID_THRE: /* Transmitter Holding Register |
| 942 | Empty */ |
| 943 | if (priv->use_dma) |
| 944 | ret = dma_handle_tx(priv); |
| 945 | else |
| 946 | ret = handle_tx(priv); |
| 947 | break; |
| 948 | case PCH_UART_IID_MS: /* Modem Status */ |
| 949 | ret = PCH_UART_HANDLED_MS_INT; |
| 950 | break; |
| 951 | default: /* Never junp to this label */ |
Tomoya MORINAGA | 23877fd | 2011-02-23 10:03:15 +0900 | [diff] [blame] | 952 | dev_err(priv->port.dev, "%s:iid=%d (%lu)\n", __func__, |
| 953 | iid, jiffies); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 954 | ret = -1; |
| 955 | break; |
| 956 | } |
| 957 | handled |= (unsigned int)ret; |
| 958 | } |
| 959 | if (handled == 0 && iid <= 1) { |
| 960 | if (priv->int_dis_flag) |
| 961 | priv->int_dis_flag = 0; |
| 962 | } |
| 963 | |
| 964 | spin_unlock_irqrestore(&priv->port.lock, flags); |
| 965 | return IRQ_RETVAL(handled); |
| 966 | } |
| 967 | |
| 968 | /* This function tests whether the transmitter fifo and shifter for the port |
| 969 | described by 'port' is empty. */ |
| 970 | static unsigned int pch_uart_tx_empty(struct uart_port *port) |
| 971 | { |
| 972 | struct eg20t_port *priv; |
| 973 | int ret; |
| 974 | priv = container_of(port, struct eg20t_port, port); |
| 975 | if (priv->tx_empty) |
| 976 | ret = TIOCSER_TEMT; |
| 977 | else |
| 978 | ret = 0; |
| 979 | |
| 980 | return ret; |
| 981 | } |
| 982 | |
| 983 | /* Returns the current state of modem control inputs. */ |
| 984 | static unsigned int pch_uart_get_mctrl(struct uart_port *port) |
| 985 | { |
| 986 | struct eg20t_port *priv; |
| 987 | u8 modem; |
| 988 | unsigned int ret = 0; |
| 989 | |
| 990 | priv = container_of(port, struct eg20t_port, port); |
| 991 | modem = pch_uart_hal_get_modem(priv); |
| 992 | |
| 993 | if (modem & UART_MSR_DCD) |
| 994 | ret |= TIOCM_CAR; |
| 995 | |
| 996 | if (modem & UART_MSR_RI) |
| 997 | ret |= TIOCM_RNG; |
| 998 | |
| 999 | if (modem & UART_MSR_DSR) |
| 1000 | ret |= TIOCM_DSR; |
| 1001 | |
| 1002 | if (modem & UART_MSR_CTS) |
| 1003 | ret |= TIOCM_CTS; |
| 1004 | |
| 1005 | return ret; |
| 1006 | } |
| 1007 | |
| 1008 | static void pch_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) |
| 1009 | { |
| 1010 | u32 mcr = 0; |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1011 | struct eg20t_port *priv = container_of(port, struct eg20t_port, port); |
| 1012 | |
| 1013 | if (mctrl & TIOCM_DTR) |
| 1014 | mcr |= UART_MCR_DTR; |
| 1015 | if (mctrl & TIOCM_RTS) |
| 1016 | mcr |= UART_MCR_RTS; |
| 1017 | if (mctrl & TIOCM_LOOP) |
| 1018 | mcr |= UART_MCR_LOOP; |
| 1019 | |
Tomoya MORINAGA | 9af7155 | 2011-02-23 10:03:17 +0900 | [diff] [blame^] | 1020 | if (priv->mcr & UART_MCR_AFE) |
| 1021 | mcr |= UART_MCR_AFE; |
| 1022 | |
| 1023 | if (mctrl) |
| 1024 | iowrite8(mcr, priv->membase + UART_MCR); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1025 | } |
| 1026 | |
| 1027 | static void pch_uart_stop_tx(struct uart_port *port) |
| 1028 | { |
| 1029 | struct eg20t_port *priv; |
| 1030 | priv = container_of(port, struct eg20t_port, port); |
| 1031 | priv->start_tx = 0; |
| 1032 | priv->tx_dma_use = 0; |
| 1033 | } |
| 1034 | |
| 1035 | static void pch_uart_start_tx(struct uart_port *port) |
| 1036 | { |
| 1037 | struct eg20t_port *priv; |
| 1038 | |
| 1039 | priv = container_of(port, struct eg20t_port, port); |
| 1040 | |
Tomoya MORINAGA | 23877fd | 2011-02-23 10:03:15 +0900 | [diff] [blame] | 1041 | if (priv->use_dma) { |
| 1042 | if (priv->tx_dma_use) { |
| 1043 | dev_dbg(priv->port.dev, "%s : Tx DMA is NOT empty.\n", |
| 1044 | __func__); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1045 | return; |
Tomoya MORINAGA | 23877fd | 2011-02-23 10:03:15 +0900 | [diff] [blame] | 1046 | } |
| 1047 | } |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1048 | |
| 1049 | priv->start_tx = 1; |
| 1050 | pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT); |
| 1051 | } |
| 1052 | |
| 1053 | static void pch_uart_stop_rx(struct uart_port *port) |
| 1054 | { |
| 1055 | struct eg20t_port *priv; |
| 1056 | priv = container_of(port, struct eg20t_port, port); |
| 1057 | priv->start_rx = 0; |
| 1058 | pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT); |
| 1059 | priv->int_dis_flag = 1; |
| 1060 | } |
| 1061 | |
| 1062 | /* Enable the modem status interrupts. */ |
| 1063 | static void pch_uart_enable_ms(struct uart_port *port) |
| 1064 | { |
| 1065 | struct eg20t_port *priv; |
| 1066 | priv = container_of(port, struct eg20t_port, port); |
| 1067 | pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_MS_INT); |
| 1068 | } |
| 1069 | |
| 1070 | /* Control the transmission of a break signal. */ |
| 1071 | static void pch_uart_break_ctl(struct uart_port *port, int ctl) |
| 1072 | { |
| 1073 | struct eg20t_port *priv; |
| 1074 | unsigned long flags; |
| 1075 | |
| 1076 | priv = container_of(port, struct eg20t_port, port); |
| 1077 | spin_lock_irqsave(&port->lock, flags); |
| 1078 | pch_uart_hal_set_break(priv, ctl); |
| 1079 | spin_unlock_irqrestore(&port->lock, flags); |
| 1080 | } |
| 1081 | |
| 1082 | /* Grab any interrupt resources and initialise any low level driver state. */ |
| 1083 | static int pch_uart_startup(struct uart_port *port) |
| 1084 | { |
| 1085 | struct eg20t_port *priv; |
| 1086 | int ret; |
| 1087 | int fifo_size; |
| 1088 | int trigger_level; |
| 1089 | |
| 1090 | priv = container_of(port, struct eg20t_port, port); |
| 1091 | priv->tx_empty = 1; |
Tomoya MORINAGA | aac6c0b | 2011-02-23 10:03:16 +0900 | [diff] [blame] | 1092 | |
| 1093 | if (port->uartclk) |
| 1094 | priv->base_baud = port->uartclk; |
| 1095 | else |
| 1096 | port->uartclk = priv->base_baud; |
| 1097 | |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1098 | pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT); |
| 1099 | ret = pch_uart_hal_set_line(priv, default_baud, |
| 1100 | PCH_UART_HAL_PARITY_NONE, PCH_UART_HAL_8BIT, |
| 1101 | PCH_UART_HAL_STB1); |
| 1102 | if (ret) |
| 1103 | return ret; |
| 1104 | |
| 1105 | switch (priv->fifo_size) { |
| 1106 | case 256: |
| 1107 | fifo_size = PCH_UART_HAL_FIFO256; |
| 1108 | break; |
| 1109 | case 64: |
| 1110 | fifo_size = PCH_UART_HAL_FIFO64; |
| 1111 | break; |
| 1112 | case 16: |
| 1113 | fifo_size = PCH_UART_HAL_FIFO16; |
| 1114 | case 1: |
| 1115 | default: |
| 1116 | fifo_size = PCH_UART_HAL_FIFO_DIS; |
| 1117 | break; |
| 1118 | } |
| 1119 | |
| 1120 | switch (priv->trigger) { |
| 1121 | case PCH_UART_HAL_TRIGGER1: |
| 1122 | trigger_level = 1; |
| 1123 | break; |
| 1124 | case PCH_UART_HAL_TRIGGER_L: |
| 1125 | trigger_level = priv->fifo_size / 4; |
| 1126 | break; |
| 1127 | case PCH_UART_HAL_TRIGGER_M: |
| 1128 | trigger_level = priv->fifo_size / 2; |
| 1129 | break; |
| 1130 | case PCH_UART_HAL_TRIGGER_H: |
| 1131 | default: |
| 1132 | trigger_level = priv->fifo_size - (priv->fifo_size / 8); |
| 1133 | break; |
| 1134 | } |
| 1135 | |
| 1136 | priv->trigger_level = trigger_level; |
| 1137 | ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0, |
| 1138 | fifo_size, priv->trigger); |
| 1139 | if (ret < 0) |
| 1140 | return ret; |
| 1141 | |
| 1142 | ret = request_irq(priv->port.irq, pch_uart_interrupt, IRQF_SHARED, |
| 1143 | KBUILD_MODNAME, priv); |
| 1144 | if (ret < 0) |
| 1145 | return ret; |
| 1146 | |
| 1147 | if (priv->use_dma) |
| 1148 | pch_request_dma(port); |
| 1149 | |
| 1150 | priv->start_rx = 1; |
| 1151 | pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT); |
| 1152 | uart_update_timeout(port, CS8, default_baud); |
| 1153 | |
| 1154 | return 0; |
| 1155 | } |
| 1156 | |
| 1157 | static void pch_uart_shutdown(struct uart_port *port) |
| 1158 | { |
| 1159 | struct eg20t_port *priv; |
| 1160 | int ret; |
| 1161 | |
| 1162 | priv = container_of(port, struct eg20t_port, port); |
| 1163 | pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT); |
| 1164 | pch_uart_hal_fifo_reset(priv, PCH_UART_HAL_CLR_ALL_FIFO); |
| 1165 | ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0, |
| 1166 | PCH_UART_HAL_FIFO_DIS, PCH_UART_HAL_TRIGGER1); |
| 1167 | if (ret) |
Tomoya MORINAGA | 23877fd | 2011-02-23 10:03:15 +0900 | [diff] [blame] | 1168 | dev_err(priv->port.dev, |
| 1169 | "pch_uart_hal_set_fifo Failed(ret=%d)\n", ret); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1170 | |
| 1171 | if (priv->use_dma_flag) |
| 1172 | pch_free_dma(port); |
| 1173 | |
| 1174 | free_irq(priv->port.irq, priv); |
| 1175 | } |
| 1176 | |
| 1177 | /* Change the port parameters, including word length, parity, stop |
| 1178 | *bits. Update read_status_mask and ignore_status_mask to indicate |
| 1179 | *the types of events we are interested in receiving. */ |
| 1180 | static void pch_uart_set_termios(struct uart_port *port, |
| 1181 | struct ktermios *termios, struct ktermios *old) |
| 1182 | { |
| 1183 | int baud; |
| 1184 | int rtn; |
| 1185 | unsigned int parity, bits, stb; |
| 1186 | struct eg20t_port *priv; |
| 1187 | unsigned long flags; |
| 1188 | |
| 1189 | priv = container_of(port, struct eg20t_port, port); |
| 1190 | switch (termios->c_cflag & CSIZE) { |
| 1191 | case CS5: |
| 1192 | bits = PCH_UART_HAL_5BIT; |
| 1193 | break; |
| 1194 | case CS6: |
| 1195 | bits = PCH_UART_HAL_6BIT; |
| 1196 | break; |
| 1197 | case CS7: |
| 1198 | bits = PCH_UART_HAL_7BIT; |
| 1199 | break; |
| 1200 | default: /* CS8 */ |
| 1201 | bits = PCH_UART_HAL_8BIT; |
| 1202 | break; |
| 1203 | } |
| 1204 | if (termios->c_cflag & CSTOPB) |
| 1205 | stb = PCH_UART_HAL_STB2; |
| 1206 | else |
| 1207 | stb = PCH_UART_HAL_STB1; |
| 1208 | |
| 1209 | if (termios->c_cflag & PARENB) { |
| 1210 | if (!(termios->c_cflag & PARODD)) |
| 1211 | parity = PCH_UART_HAL_PARITY_ODD; |
| 1212 | else |
| 1213 | parity = PCH_UART_HAL_PARITY_EVEN; |
| 1214 | |
| 1215 | } else { |
| 1216 | parity = PCH_UART_HAL_PARITY_NONE; |
| 1217 | } |
Tomoya MORINAGA | 9af7155 | 2011-02-23 10:03:17 +0900 | [diff] [blame^] | 1218 | |
| 1219 | /* Only UART0 has auto hardware flow function */ |
| 1220 | if ((termios->c_cflag & CRTSCTS) && (priv->fifo_size == 256)) |
| 1221 | priv->mcr |= UART_MCR_AFE; |
| 1222 | else |
| 1223 | priv->mcr &= ~UART_MCR_AFE; |
| 1224 | |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1225 | termios->c_cflag &= ~CMSPAR; /* Mark/Space parity is not supported */ |
| 1226 | |
| 1227 | baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16); |
| 1228 | |
| 1229 | spin_lock_irqsave(&port->lock, flags); |
| 1230 | |
| 1231 | uart_update_timeout(port, termios->c_cflag, baud); |
| 1232 | rtn = pch_uart_hal_set_line(priv, baud, parity, bits, stb); |
| 1233 | if (rtn) |
| 1234 | goto out; |
| 1235 | |
| 1236 | /* Don't rewrite B0 */ |
| 1237 | if (tty_termios_baud_rate(termios)) |
| 1238 | tty_termios_encode_baud_rate(termios, baud, baud); |
| 1239 | |
| 1240 | out: |
| 1241 | spin_unlock_irqrestore(&port->lock, flags); |
| 1242 | } |
| 1243 | |
| 1244 | static const char *pch_uart_type(struct uart_port *port) |
| 1245 | { |
| 1246 | return KBUILD_MODNAME; |
| 1247 | } |
| 1248 | |
| 1249 | static void pch_uart_release_port(struct uart_port *port) |
| 1250 | { |
| 1251 | struct eg20t_port *priv; |
| 1252 | |
| 1253 | priv = container_of(port, struct eg20t_port, port); |
| 1254 | pci_iounmap(priv->pdev, priv->membase); |
| 1255 | pci_release_regions(priv->pdev); |
| 1256 | } |
| 1257 | |
| 1258 | static int pch_uart_request_port(struct uart_port *port) |
| 1259 | { |
| 1260 | struct eg20t_port *priv; |
| 1261 | int ret; |
| 1262 | void __iomem *membase; |
| 1263 | |
| 1264 | priv = container_of(port, struct eg20t_port, port); |
| 1265 | ret = pci_request_regions(priv->pdev, KBUILD_MODNAME); |
| 1266 | if (ret < 0) |
| 1267 | return -EBUSY; |
| 1268 | |
| 1269 | membase = pci_iomap(priv->pdev, 1, 0); |
| 1270 | if (!membase) { |
| 1271 | pci_release_regions(priv->pdev); |
| 1272 | return -EBUSY; |
| 1273 | } |
| 1274 | priv->membase = port->membase = membase; |
| 1275 | |
| 1276 | return 0; |
| 1277 | } |
| 1278 | |
| 1279 | static void pch_uart_config_port(struct uart_port *port, int type) |
| 1280 | { |
| 1281 | struct eg20t_port *priv; |
| 1282 | |
| 1283 | priv = container_of(port, struct eg20t_port, port); |
| 1284 | if (type & UART_CONFIG_TYPE) { |
| 1285 | port->type = priv->port_type; |
| 1286 | pch_uart_request_port(port); |
| 1287 | } |
| 1288 | } |
| 1289 | |
| 1290 | static int pch_uart_verify_port(struct uart_port *port, |
| 1291 | struct serial_struct *serinfo) |
| 1292 | { |
| 1293 | struct eg20t_port *priv; |
| 1294 | |
| 1295 | priv = container_of(port, struct eg20t_port, port); |
| 1296 | if (serinfo->flags & UPF_LOW_LATENCY) { |
Tomoya MORINAGA | 23877fd | 2011-02-23 10:03:15 +0900 | [diff] [blame] | 1297 | dev_info(priv->port.dev, |
| 1298 | "PCH UART : Use PIO Mode (without DMA)\n"); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1299 | priv->use_dma = 0; |
| 1300 | serinfo->flags &= ~UPF_LOW_LATENCY; |
| 1301 | } else { |
| 1302 | #ifndef CONFIG_PCH_DMA |
Tomoya MORINAGA | 23877fd | 2011-02-23 10:03:15 +0900 | [diff] [blame] | 1303 | dev_err(priv->port.dev, "%s : PCH DMA is not Loaded.\n", |
| 1304 | __func__); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1305 | return -EOPNOTSUPP; |
| 1306 | #endif |
| 1307 | priv->use_dma = 1; |
| 1308 | priv->use_dma_flag = 1; |
Tomoya MORINAGA | 23877fd | 2011-02-23 10:03:15 +0900 | [diff] [blame] | 1309 | dev_info(priv->port.dev, "PCH UART : Use DMA Mode\n"); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1310 | } |
| 1311 | |
| 1312 | return 0; |
| 1313 | } |
| 1314 | |
| 1315 | static struct uart_ops pch_uart_ops = { |
| 1316 | .tx_empty = pch_uart_tx_empty, |
| 1317 | .set_mctrl = pch_uart_set_mctrl, |
| 1318 | .get_mctrl = pch_uart_get_mctrl, |
| 1319 | .stop_tx = pch_uart_stop_tx, |
| 1320 | .start_tx = pch_uart_start_tx, |
| 1321 | .stop_rx = pch_uart_stop_rx, |
| 1322 | .enable_ms = pch_uart_enable_ms, |
| 1323 | .break_ctl = pch_uart_break_ctl, |
| 1324 | .startup = pch_uart_startup, |
| 1325 | .shutdown = pch_uart_shutdown, |
| 1326 | .set_termios = pch_uart_set_termios, |
| 1327 | /* .pm = pch_uart_pm, Not supported yet */ |
| 1328 | /* .set_wake = pch_uart_set_wake, Not supported yet */ |
| 1329 | .type = pch_uart_type, |
| 1330 | .release_port = pch_uart_release_port, |
| 1331 | .request_port = pch_uart_request_port, |
| 1332 | .config_port = pch_uart_config_port, |
| 1333 | .verify_port = pch_uart_verify_port |
| 1334 | }; |
| 1335 | |
| 1336 | static struct uart_driver pch_uart_driver = { |
| 1337 | .owner = THIS_MODULE, |
| 1338 | .driver_name = KBUILD_MODNAME, |
| 1339 | .dev_name = PCH_UART_DRIVER_DEVICE, |
| 1340 | .major = 0, |
| 1341 | .minor = 0, |
| 1342 | .nr = PCH_UART_NR, |
| 1343 | }; |
| 1344 | |
| 1345 | static struct eg20t_port *pch_uart_init_port(struct pci_dev *pdev, |
Tomoya MORINAGA | 4564e1e | 2011-01-28 18:00:01 +0900 | [diff] [blame] | 1346 | const struct pci_device_id *id) |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1347 | { |
| 1348 | struct eg20t_port *priv; |
| 1349 | int ret; |
| 1350 | unsigned int iobase; |
| 1351 | unsigned int mapbase; |
Tomoya MORINAGA | 1c51899 | 2010-12-16 16:13:29 +0900 | [diff] [blame] | 1352 | unsigned char *rxbuf; |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1353 | int fifosize, base_baud; |
| 1354 | static int num; |
Tomoya MORINAGA | 4564e1e | 2011-01-28 18:00:01 +0900 | [diff] [blame] | 1355 | int port_type = id->driver_data; |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1356 | |
| 1357 | priv = kzalloc(sizeof(struct eg20t_port), GFP_KERNEL); |
| 1358 | if (priv == NULL) |
| 1359 | goto init_port_alloc_err; |
| 1360 | |
Tomoya MORINAGA | 1c51899 | 2010-12-16 16:13:29 +0900 | [diff] [blame] | 1361 | rxbuf = (unsigned char *)__get_free_page(GFP_KERNEL); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1362 | if (!rxbuf) |
| 1363 | goto init_port_free_txbuf; |
| 1364 | |
| 1365 | switch (port_type) { |
| 1366 | case PORT_UNKNOWN: |
Tomoya MORINAGA | 4564e1e | 2011-01-28 18:00:01 +0900 | [diff] [blame] | 1367 | fifosize = 256; /* EG20T/ML7213: UART0 */ |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1368 | base_baud = 1843200; /* 1.8432MHz */ |
| 1369 | break; |
| 1370 | case PORT_8250: |
Tomoya MORINAGA | 4564e1e | 2011-01-28 18:00:01 +0900 | [diff] [blame] | 1371 | fifosize = 64; /* EG20T:UART1~3 ML7213: UART1~2*/ |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1372 | base_baud = 1843200; /* 1.8432MHz */ |
| 1373 | break; |
| 1374 | default: |
| 1375 | dev_err(&pdev->dev, "Invalid Port Type(=%d)\n", port_type); |
| 1376 | goto init_port_hal_free; |
| 1377 | } |
| 1378 | |
| 1379 | iobase = pci_resource_start(pdev, 0); |
| 1380 | mapbase = pci_resource_start(pdev, 1); |
| 1381 | priv->mapbase = mapbase; |
| 1382 | priv->iobase = iobase; |
| 1383 | priv->pdev = pdev; |
| 1384 | priv->tx_empty = 1; |
Tomoya MORINAGA | 1c51899 | 2010-12-16 16:13:29 +0900 | [diff] [blame] | 1385 | priv->rxbuf.buf = rxbuf; |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1386 | priv->rxbuf.size = PAGE_SIZE; |
| 1387 | |
| 1388 | priv->fifo_size = fifosize; |
| 1389 | priv->base_baud = base_baud; |
| 1390 | priv->port_type = PORT_MAX_8250 + port_type + 1; |
| 1391 | priv->port.dev = &pdev->dev; |
| 1392 | priv->port.iobase = iobase; |
| 1393 | priv->port.membase = NULL; |
| 1394 | priv->port.mapbase = mapbase; |
| 1395 | priv->port.irq = pdev->irq; |
| 1396 | priv->port.iotype = UPIO_PORT; |
| 1397 | priv->port.ops = &pch_uart_ops; |
| 1398 | priv->port.flags = UPF_BOOT_AUTOCONF; |
| 1399 | priv->port.fifosize = fifosize; |
| 1400 | priv->port.line = num++; |
| 1401 | priv->trigger = PCH_UART_HAL_TRIGGER_M; |
| 1402 | |
Tomoya MORINAGA | 7e46132 | 2011-02-23 10:03:13 +0900 | [diff] [blame] | 1403 | spin_lock_init(&priv->port.lock); |
| 1404 | |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1405 | pci_set_drvdata(pdev, priv); |
| 1406 | pch_uart_hal_request(pdev, fifosize, base_baud); |
Tomoya MORINAGA | 4564e1e | 2011-01-28 18:00:01 +0900 | [diff] [blame] | 1407 | |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1408 | ret = uart_add_one_port(&pch_uart_driver, &priv->port); |
| 1409 | if (ret < 0) |
| 1410 | goto init_port_hal_free; |
| 1411 | |
| 1412 | return priv; |
| 1413 | |
| 1414 | init_port_hal_free: |
Tomoya MORINAGA | 1c51899 | 2010-12-16 16:13:29 +0900 | [diff] [blame] | 1415 | free_page((unsigned long)rxbuf); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1416 | init_port_free_txbuf: |
| 1417 | kfree(priv); |
| 1418 | init_port_alloc_err: |
| 1419 | |
| 1420 | return NULL; |
| 1421 | } |
| 1422 | |
| 1423 | static void pch_uart_exit_port(struct eg20t_port *priv) |
| 1424 | { |
| 1425 | uart_remove_one_port(&pch_uart_driver, &priv->port); |
| 1426 | pci_set_drvdata(priv->pdev, NULL); |
Tomoya MORINAGA | 1c51899 | 2010-12-16 16:13:29 +0900 | [diff] [blame] | 1427 | free_page((unsigned long)priv->rxbuf.buf); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1428 | } |
| 1429 | |
| 1430 | static void pch_uart_pci_remove(struct pci_dev *pdev) |
| 1431 | { |
| 1432 | struct eg20t_port *priv; |
| 1433 | |
| 1434 | priv = (struct eg20t_port *)pci_get_drvdata(pdev); |
| 1435 | pch_uart_exit_port(priv); |
| 1436 | pci_disable_device(pdev); |
| 1437 | kfree(priv); |
| 1438 | return; |
| 1439 | } |
| 1440 | #ifdef CONFIG_PM |
| 1441 | static int pch_uart_pci_suspend(struct pci_dev *pdev, pm_message_t state) |
| 1442 | { |
| 1443 | struct eg20t_port *priv = pci_get_drvdata(pdev); |
| 1444 | |
| 1445 | uart_suspend_port(&pch_uart_driver, &priv->port); |
| 1446 | |
| 1447 | pci_save_state(pdev); |
| 1448 | pci_set_power_state(pdev, pci_choose_state(pdev, state)); |
| 1449 | return 0; |
| 1450 | } |
| 1451 | |
| 1452 | static int pch_uart_pci_resume(struct pci_dev *pdev) |
| 1453 | { |
| 1454 | struct eg20t_port *priv = pci_get_drvdata(pdev); |
| 1455 | int ret; |
| 1456 | |
| 1457 | pci_set_power_state(pdev, PCI_D0); |
| 1458 | pci_restore_state(pdev); |
| 1459 | |
| 1460 | ret = pci_enable_device(pdev); |
| 1461 | if (ret) { |
| 1462 | dev_err(&pdev->dev, |
| 1463 | "%s-pci_enable_device failed(ret=%d) ", __func__, ret); |
| 1464 | return ret; |
| 1465 | } |
| 1466 | |
| 1467 | uart_resume_port(&pch_uart_driver, &priv->port); |
| 1468 | |
| 1469 | return 0; |
| 1470 | } |
| 1471 | #else |
| 1472 | #define pch_uart_pci_suspend NULL |
| 1473 | #define pch_uart_pci_resume NULL |
| 1474 | #endif |
| 1475 | |
| 1476 | static DEFINE_PCI_DEVICE_TABLE(pch_uart_pci_id) = { |
| 1477 | {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8811), |
| 1478 | .driver_data = PCH_UART_8LINE}, |
| 1479 | {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8812), |
| 1480 | .driver_data = PCH_UART_2LINE}, |
| 1481 | {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8813), |
| 1482 | .driver_data = PCH_UART_2LINE}, |
| 1483 | {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8814), |
| 1484 | .driver_data = PCH_UART_2LINE}, |
Tomoya MORINAGA | 4564e1e | 2011-01-28 18:00:01 +0900 | [diff] [blame] | 1485 | {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8027), |
| 1486 | .driver_data = PCH_UART_8LINE}, |
| 1487 | {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8028), |
| 1488 | .driver_data = PCH_UART_2LINE}, |
| 1489 | {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8029), |
| 1490 | .driver_data = PCH_UART_2LINE}, |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1491 | {0,}, |
| 1492 | }; |
| 1493 | |
| 1494 | static int __devinit pch_uart_pci_probe(struct pci_dev *pdev, |
| 1495 | const struct pci_device_id *id) |
| 1496 | { |
| 1497 | int ret; |
| 1498 | struct eg20t_port *priv; |
| 1499 | |
| 1500 | ret = pci_enable_device(pdev); |
| 1501 | if (ret < 0) |
| 1502 | goto probe_error; |
| 1503 | |
Tomoya MORINAGA | 4564e1e | 2011-01-28 18:00:01 +0900 | [diff] [blame] | 1504 | priv = pch_uart_init_port(pdev, id); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1505 | if (!priv) { |
| 1506 | ret = -EBUSY; |
| 1507 | goto probe_disable_device; |
| 1508 | } |
| 1509 | pci_set_drvdata(pdev, priv); |
| 1510 | |
| 1511 | return ret; |
| 1512 | |
| 1513 | probe_disable_device: |
| 1514 | pci_disable_device(pdev); |
| 1515 | probe_error: |
| 1516 | return ret; |
| 1517 | } |
| 1518 | |
| 1519 | static struct pci_driver pch_uart_pci_driver = { |
| 1520 | .name = "pch_uart", |
| 1521 | .id_table = pch_uart_pci_id, |
| 1522 | .probe = pch_uart_pci_probe, |
| 1523 | .remove = __devexit_p(pch_uart_pci_remove), |
| 1524 | .suspend = pch_uart_pci_suspend, |
| 1525 | .resume = pch_uart_pci_resume, |
| 1526 | }; |
| 1527 | |
| 1528 | static int __init pch_uart_module_init(void) |
| 1529 | { |
| 1530 | int ret; |
| 1531 | |
| 1532 | /* register as UART driver */ |
| 1533 | ret = uart_register_driver(&pch_uart_driver); |
| 1534 | if (ret < 0) |
| 1535 | return ret; |
| 1536 | |
| 1537 | /* register as PCI driver */ |
| 1538 | ret = pci_register_driver(&pch_uart_pci_driver); |
| 1539 | if (ret < 0) |
| 1540 | uart_unregister_driver(&pch_uart_driver); |
| 1541 | |
| 1542 | return ret; |
| 1543 | } |
| 1544 | module_init(pch_uart_module_init); |
| 1545 | |
| 1546 | static void __exit pch_uart_module_exit(void) |
| 1547 | { |
| 1548 | pci_unregister_driver(&pch_uart_pci_driver); |
| 1549 | uart_unregister_driver(&pch_uart_driver); |
| 1550 | } |
| 1551 | module_exit(pch_uart_module_exit); |
| 1552 | |
| 1553 | MODULE_LICENSE("GPL v2"); |
| 1554 | MODULE_DESCRIPTION("Intel EG20T PCH UART PCI Driver"); |
| 1555 | module_param(default_baud, uint, S_IRUGO); |