Ondrej Zary | 7648c99 | 2011-06-25 19:14:21 +0200 | [diff] [blame] | 1 | /* |
Artem Fetishev | 62ca89a | 2014-05-11 21:14:30 +0300 | [diff] [blame] | 2 | * Common structures and definitions for FT1000 Flarion Flash OFDM PCMCIA and |
| 3 | * USB devices. |
Ondrej Zary | 7648c99 | 2011-06-25 19:14:21 +0200 | [diff] [blame] | 4 | * |
| 5 | * Originally copyright (c) 2002 Flarion Technologies |
| 6 | * |
| 7 | */ |
| 8 | |
| 9 | #define DSPVERSZ 4 |
| 10 | #define HWSERNUMSZ 16 |
| 11 | #define SKUSZ 20 |
| 12 | #define EUISZ 8 |
| 13 | #define MODESZ 2 |
| 14 | #define CALVERSZ 2 |
| 15 | #define CALDATESZ 6 |
| 16 | |
| 17 | #define ELECTRABUZZ_ID 0 /* ASIC ID for Electrabuzz */ |
| 18 | #define MAGNEMITE_ID 0x1a01 /* ASIC ID for Magnemite */ |
| 19 | |
| 20 | /* MEMORY MAP common to both ELECTRABUZZ and MAGNEMITE */ |
Artem Fetishev | 62ca89a | 2014-05-11 21:14:30 +0300 | [diff] [blame] | 21 | #define FT1000_REG_DPRAM_ADDR 0x000E /* DPADR - Dual Port Ram Indirect |
| 22 | * Address Register |
| 23 | */ |
Ondrej Zary | 7648c99 | 2011-06-25 19:14:21 +0200 | [diff] [blame] | 24 | #define FT1000_REG_SUP_CTRL 0x0020 /* HCTR - Host Control Register */ |
| 25 | #define FT1000_REG_SUP_STAT 0x0022 /* HSTAT - Host Status Register */ |
| 26 | #define FT1000_REG_RESET 0x0024 /* HCTR - Host Control Register */ |
Gulsah Kose | 6d56be08 | 2014-03-19 19:47:27 +0200 | [diff] [blame] | 27 | #define FT1000_REG_SUP_ISR 0x0026 /* HISR - Host Interrupt Status |
| 28 | * Register |
| 29 | */ |
Ondrej Zary | 7648c99 | 2011-06-25 19:14:21 +0200 | [diff] [blame] | 30 | #define FT1000_REG_SUP_IMASK 0x0028 /* HIMASK - Host Interrupt Mask */ |
| 31 | #define FT1000_REG_DOORBELL 0x002a /* DBELL - Door Bell Register */ |
Gulsah Kose | 6d56be08 | 2014-03-19 19:47:27 +0200 | [diff] [blame] | 32 | #define FT1000_REG_ASIC_ID 0x002e /* ASICID - ASIC Identification |
| 33 | * Number |
| 34 | */ |
Ondrej Zary | 7648c99 | 2011-06-25 19:14:21 +0200 | [diff] [blame] | 35 | |
| 36 | /* MEMORY MAP FOR ELECTRABUZZ ASIC */ |
| 37 | #define FT1000_REG_UFIFO_STAT 0x0000 /* UFSR - Uplink FIFO status register */ |
Gulsah Kose | 6d56be08 | 2014-03-19 19:47:27 +0200 | [diff] [blame] | 38 | #define FT1000_REG_UFIFO_BEG 0x0002 /* UFBR - Uplink FIFO beginning |
| 39 | * register |
| 40 | */ |
Ondrej Zary | 7648c99 | 2011-06-25 19:14:21 +0200 | [diff] [blame] | 41 | #define FT1000_REG_UFIFO_MID 0x0004 /* UFMR - Uplink FIFO middle register */ |
| 42 | #define FT1000_REG_UFIFO_END 0x0006 /* UFER - Uplink FIFO end register */ |
Gulsah Kose | 6d56be08 | 2014-03-19 19:47:27 +0200 | [diff] [blame] | 43 | #define FT1000_REG_DFIFO_STAT 0x0008 /* DFSR - Downlink FIFO status |
| 44 | * register |
| 45 | */ |
Ondrej Zary | 7648c99 | 2011-06-25 19:14:21 +0200 | [diff] [blame] | 46 | #define FT1000_REG_DFIFO 0x000A /* DFR - Downlink FIFO Register */ |
Gulsah Kose | 6d56be08 | 2014-03-19 19:47:27 +0200 | [diff] [blame] | 47 | #define FT1000_REG_DPRAM_DATA 0x000C /* DPRAM - Dual Port Indirect |
| 48 | * Data Register |
| 49 | */ |
Ondrej Zary | 7648c99 | 2011-06-25 19:14:21 +0200 | [diff] [blame] | 50 | #define FT1000_REG_WATERMARK 0x0010 /* WMARK - Watermark Register */ |
| 51 | |
| 52 | /* MEMORY MAP FOR MAGNEMITE */ |
Gulsah Kose | 6d56be08 | 2014-03-19 19:47:27 +0200 | [diff] [blame] | 53 | #define FT1000_REG_MAG_UFDR 0x0000 /* UFDR - Uplink FIFO Data |
| 54 | * Register (32-bits) |
| 55 | */ |
| 56 | #define FT1000_REG_MAG_UFDRL 0x0000 /* UFDRL - Uplink FIFO Data |
| 57 | * Register low-word (16-bits) |
| 58 | */ |
| 59 | #define FT1000_REG_MAG_UFDRH 0x0002 /* UFDRH - Uplink FIFO Data Register |
| 60 | * high-word (16-bits) |
| 61 | */ |
Ondrej Zary | 7648c99 | 2011-06-25 19:14:21 +0200 | [diff] [blame] | 62 | #define FT1000_REG_MAG_UFER 0x0004 /* UFER - Uplink FIFO End Register */ |
| 63 | #define FT1000_REG_MAG_UFSR 0x0006 /* UFSR - Uplink FIFO Status Register */ |
Gulsah Kose | 6d56be08 | 2014-03-19 19:47:27 +0200 | [diff] [blame] | 64 | #define FT1000_REG_MAG_DFR 0x0008 /* DFR - Downlink FIFO Register |
| 65 | * (32-bits) |
| 66 | */ |
| 67 | #define FT1000_REG_MAG_DFRL 0x0008 /* DFRL - Downlink FIFO Register |
| 68 | * low-word (16-bits) |
| 69 | */ |
| 70 | #define FT1000_REG_MAG_DFRH 0x000a /* DFRH - Downlink FIFO Register |
| 71 | * high-word (16-bits) |
| 72 | */ |
| 73 | #define FT1000_REG_MAG_DFSR 0x000c /* DFSR - Downlink FIFO Status |
| 74 | * Register |
| 75 | */ |
| 76 | #define FT1000_REG_MAG_DPDATA 0x0010 /* DPDATA - Dual Port RAM Indirect |
| 77 | * Data Register (32-bits) |
| 78 | */ |
| 79 | #define FT1000_REG_MAG_DPDATAL 0x0010 /* DPDATAL - Dual Port RAM Indirect |
| 80 | * Data Register low-word (16-bits) |
| 81 | */ |
| 82 | #define FT1000_REG_MAG_DPDATAH 0x0012 /* DPDATAH - Dual Port RAM Indirect Data |
| 83 | * Register high-word (16-bits) |
| 84 | */ |
Ondrej Zary | 7648c99 | 2011-06-25 19:14:21 +0200 | [diff] [blame] | 85 | #define FT1000_REG_MAG_WATERMARK 0x002c /* WMARK - Watermark Register */ |
| 86 | #define FT1000_REG_MAG_VERSION 0x0030 /* LLC Version */ |
| 87 | |
| 88 | /* Reserved Dual Port RAM offsets for Electrabuzz */ |
| 89 | #define FT1000_DPRAM_TX_BASE 0x0002 /* Host to PC Card Messaging Area */ |
| 90 | #define FT1000_DPRAM_RX_BASE 0x0800 /* PC Card to Host Messaging Area */ |
| 91 | #define FT1000_FIFO_LEN 0x07FC /* total length for DSP FIFO tracking */ |
| 92 | #define FT1000_HI_HO 0x07FE /* heartbeat with HI/HO */ |
Gulsah Kose | 6d56be08 | 2014-03-19 19:47:27 +0200 | [diff] [blame] | 93 | #define FT1000_DSP_STATUS 0x0FFE /* dsp status - non-zero is a request |
| 94 | * to reset dsp |
| 95 | */ |
Ondrej Zary | 7648c99 | 2011-06-25 19:14:21 +0200 | [diff] [blame] | 96 | #define FT1000_DSP_LED 0x0FFA /* dsp led status for PAD device */ |
| 97 | #define FT1000_DSP_CON_STATE 0x0FF8 /* DSP Connection Status Info */ |
| 98 | #define FT1000_DPRAM_FEFE 0x0002 /* location for dsp ready indicator */ |
| 99 | #define FT1000_DSP_TIMER0 0x1FF0 /* Timer Field from Basestation */ |
| 100 | #define FT1000_DSP_TIMER1 0x1FF2 /* Timer Field from Basestation */ |
| 101 | #define FT1000_DSP_TIMER2 0x1FF4 /* Timer Field from Basestation */ |
| 102 | #define FT1000_DSP_TIMER3 0x1FF6 /* Timer Field from Basestation */ |
| 103 | |
| 104 | /* Reserved Dual Port RAM offsets for Magnemite */ |
Gulsah Kose | 6d56be08 | 2014-03-19 19:47:27 +0200 | [diff] [blame] | 105 | #define FT1000_DPRAM_MAG_TX_BASE 0x0000 /* Host to PC Card |
| 106 | * Messaging Area |
| 107 | */ |
| 108 | #define FT1000_DPRAM_MAG_RX_BASE 0x0200 /* PC Card to Host |
| 109 | * Messaging Area |
| 110 | */ |
Ondrej Zary | 7648c99 | 2011-06-25 19:14:21 +0200 | [diff] [blame] | 111 | |
Gulsah Kose | 6d56be08 | 2014-03-19 19:47:27 +0200 | [diff] [blame] | 112 | #define FT1000_MAG_FIFO_LEN 0x1FF /* total length for DSP |
| 113 | * FIFO tracking |
| 114 | */ |
Ondrej Zary | 7648c99 | 2011-06-25 19:14:21 +0200 | [diff] [blame] | 115 | #define FT1000_MAG_FIFO_LEN_INDX 0x1 /* low-word index */ |
| 116 | #define FT1000_MAG_HI_HO 0x1FF /* heartbeat with HI/HO */ |
| 117 | #define FT1000_MAG_HI_HO_INDX 0x0 /* high-word index */ |
Gulsah Kose | 6d56be08 | 2014-03-19 19:47:27 +0200 | [diff] [blame] | 118 | #define FT1000_MAG_DSP_LED 0x3FE /* dsp led status for |
| 119 | * PAD device |
| 120 | */ |
| 121 | #define FT1000_MAG_DSP_LED_INDX 0x0 /* dsp led status for |
| 122 | * PAD device |
| 123 | */ |
Ondrej Zary | 7648c99 | 2011-06-25 19:14:21 +0200 | [diff] [blame] | 124 | #define FT1000_MAG_DSP_CON_STATE 0x3FE /* DSP Connection Status Info */ |
| 125 | #define FT1000_MAG_DSP_CON_STATE_INDX 0x1 /* DSP Connection Status Info */ |
Gulsah Kose | 6d56be08 | 2014-03-19 19:47:27 +0200 | [diff] [blame] | 126 | #define FT1000_MAG_DPRAM_FEFE 0x000 /* location for dsp ready |
| 127 | * indicator |
| 128 | */ |
| 129 | #define FT1000_MAG_DPRAM_FEFE_INDX 0x0 /* location for dsp ready |
| 130 | * indicator |
| 131 | */ |
| 132 | #define FT1000_MAG_DSP_TIMER0 0x3FC /* Timer Field from |
| 133 | * Basestation |
| 134 | */ |
Ondrej Zary | 7648c99 | 2011-06-25 19:14:21 +0200 | [diff] [blame] | 135 | #define FT1000_MAG_DSP_TIMER0_INDX 0x1 |
Gulsah Kose | 6d56be08 | 2014-03-19 19:47:27 +0200 | [diff] [blame] | 136 | #define FT1000_MAG_DSP_TIMER1 0x3FC /* Timer Field from |
| 137 | * Basestation |
| 138 | */ |
Ondrej Zary | 7648c99 | 2011-06-25 19:14:21 +0200 | [diff] [blame] | 139 | #define FT1000_MAG_DSP_TIMER1_INDX 0x0 |
Gulsah Kose | 6d56be08 | 2014-03-19 19:47:27 +0200 | [diff] [blame] | 140 | #define FT1000_MAG_DSP_TIMER2 0x3FD /* Timer Field from |
| 141 | * Basestation |
| 142 | */ |
Ondrej Zary | 7648c99 | 2011-06-25 19:14:21 +0200 | [diff] [blame] | 143 | #define FT1000_MAG_DSP_TIMER2_INDX 0x1 |
Gulsah Kose | 6d56be08 | 2014-03-19 19:47:27 +0200 | [diff] [blame] | 144 | #define FT1000_MAG_DSP_TIMER3 0x3FD /* Timer Field from |
| 145 | * Basestation |
| 146 | */ |
Ondrej Zary | 7648c99 | 2011-06-25 19:14:21 +0200 | [diff] [blame] | 147 | #define FT1000_MAG_DSP_TIMER3_INDX 0x0 |
| 148 | #define FT1000_MAG_TOTAL_LEN 0x200 |
| 149 | #define FT1000_MAG_TOTAL_LEN_INDX 0x1 |
| 150 | #define FT1000_MAG_PH_LEN 0x200 |
| 151 | #define FT1000_MAG_PH_LEN_INDX 0x0 |
| 152 | #define FT1000_MAG_PORT_ID 0x201 |
| 153 | #define FT1000_MAG_PORT_ID_INDX 0x0 |
| 154 | |
| 155 | #define HOST_INTF_LE 0x0 /* Host interface little endian mode */ |
| 156 | #define HOST_INTF_BE 0x1 /* Host interface big endian mode */ |
| 157 | |
| 158 | /* FT1000 to Host Doorbell assignments */ |
Gulsah Kose | 6d56be08 | 2014-03-19 19:47:27 +0200 | [diff] [blame] | 159 | #define FT1000_DB_DPRAM_RX 0x0001 /* this value indicates that DSP |
| 160 | * has data for host in DPRAM |
| 161 | */ |
Ondrej Zary | 7648c99 | 2011-06-25 19:14:21 +0200 | [diff] [blame] | 162 | #define FT1000_DB_DNLD_RX 0x0002 /* Downloader handshake doorbell */ |
Gulsah Kose | 6d56be08 | 2014-03-19 19:47:27 +0200 | [diff] [blame] | 163 | #define FT1000_ASIC_RESET_REQ 0x0004 /* DSP requesting host to |
| 164 | * reset the ASIC |
| 165 | */ |
| 166 | #define FT1000_DSP_ASIC_RESET 0x0008 /* DSP indicating host that |
| 167 | * it will reset the ASIC |
| 168 | */ |
Ondrej Zary | 7648c99 | 2011-06-25 19:14:21 +0200 | [diff] [blame] | 169 | #define FT1000_DB_COND_RESET 0x0010 /* DSP request for a card reset. */ |
| 170 | |
| 171 | /* Host to FT1000 Doorbell assignments */ |
Gulsah Kose | 6d56be08 | 2014-03-19 19:47:27 +0200 | [diff] [blame] | 172 | #define FT1000_DB_DPRAM_TX 0x0100 /* this value indicates that host |
| 173 | * has data for DSP in DPRAM. |
| 174 | */ |
Ondrej Zary | 7648c99 | 2011-06-25 19:14:21 +0200 | [diff] [blame] | 175 | #define FT1000_DB_DNLD_TX 0x0200 /* Downloader handshake doorbell */ |
| 176 | #define FT1000_ASIC_RESET_DSP 0x0400 /* Responds to FT1000_ASIC_RESET_REQ */ |
Gulsah Kose | 6d56be08 | 2014-03-19 19:47:27 +0200 | [diff] [blame] | 177 | #define FT1000_DB_HB 0x1000 /* Indicates that supervisor has a |
| 178 | * heartbeat message for DSP. |
| 179 | */ |
Ondrej Zary | 7648c99 | 2011-06-25 19:14:21 +0200 | [diff] [blame] | 180 | |
| 181 | #define hi 0x6869 /* PC Card heartbeat values */ |
| 182 | #define ho 0x686f /* PC Card heartbeat values */ |
| 183 | |
| 184 | /* Magnemite specific defines */ |
Gulsah Kose | 6d56be08 | 2014-03-19 19:47:27 +0200 | [diff] [blame] | 185 | #define hi_mag 0x6968 /* Byte swap hi to avoid |
| 186 | * additional system call |
| 187 | */ |
| 188 | #define ho_mag 0x6f68 /* Byte swap ho to avoid |
| 189 | * additional system call |
| 190 | */ |
Ondrej Zary | 7648c99 | 2011-06-25 19:14:21 +0200 | [diff] [blame] | 191 | |
| 192 | /* Bit field definitions for Host Interrupt Status Register */ |
| 193 | /* Indicate the cause of an interrupt. */ |
| 194 | #define ISR_EMPTY 0x00 /* no bits set */ |
| 195 | #define ISR_DOORBELL_ACK 0x01 /* Doorbell acknowledge from DSP */ |
| 196 | #define ISR_DOORBELL_PEND 0x02 /* Doorbell pending from DSP */ |
| 197 | #define ISR_RCV 0x04 /* Packet available in Downlink FIFO */ |
| 198 | #define ISR_WATERMARK 0x08 /* Watermark requirements satisfied */ |
| 199 | |
| 200 | /* Bit field definition for Host Interrupt Mask */ |
| 201 | #define ISR_MASK_NONE 0x0000 /* no bits set */ |
| 202 | #define ISR_MASK_DOORBELL_ACK 0x0001 /* Doorbell acknowledge mask */ |
| 203 | #define ISR_MASK_DOORBELL_PEND 0x0002 /* Doorbell pending mask */ |
| 204 | #define ISR_MASK_RCV 0x0004 /* Downlink Packet available mask */ |
| 205 | #define ISR_MASK_WATERMARK 0x0008 /* Watermark interrupt mask */ |
| 206 | #define ISR_MASK_ALL 0xffff /* Mask all interrupts */ |
Gulsah Kose | 6d56be08 | 2014-03-19 19:47:27 +0200 | [diff] [blame] | 207 | /* Default interrupt mask |
| 208 | * (Enable Doorbell pending and Packet available interrupts) |
| 209 | */ |
Ondrej Zary | 7648c99 | 2011-06-25 19:14:21 +0200 | [diff] [blame] | 210 | #define ISR_DEFAULT_MASK 0x7ff9 |
| 211 | |
| 212 | /* Bit field definition for Host Control Register */ |
Gulsah Kose | 6d56be08 | 2014-03-19 19:47:27 +0200 | [diff] [blame] | 213 | #define DSP_RESET_BIT 0x0001 /* Bit field to control |
| 214 | * dsp reset state |
| 215 | */ |
Ondrej Zary | 7648c99 | 2011-06-25 19:14:21 +0200 | [diff] [blame] | 216 | /* (0 = out of reset 1 = reset) */ |
Gulsah Kose | 6d56be08 | 2014-03-19 19:47:27 +0200 | [diff] [blame] | 217 | #define ASIC_RESET_BIT 0x0002 /* Bit field to control |
| 218 | * ASIC reset state |
| 219 | */ |
Ondrej Zary | 7648c99 | 2011-06-25 19:14:21 +0200 | [diff] [blame] | 220 | /* (0 = out of reset 1 = reset) */ |
| 221 | #define DSP_UNENCRYPTED 0x0004 |
| 222 | #define DSP_ENCRYPTED 0x0008 |
| 223 | #define EFUSE_MEM_DISABLE 0x0040 |
| 224 | |
| 225 | /* Application specific IDs */ |
| 226 | #define DSPID 0x20 |
| 227 | #define HOSTID 0x10 |
| 228 | #define DSPAIRID 0x90 |
| 229 | #define DRIVERID 0x00 |
| 230 | #define NETWORKID 0x20 |
| 231 | |
| 232 | /* Size of DPRAM Message */ |
| 233 | #define MAX_CMD_SQSIZE 1780 |
| 234 | |
| 235 | #define ENET_MAX_SIZE 1514 |
| 236 | #define ENET_HEADER_SIZE 14 |
| 237 | |
| 238 | #define SLOWQ_TYPE 0 |
| 239 | #define FASTQ_TYPE 1 |
| 240 | |
| 241 | #define MAX_DSP_SESS_REC 1024 |
| 242 | |
| 243 | #define DSP_QID_OFFSET 4 |
| 244 | |
| 245 | /* Driver message types */ |
| 246 | #define MEDIA_STATE 0x0010 |
| 247 | #define TIME_UPDATE 0x0020 |
| 248 | #define DSP_PROVISION 0x0030 |
| 249 | #define DSP_INIT_MSG 0x0050 |
| 250 | #define DSP_HIBERNATE 0x0060 |
| 251 | #define DSP_STORE_INFO 0x0070 |
| 252 | #define DSP_GET_INFO 0x0071 |
| 253 | #define GET_DRV_ERR_RPT_MSG 0x0073 |
| 254 | #define RSP_DRV_ERR_RPT_MSG 0x0074 |
| 255 | |
| 256 | /* Driver Error Messages for DSP */ |
| 257 | #define DSP_HB_INFO 0x7ef0 |
| 258 | #define DSP_FIFO_INFO 0x7ef1 |
| 259 | #define DSP_CONDRESET_INFO 0x7ef2 |
| 260 | #define DSP_CMDLEN_INFO 0x7ef3 |
| 261 | #define DSP_CMDPHCKSUM_INFO 0x7ef4 |
| 262 | #define DSP_PKTPHCKSUM_INFO 0x7ef5 |
| 263 | #define DSP_PKTLEN_INFO 0x7ef6 |
| 264 | #define DSP_USER_RESET 0x7ef7 |
| 265 | #define FIFO_FLUSH_MAXLIMIT 0x7ef8 |
| 266 | #define FIFO_FLUSH_BADCNT 0x7ef9 |
| 267 | #define FIFO_ZERO_LEN 0x7efa |
| 268 | |
| 269 | /* Pseudo Header structure */ |
| 270 | struct pseudo_hdr { |
| 271 | unsigned short length; /* length of msg body */ |
| 272 | unsigned char source; /* hardware source id */ |
| 273 | /* Host = 0x10 */ |
| 274 | /* Dsp = 0x20 */ |
Gulsah Kose | 6d56be08 | 2014-03-19 19:47:27 +0200 | [diff] [blame] | 275 | unsigned char destination; /* hardware destination id |
| 276 | * (refer to source) |
| 277 | */ |
Ondrej Zary | 7648c99 | 2011-06-25 19:14:21 +0200 | [diff] [blame] | 278 | unsigned char portdest; /* software destination port id */ |
| 279 | /* Host = 0x00 */ |
| 280 | /* Applicaton Broadcast = 0x10 */ |
| 281 | /* Network Stack = 0x20 */ |
| 282 | /* Dsp OAM = 0x80 */ |
| 283 | /* Dsp Airlink = 0x90 */ |
| 284 | /* Dsp Loader = 0xa0 */ |
| 285 | /* Dsp MIP = 0xb0 */ |
Gulsah Kose | 6d56be08 | 2014-03-19 19:47:27 +0200 | [diff] [blame] | 286 | unsigned char portsrc; /* software source port id |
| 287 | * (refer to portdest) |
| 288 | */ |
Ondrej Zary | 7648c99 | 2011-06-25 19:14:21 +0200 | [diff] [blame] | 289 | unsigned short sh_str_id; /* not used */ |
| 290 | unsigned char control; /* not used */ |
| 291 | unsigned char rsvd1; |
| 292 | unsigned char seq_num; /* message sequence number */ |
| 293 | unsigned char rsvd2; |
| 294 | unsigned short qos_class; /* not used */ |
| 295 | unsigned short checksum; /* pseudo header checksum */ |
| 296 | } __packed; |
| 297 | |
| 298 | struct drv_msg { |
| 299 | struct pseudo_hdr pseudo; |
| 300 | u16 type; |
| 301 | u16 length; |
| 302 | u8 data[0]; |
| 303 | } __packed; |
| 304 | |
| 305 | struct media_msg { |
| 306 | struct pseudo_hdr pseudo; |
| 307 | u16 type; |
| 308 | u16 length; |
| 309 | u16 state; |
| 310 | u32 ip_addr; |
| 311 | u32 net_mask; |
| 312 | u32 gateway; |
| 313 | u32 dns_1; |
| 314 | u32 dns_2; |
| 315 | } __packed; |
| 316 | |
| 317 | struct dsp_init_msg { |
| 318 | struct pseudo_hdr pseudo; |
| 319 | u16 type; |
| 320 | u16 length; |
| 321 | u8 DspVer[DSPVERSZ]; /* DSP version number */ |
| 322 | u8 HwSerNum[HWSERNUMSZ]; /* Hardware Serial Number */ |
| 323 | u8 Sku[SKUSZ]; /* SKU */ |
| 324 | u8 eui64[EUISZ]; /* EUI64 */ |
| 325 | u8 ProductMode[MODESZ]; /* Product Mode (Market/Production) */ |
| 326 | u8 RfCalVer[CALVERSZ]; /* Rf Calibration version */ |
| 327 | u8 RfCalDate[CALDATESZ]; /* Rf Calibration date */ |
| 328 | } __packed; |
| 329 | |
| 330 | struct prov_record { |
| 331 | struct list_head list; |
| 332 | u8 *pprov_data; |
| 333 | }; |
Ondrej Zary | 3aa2303 | 2012-12-02 12:30:19 +0100 | [diff] [blame] | 334 | |
| 335 | struct ft1000_info { |
| 336 | void *priv; |
| 337 | struct net_device_stats stats; |
| 338 | u16 DrvErrNum; |
| 339 | u16 AsicID; |
| 340 | int CardReady; |
| 341 | int registered; |
| 342 | int mediastate; |
| 343 | u8 squeseqnum; /* sequence number on slow queue */ |
| 344 | spinlock_t dpram_lock; |
| 345 | u16 fifo_cnt; |
| 346 | u8 DspVer[DSPVERSZ]; /* DSP version number */ |
| 347 | u8 HwSerNum[HWSERNUMSZ]; /* Hardware Serial Number */ |
| 348 | u8 Sku[SKUSZ]; /* SKU */ |
| 349 | u8 eui64[EUISZ]; /* EUI64 */ |
| 350 | time_t ConTm; /* Connection Time */ |
| 351 | u8 ProductMode[MODESZ]; |
| 352 | u8 RfCalVer[CALVERSZ]; |
| 353 | u8 RfCalDate[CALDATESZ]; |
| 354 | u16 DSP_TIME[4]; |
| 355 | u16 LedStat; |
| 356 | u16 ConStat; |
| 357 | u16 ProgConStat; |
| 358 | struct list_head prov_list; |
| 359 | u16 DSPInfoBlklen; |
| 360 | int (*ft1000_reset)(void *); |
| 361 | u16 DSPInfoBlk[MAX_DSP_SESS_REC]; |
| 362 | union { |
| 363 | u16 Rec[MAX_DSP_SESS_REC]; |
| 364 | u32 MagRec[MAX_DSP_SESS_REC/2]; |
| 365 | } DSPSess; |
Ondrej Zary | 3aa2303 | 2012-12-02 12:30:19 +0100 | [diff] [blame] | 366 | }; |