blob: 4b26d8528133f6a7c8c6289622cd1428d6d3257b [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1994, 95, 96, 97, 98, 99, 2000, 2003 Ralf Baechle
7 * Copyright (C) 1999, 2000, 2001 Silicon Graphics, Inc.
8 */
9#ifndef _ASM_PGTABLE_32_H
10#define _ASM_PGTABLE_32_H
11
Linus Torvalds1da177e2005-04-16 15:20:36 -070012#include <asm/addrspace.h>
13#include <asm/page.h>
14
15#include <linux/linkage.h>
16#include <asm/cachectl.h>
17#include <asm/fixmap.h>
18
Ralf Baechlec6e8b582005-02-10 12:19:59 +000019#include <asm-generic/pgtable-nopmd.h>
20
Linus Torvalds1da177e2005-04-16 15:20:36 -070021/*
22 * - add_wired_entry() add a fixed TLB entry, and move wired register
23 */
24extern void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1,
25 unsigned long entryhi, unsigned long pagemask);
26
27/*
28 * - add_temporary_entry() add a temporary TLB entry. We use TLB entries
29 * starting at the top and working down. This is for populating the
30 * TLB before trap_init() puts the TLB miss handler in place. It
31 * should be used only for entries matching the actual page tables,
32 * to prevent inconsistencies.
33 */
34extern int add_temporary_entry(unsigned long entrylo0, unsigned long entrylo1,
35 unsigned long entryhi, unsigned long pagemask);
36
37
38/* Basically we have the same two-level (which is the logical three level
39 * Linux page table layout folded) page tables as the i386. Some day
40 * when we have proper page coloring support we can have a 1% quicker
41 * tlb refill handling mechanism, but for now it is a bit slower but
42 * works even with the cache aliasing problem the R4k and above have.
43 */
44
Linus Torvalds1da177e2005-04-16 15:20:36 -070045/* PGDIR_SHIFT determines what a third-level page table entry can map */
Ralf Baechlec6e8b582005-02-10 12:19:59 +000046#ifdef CONFIG_64BIT_PHYS_ADDR
47#define PGDIR_SHIFT 21
48#else
49#define PGDIR_SHIFT 22
50#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -070051#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
52#define PGDIR_MASK (~(PGDIR_SIZE-1))
53
54/*
55 * Entries per page directory level: we use two-level, so
Ralf Baechlec6e8b582005-02-10 12:19:59 +000056 * we don't really have any PUD/PMD directory physically.
Linus Torvalds1da177e2005-04-16 15:20:36 -070057 */
58#ifdef CONFIG_64BIT_PHYS_ADDR
59#define PGD_ORDER 1
Ralf Baechlec6e8b582005-02-10 12:19:59 +000060#define PUD_ORDER aieeee_attempt_to_allocate_pud
61#define PMD_ORDER 1
Linus Torvalds1da177e2005-04-16 15:20:36 -070062#define PTE_ORDER 0
63#else
64#define PGD_ORDER 0
Ralf Baechlec6e8b582005-02-10 12:19:59 +000065#define PUD_ORDER aieeee_attempt_to_allocate_pud
66#define PMD_ORDER 1
Linus Torvalds1da177e2005-04-16 15:20:36 -070067#define PTE_ORDER 0
68#endif
69
70#define PTRS_PER_PGD ((PAGE_SIZE << PGD_ORDER) / sizeof(pgd_t))
Linus Torvalds1da177e2005-04-16 15:20:36 -070071#define PTRS_PER_PTE ((PAGE_SIZE << PTE_ORDER) / sizeof(pte_t))
72
73#define USER_PTRS_PER_PGD (0x80000000UL/PGDIR_SIZE)
Hugh Dickinsd455a362005-04-19 13:29:23 -070074#define FIRST_USER_ADDRESS 0
Linus Torvalds1da177e2005-04-16 15:20:36 -070075
Thiemo Seuferf29244a2005-02-21 11:11:32 +000076#define VMALLOC_START MAP_BASE
Linus Torvalds1da177e2005-04-16 15:20:36 -070077
78#ifdef CONFIG_HIGHMEM
79# define VMALLOC_END (PKMAP_BASE-2*PAGE_SIZE)
80#else
81# define VMALLOC_END (FIXADDR_START-2*PAGE_SIZE)
82#endif
83
84#ifdef CONFIG_64BIT_PHYS_ADDR
85#define pte_ERROR(e) \
86 printk("%s:%d: bad pte %016Lx.\n", __FILE__, __LINE__, pte_val(e))
87#else
88#define pte_ERROR(e) \
89 printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
90#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -070091#define pgd_ERROR(e) \
92 printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
93
94extern void load_pgd(unsigned long pg_dir);
95
96extern pte_t invalid_pte_table[PAGE_SIZE/sizeof(pte_t)];
97
98/*
99 * Empty pgd/pmd entries point to the invalid_pte_table.
100 */
101static inline int pmd_none(pmd_t pmd)
102{
103 return pmd_val(pmd) == (unsigned long) invalid_pte_table;
104}
105
106#define pmd_bad(pmd) (pmd_val(pmd) & ~PAGE_MASK)
107
108static inline int pmd_present(pmd_t pmd)
109{
110 return pmd_val(pmd) != (unsigned long) invalid_pte_table;
111}
112
113static inline void pmd_clear(pmd_t *pmdp)
114{
115 pmd_val(*pmdp) = ((unsigned long) invalid_pte_table);
116}
117
Ralf Baechle6e760c82005-07-06 12:08:11 +0000118#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700119#define pte_page(x) pfn_to_page(pte_pfn(x))
120#define pte_pfn(x) ((unsigned long)((x).pte_high >> 6))
121static inline pte_t
122pfn_pte(unsigned long pfn, pgprot_t prot)
123{
124 pte_t pte;
125 pte.pte_high = (pfn << 6) | (pgprot_val(prot) & 0x3f);
126 pte.pte_low = pgprot_val(prot);
127 return pte;
128}
129
130#else
131
132#define pte_page(x) pfn_to_page(pte_pfn(x))
133
134#ifdef CONFIG_CPU_VR41XX
135#define pte_pfn(x) ((unsigned long)((x).pte >> (PAGE_SHIFT + 2)))
136#define pfn_pte(pfn, prot) __pte(((pfn) << (PAGE_SHIFT + 2)) | pgprot_val(prot))
137#else
138#define pte_pfn(x) ((unsigned long)((x).pte >> PAGE_SHIFT))
Ralf Baechle533330b2005-08-17 10:11:10 +0000139#define pfn_pte(pfn, prot) __pte(((unsigned long long)(pfn) << PAGE_SHIFT) | pgprot_val(prot))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700140#endif
Ralf Baechle6e760c82005-07-06 12:08:11 +0000141#endif /* defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1) */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700142
143#define __pgd_offset(address) pgd_index(address)
Thiemo Seuferf29244a2005-02-21 11:11:32 +0000144#define __pud_offset(address) (((address) >> PUD_SHIFT) & (PTRS_PER_PUD-1))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700145#define __pmd_offset(address) (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1))
146
147/* to find an entry in a kernel page-table-directory */
148#define pgd_offset_k(address) pgd_offset(&init_mm, address)
149
Thiemo Seuferf29244a2005-02-21 11:11:32 +0000150#define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700151
152/* to find an entry in a page-table-directory */
153#define pgd_offset(mm,addr) ((mm)->pgd + pgd_index(addr))
154
Linus Torvalds1da177e2005-04-16 15:20:36 -0700155/* Find an entry in the third-level page table.. */
156#define __pte_offset(address) \
157 (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
158#define pte_offset(dir, address) \
159 ((pte_t *) (pmd_page_kernel(*dir)) + __pte_offset(address))
160#define pte_offset_kernel(dir, address) \
161 ((pte_t *) pmd_page_kernel(*(dir)) + __pte_offset(address))
162
163#define pte_offset_map(dir, address) \
164 ((pte_t *)page_address(pmd_page(*(dir))) + __pte_offset(address))
165#define pte_offset_map_nested(dir, address) \
166 ((pte_t *)page_address(pmd_page(*(dir))) + __pte_offset(address))
167#define pte_unmap(pte) ((void)(pte))
168#define pte_unmap_nested(pte) ((void)(pte))
169
170#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
171
172/* Swap entries must have VALID bit cleared. */
173#define __swp_type(x) (((x).val >> 10) & 0x1f)
174#define __swp_offset(x) ((x).val >> 15)
175#define __swp_entry(type,offset) \
176 ((swp_entry_t) { ((type) << 10) | ((offset) << 15) })
177
178/*
Sergei Shtylyov7cb710c2006-05-27 22:39:39 +0400179 * Bits 0, 4, 8, and 9 are taken, split up 28 bits of offset into this range:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700180 */
Sergei Shtylyov7cb710c2006-05-27 22:39:39 +0400181#define PTE_FILE_MAX_BITS 28
Linus Torvalds1da177e2005-04-16 15:20:36 -0700182
Sergei Shtylyov7cb710c2006-05-27 22:39:39 +0400183#define pte_to_pgoff(_pte) ((((_pte).pte >> 1 ) & 0x07) | \
184 (((_pte).pte >> 2 ) & 0x38) | \
185 (((_pte).pte >> 10) << 6 ))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700186
Sergei Shtylyov7cb710c2006-05-27 22:39:39 +0400187#define pgoff_to_pte(off) ((pte_t) { (((off) & 0x07) << 1 ) | \
188 (((off) & 0x38) << 2 ) | \
189 (((off) >> 6 ) << 10) | \
190 _PAGE_FILE })
Linus Torvalds1da177e2005-04-16 15:20:36 -0700191
192#else
193
194/* Swap entries must have VALID and GLOBAL bits cleared. */
Sergei Shtylyov6ebba0e2006-05-27 20:43:04 +0400195#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
196#define __swp_type(x) (((x).val >> 2) & 0x1f)
197#define __swp_offset(x) ((x).val >> 7)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700198#define __swp_entry(type,offset) \
Sergei Shtylyov6ebba0e2006-05-27 20:43:04 +0400199 ((swp_entry_t) { ((type) << 2) | ((offset) << 7) })
200#else
201#define __swp_type(x) (((x).val >> 8) & 0x1f)
202#define __swp_offset(x) ((x).val >> 13)
203#define __swp_entry(type,offset) \
204 ((swp_entry_t) { ((type) << 8) | ((offset) << 13) })
205#endif /* defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700206
Sergei Shtylyov7cb710c2006-05-27 22:39:39 +0400207#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700208/*
Sergei Shtylyov7cb710c2006-05-27 22:39:39 +0400209 * Bits 0 and 1 of pte_high are taken, use the rest for the page offset...
Linus Torvalds1da177e2005-04-16 15:20:36 -0700210 */
Sergei Shtylyov7cb710c2006-05-27 22:39:39 +0400211#define PTE_FILE_MAX_BITS 30
Linus Torvalds1da177e2005-04-16 15:20:36 -0700212
Sergei Shtylyov7cb710c2006-05-27 22:39:39 +0400213#define pte_to_pgoff(_pte) ((_pte).pte_high >> 2)
214#define pgoff_to_pte(off) ((pte_t) { _PAGE_FILE, (off) << 2 })
Linus Torvalds1da177e2005-04-16 15:20:36 -0700215
216#else
Sergei Shtylyov7cb710c2006-05-27 22:39:39 +0400217/*
218 * Bits 0, 4, 6, and 7 are taken, split up 28 bits of offset into this range:
219 */
220#define PTE_FILE_MAX_BITS 28
Linus Torvalds1da177e2005-04-16 15:20:36 -0700221
Sergei Shtylyov7cb710c2006-05-27 22:39:39 +0400222#define pte_to_pgoff(_pte) ((((_pte).pte >> 1) & 0x7) | \
223 (((_pte).pte >> 2) & 0x8) | \
224 (((_pte).pte >> 8) << 4))
225
226#define pgoff_to_pte(off) ((pte_t) { (((off) & 0x7) << 1) | \
227 (((off) & 0x8) << 2) | \
228 (((off) >> 4) << 8) | \
229 _PAGE_FILE })
Linus Torvalds1da177e2005-04-16 15:20:36 -0700230#endif
231
232#endif
233
Sergei Shtylyov6ebba0e2006-05-27 20:43:04 +0400234#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
235#define __pte_to_swp_entry(pte) ((swp_entry_t) { (pte).pte_high })
236#define __swp_entry_to_pte(x) ((pte_t) { 0, (x).val })
237#else
Linus Torvalds1da177e2005-04-16 15:20:36 -0700238#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
239#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
Sergei Shtylyov6ebba0e2006-05-27 20:43:04 +0400240#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700241
242#endif /* _ASM_PGTABLE_32_H */