| Ralf Baechle | 41c594a | 2006-04-05 09:45:45 +0100 | [diff] [blame] | 1 | #ifndef _ASM_SMTC_MT_H |
| 2 | #define _ASM_SMTC_MT_H |
| 3 | |
| 4 | /* |
| 5 | * Definitions for SMTC multitasking on MIPS MT cores |
| 6 | */ |
| 7 | |
| 8 | #include <asm/mips_mt.h> |
| 9 | |
| 10 | /* |
| 11 | * System-wide SMTC status information |
| 12 | */ |
| 13 | |
| 14 | extern unsigned int smtc_status; |
| 15 | |
| 16 | #define SMTC_TLB_SHARED 0x00000001 |
| 17 | #define SMTC_MTC_ACTIVE 0x00000002 |
| 18 | |
| 19 | /* |
| 20 | * TLB/ASID Management information |
| 21 | */ |
| 22 | |
| 23 | #define MAX_SMTC_TLBS 2 |
| 24 | #define MAX_SMTC_ASIDS 256 |
| 25 | #if NR_CPUS <= 8 |
| 26 | typedef char asiduse; |
| 27 | #else |
| 28 | #if NR_CPUS <= 16 |
| 29 | typedef short asiduse; |
| 30 | #else |
| 31 | typedef long asiduse; |
| 32 | #endif |
| 33 | #endif |
| 34 | |
| 35 | extern asiduse smtc_live_asid[MAX_SMTC_TLBS][MAX_SMTC_ASIDS]; |
| 36 | |
| 37 | void smtc_get_new_mmu_context(struct mm_struct *mm, unsigned long cpu); |
| 38 | |
| 39 | void smtc_flush_tlb_asid(unsigned long asid); |
| 40 | extern int mipsmt_build_cpu_map(int startslot); |
| 41 | extern void mipsmt_prepare_cpus(void); |
| 42 | extern void smtc_smp_finish(void); |
| 43 | extern void smtc_boot_secondary(int cpu, struct task_struct *t); |
| 44 | |
| 45 | /* |
| 46 | * Sharing the TLB between multiple VPEs means that the |
| 47 | * "random" index selection function is not allowed to |
| 48 | * select the current value of the Index register. To |
| 49 | * avoid additional TLB pressure, the Index registers |
| 50 | * are "parked" with an non-Valid value. |
| 51 | */ |
| 52 | |
| 53 | #define PARKED_INDEX ((unsigned int)0x80000000) |
| 54 | |
| 55 | #endif /* _ASM_SMTC_MT_H */ |