Alexander Shiyan | 4090635 | 2014-04-12 09:29:05 +0400 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru> |
| 3 | * |
| 4 | * The code contained herein is licensed under the GNU General Public |
| 5 | * License. You may obtain a copy of the GNU General Public License |
| 6 | * Version 2 or later at the following locations: |
| 7 | * |
| 8 | * http://www.opensource.org/licenses/gpl-license.html |
| 9 | * http://www.gnu.org/copyleft/gpl.html |
| 10 | */ |
| 11 | |
| 12 | /dts-v1/; |
| 13 | #include "imx51.dtsi" |
| 14 | |
| 15 | / { |
| 16 | model = "Digi ConnectCore CC(W)-MX51"; |
| 17 | compatible = "digi,connectcore-ccxmx51-som", "fsl,imx51"; |
| 18 | |
| 19 | memory { |
| 20 | reg = <0x90000000 0x08000000>; |
| 21 | }; |
| 22 | }; |
| 23 | |
| 24 | &ecspi1 { |
| 25 | pinctrl-names = "default"; |
| 26 | pinctrl-0 = <&pinctrl_ecspi1>; |
| 27 | fsl,spi-num-chipselects = <1>; |
| 28 | cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>; |
| 29 | status = "okay"; |
| 30 | |
| 31 | pmic: mc13892@0 { |
| 32 | pinctrl-names = "default"; |
| 33 | pinctrl-0 = <&pinctrl_mc13892>; |
| 34 | compatible = "fsl,mc13892"; |
| 35 | spi-max-frequency = <16000000>; |
| 36 | spi-cs-high; |
| 37 | reg = <0>; |
| 38 | interrupt-parent = <&gpio1>; |
| 39 | interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; |
| 40 | fsl,mc13xxx-uses-rtc; |
| 41 | |
| 42 | regulators { |
| 43 | sw1_reg: sw1 { |
| 44 | regulator-min-microvolt = <1000000>; |
| 45 | regulator-max-microvolt = <1100000>; |
| 46 | regulator-boot-on; |
| 47 | regulator-always-on; |
| 48 | }; |
| 49 | |
| 50 | sw2_reg: sw2 { |
| 51 | regulator-min-microvolt = <1225000>; |
| 52 | regulator-max-microvolt = <1225000>; |
| 53 | regulator-boot-on; |
| 54 | regulator-always-on; |
| 55 | }; |
| 56 | |
| 57 | sw3_reg: sw3 { |
| 58 | regulator-min-microvolt = <1200000>; |
| 59 | regulator-max-microvolt = <1200000>; |
| 60 | regulator-boot-on; |
| 61 | regulator-always-on; |
| 62 | }; |
| 63 | |
| 64 | swbst_reg: swbst { }; |
| 65 | |
| 66 | viohi_reg: viohi { |
| 67 | regulator-always-on; |
| 68 | }; |
| 69 | |
| 70 | vpll_reg: vpll { |
| 71 | regulator-min-microvolt = <1800000>; |
| 72 | regulator-max-microvolt = <1800000>; |
| 73 | regulator-always-on; |
| 74 | }; |
| 75 | |
| 76 | vdig_reg: vdig { |
| 77 | regulator-min-microvolt = <1250000>; |
| 78 | regulator-max-microvolt = <1250000>; |
| 79 | regulator-always-on; |
| 80 | }; |
| 81 | |
| 82 | vsd_reg: vsd { |
| 83 | regulator-min-microvolt = <3150000>; |
| 84 | regulator-max-microvolt = <3150000>; |
| 85 | regulator-always-on; |
| 86 | }; |
| 87 | |
| 88 | vusb2_reg: vusb2 { |
| 89 | regulator-min-microvolt = <2600000>; |
| 90 | regulator-max-microvolt = <2600000>; |
| 91 | regulator-always-on; |
| 92 | }; |
| 93 | |
| 94 | vvideo_reg: vvideo { |
| 95 | regulator-min-microvolt = <2775000>; |
| 96 | regulator-max-microvolt = <2775000>; |
| 97 | regulator-always-on; |
| 98 | }; |
| 99 | |
| 100 | vaudio_reg: vaudio { |
| 101 | regulator-min-microvolt = <3000000>; |
| 102 | regulator-max-microvolt = <3000000>; |
| 103 | regulator-always-on; |
| 104 | }; |
| 105 | |
| 106 | vcam_reg: vcam { |
| 107 | regulator-min-microvolt = <2750000>; |
| 108 | regulator-max-microvolt = <2750000>; |
| 109 | regulator-always-on; |
| 110 | }; |
| 111 | |
| 112 | vgen1_reg: vgen1 { |
| 113 | regulator-min-microvolt = <1200000>; |
| 114 | regulator-max-microvolt = <1200000>; |
| 115 | regulator-always-on; |
| 116 | }; |
| 117 | |
| 118 | vgen2_reg: vgen2 { |
| 119 | regulator-min-microvolt = <3150000>; |
| 120 | regulator-max-microvolt = <3150000>; |
| 121 | regulator-always-on; |
| 122 | }; |
| 123 | |
| 124 | vgen3_reg: vgen3 { |
| 125 | regulator-min-microvolt = <1800000>; |
| 126 | regulator-max-microvolt = <1800000>; |
| 127 | regulator-always-on; |
| 128 | }; |
| 129 | |
| 130 | vusb_reg: vusb { |
| 131 | regulator-always-on; |
| 132 | }; |
| 133 | |
| 134 | gpo1_reg: gpo1 { }; |
| 135 | |
| 136 | gpo2_reg: gpo2 { }; |
| 137 | |
| 138 | gpo3_reg: gpo3 { }; |
| 139 | |
| 140 | gpo4_reg: gpo4 { }; |
| 141 | |
| 142 | pwgt2spi_reg: pwgt2spi { |
| 143 | regulator-always-on; |
| 144 | }; |
| 145 | |
| 146 | vcoincell_reg: vcoincell { |
| 147 | regulator-min-microvolt = <3000000>; |
| 148 | regulator-max-microvolt = <3000000>; |
| 149 | regulator-always-on; |
| 150 | }; |
| 151 | }; |
| 152 | }; |
| 153 | }; |
| 154 | |
| 155 | &esdhc2 { |
| 156 | pinctrl-names = "default"; |
| 157 | pinctrl-0 = <&pinctrl_esdhc2>; |
| 158 | cap-sdio-irq; |
Sudeep Holla | 26cefdd | 2015-10-21 11:10:08 +0100 | [diff] [blame] | 159 | wakeup-source; |
Alexander Shiyan | 4090635 | 2014-04-12 09:29:05 +0400 | [diff] [blame] | 160 | keep-power-in-suspend; |
| 161 | max-frequency = <50000000>; |
| 162 | no-1-8-v; |
| 163 | non-removable; |
| 164 | vmmc-supply = <&gpo4_reg>; |
| 165 | status = "okay"; |
| 166 | }; |
| 167 | |
| 168 | &fec { |
| 169 | pinctrl-names = "default"; |
| 170 | pinctrl-0 = <&pinctrl_fec>; |
| 171 | phy-mode = "mii"; |
| 172 | phy-supply = <&gpo3_reg>; |
| 173 | /* Pins shared with LCD2, keep status disabled */ |
| 174 | }; |
| 175 | |
| 176 | &i2c2 { |
| 177 | pinctrl-names = "default"; |
| 178 | pinctrl-0 = <&pinctrl_i2c2>; |
| 179 | clock-frequency = <400000>; |
| 180 | status = "okay"; |
| 181 | |
| 182 | mma7455l@1d { |
| 183 | pinctrl-names = "default"; |
| 184 | pinctrl-0 = <&pinctrl_mma7455l>; |
| 185 | compatible = "fsl,mma7455l"; |
| 186 | reg = <0x1d>; |
| 187 | interrupt-parent = <&gpio1>; |
| 188 | interrupts = <7 IRQ_TYPE_LEVEL_HIGH>, <6 IRQ_TYPE_LEVEL_HIGH>; |
| 189 | }; |
| 190 | }; |
| 191 | |
| 192 | &nfc { |
| 193 | pinctrl-names = "default"; |
| 194 | pinctrl-0 = <&pinctrl_nfc>; |
| 195 | nand-bus-width = <8>; |
| 196 | nand-ecc-mode = "hw"; |
| 197 | nand-on-flash-bbt; |
Alexander Shiyan | 4090635 | 2014-04-12 09:29:05 +0400 | [diff] [blame] | 198 | status = "okay"; |
| 199 | }; |
| 200 | |
| 201 | &usbotg { |
| 202 | phy_type = "utmi_wide"; |
| 203 | disable-over-current; |
| 204 | /* Device role is not known, keep status disabled */ |
| 205 | }; |
| 206 | |
| 207 | &weim { |
| 208 | pinctrl-names = "default"; |
| 209 | pinctrl-0 = <&pinctrl_weim>; |
| 210 | status = "okay"; |
| 211 | |
| 212 | lan9221: lan9221@5,0 { |
| 213 | pinctrl-names = "default"; |
| 214 | pinctrl-0 = <&pinctrl_lan9221>; |
| 215 | compatible = "smsc,lan9221", "smsc,lan9115"; |
| 216 | reg = <5 0x00000000 0x1000>; |
| 217 | fsl,weim-cs-timing = < |
| 218 | 0x00420081 0x00000000 |
| 219 | 0x32260000 0x00000000 |
| 220 | 0x72080f00 0x00000000 |
| 221 | >; |
| 222 | clocks = <&clks IMX5_CLK_DUMMY>; |
| 223 | interrupt-parent = <&gpio1>; |
| 224 | interrupts = <9 IRQ_TYPE_LEVEL_LOW>; |
| 225 | phy-mode = "mii"; |
| 226 | reg-io-width = <2>; |
| 227 | smsc,irq-push-pull; |
| 228 | vdd33a-supply = <&gpo2_reg>; |
| 229 | vddvario-supply = <&gpo2_reg>; |
| 230 | }; |
| 231 | }; |
| 232 | |
| 233 | &iomuxc { |
| 234 | imx51-digi-connectcore-som { |
| 235 | pinctrl_ecspi1: ecspi1grp { |
| 236 | fsl,pins = < |
| 237 | MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185 |
| 238 | MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185 |
| 239 | MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185 |
| 240 | MX51_PAD_CSPI1_SS0__GPIO4_24 0x85 /* CS0 */ |
| 241 | >; |
| 242 | }; |
| 243 | |
| 244 | pinctrl_esdhc2: esdhc2grp { |
| 245 | fsl,pins = < |
| 246 | MX51_PAD_SD2_CMD__SD2_CMD 0x400020d5 |
| 247 | MX51_PAD_SD2_CLK__SD2_CLK 0x20d5 |
| 248 | MX51_PAD_SD2_DATA0__SD2_DATA0 0x20d5 |
| 249 | MX51_PAD_SD2_DATA1__SD2_DATA1 0x20d5 |
| 250 | MX51_PAD_SD2_DATA2__SD2_DATA2 0x20d5 |
| 251 | MX51_PAD_SD2_DATA3__SD2_DATA3 0x20d5 |
| 252 | >; |
| 253 | }; |
| 254 | |
| 255 | pinctrl_fec: fecgrp { |
| 256 | fsl,pins = < |
| 257 | MX51_PAD_DI_GP3__FEC_TX_ER 0x80000000 |
| 258 | MX51_PAD_DI2_PIN4__FEC_CRS 0x80000000 |
| 259 | MX51_PAD_DI2_PIN2__FEC_MDC 0x80000000 |
| 260 | MX51_PAD_DI2_PIN3__FEC_MDIO 0x80000000 |
| 261 | MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x80000000 |
| 262 | MX51_PAD_DI_GP4__FEC_RDATA2 0x80000000 |
| 263 | MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x80000000 |
| 264 | MX51_PAD_DISP2_DAT1__FEC_RX_ER 0x80000000 |
| 265 | MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x80000000 |
| 266 | MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x80000000 |
| 267 | MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x80000000 |
| 268 | MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x80000000 |
| 269 | MX51_PAD_DISP2_DAT10__FEC_COL 0x80000000 |
| 270 | MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x80000000 |
| 271 | MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x80000000 |
| 272 | MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x80000000 |
| 273 | MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x80000000 |
| 274 | MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x80000000 |
| 275 | >; |
| 276 | }; |
| 277 | |
| 278 | pinctrl_i2c2: i2c2grp { |
| 279 | fsl,pins = < |
| 280 | MX51_PAD_GPIO1_2__I2C2_SCL 0x400001ed |
| 281 | MX51_PAD_GPIO1_3__I2C2_SDA 0x400001ed |
| 282 | >; |
| 283 | }; |
| 284 | |
| 285 | pinctrl_nfc: nfcgrp { |
| 286 | fsl,pins = < |
| 287 | MX51_PAD_NANDF_D0__NANDF_D0 0x80000000 |
| 288 | MX51_PAD_NANDF_D1__NANDF_D1 0x80000000 |
| 289 | MX51_PAD_NANDF_D2__NANDF_D2 0x80000000 |
| 290 | MX51_PAD_NANDF_D3__NANDF_D3 0x80000000 |
| 291 | MX51_PAD_NANDF_D4__NANDF_D4 0x80000000 |
| 292 | MX51_PAD_NANDF_D5__NANDF_D5 0x80000000 |
| 293 | MX51_PAD_NANDF_D6__NANDF_D6 0x80000000 |
| 294 | MX51_PAD_NANDF_D7__NANDF_D7 0x80000000 |
| 295 | MX51_PAD_NANDF_ALE__NANDF_ALE 0x80000000 |
| 296 | MX51_PAD_NANDF_CLE__NANDF_CLE 0x80000000 |
| 297 | MX51_PAD_NANDF_RE_B__NANDF_RE_B 0x80000000 |
| 298 | MX51_PAD_NANDF_WE_B__NANDF_WE_B 0x80000000 |
| 299 | MX51_PAD_NANDF_WP_B__NANDF_WP_B 0x80000000 |
| 300 | MX51_PAD_NANDF_CS0__NANDF_CS0 0x80000000 |
| 301 | MX51_PAD_NANDF_RB0__NANDF_RB0 0x80000000 |
| 302 | >; |
| 303 | }; |
| 304 | |
| 305 | pinctrl_lan9221: lan9221grp { |
| 306 | fsl,pins = < |
| 307 | MX51_PAD_GPIO1_9__GPIO1_9 0xe5 /* IRQ */ |
| 308 | >; |
| 309 | }; |
| 310 | |
| 311 | pinctrl_mc13892: mc13892grp { |
| 312 | fsl,pins = < |
| 313 | MX51_PAD_GPIO1_5__GPIO1_5 0xe5 /* IRQ */ |
| 314 | >; |
| 315 | }; |
| 316 | |
| 317 | pinctrl_mma7455l: mma7455lgrp { |
| 318 | fsl,pins = < |
| 319 | MX51_PAD_GPIO1_7__GPIO1_7 0xe5 /* IRQ1 */ |
| 320 | MX51_PAD_GPIO1_6__GPIO1_6 0xe5 /* IRQ2 */ |
| 321 | >; |
| 322 | }; |
| 323 | |
| 324 | pinctrl_weim: weimgrp { |
| 325 | fsl,pins = < |
| 326 | MX51_PAD_EIM_DA0__EIM_DA0 0x80000000 |
| 327 | MX51_PAD_EIM_DA1__EIM_DA1 0x80000000 |
| 328 | MX51_PAD_EIM_DA2__EIM_DA2 0x80000000 |
| 329 | MX51_PAD_EIM_DA3__EIM_DA3 0x80000000 |
| 330 | MX51_PAD_EIM_DA4__EIM_DA4 0x80000000 |
| 331 | MX51_PAD_EIM_DA5__EIM_DA5 0x80000000 |
| 332 | MX51_PAD_EIM_DA6__EIM_DA6 0x80000000 |
| 333 | MX51_PAD_EIM_DA7__EIM_DA7 0x80000000 |
| 334 | MX51_PAD_EIM_DA8__EIM_DA8 0x80000000 |
| 335 | MX51_PAD_EIM_DA9__EIM_DA9 0x80000000 |
| 336 | MX51_PAD_EIM_DA10__EIM_DA10 0x80000000 |
| 337 | MX51_PAD_EIM_DA11__EIM_DA11 0x80000000 |
| 338 | MX51_PAD_EIM_DA12__EIM_DA12 0x80000000 |
| 339 | MX51_PAD_EIM_DA13__EIM_DA13 0x80000000 |
| 340 | MX51_PAD_EIM_DA14__EIM_DA14 0x80000000 |
| 341 | MX51_PAD_EIM_DA15__EIM_DA15 0x80000000 |
| 342 | MX51_PAD_EIM_A16__EIM_A16 0x80000000 |
| 343 | MX51_PAD_EIM_A17__EIM_A17 0x80000000 |
| 344 | MX51_PAD_EIM_A18__EIM_A18 0x80000000 |
| 345 | MX51_PAD_EIM_A19__EIM_A19 0x80000000 |
| 346 | MX51_PAD_EIM_A20__EIM_A20 0x80000000 |
| 347 | MX51_PAD_EIM_A21__EIM_A21 0x80000000 |
| 348 | MX51_PAD_EIM_A22__EIM_A22 0x80000000 |
| 349 | MX51_PAD_EIM_A23__EIM_A23 0x80000000 |
| 350 | MX51_PAD_EIM_A24__EIM_A24 0x80000000 |
| 351 | MX51_PAD_EIM_A25__EIM_A25 0x80000000 |
| 352 | MX51_PAD_EIM_A26__EIM_A26 0x80000000 |
| 353 | MX51_PAD_EIM_A27__EIM_A27 0x80000000 |
| 354 | MX51_PAD_EIM_D16__EIM_D16 0x80000000 |
| 355 | MX51_PAD_EIM_D17__EIM_D17 0x80000000 |
| 356 | MX51_PAD_EIM_D18__EIM_D18 0x80000000 |
| 357 | MX51_PAD_EIM_D19__EIM_D19 0x80000000 |
| 358 | MX51_PAD_EIM_D20__EIM_D20 0x80000000 |
| 359 | MX51_PAD_EIM_D21__EIM_D21 0x80000000 |
| 360 | MX51_PAD_EIM_D22__EIM_D22 0x80000000 |
| 361 | MX51_PAD_EIM_D23__EIM_D23 0x80000000 |
| 362 | MX51_PAD_EIM_D24__EIM_D24 0x80000000 |
| 363 | MX51_PAD_EIM_D25__EIM_D25 0x80000000 |
| 364 | MX51_PAD_EIM_D26__EIM_D26 0x80000000 |
| 365 | MX51_PAD_EIM_D27__EIM_D27 0x80000000 |
| 366 | MX51_PAD_EIM_D28__EIM_D28 0x80000000 |
| 367 | MX51_PAD_EIM_D29__EIM_D29 0x80000000 |
| 368 | MX51_PAD_EIM_D30__EIM_D30 0x80000000 |
| 369 | MX51_PAD_EIM_D31__EIM_D31 0x80000000 |
| 370 | MX51_PAD_EIM_OE__EIM_OE 0x80000000 |
| 371 | MX51_PAD_EIM_DTACK__EIM_DTACK 0x80000000 |
| 372 | MX51_PAD_EIM_LBA__EIM_LBA 0x80000000 |
| 373 | MX51_PAD_EIM_CS5__EIM_CS5 0x80000000 /* CS5 */ |
| 374 | >; |
| 375 | }; |
| 376 | }; |
| 377 | }; |