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Maxime Ripardd3ae0782013-06-09 10:40:53 +02001/*
2 * Copyright 2013 Maxime Ripard
3 *
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
5 *
Maxime Ripard1d86b4b2014-09-02 19:25:26 +02006 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
9 * whole.
Maxime Ripardd3ae0782013-06-09 10:40:53 +020010 *
Maxime Ripard1d86b4b2014-09-02 19:25:26 +020011 * a) This library is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
15 *
16 * This library is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
Maxime Ripard1d86b4b2014-09-02 19:25:26 +020021 * Or, alternatively,
22 *
23 * b) Permission is hereby granted, free of charge, to any person
24 * obtaining a copy of this software and associated documentation
25 * files (the "Software"), to deal in the Software without
26 * restriction, including without limitation the rights to use,
27 * copy, modify, merge, publish, distribute, sublicense, and/or
28 * sell copies of the Software, and to permit persons to whom the
29 * Software is furnished to do so, subject to the following
30 * conditions:
31 *
32 * The above copyright notice and this permission notice shall be
33 * included in all copies or substantial portions of the Software.
34 *
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42 * OTHER DEALINGS IN THE SOFTWARE.
Maxime Ripardd3ae0782013-06-09 10:40:53 +020043 */
44
Maxime Ripard71455702014-12-16 22:59:54 +010045#include "skeleton.dtsi"
Maxime Ripardd3ae0782013-06-09 10:40:53 +020046
Maxime Ripard903b2d72015-01-30 16:42:13 +010047#include "sun5i.dtsi"
48
Maxime Ripard1f9f6a72014-12-16 22:59:56 +010049#include <dt-bindings/dma/sun4i-a10.h>
Maxime Ripard092a0c32014-12-16 22:59:57 +010050#include <dt-bindings/pinctrl/sun4i-a10.h>
Maxime Ripardd3ae0782013-06-09 10:40:53 +020051
52/ {
53 interrupt-parent = <&intc>;
54
Emilio Lópeze751cce2013-11-16 15:17:29 -030055 aliases {
56 ethernet0 = &emac;
57 };
58
Hans de Goeded5018412014-11-14 16:34:35 +010059 chosen {
60 #address-cells = <1>;
61 #size-cells = <1>;
62 ranges;
63
Hans de Goedea9f8cda2014-11-18 12:07:13 +010064 framebuffer@0 {
Maxime Ripardd8cacaa2015-05-03 11:53:07 +020065 compatible = "allwinner,simple-framebuffer",
66 "simple-framebuffer";
Hans de Goedea9f8cda2014-11-18 12:07:13 +010067 allwinner,pipeline = "de_be0-lcd0-hdmi";
Hans de Goedeb3b630b2016-06-20 22:57:22 +020068 clocks = <&pll3>, <&pll5 1>, <&ahb_gates 36>,
69 <&ahb_gates 43>, <&ahb_gates 44>;
Hans de Goeded5018412014-11-14 16:34:35 +010070 status = "disabled";
71 };
Hans de Goedefd18c7e2015-01-19 14:05:12 +010072
73 framebuffer@1 {
74 compatible = "allwinner,simple-framebuffer",
75 "simple-framebuffer";
76 allwinner,pipeline = "de_be0-lcd0";
Hans de Goedeb3b630b2016-06-20 22:57:22 +020077 clocks = <&pll3>, <&pll5 1>, <&ahb_gates 36>,
78 <&ahb_gates 44>;
Hans de Goedefd18c7e2015-01-19 14:05:12 +010079 status = "disabled";
80 };
Hans de Goedeaf283532015-08-14 16:44:32 +020081
82 framebuffer@2 {
83 compatible = "allwinner,simple-framebuffer",
84 "simple-framebuffer";
85 allwinner,pipeline = "de_be0-lcd0-tve0";
Hans de Goedeb3b630b2016-06-20 22:57:22 +020086 clocks = <&pll3>, <&pll5 1>, <&ahb_gates 34>,
87 <&ahb_gates 36>, <&ahb_gates 44>;
Hans de Goedeaf283532015-08-14 16:44:32 +020088 status = "disabled";
89 };
Hans de Goeded5018412014-11-14 16:34:35 +010090 };
91
Maxime Ripardd3ae0782013-06-09 10:40:53 +020092 clocks {
Chen-Yu Tsai3dce8322014-02-03 09:51:42 +080093 ahb_gates: clk@01c20060 {
Maxime Ripardd3ae0782013-06-09 10:40:53 +020094 #clock-cells = <1>;
Maxime Ripard29bb8052013-07-16 11:28:58 +020095 compatible = "allwinner,sun5i-a10s-ahb-gates-clk";
Maxime Ripardd3ae0782013-06-09 10:40:53 +020096 reg = <0x01c20060 0x8>;
97 clocks = <&ahb>;
Maxime Riparddd4de432015-07-31 19:46:17 +020098 clock-indices = <0>, <1>,
99 <2>, <5>, <6>,
100 <7>, <8>, <9>,
101 <10>, <13>,
102 <14>, <17>, <18>,
103 <20>, <21>, <22>,
104 <26>, <28>, <32>,
105 <34>, <36>, <40>,
106 <43>, <44>,
107 <46>, <51>,
108 <52>;
Maxime Ripardd8cacaa2015-05-03 11:53:07 +0200109 clock-output-names = "ahb_usbotg", "ahb_ehci",
110 "ahb_ohci", "ahb_ss", "ahb_dma",
111 "ahb_bist", "ahb_mmc0", "ahb_mmc1",
112 "ahb_mmc2", "ahb_nand",
113 "ahb_sdram", "ahb_emac", "ahb_ts",
114 "ahb_spi0", "ahb_spi1", "ahb_spi2",
115 "ahb_gps", "ahb_stimer", "ahb_ve",
116 "ahb_tve", "ahb_lcd", "ahb_csi",
117 "ahb_hdmi", "ahb_de_be",
118 "ahb_de_fe", "ahb_iep",
119 "ahb_mali400";
Maxime Ripardd3ae0782013-06-09 10:40:53 +0200120 };
121
Chen-Yu Tsai3dce8322014-02-03 09:51:42 +0800122 apb0_gates: clk@01c20068 {
Maxime Ripardd3ae0782013-06-09 10:40:53 +0200123 #clock-cells = <1>;
Maxime Ripard29bb8052013-07-16 11:28:58 +0200124 compatible = "allwinner,sun5i-a10s-apb0-gates-clk";
Maxime Ripardd3ae0782013-06-09 10:40:53 +0200125 reg = <0x01c20068 0x4>;
126 clocks = <&apb0>;
Maxime Riparddd4de432015-07-31 19:46:17 +0200127 clock-indices = <0>, <3>,
128 <5>, <6>,
129 <10>;
Maxime Ripardd8cacaa2015-05-03 11:53:07 +0200130 clock-output-names = "apb0_codec", "apb0_iis",
131 "apb0_pio", "apb0_ir",
132 "apb0_keypad";
Maxime Ripardd3ae0782013-06-09 10:40:53 +0200133 };
134
Chen-Yu Tsai3dce8322014-02-03 09:51:42 +0800135 apb1_gates: clk@01c2006c {
Maxime Ripardd3ae0782013-06-09 10:40:53 +0200136 #clock-cells = <1>;
Maxime Ripard29bb8052013-07-16 11:28:58 +0200137 compatible = "allwinner,sun5i-a10s-apb1-gates-clk";
Maxime Ripardd3ae0782013-06-09 10:40:53 +0200138 reg = <0x01c2006c 0x4>;
139 clocks = <&apb1>;
Maxime Riparddd4de432015-07-31 19:46:17 +0200140 clock-indices = <0>, <1>,
141 <2>, <16>,
142 <17>, <18>,
143 <19>;
Maxime Ripardd3ae0782013-06-09 10:40:53 +0200144 clock-output-names = "apb1_i2c0", "apb1_i2c1",
Maxime Riparddd4de432015-07-31 19:46:17 +0200145 "apb1_i2c2", "apb1_uart0",
146 "apb1_uart1", "apb1_uart2",
147 "apb1_uart3";
Maxime Ripardd3ae0782013-06-09 10:40:53 +0200148 };
149 };
150
Maxime Ripard9e199292013-08-03 16:07:36 +0200151 soc@01c00000 {
Maxime Ripardd3ae0782013-06-09 10:40:53 +0200152 emac: ethernet@01c0b000 {
Maxime Ripard1c70e092014-02-02 14:49:13 +0100153 compatible = "allwinner,sun4i-a10-emac";
Maxime Ripardd3ae0782013-06-09 10:40:53 +0200154 reg = <0x01c0b000 0x1000>;
155 interrupts = <55>;
156 clocks = <&ahb_gates 17>;
Maxime Ripard00f69ba2015-03-26 15:53:44 +0100157 allwinner,sram = <&emac_sram 1>;
Maxime Ripardd3ae0782013-06-09 10:40:53 +0200158 status = "disabled";
159 };
160
Aleksei Mamlin92395f52015-01-19 22:35:22 +0300161 mdio: mdio@01c0b080 {
Maxime Ripard1c70e092014-02-02 14:49:13 +0100162 compatible = "allwinner,sun4i-a10-mdio";
Maxime Ripardd3ae0782013-06-09 10:40:53 +0200163 reg = <0x01c0b080 0x14>;
164 status = "disabled";
165 #address-cells = <1>;
166 #size-cells = <0>;
167 };
168
Hans de Goede51763bd2015-10-11 11:55:05 +0200169 pwm: pwm@01c20e00 {
170 compatible = "allwinner,sun5i-a10s-pwm";
171 reg = <0x01c20e00 0xc>;
172 clocks = <&osc24M>;
173 #pwm-cells = <3>;
174 status = "disabled";
175 };
176
Maxime Ripardd3ae0782013-06-09 10:40:53 +0200177 uart0: serial@01c28000 {
178 compatible = "snps,dw-apb-uart";
179 reg = <0x01c28000 0x400>;
180 interrupts = <1>;
181 reg-shift = <2>;
182 reg-io-width = <4>;
183 clocks = <&apb1_gates 16>;
184 status = "disabled";
185 };
186
Maxime Ripardd3ae0782013-06-09 10:40:53 +0200187 uart2: serial@01c28800 {
188 compatible = "snps,dw-apb-uart";
189 reg = <0x01c28800 0x400>;
190 interrupts = <3>;
191 reg-shift = <2>;
192 reg-io-width = <4>;
193 clocks = <&apb1_gates 18>;
194 status = "disabled";
195 };
Maxime Ripard903b2d72015-01-30 16:42:13 +0100196 };
197};
Maxime Ripardd3ae0782013-06-09 10:40:53 +0200198
Maxime Ripard903b2d72015-01-30 16:42:13 +0100199&pio {
200 compatible = "allwinner,sun5i-a10s-pinctrl";
Emilio Lópezca3d4ed2013-07-07 18:31:57 -0300201
Maxime Ripard903b2d72015-01-30 16:42:13 +0100202 uart0_pins_a: uart0@0 {
203 allwinner,pins = "PB19", "PB20";
204 allwinner,function = "uart0";
205 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
206 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
207 };
Maxime Ripardf2b50022013-11-07 12:01:48 +0100208
Maxime Ripard903b2d72015-01-30 16:42:13 +0100209 uart2_pins_a: uart2@0 {
210 allwinner,pins = "PC18", "PC19";
211 allwinner,function = "uart2";
212 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
213 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
214 };
215
Maxime Ripard903b2d72015-01-30 16:42:13 +0100216 emac_pins_a: emac0@0 {
217 allwinner,pins = "PA0", "PA1", "PA2",
218 "PA3", "PA4", "PA5", "PA6",
219 "PA7", "PA8", "PA9", "PA10",
220 "PA11", "PA12", "PA13", "PA14",
221 "PA15", "PA16";
222 allwinner,function = "emac";
223 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
224 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
225 };
226
Jelle van der Waabea9b7b2015-09-10 15:05:58 +0200227 emac_pins_b: emac0@1 {
228 allwinner,pins = "PD6", "PD7", "PD10",
229 "PD11", "PD12", "PD13", "PD14",
230 "PD15", "PD18", "PD19", "PD20",
231 "PD21", "PD22", "PD23", "PD24",
232 "PD25", "PD26", "PD27";
233 allwinner,function = "emac";
234 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
235 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
236 };
237
Maxime Ripard903b2d72015-01-30 16:42:13 +0100238 mmc1_pins_a: mmc1@0 {
Maxime Ripardd8cacaa2015-05-03 11:53:07 +0200239 allwinner,pins = "PG3", "PG4", "PG5",
240 "PG6", "PG7", "PG8";
Maxime Ripard903b2d72015-01-30 16:42:13 +0100241 allwinner,function = "mmc1";
242 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
243 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
Maxime Ripardd3ae0782013-06-09 10:40:53 +0200244 };
Michal Suchanek5c7b7452016-05-26 19:25:22 +0000245
246 spi2_pins_a: spi2@0 {
247 allwinner,pins = "PB12", "PB13", "PB14";
248 allwinner,function = "spi2";
249 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
250 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
251 };
252
253 spi2_cs0_pins_a: spi2_cs0@0 {
254 allwinner,pins = "PB11";
255 allwinner,function = "spi2";
256 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
257 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
258 };
Maxime Ripardd3ae0782013-06-09 10:40:53 +0200259};
Maxime Ripard00f69ba2015-03-26 15:53:44 +0100260
261&sram_a {
262 emac_sram: sram-section@8000 {
263 compatible = "allwinner,sun4i-a10-sram-a3-a4";
264 reg = <0x8000 0x4000>;
265 status = "disabled";
266 };
267};