Mathias Nyman | a5d811b | 2013-06-18 14:33:02 +0300 | [diff] [blame] | 1 | /* |
| 2 | * Pinctrl GPIO driver for Intel Baytrail |
| 3 | * Copyright (c) 2012-2013, Intel Corporation. |
| 4 | * |
| 5 | * Author: Mathias Nyman <mathias.nyman@linux.intel.com> |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify it |
| 8 | * under the terms and conditions of the GNU General Public License, |
| 9 | * version 2, as published by the Free Software Foundation. |
| 10 | * |
| 11 | * This program is distributed in the hope it will be useful, but WITHOUT |
| 12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 14 | * more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License along with |
| 17 | * this program; if not, write to the Free Software Foundation, Inc., |
| 18 | * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. |
| 19 | * |
| 20 | */ |
| 21 | |
| 22 | #include <linux/kernel.h> |
| 23 | #include <linux/module.h> |
| 24 | #include <linux/init.h> |
| 25 | #include <linux/types.h> |
| 26 | #include <linux/bitops.h> |
| 27 | #include <linux/interrupt.h> |
| 28 | #include <linux/irq.h> |
| 29 | #include <linux/gpio.h> |
| 30 | #include <linux/irqdomain.h> |
| 31 | #include <linux/acpi.h> |
| 32 | #include <linux/acpi_gpio.h> |
| 33 | #include <linux/platform_device.h> |
| 34 | #include <linux/seq_file.h> |
| 35 | #include <linux/io.h> |
| 36 | #include <linux/pm_runtime.h> |
| 37 | #include <linux/pinctrl/pinctrl.h> |
| 38 | |
| 39 | /* memory mapped register offsets */ |
| 40 | #define BYT_CONF0_REG 0x000 |
| 41 | #define BYT_CONF1_REG 0x004 |
| 42 | #define BYT_VAL_REG 0x008 |
| 43 | #define BYT_DFT_REG 0x00c |
| 44 | #define BYT_INT_STAT_REG 0x800 |
| 45 | |
| 46 | /* BYT_CONF0_REG register bits */ |
| 47 | #define BYT_TRIG_NEG BIT(26) |
| 48 | #define BYT_TRIG_POS BIT(25) |
| 49 | #define BYT_TRIG_LVL BIT(24) |
| 50 | #define BYT_PIN_MUX 0x07 |
| 51 | |
| 52 | /* BYT_VAL_REG register bits */ |
| 53 | #define BYT_INPUT_EN BIT(2) /* 0: input enabled (active low)*/ |
| 54 | #define BYT_OUTPUT_EN BIT(1) /* 0: output enabled (active low)*/ |
| 55 | #define BYT_LEVEL BIT(0) |
| 56 | |
| 57 | #define BYT_DIR_MASK (BIT(1) | BIT(2)) |
| 58 | #define BYT_TRIG_MASK (BIT(26) | BIT(25) | BIT(24)) |
| 59 | |
| 60 | #define BYT_NGPIO_SCORE 102 |
| 61 | #define BYT_NGPIO_NCORE 28 |
| 62 | #define BYT_NGPIO_SUS 44 |
| 63 | |
| 64 | /* |
| 65 | * Baytrail gpio controller consist of three separate sub-controllers called |
| 66 | * SCORE, NCORE and SUS. The sub-controllers are identified by their acpi UID. |
| 67 | * |
| 68 | * GPIO numbering is _not_ ordered meaning that gpio # 0 in ACPI namespace does |
| 69 | * _not_ correspond to the first gpio register at controller's gpio base. |
| 70 | * There is no logic or pattern in mapping gpio numbers to registers (pads) so |
| 71 | * each sub-controller needs to have its own mapping table |
| 72 | */ |
| 73 | |
| 74 | /* score_pins[gpio_nr] = pad_nr */ |
| 75 | |
| 76 | static unsigned const score_pins[BYT_NGPIO_SCORE] = { |
| 77 | 85, 89, 93, 96, 99, 102, 98, 101, 34, 37, |
| 78 | 36, 38, 39, 35, 40, 84, 62, 61, 64, 59, |
| 79 | 54, 56, 60, 55, 63, 57, 51, 50, 53, 47, |
| 80 | 52, 49, 48, 43, 46, 41, 45, 42, 58, 44, |
| 81 | 95, 105, 70, 68, 67, 66, 69, 71, 65, 72, |
| 82 | 86, 90, 88, 92, 103, 77, 79, 83, 78, 81, |
| 83 | 80, 82, 13, 12, 15, 14, 17, 18, 19, 16, |
| 84 | 2, 1, 0, 4, 6, 7, 9, 8, 33, 32, |
| 85 | 31, 30, 29, 27, 25, 28, 26, 23, 21, 20, |
| 86 | 24, 22, 5, 3, 10, 11, 106, 87, 91, 104, |
| 87 | 97, 100, |
| 88 | }; |
| 89 | |
| 90 | static unsigned const ncore_pins[BYT_NGPIO_NCORE] = { |
| 91 | 19, 18, 17, 20, 21, 22, 24, 25, 23, 16, |
| 92 | 14, 15, 12, 26, 27, 1, 4, 8, 11, 0, |
| 93 | 3, 6, 10, 13, 2, 5, 9, 7, |
| 94 | }; |
| 95 | |
| 96 | static unsigned const sus_pins[BYT_NGPIO_SUS] = { |
| 97 | 29, 33, 30, 31, 32, 34, 36, 35, 38, 37, |
| 98 | 18, 7, 11, 20, 17, 1, 8, 10, 19, 12, |
| 99 | 0, 2, 23, 39, 28, 27, 22, 21, 24, 25, |
| 100 | 26, 51, 56, 54, 49, 55, 48, 57, 50, 58, |
| 101 | 52, 53, 59, 40, |
| 102 | }; |
| 103 | |
| 104 | static struct pinctrl_gpio_range byt_ranges[] = { |
| 105 | { |
| 106 | .name = "1", /* match with acpi _UID in probe */ |
| 107 | .npins = BYT_NGPIO_SCORE, |
| 108 | .pins = score_pins, |
| 109 | }, |
| 110 | { |
| 111 | .name = "2", |
| 112 | .npins = BYT_NGPIO_NCORE, |
| 113 | .pins = ncore_pins, |
| 114 | }, |
| 115 | { |
| 116 | .name = "3", |
| 117 | .npins = BYT_NGPIO_SUS, |
| 118 | .pins = sus_pins, |
| 119 | }, |
| 120 | { |
| 121 | }, |
| 122 | }; |
| 123 | |
| 124 | struct byt_gpio { |
| 125 | struct gpio_chip chip; |
| 126 | struct irq_domain *domain; |
| 127 | struct platform_device *pdev; |
| 128 | spinlock_t lock; |
| 129 | void __iomem *reg_base; |
| 130 | struct pinctrl_gpio_range *range; |
| 131 | }; |
| 132 | |
| 133 | static void __iomem *byt_gpio_reg(struct gpio_chip *chip, unsigned offset, |
| 134 | int reg) |
| 135 | { |
| 136 | struct byt_gpio *vg = container_of(chip, struct byt_gpio, chip); |
| 137 | u32 reg_offset; |
Mathias Nyman | a5d811b | 2013-06-18 14:33:02 +0300 | [diff] [blame] | 138 | |
| 139 | if (reg == BYT_INT_STAT_REG) |
| 140 | reg_offset = (offset / 32) * 4; |
| 141 | else |
| 142 | reg_offset = vg->range->pins[offset] * 16; |
| 143 | |
Andy Shevchenko | 9c5b655 | 2013-07-10 14:55:38 +0300 | [diff] [blame^] | 144 | return vg->reg_base + reg_offset + reg; |
Mathias Nyman | a5d811b | 2013-06-18 14:33:02 +0300 | [diff] [blame] | 145 | } |
| 146 | |
| 147 | static int byt_gpio_request(struct gpio_chip *chip, unsigned offset) |
| 148 | { |
| 149 | struct byt_gpio *vg = container_of(chip, struct byt_gpio, chip); |
| 150 | |
| 151 | pm_runtime_get(&vg->pdev->dev); |
| 152 | |
| 153 | return 0; |
| 154 | } |
| 155 | |
| 156 | static void byt_gpio_free(struct gpio_chip *chip, unsigned offset) |
| 157 | { |
| 158 | struct byt_gpio *vg = container_of(chip, struct byt_gpio, chip); |
| 159 | void __iomem *reg = byt_gpio_reg(&vg->chip, offset, BYT_CONF0_REG); |
| 160 | u32 value; |
| 161 | |
| 162 | /* clear interrupt triggering */ |
| 163 | value = readl(reg); |
| 164 | value &= ~(BYT_TRIG_POS | BYT_TRIG_NEG | BYT_TRIG_LVL); |
| 165 | writel(value, reg); |
| 166 | |
| 167 | pm_runtime_put(&vg->pdev->dev); |
| 168 | } |
| 169 | |
| 170 | static int byt_irq_type(struct irq_data *d, unsigned type) |
| 171 | { |
| 172 | struct byt_gpio *vg = irq_data_get_irq_chip_data(d); |
| 173 | u32 offset = irqd_to_hwirq(d); |
| 174 | u32 value; |
| 175 | unsigned long flags; |
| 176 | void __iomem *reg = byt_gpio_reg(&vg->chip, offset, BYT_CONF0_REG); |
| 177 | |
| 178 | if (offset >= vg->chip.ngpio) |
| 179 | return -EINVAL; |
| 180 | |
| 181 | spin_lock_irqsave(&vg->lock, flags); |
| 182 | value = readl(reg); |
| 183 | |
| 184 | /* For level trigges the BYT_TRIG_POS and BYT_TRIG_NEG bits |
| 185 | * are used to indicate high and low level triggering |
| 186 | */ |
| 187 | value &= ~(BYT_TRIG_POS | BYT_TRIG_NEG | BYT_TRIG_LVL); |
| 188 | |
| 189 | switch (type) { |
| 190 | case IRQ_TYPE_LEVEL_HIGH: |
| 191 | value |= BYT_TRIG_LVL; |
| 192 | case IRQ_TYPE_EDGE_RISING: |
| 193 | value |= BYT_TRIG_POS; |
| 194 | break; |
| 195 | case IRQ_TYPE_LEVEL_LOW: |
| 196 | value |= BYT_TRIG_LVL; |
| 197 | case IRQ_TYPE_EDGE_FALLING: |
| 198 | value |= BYT_TRIG_NEG; |
| 199 | break; |
| 200 | case IRQ_TYPE_EDGE_BOTH: |
| 201 | value |= (BYT_TRIG_NEG | BYT_TRIG_POS); |
| 202 | break; |
| 203 | } |
| 204 | writel(value, reg); |
| 205 | |
| 206 | spin_unlock_irqrestore(&vg->lock, flags); |
| 207 | |
| 208 | return 0; |
| 209 | } |
| 210 | |
| 211 | static int byt_gpio_get(struct gpio_chip *chip, unsigned offset) |
| 212 | { |
| 213 | void __iomem *reg = byt_gpio_reg(chip, offset, BYT_VAL_REG); |
| 214 | return readl(reg) & BYT_LEVEL; |
| 215 | } |
| 216 | |
| 217 | static void byt_gpio_set(struct gpio_chip *chip, unsigned offset, int value) |
| 218 | { |
| 219 | struct byt_gpio *vg = container_of(chip, struct byt_gpio, chip); |
| 220 | void __iomem *reg = byt_gpio_reg(chip, offset, BYT_VAL_REG); |
| 221 | unsigned long flags; |
| 222 | u32 old_val; |
| 223 | |
| 224 | spin_lock_irqsave(&vg->lock, flags); |
| 225 | |
| 226 | old_val = readl(reg); |
| 227 | |
| 228 | if (value) |
| 229 | writel(old_val | BYT_LEVEL, reg); |
| 230 | else |
| 231 | writel(old_val & ~BYT_LEVEL, reg); |
| 232 | |
| 233 | spin_unlock_irqrestore(&vg->lock, flags); |
| 234 | } |
| 235 | |
| 236 | static int byt_gpio_direction_input(struct gpio_chip *chip, unsigned offset) |
| 237 | { |
| 238 | struct byt_gpio *vg = container_of(chip, struct byt_gpio, chip); |
| 239 | void __iomem *reg = byt_gpio_reg(chip, offset, BYT_VAL_REG); |
| 240 | unsigned long flags; |
| 241 | u32 value; |
| 242 | |
| 243 | spin_lock_irqsave(&vg->lock, flags); |
| 244 | |
| 245 | value = readl(reg) | BYT_DIR_MASK; |
| 246 | value = value & (~BYT_INPUT_EN); /* active low */ |
| 247 | writel(value, reg); |
| 248 | |
| 249 | spin_unlock_irqrestore(&vg->lock, flags); |
| 250 | |
| 251 | return 0; |
| 252 | } |
| 253 | |
| 254 | static int byt_gpio_direction_output(struct gpio_chip *chip, |
| 255 | unsigned gpio, int value) |
| 256 | { |
| 257 | struct byt_gpio *vg = container_of(chip, struct byt_gpio, chip); |
| 258 | void __iomem *reg = byt_gpio_reg(chip, gpio, BYT_VAL_REG); |
| 259 | unsigned long flags; |
| 260 | u32 reg_val; |
| 261 | |
| 262 | spin_lock_irqsave(&vg->lock, flags); |
| 263 | |
| 264 | reg_val = readl(reg) | (BYT_DIR_MASK | !!value); |
| 265 | reg_val &= ~(BYT_OUTPUT_EN | !value); |
| 266 | writel(reg_val, reg); |
| 267 | |
| 268 | spin_unlock_irqrestore(&vg->lock, flags); |
| 269 | |
| 270 | return 0; |
| 271 | } |
| 272 | |
| 273 | static void byt_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) |
| 274 | { |
| 275 | struct byt_gpio *vg = container_of(chip, struct byt_gpio, chip); |
| 276 | int i; |
| 277 | unsigned long flags; |
| 278 | u32 conf0, val, offs; |
| 279 | |
| 280 | spin_lock_irqsave(&vg->lock, flags); |
| 281 | |
| 282 | for (i = 0; i < vg->chip.ngpio; i++) { |
| 283 | offs = vg->range->pins[i] * 16; |
| 284 | conf0 = readl(vg->reg_base + offs + BYT_CONF0_REG); |
| 285 | val = readl(vg->reg_base + offs + BYT_VAL_REG); |
| 286 | |
| 287 | seq_printf(s, |
| 288 | " gpio-%-3d %s %s %s pad-%-3d offset:0x%03x mux:%d %s%s%s\n", |
| 289 | i, |
| 290 | val & BYT_INPUT_EN ? " " : "in", |
| 291 | val & BYT_OUTPUT_EN ? " " : "out", |
| 292 | val & BYT_LEVEL ? "hi" : "lo", |
| 293 | vg->range->pins[i], offs, |
| 294 | conf0 & 0x7, |
Andy Shevchenko | 1583449 | 2013-07-10 16:42:14 +0300 | [diff] [blame] | 295 | conf0 & BYT_TRIG_NEG ? " fall" : "", |
| 296 | conf0 & BYT_TRIG_POS ? " rise" : "", |
| 297 | conf0 & BYT_TRIG_LVL ? " level" : ""); |
Mathias Nyman | a5d811b | 2013-06-18 14:33:02 +0300 | [diff] [blame] | 298 | } |
| 299 | spin_unlock_irqrestore(&vg->lock, flags); |
| 300 | } |
| 301 | |
| 302 | static int byt_gpio_to_irq(struct gpio_chip *chip, unsigned offset) |
| 303 | { |
| 304 | struct byt_gpio *vg = container_of(chip, struct byt_gpio, chip); |
| 305 | return irq_create_mapping(vg->domain, offset); |
| 306 | } |
| 307 | |
| 308 | static void byt_gpio_irq_handler(unsigned irq, struct irq_desc *desc) |
| 309 | { |
| 310 | struct irq_data *data = irq_desc_get_irq_data(desc); |
| 311 | struct byt_gpio *vg = irq_data_get_irq_handler_data(data); |
| 312 | struct irq_chip *chip = irq_data_get_irq_chip(data); |
| 313 | u32 base, pin, mask; |
| 314 | void __iomem *reg; |
| 315 | u32 pending; |
| 316 | unsigned virq; |
| 317 | int looplimit = 0; |
| 318 | |
| 319 | /* check from GPIO controller which pin triggered the interrupt */ |
| 320 | for (base = 0; base < vg->chip.ngpio; base += 32) { |
| 321 | |
| 322 | reg = byt_gpio_reg(&vg->chip, base, BYT_INT_STAT_REG); |
| 323 | |
| 324 | while ((pending = readl(reg))) { |
| 325 | pin = __ffs(pending); |
| 326 | mask = BIT(pin); |
| 327 | /* Clear before handling so we can't lose an edge */ |
| 328 | writel(mask, reg); |
| 329 | |
| 330 | virq = irq_find_mapping(vg->domain, base + pin); |
| 331 | generic_handle_irq(virq); |
| 332 | |
| 333 | /* In case bios or user sets triggering incorretly a pin |
| 334 | * might remain in "interrupt triggered" state. |
| 335 | */ |
| 336 | if (looplimit++ > 32) { |
| 337 | dev_err(&vg->pdev->dev, |
| 338 | "Gpio %d interrupt flood, disabling\n", |
| 339 | base + pin); |
| 340 | |
| 341 | reg = byt_gpio_reg(&vg->chip, base + pin, |
| 342 | BYT_CONF0_REG); |
| 343 | mask = readl(reg); |
| 344 | mask &= ~(BYT_TRIG_NEG | BYT_TRIG_POS | |
| 345 | BYT_TRIG_LVL); |
| 346 | writel(mask, reg); |
| 347 | mask = readl(reg); /* flush */ |
| 348 | break; |
| 349 | } |
| 350 | } |
| 351 | } |
| 352 | chip->irq_eoi(data); |
| 353 | } |
| 354 | |
| 355 | static void byt_irq_unmask(struct irq_data *d) |
| 356 | { |
| 357 | } |
| 358 | |
| 359 | static void byt_irq_mask(struct irq_data *d) |
| 360 | { |
| 361 | } |
| 362 | |
| 363 | static struct irq_chip byt_irqchip = { |
| 364 | .name = "BYT-GPIO", |
| 365 | .irq_mask = byt_irq_mask, |
| 366 | .irq_unmask = byt_irq_unmask, |
| 367 | .irq_set_type = byt_irq_type, |
| 368 | }; |
| 369 | |
| 370 | static void byt_gpio_irq_init_hw(struct byt_gpio *vg) |
| 371 | { |
| 372 | void __iomem *reg; |
| 373 | u32 base, value; |
| 374 | |
| 375 | /* clear interrupt status trigger registers */ |
| 376 | for (base = 0; base < vg->chip.ngpio; base += 32) { |
| 377 | reg = byt_gpio_reg(&vg->chip, base, BYT_INT_STAT_REG); |
| 378 | writel(0xffffffff, reg); |
| 379 | /* make sure trigger bits are cleared, if not then a pin |
| 380 | might be misconfigured in bios */ |
| 381 | value = readl(reg); |
| 382 | if (value) |
| 383 | dev_err(&vg->pdev->dev, |
| 384 | "GPIO interrupt error, pins misconfigured\n"); |
| 385 | } |
| 386 | } |
| 387 | |
| 388 | static int byt_gpio_irq_map(struct irq_domain *d, unsigned int virq, |
| 389 | irq_hw_number_t hw) |
| 390 | { |
| 391 | struct byt_gpio *vg = d->host_data; |
| 392 | |
| 393 | irq_set_chip_and_handler_name(virq, &byt_irqchip, handle_simple_irq, |
| 394 | "demux"); |
| 395 | irq_set_chip_data(virq, vg); |
| 396 | irq_set_irq_type(virq, IRQ_TYPE_NONE); |
| 397 | |
| 398 | return 0; |
| 399 | } |
| 400 | |
| 401 | static const struct irq_domain_ops byt_gpio_irq_ops = { |
| 402 | .map = byt_gpio_irq_map, |
| 403 | }; |
| 404 | |
| 405 | static int byt_gpio_probe(struct platform_device *pdev) |
| 406 | { |
| 407 | struct byt_gpio *vg; |
| 408 | struct gpio_chip *gc; |
| 409 | struct resource *mem_rc, *irq_rc; |
| 410 | struct device *dev = &pdev->dev; |
| 411 | struct acpi_device *acpi_dev; |
| 412 | struct pinctrl_gpio_range *range; |
| 413 | acpi_handle handle = ACPI_HANDLE(dev); |
| 414 | unsigned hwirq; |
| 415 | int ret; |
| 416 | |
| 417 | if (acpi_bus_get_device(handle, &acpi_dev)) |
| 418 | return -ENODEV; |
| 419 | |
| 420 | vg = devm_kzalloc(dev, sizeof(struct byt_gpio), GFP_KERNEL); |
| 421 | if (!vg) { |
| 422 | dev_err(&pdev->dev, "can't allocate byt_gpio chip data\n"); |
| 423 | return -ENOMEM; |
| 424 | } |
| 425 | |
| 426 | for (range = byt_ranges; range->name; range++) { |
| 427 | if (!strcmp(acpi_dev->pnp.unique_id, range->name)) { |
| 428 | vg->chip.ngpio = range->npins; |
| 429 | vg->range = range; |
| 430 | break; |
| 431 | } |
| 432 | } |
| 433 | |
| 434 | if (!vg->chip.ngpio || !vg->range) |
| 435 | return -ENODEV; |
| 436 | |
| 437 | vg->pdev = pdev; |
| 438 | platform_set_drvdata(pdev, vg); |
| 439 | |
| 440 | mem_rc = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 441 | vg->reg_base = devm_ioremap_resource(dev, mem_rc); |
| 442 | if (IS_ERR(vg->reg_base)) |
| 443 | return PTR_ERR(vg->reg_base); |
| 444 | |
| 445 | spin_lock_init(&vg->lock); |
| 446 | |
| 447 | gc = &vg->chip; |
| 448 | gc->label = dev_name(&pdev->dev); |
| 449 | gc->owner = THIS_MODULE; |
| 450 | gc->request = byt_gpio_request; |
| 451 | gc->free = byt_gpio_free; |
| 452 | gc->direction_input = byt_gpio_direction_input; |
| 453 | gc->direction_output = byt_gpio_direction_output; |
| 454 | gc->get = byt_gpio_get; |
| 455 | gc->set = byt_gpio_set; |
| 456 | gc->dbg_show = byt_gpio_dbg_show; |
| 457 | gc->base = -1; |
| 458 | gc->can_sleep = 0; |
| 459 | gc->dev = dev; |
| 460 | |
| 461 | ret = gpiochip_add(gc); |
| 462 | if (ret) { |
| 463 | dev_err(&pdev->dev, "failed adding byt-gpio chip\n"); |
| 464 | return ret; |
| 465 | } |
| 466 | |
| 467 | /* set up interrupts */ |
| 468 | irq_rc = platform_get_resource(pdev, IORESOURCE_IRQ, 0); |
| 469 | if (irq_rc && irq_rc->start) { |
| 470 | hwirq = irq_rc->start; |
| 471 | gc->to_irq = byt_gpio_to_irq; |
| 472 | |
| 473 | vg->domain = irq_domain_add_linear(NULL, gc->ngpio, |
| 474 | &byt_gpio_irq_ops, vg); |
| 475 | if (!vg->domain) |
| 476 | return -ENXIO; |
| 477 | |
| 478 | byt_gpio_irq_init_hw(vg); |
| 479 | |
| 480 | irq_set_handler_data(hwirq, vg); |
| 481 | irq_set_chained_handler(hwirq, byt_gpio_irq_handler); |
| 482 | |
| 483 | /* Register interrupt handlers for gpio signaled acpi events */ |
| 484 | acpi_gpiochip_request_interrupts(gc); |
| 485 | } |
| 486 | |
| 487 | pm_runtime_enable(dev); |
| 488 | |
| 489 | return 0; |
| 490 | } |
| 491 | |
| 492 | static int byt_gpio_runtime_suspend(struct device *dev) |
| 493 | { |
| 494 | return 0; |
| 495 | } |
| 496 | |
| 497 | static int byt_gpio_runtime_resume(struct device *dev) |
| 498 | { |
| 499 | return 0; |
| 500 | } |
| 501 | |
| 502 | static const struct dev_pm_ops byt_gpio_pm_ops = { |
| 503 | .runtime_suspend = byt_gpio_runtime_suspend, |
| 504 | .runtime_resume = byt_gpio_runtime_resume, |
| 505 | }; |
| 506 | |
| 507 | static const struct acpi_device_id byt_gpio_acpi_match[] = { |
| 508 | { "INT33B2", 0 }, |
| 509 | { } |
| 510 | }; |
| 511 | MODULE_DEVICE_TABLE(acpi, byt_gpio_acpi_match); |
| 512 | |
| 513 | static int byt_gpio_remove(struct platform_device *pdev) |
| 514 | { |
| 515 | struct byt_gpio *vg = platform_get_drvdata(pdev); |
| 516 | int err; |
Andy Shevchenko | ec24332 | 2013-07-10 14:55:36 +0300 | [diff] [blame] | 517 | |
Mathias Nyman | a5d811b | 2013-06-18 14:33:02 +0300 | [diff] [blame] | 518 | pm_runtime_disable(&pdev->dev); |
| 519 | err = gpiochip_remove(&vg->chip); |
| 520 | if (err) |
| 521 | dev_warn(&pdev->dev, "failed to remove gpio_chip.\n"); |
| 522 | |
| 523 | return 0; |
| 524 | } |
| 525 | |
| 526 | static struct platform_driver byt_gpio_driver = { |
| 527 | .probe = byt_gpio_probe, |
| 528 | .remove = byt_gpio_remove, |
| 529 | .driver = { |
| 530 | .name = "byt_gpio", |
| 531 | .owner = THIS_MODULE, |
| 532 | .pm = &byt_gpio_pm_ops, |
| 533 | .acpi_match_table = ACPI_PTR(byt_gpio_acpi_match), |
| 534 | }, |
| 535 | }; |
| 536 | |
| 537 | static int __init byt_gpio_init(void) |
| 538 | { |
| 539 | return platform_driver_register(&byt_gpio_driver); |
| 540 | } |
| 541 | |
| 542 | subsys_initcall(byt_gpio_init); |