Juergen Beisert | d0f349f | 2008-07-05 10:02:50 +0200 | [diff] [blame] | 1 | /* |
| 2 | * linux/arch/arm/plat-mxc/time.c |
| 3 | * |
| 4 | * Copyright (C) 2000-2001 Deep Blue Solutions |
| 5 | * Copyright (C) 2002 Shane Nay (shane@minirl.com) |
| 6 | * Copyright (C) 2006-2007 Pavel Pisa (ppisa@pikron.com) |
| 7 | * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de) |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or |
| 10 | * modify it under the terms of the GNU General Public License |
| 11 | * as published by the Free Software Foundation; either version 2 |
| 12 | * of the License, or (at your option) any later version. |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License |
| 19 | * along with this program; if not, write to the Free Software |
| 20 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, |
| 21 | * MA 02110-1301, USA. |
| 22 | */ |
| 23 | |
| 24 | #include <linux/interrupt.h> |
| 25 | #include <linux/irq.h> |
| 26 | #include <linux/clockchips.h> |
| 27 | #include <linux/clk.h> |
Sebastian Andrzej Siewior | 1119c84 | 2014-01-22 12:35:44 +0100 | [diff] [blame] | 28 | #include <linux/delay.h> |
Sascha Hauer | 821dc4d | 2012-03-09 09:29:27 +0100 | [diff] [blame] | 29 | #include <linux/err.h> |
Stephen Boyd | 38ff87f | 2013-06-01 23:39:40 -0700 | [diff] [blame] | 30 | #include <linux/sched_clock.h> |
Shawn Guo | 6dd7478 | 2015-05-22 13:53:45 +0800 | [diff] [blame] | 31 | #include <linux/slab.h> |
Gilles Chanteperdrix | 876292d | 2014-04-05 17:57:45 +0200 | [diff] [blame] | 32 | #include <linux/of.h> |
| 33 | #include <linux/of_address.h> |
| 34 | #include <linux/of_irq.h> |
Shawn Guo | 0931aff | 2015-05-15 11:41:39 +0800 | [diff] [blame] | 35 | #include <soc/imx/timer.h> |
Juergen Beisert | d0f349f | 2008-07-05 10:02:50 +0200 | [diff] [blame] | 36 | |
Juergen Beisert | d0f349f | 2008-07-05 10:02:50 +0200 | [diff] [blame] | 37 | #include <asm/mach/time.h> |
Shawn Guo | e337247 | 2012-09-13 21:01:00 +0800 | [diff] [blame] | 38 | |
| 39 | #include "common.h" |
Shawn Guo | 50f2de6 | 2012-09-14 14:14:45 +0800 | [diff] [blame] | 40 | #include "hardware.h" |
Sascha Hauer | ec996ba | 2009-02-18 20:58:40 +0100 | [diff] [blame] | 41 | |
Sascha Hauer | 0f3332c | 2009-12-04 09:34:51 +0100 | [diff] [blame] | 42 | /* |
Shenwei Wang | 65d0a16 | 2015-04-29 16:40:27 -0500 | [diff] [blame] | 43 | * There are 4 versions of the timer hardware on Freescale MXC hardware. |
| 44 | * - MX1/MXL |
| 45 | * - MX21, MX27. |
| 46 | * - MX25, MX31, MX35, MX37, MX51, MX6Q(rev1.0) |
| 47 | * - MX6DL, MX6SX, MX6Q(rev1.1+) |
Sascha Hauer | 0f3332c | 2009-12-04 09:34:51 +0100 | [diff] [blame] | 48 | */ |
| 49 | |
Sascha Hauer | ec996ba | 2009-02-18 20:58:40 +0100 | [diff] [blame] | 50 | /* defines common for all i.MX */ |
| 51 | #define MXC_TCTL 0x00 |
Sascha Hauer | 0f3332c | 2009-12-04 09:34:51 +0100 | [diff] [blame] | 52 | #define MXC_TCTL_TEN (1 << 0) /* Enable module */ |
Sascha Hauer | ec996ba | 2009-02-18 20:58:40 +0100 | [diff] [blame] | 53 | #define MXC_TPRER 0x04 |
| 54 | |
| 55 | /* MX1, MX21, MX27 */ |
| 56 | #define MX1_2_TCTL_CLK_PCLK1 (1 << 1) |
| 57 | #define MX1_2_TCTL_IRQEN (1 << 4) |
| 58 | #define MX1_2_TCTL_FRR (1 << 8) |
| 59 | #define MX1_2_TCMP 0x08 |
| 60 | #define MX1_2_TCN 0x10 |
| 61 | #define MX1_2_TSTAT 0x14 |
| 62 | |
| 63 | /* MX21, MX27 */ |
| 64 | #define MX2_TSTAT_CAPT (1 << 1) |
| 65 | #define MX2_TSTAT_COMP (1 << 0) |
| 66 | |
Anson Huang | bad3db1 | 2014-09-11 11:29:42 +0800 | [diff] [blame] | 67 | /* MX31, MX35, MX25, MX5, MX6 */ |
Amit Kucheria | 38a66f5 | 2010-04-21 21:34:36 +0300 | [diff] [blame] | 68 | #define V2_TCTL_WAITEN (1 << 3) /* Wait enable mode */ |
| 69 | #define V2_TCTL_CLK_IPG (1 << 6) |
Richard Zhao | 1f152b4 | 2012-05-15 15:34:40 +0800 | [diff] [blame] | 70 | #define V2_TCTL_CLK_PER (2 << 6) |
Anson Huang | bad3db1 | 2014-09-11 11:29:42 +0800 | [diff] [blame] | 71 | #define V2_TCTL_CLK_OSC_DIV8 (5 << 6) |
Amit Kucheria | 38a66f5 | 2010-04-21 21:34:36 +0300 | [diff] [blame] | 72 | #define V2_TCTL_FRR (1 << 9) |
Anson Huang | bad3db1 | 2014-09-11 11:29:42 +0800 | [diff] [blame] | 73 | #define V2_TCTL_24MEN (1 << 10) |
| 74 | #define V2_TPRER_PRE24M 12 |
Amit Kucheria | 38a66f5 | 2010-04-21 21:34:36 +0300 | [diff] [blame] | 75 | #define V2_IR 0x0c |
| 76 | #define V2_TSTAT 0x08 |
| 77 | #define V2_TSTAT_OF1 (1 << 0) |
| 78 | #define V2_TCN 0x24 |
| 79 | #define V2_TCMP 0x10 |
Juergen Beisert | d0f349f | 2008-07-05 10:02:50 +0200 | [diff] [blame] | 80 | |
Anson Huang | bad3db1 | 2014-09-11 11:29:42 +0800 | [diff] [blame] | 81 | #define V2_TIMER_RATE_OSC_DIV8 3000000 |
| 82 | |
Sascha Hauer | 0f3332c | 2009-12-04 09:34:51 +0100 | [diff] [blame] | 83 | #define timer_is_v1() (cpu_is_mx1() || cpu_is_mx21() || cpu_is_mx27()) |
| 84 | #define timer_is_v2() (!timer_is_v1()) |
| 85 | |
Juergen Beisert | d0f349f | 2008-07-05 10:02:50 +0200 | [diff] [blame] | 86 | static struct clock_event_device clockevent_mxc; |
| 87 | static enum clock_event_mode clockevent_mode = CLOCK_EVT_MODE_UNUSED; |
| 88 | |
Shawn Guo | 6dd7478 | 2015-05-22 13:53:45 +0800 | [diff] [blame] | 89 | struct imx_timer { |
Shawn Guo | 0931aff | 2015-05-15 11:41:39 +0800 | [diff] [blame] | 90 | enum imx_gpt_type type; |
Shawn Guo | 6dd7478 | 2015-05-22 13:53:45 +0800 | [diff] [blame] | 91 | void __iomem *base; |
| 92 | int irq; |
| 93 | struct clk *clk_per; |
| 94 | struct clk *clk_ipg; |
Shawn Guo | 9c8694b | 2015-05-15 14:24:41 +0800 | [diff] [blame^] | 95 | const struct imx_gpt_data *gpt; |
| 96 | }; |
| 97 | |
| 98 | struct imx_gpt_data { |
| 99 | void (*gpt_setup_tctl)(struct imx_timer *imxtm); |
Shawn Guo | 6dd7478 | 2015-05-22 13:53:45 +0800 | [diff] [blame] | 100 | }; |
| 101 | |
Sascha Hauer | ec996ba | 2009-02-18 20:58:40 +0100 | [diff] [blame] | 102 | static void __iomem *timer_base; |
Juergen Beisert | d0f349f | 2008-07-05 10:02:50 +0200 | [diff] [blame] | 103 | |
Sascha Hauer | ec996ba | 2009-02-18 20:58:40 +0100 | [diff] [blame] | 104 | static inline void gpt_irq_disable(void) |
Juergen Beisert | d0f349f | 2008-07-05 10:02:50 +0200 | [diff] [blame] | 105 | { |
Sascha Hauer | ec996ba | 2009-02-18 20:58:40 +0100 | [diff] [blame] | 106 | unsigned int tmp; |
| 107 | |
Sascha Hauer | 0f3332c | 2009-12-04 09:34:51 +0100 | [diff] [blame] | 108 | if (timer_is_v2()) |
Shawn Guo | c7770bb | 2015-05-19 18:47:47 +0800 | [diff] [blame] | 109 | writel_relaxed(0, timer_base + V2_IR); |
Sascha Hauer | ec996ba | 2009-02-18 20:58:40 +0100 | [diff] [blame] | 110 | else { |
Shawn Guo | c7770bb | 2015-05-19 18:47:47 +0800 | [diff] [blame] | 111 | tmp = readl_relaxed(timer_base + MXC_TCTL); |
| 112 | writel_relaxed(tmp & ~MX1_2_TCTL_IRQEN, timer_base + MXC_TCTL); |
Sascha Hauer | ec996ba | 2009-02-18 20:58:40 +0100 | [diff] [blame] | 113 | } |
| 114 | } |
| 115 | |
| 116 | static inline void gpt_irq_enable(void) |
| 117 | { |
Sascha Hauer | 0f3332c | 2009-12-04 09:34:51 +0100 | [diff] [blame] | 118 | if (timer_is_v2()) |
Shawn Guo | c7770bb | 2015-05-19 18:47:47 +0800 | [diff] [blame] | 119 | writel_relaxed(1<<0, timer_base + V2_IR); |
Sascha Hauer | ec996ba | 2009-02-18 20:58:40 +0100 | [diff] [blame] | 120 | else { |
Shawn Guo | c7770bb | 2015-05-19 18:47:47 +0800 | [diff] [blame] | 121 | writel_relaxed(readl_relaxed(timer_base + MXC_TCTL) | MX1_2_TCTL_IRQEN, |
Sascha Hauer | ec996ba | 2009-02-18 20:58:40 +0100 | [diff] [blame] | 122 | timer_base + MXC_TCTL); |
| 123 | } |
| 124 | } |
| 125 | |
| 126 | static void gpt_irq_acknowledge(void) |
| 127 | { |
Sascha Hauer | 0f3332c | 2009-12-04 09:34:51 +0100 | [diff] [blame] | 128 | if (timer_is_v1()) { |
| 129 | if (cpu_is_mx1()) |
Shawn Guo | c7770bb | 2015-05-19 18:47:47 +0800 | [diff] [blame] | 130 | writel_relaxed(0, timer_base + MX1_2_TSTAT); |
Sascha Hauer | 0f3332c | 2009-12-04 09:34:51 +0100 | [diff] [blame] | 131 | else |
Shawn Guo | c7770bb | 2015-05-19 18:47:47 +0800 | [diff] [blame] | 132 | writel_relaxed(MX2_TSTAT_CAPT | MX2_TSTAT_COMP, |
Sascha Hauer | 0f3332c | 2009-12-04 09:34:51 +0100 | [diff] [blame] | 133 | timer_base + MX1_2_TSTAT); |
| 134 | } else if (timer_is_v2()) |
Shawn Guo | c7770bb | 2015-05-19 18:47:47 +0800 | [diff] [blame] | 135 | writel_relaxed(V2_TSTAT_OF1, timer_base + V2_TSTAT); |
Sascha Hauer | ec996ba | 2009-02-18 20:58:40 +0100 | [diff] [blame] | 136 | } |
| 137 | |
Russell King | 234b6ced | 2011-05-08 14:09:47 +0100 | [diff] [blame] | 138 | static void __iomem *sched_clock_reg; |
Juergen Beisert | d0f349f | 2008-07-05 10:02:50 +0200 | [diff] [blame] | 139 | |
Stephen Boyd | b93767e | 2013-11-15 15:26:12 -0800 | [diff] [blame] | 140 | static u64 notrace mxc_read_sched_clock(void) |
Jan Weitzel | c124bef | 2011-03-17 13:44:30 +0100 | [diff] [blame] | 141 | { |
Shawn Guo | c7770bb | 2015-05-19 18:47:47 +0800 | [diff] [blame] | 142 | return sched_clock_reg ? readl_relaxed(sched_clock_reg) : 0; |
Jan Weitzel | c124bef | 2011-03-17 13:44:30 +0100 | [diff] [blame] | 143 | } |
| 144 | |
Sebastian Andrzej Siewior | 1119c84 | 2014-01-22 12:35:44 +0100 | [diff] [blame] | 145 | static struct delay_timer imx_delay_timer; |
| 146 | |
| 147 | static unsigned long imx_read_current_timer(void) |
| 148 | { |
Shawn Guo | c7770bb | 2015-05-19 18:47:47 +0800 | [diff] [blame] | 149 | return readl_relaxed(sched_clock_reg); |
Sebastian Andrzej Siewior | 1119c84 | 2014-01-22 12:35:44 +0100 | [diff] [blame] | 150 | } |
| 151 | |
Shawn Guo | 6dd7478 | 2015-05-22 13:53:45 +0800 | [diff] [blame] | 152 | static int __init mxc_clocksource_init(struct imx_timer *imxtm) |
Juergen Beisert | d0f349f | 2008-07-05 10:02:50 +0200 | [diff] [blame] | 153 | { |
Shawn Guo | 6dd7478 | 2015-05-22 13:53:45 +0800 | [diff] [blame] | 154 | unsigned int c = clk_get_rate(imxtm->clk_per); |
| 155 | void __iomem *reg = imxtm->base + (timer_is_v2() ? V2_TCN : MX1_2_TCN); |
Juergen Beisert | d0f349f | 2008-07-05 10:02:50 +0200 | [diff] [blame] | 156 | |
Sebastian Andrzej Siewior | 1119c84 | 2014-01-22 12:35:44 +0100 | [diff] [blame] | 157 | imx_delay_timer.read_current_timer = &imx_read_current_timer; |
| 158 | imx_delay_timer.freq = c; |
| 159 | register_current_timer_delay(&imx_delay_timer); |
| 160 | |
Russell King | 234b6ced | 2011-05-08 14:09:47 +0100 | [diff] [blame] | 161 | sched_clock_reg = reg; |
Sascha Hauer | ec996ba | 2009-02-18 20:58:40 +0100 | [diff] [blame] | 162 | |
Stephen Boyd | b93767e | 2013-11-15 15:26:12 -0800 | [diff] [blame] | 163 | sched_clock_register(mxc_read_sched_clock, 32, c); |
Russell King | 234b6ced | 2011-05-08 14:09:47 +0100 | [diff] [blame] | 164 | return clocksource_mmio_init(reg, "mxc_timer1", c, 200, 32, |
| 165 | clocksource_mmio_readl_up); |
Juergen Beisert | d0f349f | 2008-07-05 10:02:50 +0200 | [diff] [blame] | 166 | } |
| 167 | |
| 168 | /* clock event */ |
| 169 | |
Sascha Hauer | ec996ba | 2009-02-18 20:58:40 +0100 | [diff] [blame] | 170 | static int mx1_2_set_next_event(unsigned long evt, |
Juergen Beisert | d0f349f | 2008-07-05 10:02:50 +0200 | [diff] [blame] | 171 | struct clock_event_device *unused) |
| 172 | { |
| 173 | unsigned long tcmp; |
| 174 | |
Shawn Guo | c7770bb | 2015-05-19 18:47:47 +0800 | [diff] [blame] | 175 | tcmp = readl_relaxed(timer_base + MX1_2_TCN) + evt; |
Juergen Beisert | d0f349f | 2008-07-05 10:02:50 +0200 | [diff] [blame] | 176 | |
Shawn Guo | c7770bb | 2015-05-19 18:47:47 +0800 | [diff] [blame] | 177 | writel_relaxed(tcmp, timer_base + MX1_2_TCMP); |
Sascha Hauer | ec996ba | 2009-02-18 20:58:40 +0100 | [diff] [blame] | 178 | |
Shawn Guo | c7770bb | 2015-05-19 18:47:47 +0800 | [diff] [blame] | 179 | return (int)(tcmp - readl_relaxed(timer_base + MX1_2_TCN)) < 0 ? |
Sascha Hauer | ec996ba | 2009-02-18 20:58:40 +0100 | [diff] [blame] | 180 | -ETIME : 0; |
| 181 | } |
| 182 | |
Amit Kucheria | 38a66f5 | 2010-04-21 21:34:36 +0300 | [diff] [blame] | 183 | static int v2_set_next_event(unsigned long evt, |
Sascha Hauer | ec996ba | 2009-02-18 20:58:40 +0100 | [diff] [blame] | 184 | struct clock_event_device *unused) |
| 185 | { |
| 186 | unsigned long tcmp; |
| 187 | |
Shawn Guo | c7770bb | 2015-05-19 18:47:47 +0800 | [diff] [blame] | 188 | tcmp = readl_relaxed(timer_base + V2_TCN) + evt; |
Sascha Hauer | ec996ba | 2009-02-18 20:58:40 +0100 | [diff] [blame] | 189 | |
Shawn Guo | c7770bb | 2015-05-19 18:47:47 +0800 | [diff] [blame] | 190 | writel_relaxed(tcmp, timer_base + V2_TCMP); |
Sascha Hauer | ec996ba | 2009-02-18 20:58:40 +0100 | [diff] [blame] | 191 | |
Shawn Guo | eea8e32 | 2012-12-06 22:54:41 +0800 | [diff] [blame] | 192 | return evt < 0x7fffffff && |
Shawn Guo | c7770bb | 2015-05-19 18:47:47 +0800 | [diff] [blame] | 193 | (int)(tcmp - readl_relaxed(timer_base + V2_TCN)) < 0 ? |
Juergen Beisert | d0f349f | 2008-07-05 10:02:50 +0200 | [diff] [blame] | 194 | -ETIME : 0; |
| 195 | } |
| 196 | |
| 197 | #ifdef DEBUG |
| 198 | static const char *clock_event_mode_label[] = { |
| 199 | [CLOCK_EVT_MODE_PERIODIC] = "CLOCK_EVT_MODE_PERIODIC", |
| 200 | [CLOCK_EVT_MODE_ONESHOT] = "CLOCK_EVT_MODE_ONESHOT", |
| 201 | [CLOCK_EVT_MODE_SHUTDOWN] = "CLOCK_EVT_MODE_SHUTDOWN", |
Uwe Kleine-König | de9c515 | 2012-07-16 22:07:06 +0200 | [diff] [blame] | 202 | [CLOCK_EVT_MODE_UNUSED] = "CLOCK_EVT_MODE_UNUSED", |
| 203 | [CLOCK_EVT_MODE_RESUME] = "CLOCK_EVT_MODE_RESUME", |
Juergen Beisert | d0f349f | 2008-07-05 10:02:50 +0200 | [diff] [blame] | 204 | }; |
| 205 | #endif /* DEBUG */ |
| 206 | |
| 207 | static void mxc_set_mode(enum clock_event_mode mode, |
| 208 | struct clock_event_device *evt) |
| 209 | { |
| 210 | unsigned long flags; |
| 211 | |
| 212 | /* |
| 213 | * The timer interrupt generation is disabled at least |
| 214 | * for enough time to call mxc_set_next_event() |
| 215 | */ |
| 216 | local_irq_save(flags); |
| 217 | |
| 218 | /* Disable interrupt in GPT module */ |
| 219 | gpt_irq_disable(); |
| 220 | |
| 221 | if (mode != clockevent_mode) { |
| 222 | /* Set event time into far-far future */ |
Sascha Hauer | 0f3332c | 2009-12-04 09:34:51 +0100 | [diff] [blame] | 223 | if (timer_is_v2()) |
Shawn Guo | c7770bb | 2015-05-19 18:47:47 +0800 | [diff] [blame] | 224 | writel_relaxed(readl_relaxed(timer_base + V2_TCN) - 3, |
Amit Kucheria | 38a66f5 | 2010-04-21 21:34:36 +0300 | [diff] [blame] | 225 | timer_base + V2_TCMP); |
Sascha Hauer | ec996ba | 2009-02-18 20:58:40 +0100 | [diff] [blame] | 226 | else |
Shawn Guo | c7770bb | 2015-05-19 18:47:47 +0800 | [diff] [blame] | 227 | writel_relaxed(readl_relaxed(timer_base + MX1_2_TCN) - 3, |
Sascha Hauer | ec996ba | 2009-02-18 20:58:40 +0100 | [diff] [blame] | 228 | timer_base + MX1_2_TCMP); |
| 229 | |
Juergen Beisert | d0f349f | 2008-07-05 10:02:50 +0200 | [diff] [blame] | 230 | /* Clear pending interrupt */ |
| 231 | gpt_irq_acknowledge(); |
| 232 | } |
| 233 | |
| 234 | #ifdef DEBUG |
| 235 | printk(KERN_INFO "mxc_set_mode: changing mode from %s to %s\n", |
| 236 | clock_event_mode_label[clockevent_mode], |
| 237 | clock_event_mode_label[mode]); |
| 238 | #endif /* DEBUG */ |
| 239 | |
| 240 | /* Remember timer mode */ |
| 241 | clockevent_mode = mode; |
| 242 | local_irq_restore(flags); |
| 243 | |
| 244 | switch (mode) { |
| 245 | case CLOCK_EVT_MODE_PERIODIC: |
| 246 | printk(KERN_ERR"mxc_set_mode: Periodic mode is not " |
| 247 | "supported for i.MX\n"); |
| 248 | break; |
| 249 | case CLOCK_EVT_MODE_ONESHOT: |
| 250 | /* |
| 251 | * Do not put overhead of interrupt enable/disable into |
| 252 | * mxc_set_next_event(), the core has about 4 minutes |
| 253 | * to call mxc_set_next_event() or shutdown clock after |
| 254 | * mode switching |
| 255 | */ |
| 256 | local_irq_save(flags); |
| 257 | gpt_irq_enable(); |
| 258 | local_irq_restore(flags); |
| 259 | break; |
| 260 | case CLOCK_EVT_MODE_SHUTDOWN: |
| 261 | case CLOCK_EVT_MODE_UNUSED: |
| 262 | case CLOCK_EVT_MODE_RESUME: |
| 263 | /* Left event sources disabled, no more interrupts appear */ |
| 264 | break; |
| 265 | } |
| 266 | } |
| 267 | |
| 268 | /* |
| 269 | * IRQ handler for the timer |
| 270 | */ |
| 271 | static irqreturn_t mxc_timer_interrupt(int irq, void *dev_id) |
| 272 | { |
| 273 | struct clock_event_device *evt = &clockevent_mxc; |
| 274 | uint32_t tstat; |
| 275 | |
Sascha Hauer | 0f3332c | 2009-12-04 09:34:51 +0100 | [diff] [blame] | 276 | if (timer_is_v2()) |
Shawn Guo | c7770bb | 2015-05-19 18:47:47 +0800 | [diff] [blame] | 277 | tstat = readl_relaxed(timer_base + V2_TSTAT); |
Sascha Hauer | 81ec1f9 | 2009-04-29 13:55:13 +0200 | [diff] [blame] | 278 | else |
Shawn Guo | c7770bb | 2015-05-19 18:47:47 +0800 | [diff] [blame] | 279 | tstat = readl_relaxed(timer_base + MX1_2_TSTAT); |
Juergen Beisert | d0f349f | 2008-07-05 10:02:50 +0200 | [diff] [blame] | 280 | |
| 281 | gpt_irq_acknowledge(); |
| 282 | |
| 283 | evt->event_handler(evt); |
| 284 | |
| 285 | return IRQ_HANDLED; |
| 286 | } |
| 287 | |
| 288 | static struct irqaction mxc_timer_irq = { |
| 289 | .name = "i.MX Timer Tick", |
Michael Opdenacker | 4c1dd3e | 2013-09-04 07:04:39 +0200 | [diff] [blame] | 290 | .flags = IRQF_TIMER | IRQF_IRQPOLL, |
Juergen Beisert | d0f349f | 2008-07-05 10:02:50 +0200 | [diff] [blame] | 291 | .handler = mxc_timer_interrupt, |
| 292 | }; |
| 293 | |
| 294 | static struct clock_event_device clockevent_mxc = { |
| 295 | .name = "mxc_timer1", |
| 296 | .features = CLOCK_EVT_FEAT_ONESHOT, |
Juergen Beisert | d0f349f | 2008-07-05 10:02:50 +0200 | [diff] [blame] | 297 | .set_mode = mxc_set_mode, |
Sascha Hauer | ec996ba | 2009-02-18 20:58:40 +0100 | [diff] [blame] | 298 | .set_next_event = mx1_2_set_next_event, |
Juergen Beisert | d0f349f | 2008-07-05 10:02:50 +0200 | [diff] [blame] | 299 | .rating = 200, |
| 300 | }; |
| 301 | |
Shawn Guo | 6dd7478 | 2015-05-22 13:53:45 +0800 | [diff] [blame] | 302 | static int __init mxc_clockevent_init(struct imx_timer *imxtm) |
Juergen Beisert | d0f349f | 2008-07-05 10:02:50 +0200 | [diff] [blame] | 303 | { |
Sascha Hauer | 0f3332c | 2009-12-04 09:34:51 +0100 | [diff] [blame] | 304 | if (timer_is_v2()) |
Amit Kucheria | 38a66f5 | 2010-04-21 21:34:36 +0300 | [diff] [blame] | 305 | clockevent_mxc.set_next_event = v2_set_next_event; |
Sascha Hauer | ec996ba | 2009-02-18 20:58:40 +0100 | [diff] [blame] | 306 | |
Rusty Russell | 320ab2b | 2008-12-13 21:20:26 +1030 | [diff] [blame] | 307 | clockevent_mxc.cpumask = cpumask_of(0); |
Shawn Guo | 838a2ae | 2013-01-12 11:50:05 +0000 | [diff] [blame] | 308 | clockevents_config_and_register(&clockevent_mxc, |
Shawn Guo | 6dd7478 | 2015-05-22 13:53:45 +0800 | [diff] [blame] | 309 | clk_get_rate(imxtm->clk_per), |
Shawn Guo | 838a2ae | 2013-01-12 11:50:05 +0000 | [diff] [blame] | 310 | 0xff, 0xfffffffe); |
Juergen Beisert | d0f349f | 2008-07-05 10:02:50 +0200 | [diff] [blame] | 311 | |
| 312 | return 0; |
| 313 | } |
| 314 | |
Shawn Guo | 9c8694b | 2015-05-15 14:24:41 +0800 | [diff] [blame^] | 315 | static void imx1_gpt_setup_tctl(struct imx_timer *imxtm) |
| 316 | { |
| 317 | u32 tctl_val; |
| 318 | |
| 319 | tctl_val = MX1_2_TCTL_FRR | MX1_2_TCTL_CLK_PCLK1 | MXC_TCTL_TEN; |
| 320 | writel_relaxed(tctl_val, imxtm->base + MXC_TCTL); |
| 321 | } |
| 322 | #define imx21_gpt_setup_tctl imx1_gpt_setup_tctl |
| 323 | |
| 324 | static void imx31_gpt_setup_tctl(struct imx_timer *imxtm) |
| 325 | { |
| 326 | u32 tctl_val; |
| 327 | |
| 328 | tctl_val = V2_TCTL_FRR | V2_TCTL_WAITEN | MXC_TCTL_TEN; |
| 329 | if (clk_get_rate(imxtm->clk_per) == V2_TIMER_RATE_OSC_DIV8) |
| 330 | tctl_val |= V2_TCTL_CLK_OSC_DIV8; |
| 331 | else |
| 332 | tctl_val |= V2_TCTL_CLK_PER; |
| 333 | |
| 334 | writel_relaxed(tctl_val, imxtm->base + MXC_TCTL); |
| 335 | } |
| 336 | |
| 337 | static void imx6dl_gpt_setup_tctl(struct imx_timer *imxtm) |
| 338 | { |
| 339 | u32 tctl_val; |
| 340 | |
| 341 | tctl_val = V2_TCTL_FRR | V2_TCTL_WAITEN | MXC_TCTL_TEN; |
| 342 | if (clk_get_rate(imxtm->clk_per) == V2_TIMER_RATE_OSC_DIV8) { |
| 343 | tctl_val |= V2_TCTL_CLK_OSC_DIV8; |
| 344 | /* 24 / 8 = 3 MHz */ |
| 345 | writel_relaxed(7 << V2_TPRER_PRE24M, imxtm->base + MXC_TPRER); |
| 346 | tctl_val |= V2_TCTL_24MEN; |
| 347 | } else { |
| 348 | tctl_val |= V2_TCTL_CLK_PER; |
| 349 | } |
| 350 | |
| 351 | writel_relaxed(tctl_val, imxtm->base + MXC_TCTL); |
| 352 | } |
| 353 | |
| 354 | static const struct imx_gpt_data imx1_gpt_data = { |
| 355 | .gpt_setup_tctl = imx1_gpt_setup_tctl, |
| 356 | }; |
| 357 | |
| 358 | static const struct imx_gpt_data imx21_gpt_data = { |
| 359 | .gpt_setup_tctl = imx21_gpt_setup_tctl, |
| 360 | }; |
| 361 | |
| 362 | static const struct imx_gpt_data imx31_gpt_data = { |
| 363 | .gpt_setup_tctl = imx31_gpt_setup_tctl, |
| 364 | }; |
| 365 | |
| 366 | static const struct imx_gpt_data imx6dl_gpt_data = { |
| 367 | .gpt_setup_tctl = imx6dl_gpt_setup_tctl, |
| 368 | }; |
| 369 | |
Shawn Guo | 6dd7478 | 2015-05-22 13:53:45 +0800 | [diff] [blame] | 370 | static void __init _mxc_timer_init(struct imx_timer *imxtm) |
Juergen Beisert | d0f349f | 2008-07-05 10:02:50 +0200 | [diff] [blame] | 371 | { |
Shawn Guo | 6dd7478 | 2015-05-22 13:53:45 +0800 | [diff] [blame] | 372 | /* Temporary */ |
| 373 | timer_base = imxtm->base; |
| 374 | |
Shawn Guo | 9c8694b | 2015-05-15 14:24:41 +0800 | [diff] [blame^] | 375 | switch (imxtm->type) { |
| 376 | case GPT_TYPE_IMX1: |
| 377 | imxtm->gpt = &imx1_gpt_data; |
| 378 | break; |
| 379 | case GPT_TYPE_IMX21: |
| 380 | imxtm->gpt = &imx21_gpt_data; |
| 381 | break; |
| 382 | case GPT_TYPE_IMX31: |
| 383 | imxtm->gpt = &imx31_gpt_data; |
| 384 | break; |
| 385 | case GPT_TYPE_IMX6DL: |
| 386 | imxtm->gpt = &imx6dl_gpt_data; |
| 387 | break; |
| 388 | default: |
| 389 | BUG(); |
| 390 | } |
| 391 | |
Shawn Guo | 6dd7478 | 2015-05-22 13:53:45 +0800 | [diff] [blame] | 392 | if (IS_ERR(imxtm->clk_per)) { |
Sascha Hauer | 2cfb451 | 2012-05-16 12:29:53 +0200 | [diff] [blame] | 393 | pr_err("i.MX timer: unable to get clk\n"); |
| 394 | return; |
Sascha Hauer | 821dc4d | 2012-03-09 09:29:27 +0100 | [diff] [blame] | 395 | } |
Sascha Hauer | ec996ba | 2009-02-18 20:58:40 +0100 | [diff] [blame] | 396 | |
Shawn Guo | 6dd7478 | 2015-05-22 13:53:45 +0800 | [diff] [blame] | 397 | if (!IS_ERR(imxtm->clk_ipg)) |
| 398 | clk_prepare_enable(imxtm->clk_ipg); |
Sascha Hauer | 2cfb451 | 2012-05-16 12:29:53 +0200 | [diff] [blame] | 399 | |
Shawn Guo | 6dd7478 | 2015-05-22 13:53:45 +0800 | [diff] [blame] | 400 | clk_prepare_enable(imxtm->clk_per); |
Juergen Beisert | d0f349f | 2008-07-05 10:02:50 +0200 | [diff] [blame] | 401 | |
| 402 | /* |
| 403 | * Initialise to a known state (all timers off, and timing reset) |
| 404 | */ |
Juergen Beisert | d0f349f | 2008-07-05 10:02:50 +0200 | [diff] [blame] | 405 | |
Shawn Guo | 6dd7478 | 2015-05-22 13:53:45 +0800 | [diff] [blame] | 406 | writel_relaxed(0, imxtm->base + MXC_TCTL); |
| 407 | writel_relaxed(0, imxtm->base + MXC_TPRER); /* see datasheet note */ |
Sascha Hauer | ec996ba | 2009-02-18 20:58:40 +0100 | [diff] [blame] | 408 | |
Shawn Guo | 9c8694b | 2015-05-15 14:24:41 +0800 | [diff] [blame^] | 409 | imxtm->gpt->gpt_setup_tctl(imxtm); |
Juergen Beisert | d0f349f | 2008-07-05 10:02:50 +0200 | [diff] [blame] | 410 | |
| 411 | /* init and register the timer to the framework */ |
Shawn Guo | 6dd7478 | 2015-05-22 13:53:45 +0800 | [diff] [blame] | 412 | mxc_clocksource_init(imxtm); |
| 413 | mxc_clockevent_init(imxtm); |
Juergen Beisert | d0f349f | 2008-07-05 10:02:50 +0200 | [diff] [blame] | 414 | |
| 415 | /* Make irqs happen */ |
Shawn Guo | 6dd7478 | 2015-05-22 13:53:45 +0800 | [diff] [blame] | 416 | setup_irq(imxtm->irq, &mxc_timer_irq); |
Juergen Beisert | d0f349f | 2008-07-05 10:02:50 +0200 | [diff] [blame] | 417 | } |
Gilles Chanteperdrix | 876292d | 2014-04-05 17:57:45 +0200 | [diff] [blame] | 418 | |
Shawn Guo | 0931aff | 2015-05-15 11:41:39 +0800 | [diff] [blame] | 419 | void __init mxc_timer_init(unsigned long pbase, int irq, enum imx_gpt_type type) |
Alexander Shiyan | f469675 | 2014-05-27 13:04:46 +0400 | [diff] [blame] | 420 | { |
Shawn Guo | 6dd7478 | 2015-05-22 13:53:45 +0800 | [diff] [blame] | 421 | struct imx_timer *imxtm; |
Alexander Shiyan | f469675 | 2014-05-27 13:04:46 +0400 | [diff] [blame] | 422 | |
Shawn Guo | 6dd7478 | 2015-05-22 13:53:45 +0800 | [diff] [blame] | 423 | imxtm = kzalloc(sizeof(*imxtm), GFP_KERNEL); |
| 424 | BUG_ON(!imxtm); |
Alexander Shiyan | d7f9891 | 2014-05-27 13:04:47 +0400 | [diff] [blame] | 425 | |
Shawn Guo | 6dd7478 | 2015-05-22 13:53:45 +0800 | [diff] [blame] | 426 | imxtm->clk_per = clk_get_sys("imx-gpt.0", "per"); |
| 427 | imxtm->clk_ipg = clk_get_sys("imx-gpt.0", "ipg"); |
| 428 | |
| 429 | imxtm->base = ioremap(pbase, SZ_4K); |
| 430 | BUG_ON(!imxtm->base); |
| 431 | |
Shawn Guo | 0931aff | 2015-05-15 11:41:39 +0800 | [diff] [blame] | 432 | imxtm->type = type; |
| 433 | |
Shawn Guo | 6dd7478 | 2015-05-22 13:53:45 +0800 | [diff] [blame] | 434 | _mxc_timer_init(imxtm); |
Alexander Shiyan | f469675 | 2014-05-27 13:04:46 +0400 | [diff] [blame] | 435 | } |
| 436 | |
Shawn Guo | bef11c8 | 2015-05-15 13:38:20 +0800 | [diff] [blame] | 437 | static void __init mxc_timer_init_dt(struct device_node *np, enum imx_gpt_type type) |
Gilles Chanteperdrix | 876292d | 2014-04-05 17:57:45 +0200 | [diff] [blame] | 438 | { |
Shawn Guo | 6dd7478 | 2015-05-22 13:53:45 +0800 | [diff] [blame] | 439 | struct imx_timer *imxtm; |
| 440 | static int initialized; |
Gilles Chanteperdrix | 876292d | 2014-04-05 17:57:45 +0200 | [diff] [blame] | 441 | |
Shawn Guo | 6dd7478 | 2015-05-22 13:53:45 +0800 | [diff] [blame] | 442 | /* Support one instance only */ |
| 443 | if (initialized) |
Alexander Shiyan | fd4959d | 2014-07-13 09:34:00 +0400 | [diff] [blame] | 444 | return; |
| 445 | |
Shawn Guo | 6dd7478 | 2015-05-22 13:53:45 +0800 | [diff] [blame] | 446 | imxtm = kzalloc(sizeof(*imxtm), GFP_KERNEL); |
| 447 | BUG_ON(!imxtm); |
Gilles Chanteperdrix | 876292d | 2014-04-05 17:57:45 +0200 | [diff] [blame] | 448 | |
Shawn Guo | 6dd7478 | 2015-05-22 13:53:45 +0800 | [diff] [blame] | 449 | imxtm->base = of_iomap(np, 0); |
| 450 | WARN_ON(!imxtm->base); |
| 451 | imxtm->irq = irq_of_parse_and_map(np, 0); |
| 452 | |
| 453 | imxtm->clk_ipg = of_clk_get_by_name(np, "ipg"); |
Alexander Shiyan | f469675 | 2014-05-27 13:04:46 +0400 | [diff] [blame] | 454 | |
Anson Huang | bad3db1 | 2014-09-11 11:29:42 +0800 | [diff] [blame] | 455 | /* Try osc_per first, and fall back to per otherwise */ |
Shawn Guo | 6dd7478 | 2015-05-22 13:53:45 +0800 | [diff] [blame] | 456 | imxtm->clk_per = of_clk_get_by_name(np, "osc_per"); |
| 457 | if (IS_ERR(imxtm->clk_per)) |
| 458 | imxtm->clk_per = of_clk_get_by_name(np, "per"); |
Anson Huang | bad3db1 | 2014-09-11 11:29:42 +0800 | [diff] [blame] | 459 | |
Shawn Guo | bef11c8 | 2015-05-15 13:38:20 +0800 | [diff] [blame] | 460 | imxtm->type = type; |
| 461 | |
Shawn Guo | 6dd7478 | 2015-05-22 13:53:45 +0800 | [diff] [blame] | 462 | _mxc_timer_init(imxtm); |
| 463 | |
| 464 | initialized = 1; |
Gilles Chanteperdrix | 876292d | 2014-04-05 17:57:45 +0200 | [diff] [blame] | 465 | } |
Shawn Guo | bef11c8 | 2015-05-15 13:38:20 +0800 | [diff] [blame] | 466 | |
| 467 | static void __init imx1_timer_init_dt(struct device_node *np) |
| 468 | { |
| 469 | mxc_timer_init_dt(np, GPT_TYPE_IMX1); |
| 470 | } |
| 471 | |
| 472 | static void __init imx21_timer_init_dt(struct device_node *np) |
| 473 | { |
| 474 | mxc_timer_init_dt(np, GPT_TYPE_IMX21); |
| 475 | } |
| 476 | |
| 477 | static void __init imx31_timer_init_dt(struct device_node *np) |
| 478 | { |
| 479 | enum imx_gpt_type type = GPT_TYPE_IMX31; |
| 480 | |
| 481 | /* |
| 482 | * We were using the same compatible string for i.MX6Q/D and i.MX6DL/S |
| 483 | * GPT device, while they actually have different programming model. |
| 484 | * This is a workaround to keep the existing i.MX6DL/S DTBs continue |
| 485 | * working with the new kernel. |
| 486 | */ |
| 487 | if (of_machine_is_compatible("fsl,imx6dl")) |
| 488 | type = GPT_TYPE_IMX6DL; |
| 489 | |
| 490 | mxc_timer_init_dt(np, type); |
| 491 | } |
| 492 | |
| 493 | static void __init imx6dl_timer_init_dt(struct device_node *np) |
| 494 | { |
| 495 | mxc_timer_init_dt(np, GPT_TYPE_IMX6DL); |
| 496 | } |
| 497 | |
| 498 | CLOCKSOURCE_OF_DECLARE(imx1_timer, "fsl,imx1-gpt", imx1_timer_init_dt); |
| 499 | CLOCKSOURCE_OF_DECLARE(imx21_timer, "fsl,imx21-gpt", imx21_timer_init_dt); |
| 500 | CLOCKSOURCE_OF_DECLARE(imx31_timer, "fsl,imx31-gpt", imx31_timer_init_dt); |
| 501 | CLOCKSOURCE_OF_DECLARE(imx25_timer, "fsl,imx25-gpt", imx31_timer_init_dt); |
| 502 | CLOCKSOURCE_OF_DECLARE(imx50_timer, "fsl,imx50-gpt", imx31_timer_init_dt); |
| 503 | CLOCKSOURCE_OF_DECLARE(imx51_timer, "fsl,imx51-gpt", imx31_timer_init_dt); |
| 504 | CLOCKSOURCE_OF_DECLARE(imx53_timer, "fsl,imx53-gpt", imx31_timer_init_dt); |
| 505 | CLOCKSOURCE_OF_DECLARE(imx6q_timer, "fsl,imx6q-gpt", imx31_timer_init_dt); |
| 506 | CLOCKSOURCE_OF_DECLARE(imx6dl_timer, "fsl,imx6dl-gpt", imx6dl_timer_init_dt); |
| 507 | CLOCKSOURCE_OF_DECLARE(imx6sl_timer, "fsl,imx6sl-gpt", imx6dl_timer_init_dt); |
| 508 | CLOCKSOURCE_OF_DECLARE(imx6sx_timer, "fsl,imx6sx-gpt", imx6dl_timer_init_dt); |