Vishnu Patekar | a0e9e9b | 2015-05-30 16:55:03 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2014 Chen-Yu Tsai |
| 3 | * |
| 4 | * Chen-Yu Tsai <wens@csie.org> |
| 5 | * |
| 6 | * This file is dual-licensed: you can use it either under the terms |
| 7 | * of the GPL or the X11 license, at your option. Note that this dual |
| 8 | * licensing only applies to this file, and not this project as a |
| 9 | * whole. |
| 10 | * |
| 11 | * a) This file is free software; you can redistribute it and/or |
| 12 | * modify it under the terms of the GNU General Public License as |
| 13 | * published by the Free Software Foundation; either version 2 of the |
| 14 | * License, or (at your option) any later version. |
| 15 | * |
| 16 | * This file is distributed in the hope that it will be useful, |
| 17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 19 | * GNU General Public License for more details. |
| 20 | * |
| 21 | * Or, alternatively, |
| 22 | * |
| 23 | * b) Permission is hereby granted, free of charge, to any person |
| 24 | * obtaining a copy of this software and associated documentation |
| 25 | * files (the "Software"), to deal in the Software without |
| 26 | * restriction, including without limitation the rights to use, |
| 27 | * copy, modify, merge, publish, distribute, sublicense, and/or |
| 28 | * sell copies of the Software, and to permit persons to whom the |
| 29 | * Software is furnished to do so, subject to the following |
| 30 | * conditions: |
| 31 | * |
| 32 | * The above copyright notice and this permission notice shall be |
| 33 | * included in all copies or substantial portions of the Software. |
| 34 | * |
| 35 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
| 36 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES |
| 37 | * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
| 38 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT |
| 39 | * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, |
| 40 | * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 41 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 42 | * OTHER DEALINGS IN THE SOFTWARE. |
| 43 | */ |
| 44 | |
| 45 | #include "skeleton.dtsi" |
| 46 | |
| 47 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 48 | |
Maxime Ripard | 2c89ce4f4 | 2016-08-31 14:58:20 +0200 | [diff] [blame] | 49 | #include <dt-bindings/clock/sun8i-a23-a33-ccu.h> |
Vishnu Patekar | a0e9e9b | 2015-05-30 16:55:03 +0200 | [diff] [blame] | 50 | #include <dt-bindings/pinctrl/sun4i-a10.h> |
Maxime Ripard | 2c89ce4f4 | 2016-08-31 14:58:20 +0200 | [diff] [blame] | 51 | #include <dt-bindings/reset/sun8i-a23-a33-ccu.h> |
Vishnu Patekar | a0e9e9b | 2015-05-30 16:55:03 +0200 | [diff] [blame] | 52 | |
| 53 | / { |
| 54 | interrupt-parent = <&gic>; |
| 55 | |
| 56 | chosen { |
| 57 | #address-cells = <1>; |
| 58 | #size-cells = <1>; |
| 59 | ranges; |
| 60 | |
Chen-Yu Tsai | aea4c39 | 2015-11-17 00:38:25 +0800 | [diff] [blame] | 61 | simplefb_lcd: framebuffer@0 { |
Vishnu Patekar | a0e9e9b | 2015-05-30 16:55:03 +0200 | [diff] [blame] | 62 | compatible = "allwinner,simple-framebuffer", |
| 63 | "simple-framebuffer"; |
| 64 | allwinner,pipeline = "de_be0-lcd0"; |
Maxime Ripard | 2c89ce4f4 | 2016-08-31 14:58:20 +0200 | [diff] [blame] | 65 | clocks = <&ccu CLK_BUS_LCD>, <&ccu CLK_BUS_DE_BE>, |
| 66 | <&ccu CLK_LCD_CH0>, <&ccu CLK_DE_BE>, |
| 67 | <&ccu CLK_DRAM_DE_BE>, <&ccu CLK_DRC>; |
Vishnu Patekar | a0e9e9b | 2015-05-30 16:55:03 +0200 | [diff] [blame] | 68 | status = "disabled"; |
| 69 | }; |
| 70 | }; |
| 71 | |
| 72 | timer { |
| 73 | compatible = "arm,armv7-timer"; |
| 74 | interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
| 75 | <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
| 76 | <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
| 77 | <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; |
| 78 | clock-frequency = <24000000>; |
| 79 | arm,cpu-registers-not-fw-configured; |
| 80 | }; |
| 81 | |
| 82 | cpus { |
| 83 | enable-method = "allwinner,sun8i-a23"; |
| 84 | #address-cells = <1>; |
| 85 | #size-cells = <0>; |
| 86 | |
| 87 | cpu@0 { |
| 88 | compatible = "arm,cortex-a7"; |
| 89 | device_type = "cpu"; |
| 90 | reg = <0>; |
| 91 | }; |
| 92 | |
| 93 | cpu@1 { |
| 94 | compatible = "arm,cortex-a7"; |
| 95 | device_type = "cpu"; |
| 96 | reg = <1>; |
| 97 | }; |
| 98 | }; |
| 99 | |
| 100 | clocks { |
| 101 | #address-cells = <1>; |
| 102 | #size-cells = <1>; |
| 103 | ranges; |
| 104 | |
| 105 | osc24M: osc24M_clk { |
| 106 | #clock-cells = <0>; |
| 107 | compatible = "fixed-clock"; |
| 108 | clock-frequency = <24000000>; |
| 109 | clock-output-names = "osc24M"; |
| 110 | }; |
| 111 | |
| 112 | osc32k: osc32k_clk { |
| 113 | #clock-cells = <0>; |
| 114 | compatible = "fixed-clock"; |
| 115 | clock-frequency = <32768>; |
| 116 | clock-output-names = "osc32k"; |
| 117 | }; |
Vishnu Patekar | a0e9e9b | 2015-05-30 16:55:03 +0200 | [diff] [blame] | 118 | }; |
| 119 | |
| 120 | soc@01c00000 { |
| 121 | compatible = "simple-bus"; |
| 122 | #address-cells = <1>; |
| 123 | #size-cells = <1>; |
| 124 | ranges; |
| 125 | |
| 126 | dma: dma-controller@01c02000 { |
| 127 | compatible = "allwinner,sun8i-a23-dma"; |
| 128 | reg = <0x01c02000 0x1000>; |
| 129 | interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; |
Maxime Ripard | 2c89ce4f4 | 2016-08-31 14:58:20 +0200 | [diff] [blame] | 130 | clocks = <&ccu CLK_BUS_DMA>; |
| 131 | resets = <&ccu RST_BUS_DMA>; |
Vishnu Patekar | a0e9e9b | 2015-05-30 16:55:03 +0200 | [diff] [blame] | 132 | #dma-cells = <1>; |
| 133 | }; |
| 134 | |
| 135 | mmc0: mmc@01c0f000 { |
Hans de Goede | 57af711 | 2016-07-30 16:25:48 +0200 | [diff] [blame] | 136 | compatible = "allwinner,sun7i-a20-mmc"; |
Vishnu Patekar | a0e9e9b | 2015-05-30 16:55:03 +0200 | [diff] [blame] | 137 | reg = <0x01c0f000 0x1000>; |
Maxime Ripard | 2c89ce4f4 | 2016-08-31 14:58:20 +0200 | [diff] [blame] | 138 | clocks = <&ccu CLK_BUS_MMC0>, |
| 139 | <&ccu CLK_MMC0>, |
| 140 | <&ccu CLK_MMC0_OUTPUT>, |
| 141 | <&ccu CLK_MMC0_SAMPLE>; |
Vishnu Patekar | a0e9e9b | 2015-05-30 16:55:03 +0200 | [diff] [blame] | 142 | clock-names = "ahb", |
| 143 | "mmc", |
| 144 | "output", |
| 145 | "sample"; |
Maxime Ripard | 2c89ce4f4 | 2016-08-31 14:58:20 +0200 | [diff] [blame] | 146 | resets = <&ccu RST_BUS_MMC0>; |
Vishnu Patekar | a0e9e9b | 2015-05-30 16:55:03 +0200 | [diff] [blame] | 147 | reset-names = "ahb"; |
| 148 | interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; |
| 149 | status = "disabled"; |
| 150 | #address-cells = <1>; |
| 151 | #size-cells = <0>; |
| 152 | }; |
| 153 | |
| 154 | mmc1: mmc@01c10000 { |
Hans de Goede | 57af711 | 2016-07-30 16:25:48 +0200 | [diff] [blame] | 155 | compatible = "allwinner,sun7i-a20-mmc"; |
Vishnu Patekar | a0e9e9b | 2015-05-30 16:55:03 +0200 | [diff] [blame] | 156 | reg = <0x01c10000 0x1000>; |
Maxime Ripard | 2c89ce4f4 | 2016-08-31 14:58:20 +0200 | [diff] [blame] | 157 | clocks = <&ccu CLK_BUS_MMC1>, |
| 158 | <&ccu CLK_MMC1>, |
| 159 | <&ccu CLK_MMC1_OUTPUT>, |
| 160 | <&ccu CLK_MMC1_SAMPLE>; |
Vishnu Patekar | a0e9e9b | 2015-05-30 16:55:03 +0200 | [diff] [blame] | 161 | clock-names = "ahb", |
| 162 | "mmc", |
| 163 | "output", |
| 164 | "sample"; |
Maxime Ripard | 2c89ce4f4 | 2016-08-31 14:58:20 +0200 | [diff] [blame] | 165 | resets = <&ccu RST_BUS_MMC1>; |
Vishnu Patekar | a0e9e9b | 2015-05-30 16:55:03 +0200 | [diff] [blame] | 166 | reset-names = "ahb"; |
| 167 | interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; |
| 168 | status = "disabled"; |
| 169 | #address-cells = <1>; |
| 170 | #size-cells = <0>; |
| 171 | }; |
| 172 | |
| 173 | mmc2: mmc@01c11000 { |
Hans de Goede | 57af711 | 2016-07-30 16:25:48 +0200 | [diff] [blame] | 174 | compatible = "allwinner,sun7i-a20-mmc"; |
Vishnu Patekar | a0e9e9b | 2015-05-30 16:55:03 +0200 | [diff] [blame] | 175 | reg = <0x01c11000 0x1000>; |
Maxime Ripard | 2c89ce4f4 | 2016-08-31 14:58:20 +0200 | [diff] [blame] | 176 | clocks = <&ccu CLK_BUS_MMC2>, |
| 177 | <&ccu CLK_MMC2>, |
| 178 | <&ccu CLK_MMC2_OUTPUT>, |
| 179 | <&ccu CLK_MMC2_SAMPLE>; |
Vishnu Patekar | a0e9e9b | 2015-05-30 16:55:03 +0200 | [diff] [blame] | 180 | clock-names = "ahb", |
| 181 | "mmc", |
| 182 | "output", |
| 183 | "sample"; |
Maxime Ripard | 2c89ce4f4 | 2016-08-31 14:58:20 +0200 | [diff] [blame] | 184 | resets = <&ccu RST_BUS_MMC2>; |
Vishnu Patekar | a0e9e9b | 2015-05-30 16:55:03 +0200 | [diff] [blame] | 185 | reset-names = "ahb"; |
| 186 | interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; |
| 187 | status = "disabled"; |
| 188 | #address-cells = <1>; |
| 189 | #size-cells = <0>; |
| 190 | }; |
| 191 | |
Icenowy Zheng | d7b843df | 2016-08-23 21:55:46 +0800 | [diff] [blame] | 192 | nfc: nand@01c03000 { |
| 193 | compatible = "allwinner,sun4i-a10-nand"; |
| 194 | reg = <0x01c03000 0x1000>; |
| 195 | interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; |
Maxime Ripard | 2c89ce4f4 | 2016-08-31 14:58:20 +0200 | [diff] [blame] | 196 | clocks = <&ccu CLK_BUS_NAND>, <&ccu CLK_NAND>; |
Icenowy Zheng | d7b843df | 2016-08-23 21:55:46 +0800 | [diff] [blame] | 197 | clock-names = "ahb", "mod"; |
Maxime Ripard | 2c89ce4f4 | 2016-08-31 14:58:20 +0200 | [diff] [blame] | 198 | resets = <&ccu RST_BUS_NAND>; |
Icenowy Zheng | d7b843df | 2016-08-23 21:55:46 +0800 | [diff] [blame] | 199 | reset-names = "ahb"; |
| 200 | status = "disabled"; |
| 201 | #address-cells = <1>; |
| 202 | #size-cells = <0>; |
| 203 | }; |
| 204 | |
Chen-Yu Tsai | bd33544 | 2016-09-08 11:25:35 +0800 | [diff] [blame] | 205 | usb_otg: usb@01c19000 { |
| 206 | /* compatible gets set in SoC specific dtsi file */ |
| 207 | reg = <0x01c19000 0x0400>; |
| 208 | clocks = <&ccu CLK_BUS_OTG>; |
| 209 | resets = <&ccu RST_BUS_OTG>; |
| 210 | interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; |
| 211 | interrupt-names = "mc"; |
| 212 | phys = <&usbphy 0>; |
| 213 | phy-names = "usb"; |
| 214 | extcon = <&usbphy 0>; |
| 215 | status = "disabled"; |
| 216 | }; |
| 217 | |
| 218 | usbphy: phy@01c19400 { |
| 219 | /* |
| 220 | * compatible and address regions get set in |
| 221 | * SoC specific dtsi file |
| 222 | */ |
| 223 | clocks = <&ccu CLK_USB_PHY0>, |
| 224 | <&ccu CLK_USB_PHY1>; |
| 225 | clock-names = "usb0_phy", |
| 226 | "usb1_phy"; |
| 227 | resets = <&ccu RST_USB_PHY0>, |
| 228 | <&ccu RST_USB_PHY1>; |
| 229 | reset-names = "usb0_reset", |
| 230 | "usb1_reset"; |
| 231 | status = "disabled"; |
| 232 | #phy-cells = <1>; |
| 233 | }; |
| 234 | |
Chen-Yu Tsai | e385c09 | 2015-06-02 20:29:11 +0800 | [diff] [blame] | 235 | ehci0: usb@01c1a000 { |
| 236 | compatible = "allwinner,sun8i-a23-ehci", "generic-ehci"; |
| 237 | reg = <0x01c1a000 0x100>; |
| 238 | interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; |
Maxime Ripard | 2c89ce4f4 | 2016-08-31 14:58:20 +0200 | [diff] [blame] | 239 | clocks = <&ccu CLK_BUS_EHCI>; |
| 240 | resets = <&ccu RST_BUS_EHCI>; |
Chen-Yu Tsai | e385c09 | 2015-06-02 20:29:11 +0800 | [diff] [blame] | 241 | phys = <&usbphy 1>; |
| 242 | phy-names = "usb"; |
| 243 | status = "disabled"; |
| 244 | }; |
| 245 | |
| 246 | ohci0: usb@01c1a400 { |
| 247 | compatible = "allwinner,sun8i-a23-ohci", "generic-ohci"; |
| 248 | reg = <0x01c1a400 0x100>; |
| 249 | interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; |
Maxime Ripard | 2c89ce4f4 | 2016-08-31 14:58:20 +0200 | [diff] [blame] | 250 | clocks = <&ccu CLK_BUS_OHCI>, <&ccu CLK_USB_OHCI>; |
| 251 | resets = <&ccu RST_BUS_OHCI>; |
Chen-Yu Tsai | e385c09 | 2015-06-02 20:29:11 +0800 | [diff] [blame] | 252 | phys = <&usbphy 1>; |
| 253 | phy-names = "usb"; |
| 254 | status = "disabled"; |
| 255 | }; |
| 256 | |
Maxime Ripard | 2c89ce4f4 | 2016-08-31 14:58:20 +0200 | [diff] [blame] | 257 | ccu: clock@01c20000 { |
| 258 | reg = <0x01c20000 0x400>; |
| 259 | clocks = <&osc24M>, <&osc32k>; |
| 260 | clock-names = "hosc", "losc"; |
| 261 | #clock-cells = <1>; |
| 262 | #reset-cells = <1>; |
| 263 | }; |
| 264 | |
Vishnu Patekar | a0e9e9b | 2015-05-30 16:55:03 +0200 | [diff] [blame] | 265 | pio: pinctrl@01c20800 { |
| 266 | /* compatible gets set in SoC specific dtsi file */ |
| 267 | reg = <0x01c20800 0x400>; |
| 268 | /* interrupts get set in SoC specific dtsi file */ |
Maxime Ripard | 2c89ce4f4 | 2016-08-31 14:58:20 +0200 | [diff] [blame] | 269 | clocks = <&ccu CLK_BUS_PIO>; |
Vishnu Patekar | a0e9e9b | 2015-05-30 16:55:03 +0200 | [diff] [blame] | 270 | gpio-controller; |
| 271 | interrupt-controller; |
Maxime Ripard | b03e081 | 2015-06-17 11:44:24 +0200 | [diff] [blame] | 272 | #interrupt-cells = <3>; |
Vishnu Patekar | a0e9e9b | 2015-05-30 16:55:03 +0200 | [diff] [blame] | 273 | #gpio-cells = <3>; |
| 274 | |
| 275 | uart0_pins_a: uart0@0 { |
| 276 | allwinner,pins = "PF2", "PF4"; |
| 277 | allwinner,function = "uart0"; |
| 278 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
| 279 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; |
| 280 | }; |
| 281 | |
Icenowy Zheng | 82eec38 | 2016-09-16 23:16:41 +0800 | [diff] [blame] | 282 | uart1_pins_a: uart1@0 { |
| 283 | allwinner,pins = "PG6", "PG7"; |
| 284 | allwinner,function = "uart1"; |
Icenowy Zheng | b7f865e | 2016-10-25 01:08:31 +0800 | [diff] [blame] | 285 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
| 286 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; |
Icenowy Zheng | 82eec38 | 2016-09-16 23:16:41 +0800 | [diff] [blame] | 287 | }; |
| 288 | |
| 289 | uart1_pins_cts_rts_a: uart1-cts-rts@0 { |
| 290 | allwinner,pins = "PG8", "PG9"; |
| 291 | allwinner,function = "uart1"; |
Icenowy Zheng | b7f865e | 2016-10-25 01:08:31 +0800 | [diff] [blame] | 292 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
| 293 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; |
Icenowy Zheng | 82eec38 | 2016-09-16 23:16:41 +0800 | [diff] [blame] | 294 | }; |
| 295 | |
Vishnu Patekar | a0e9e9b | 2015-05-30 16:55:03 +0200 | [diff] [blame] | 296 | mmc0_pins_a: mmc0@0 { |
| 297 | allwinner,pins = "PF0", "PF1", "PF2", |
| 298 | "PF3", "PF4", "PF5"; |
| 299 | allwinner,function = "mmc0"; |
| 300 | allwinner,drive = <SUN4I_PINCTRL_30_MA>; |
| 301 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; |
| 302 | }; |
| 303 | |
| 304 | mmc1_pins_a: mmc1@0 { |
| 305 | allwinner,pins = "PG0", "PG1", "PG2", |
| 306 | "PG3", "PG4", "PG5"; |
| 307 | allwinner,function = "mmc1"; |
| 308 | allwinner,drive = <SUN4I_PINCTRL_30_MA>; |
| 309 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; |
| 310 | }; |
| 311 | |
Chen-Yu Tsai | 93b129d | 2015-06-02 18:04:01 +0800 | [diff] [blame] | 312 | mmc2_8bit_pins: mmc2_8bit { |
| 313 | allwinner,pins = "PC5", "PC6", "PC8", |
| 314 | "PC9", "PC10", "PC11", |
| 315 | "PC12", "PC13", "PC14", |
Chen-Yu Tsai | 3b5d8dc | 2016-01-21 13:26:37 +0800 | [diff] [blame] | 316 | "PC15", "PC16"; |
Chen-Yu Tsai | 93b129d | 2015-06-02 18:04:01 +0800 | [diff] [blame] | 317 | allwinner,function = "mmc2"; |
| 318 | allwinner,drive = <SUN4I_PINCTRL_30_MA>; |
| 319 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; |
| 320 | }; |
| 321 | |
Chen-Yu Tsai | 29a0d08 | 2015-09-18 15:35:37 +0800 | [diff] [blame] | 322 | pwm0_pins: pwm0 { |
| 323 | allwinner,pins = "PH0"; |
| 324 | allwinner,function = "pwm0"; |
| 325 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
| 326 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; |
| 327 | }; |
| 328 | |
Vishnu Patekar | a0e9e9b | 2015-05-30 16:55:03 +0200 | [diff] [blame] | 329 | i2c0_pins_a: i2c0@0 { |
| 330 | allwinner,pins = "PH2", "PH3"; |
| 331 | allwinner,function = "i2c0"; |
| 332 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
| 333 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; |
| 334 | }; |
| 335 | |
| 336 | i2c1_pins_a: i2c1@0 { |
| 337 | allwinner,pins = "PH4", "PH5"; |
| 338 | allwinner,function = "i2c1"; |
| 339 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
| 340 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; |
| 341 | }; |
| 342 | |
| 343 | i2c2_pins_a: i2c2@0 { |
| 344 | allwinner,pins = "PE12", "PE13"; |
| 345 | allwinner,function = "i2c2"; |
| 346 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
| 347 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; |
| 348 | }; |
Vishnu Patekar | a0e9e9b | 2015-05-30 16:55:03 +0200 | [diff] [blame] | 349 | |
Maxime Ripard | 3353bed | 2016-06-09 13:56:21 +0200 | [diff] [blame] | 350 | lcd_rgb666_pins: lcd-rgb666@0 { |
| 351 | allwinner,pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7", |
| 352 | "PD10", "PD11", "PD12", "PD13", "PD14", "PD15", |
| 353 | "PD18", "PD19", "PD20", "PD21", "PD22", "PD23", |
| 354 | "PD24", "PD25", "PD26", "PD27"; |
| 355 | allwinner,function = "lcd0"; |
| 356 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
| 357 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; |
| 358 | }; |
Vishnu Patekar | a0e9e9b | 2015-05-30 16:55:03 +0200 | [diff] [blame] | 359 | }; |
| 360 | |
| 361 | timer@01c20c00 { |
| 362 | compatible = "allwinner,sun4i-a10-timer"; |
| 363 | reg = <0x01c20c00 0xa0>; |
| 364 | interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, |
| 365 | <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; |
| 366 | clocks = <&osc24M>; |
| 367 | }; |
| 368 | |
| 369 | wdt0: watchdog@01c20ca0 { |
| 370 | compatible = "allwinner,sun6i-a31-wdt"; |
| 371 | reg = <0x01c20ca0 0x20>; |
| 372 | interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; |
| 373 | }; |
| 374 | |
Chen-Yu Tsai | 832f977 | 2015-09-18 15:35:36 +0800 | [diff] [blame] | 375 | pwm: pwm@01c21400 { |
| 376 | compatible = "allwinner,sun7i-a20-pwm"; |
| 377 | reg = <0x01c21400 0xc>; |
| 378 | clocks = <&osc24M>; |
| 379 | #pwm-cells = <3>; |
| 380 | status = "disabled"; |
| 381 | }; |
| 382 | |
Vishnu Patekar | a0e9e9b | 2015-05-30 16:55:03 +0200 | [diff] [blame] | 383 | lradc: lradc@01c22800 { |
| 384 | compatible = "allwinner,sun4i-a10-lradc-keys"; |
| 385 | reg = <0x01c22800 0x100>; |
| 386 | interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; |
| 387 | status = "disabled"; |
| 388 | }; |
| 389 | |
| 390 | uart0: serial@01c28000 { |
| 391 | compatible = "snps,dw-apb-uart"; |
| 392 | reg = <0x01c28000 0x400>; |
| 393 | interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; |
| 394 | reg-shift = <2>; |
| 395 | reg-io-width = <4>; |
Maxime Ripard | 2c89ce4f4 | 2016-08-31 14:58:20 +0200 | [diff] [blame] | 396 | clocks = <&ccu CLK_BUS_UART0>; |
| 397 | resets = <&ccu RST_BUS_UART0>; |
Vishnu Patekar | a0e9e9b | 2015-05-30 16:55:03 +0200 | [diff] [blame] | 398 | dmas = <&dma 6>, <&dma 6>; |
| 399 | dma-names = "rx", "tx"; |
| 400 | status = "disabled"; |
| 401 | }; |
| 402 | |
| 403 | uart1: serial@01c28400 { |
| 404 | compatible = "snps,dw-apb-uart"; |
| 405 | reg = <0x01c28400 0x400>; |
| 406 | interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; |
| 407 | reg-shift = <2>; |
| 408 | reg-io-width = <4>; |
Maxime Ripard | 2c89ce4f4 | 2016-08-31 14:58:20 +0200 | [diff] [blame] | 409 | clocks = <&ccu CLK_BUS_UART1>; |
| 410 | resets = <&ccu RST_BUS_UART1>; |
Vishnu Patekar | a0e9e9b | 2015-05-30 16:55:03 +0200 | [diff] [blame] | 411 | dmas = <&dma 7>, <&dma 7>; |
| 412 | dma-names = "rx", "tx"; |
| 413 | status = "disabled"; |
| 414 | }; |
| 415 | |
| 416 | uart2: serial@01c28800 { |
| 417 | compatible = "snps,dw-apb-uart"; |
| 418 | reg = <0x01c28800 0x400>; |
| 419 | interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; |
| 420 | reg-shift = <2>; |
| 421 | reg-io-width = <4>; |
Maxime Ripard | 2c89ce4f4 | 2016-08-31 14:58:20 +0200 | [diff] [blame] | 422 | clocks = <&ccu CLK_BUS_UART2>; |
| 423 | resets = <&ccu RST_BUS_UART2>; |
Vishnu Patekar | a0e9e9b | 2015-05-30 16:55:03 +0200 | [diff] [blame] | 424 | dmas = <&dma 8>, <&dma 8>; |
| 425 | dma-names = "rx", "tx"; |
| 426 | status = "disabled"; |
| 427 | }; |
| 428 | |
| 429 | uart3: serial@01c28c00 { |
| 430 | compatible = "snps,dw-apb-uart"; |
| 431 | reg = <0x01c28c00 0x400>; |
| 432 | interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; |
| 433 | reg-shift = <2>; |
| 434 | reg-io-width = <4>; |
Maxime Ripard | 2c89ce4f4 | 2016-08-31 14:58:20 +0200 | [diff] [blame] | 435 | clocks = <&ccu CLK_BUS_UART3>; |
| 436 | resets = <&ccu RST_BUS_UART3>; |
Vishnu Patekar | a0e9e9b | 2015-05-30 16:55:03 +0200 | [diff] [blame] | 437 | dmas = <&dma 9>, <&dma 9>; |
| 438 | dma-names = "rx", "tx"; |
| 439 | status = "disabled"; |
| 440 | }; |
| 441 | |
| 442 | uart4: serial@01c29000 { |
| 443 | compatible = "snps,dw-apb-uart"; |
| 444 | reg = <0x01c29000 0x400>; |
| 445 | interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; |
| 446 | reg-shift = <2>; |
| 447 | reg-io-width = <4>; |
Maxime Ripard | 2c89ce4f4 | 2016-08-31 14:58:20 +0200 | [diff] [blame] | 448 | clocks = <&ccu CLK_BUS_UART4>; |
| 449 | resets = <&ccu RST_BUS_UART4>; |
Vishnu Patekar | a0e9e9b | 2015-05-30 16:55:03 +0200 | [diff] [blame] | 450 | dmas = <&dma 10>, <&dma 10>; |
| 451 | dma-names = "rx", "tx"; |
| 452 | status = "disabled"; |
| 453 | }; |
| 454 | |
| 455 | i2c0: i2c@01c2ac00 { |
| 456 | compatible = "allwinner,sun6i-a31-i2c"; |
| 457 | reg = <0x01c2ac00 0x400>; |
| 458 | interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; |
Maxime Ripard | 2c89ce4f4 | 2016-08-31 14:58:20 +0200 | [diff] [blame] | 459 | clocks = <&ccu CLK_BUS_I2C0>; |
| 460 | resets = <&ccu RST_BUS_I2C0>; |
Vishnu Patekar | a0e9e9b | 2015-05-30 16:55:03 +0200 | [diff] [blame] | 461 | status = "disabled"; |
| 462 | #address-cells = <1>; |
| 463 | #size-cells = <0>; |
| 464 | }; |
| 465 | |
| 466 | i2c1: i2c@01c2b000 { |
| 467 | compatible = "allwinner,sun6i-a31-i2c"; |
| 468 | reg = <0x01c2b000 0x400>; |
| 469 | interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; |
Maxime Ripard | 2c89ce4f4 | 2016-08-31 14:58:20 +0200 | [diff] [blame] | 470 | clocks = <&ccu CLK_BUS_I2C1>; |
| 471 | resets = <&ccu RST_BUS_I2C1>; |
Vishnu Patekar | a0e9e9b | 2015-05-30 16:55:03 +0200 | [diff] [blame] | 472 | status = "disabled"; |
| 473 | #address-cells = <1>; |
| 474 | #size-cells = <0>; |
| 475 | }; |
| 476 | |
| 477 | i2c2: i2c@01c2b400 { |
| 478 | compatible = "allwinner,sun6i-a31-i2c"; |
| 479 | reg = <0x01c2b400 0x400>; |
| 480 | interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; |
Maxime Ripard | 2c89ce4f4 | 2016-08-31 14:58:20 +0200 | [diff] [blame] | 481 | clocks = <&ccu CLK_BUS_I2C2>; |
| 482 | resets = <&ccu RST_BUS_I2C2>; |
Vishnu Patekar | a0e9e9b | 2015-05-30 16:55:03 +0200 | [diff] [blame] | 483 | status = "disabled"; |
| 484 | #address-cells = <1>; |
| 485 | #size-cells = <0>; |
| 486 | }; |
| 487 | |
| 488 | gic: interrupt-controller@01c81000 { |
| 489 | compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; |
| 490 | reg = <0x01c81000 0x1000>, |
| 491 | <0x01c82000 0x1000>, |
| 492 | <0x01c84000 0x2000>, |
| 493 | <0x01c86000 0x2000>; |
| 494 | interrupt-controller; |
| 495 | #interrupt-cells = <3>; |
| 496 | interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; |
| 497 | }; |
| 498 | |
| 499 | rtc: rtc@01f00000 { |
| 500 | compatible = "allwinner,sun6i-a31-rtc"; |
| 501 | reg = <0x01f00000 0x54>; |
| 502 | interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, |
| 503 | <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; |
| 504 | }; |
| 505 | |
Chen-Yu Tsai | 6c06796 | 2015-10-15 00:32:21 +0800 | [diff] [blame] | 506 | nmi_intc: interrupt-controller@01f00c0c { |
| 507 | compatible = "allwinner,sun6i-a31-sc-nmi"; |
| 508 | interrupt-controller; |
| 509 | #interrupt-cells = <2>; |
| 510 | reg = <0x01f00c0c 0x38>; |
| 511 | interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; |
| 512 | }; |
| 513 | |
Vishnu Patekar | a0e9e9b | 2015-05-30 16:55:03 +0200 | [diff] [blame] | 514 | prcm@01f01400 { |
| 515 | compatible = "allwinner,sun8i-a23-prcm"; |
| 516 | reg = <0x01f01400 0x200>; |
| 517 | |
| 518 | ar100: ar100_clk { |
| 519 | compatible = "fixed-factor-clock"; |
| 520 | #clock-cells = <0>; |
| 521 | clock-div = <1>; |
| 522 | clock-mult = <1>; |
| 523 | clocks = <&osc24M>; |
| 524 | clock-output-names = "ar100"; |
| 525 | }; |
| 526 | |
| 527 | ahb0: ahb0_clk { |
| 528 | compatible = "fixed-factor-clock"; |
| 529 | #clock-cells = <0>; |
| 530 | clock-div = <1>; |
| 531 | clock-mult = <1>; |
| 532 | clocks = <&ar100>; |
| 533 | clock-output-names = "ahb0"; |
| 534 | }; |
| 535 | |
| 536 | apb0: apb0_clk { |
| 537 | compatible = "allwinner,sun8i-a23-apb0-clk"; |
| 538 | #clock-cells = <0>; |
| 539 | clocks = <&ahb0>; |
| 540 | clock-output-names = "apb0"; |
| 541 | }; |
| 542 | |
| 543 | apb0_gates: apb0_gates_clk { |
| 544 | compatible = "allwinner,sun8i-a23-apb0-gates-clk"; |
| 545 | #clock-cells = <1>; |
| 546 | clocks = <&apb0>; |
| 547 | clock-output-names = "apb0_pio", "apb0_timer", |
| 548 | "apb0_rsb", "apb0_uart", |
| 549 | "apb0_i2c"; |
| 550 | }; |
| 551 | |
| 552 | apb0_rst: apb0_rst { |
| 553 | compatible = "allwinner,sun6i-a31-clock-reset"; |
| 554 | #reset-cells = <1>; |
| 555 | }; |
| 556 | }; |
| 557 | |
| 558 | cpucfg@01f01c00 { |
| 559 | compatible = "allwinner,sun8i-a23-cpuconfig"; |
| 560 | reg = <0x01f01c00 0x300>; |
| 561 | }; |
| 562 | |
| 563 | r_uart: serial@01f02800 { |
| 564 | compatible = "snps,dw-apb-uart"; |
| 565 | reg = <0x01f02800 0x400>; |
| 566 | interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; |
| 567 | reg-shift = <2>; |
| 568 | reg-io-width = <4>; |
| 569 | clocks = <&apb0_gates 4>; |
| 570 | resets = <&apb0_rst 4>; |
| 571 | status = "disabled"; |
| 572 | }; |
| 573 | |
| 574 | r_pio: pinctrl@01f02c00 { |
| 575 | compatible = "allwinner,sun8i-a23-r-pinctrl"; |
| 576 | reg = <0x01f02c00 0x400>; |
| 577 | interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; |
| 578 | clocks = <&apb0_gates 0>; |
| 579 | resets = <&apb0_rst 0>; |
| 580 | gpio-controller; |
| 581 | interrupt-controller; |
Hans de Goede | 6d55d33 | 2015-10-15 16:28:45 +0200 | [diff] [blame] | 582 | #interrupt-cells = <3>; |
Vishnu Patekar | a0e9e9b | 2015-05-30 16:55:03 +0200 | [diff] [blame] | 583 | #address-cells = <1>; |
| 584 | #size-cells = <0>; |
| 585 | #gpio-cells = <3>; |
| 586 | |
Chen-Yu Tsai | 79d05ec | 2015-10-01 19:57:49 +0800 | [diff] [blame] | 587 | r_rsb_pins: r_rsb { |
| 588 | allwinner,pins = "PL0", "PL1"; |
| 589 | allwinner,function = "s_rsb"; |
| 590 | allwinner,drive = <SUN4I_PINCTRL_20_MA>; |
| 591 | allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; |
| 592 | }; |
| 593 | |
Vishnu Patekar | a0e9e9b | 2015-05-30 16:55:03 +0200 | [diff] [blame] | 594 | r_uart_pins_a: r_uart@0 { |
| 595 | allwinner,pins = "PL2", "PL3"; |
| 596 | allwinner,function = "s_uart"; |
| 597 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
| 598 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; |
| 599 | }; |
| 600 | }; |
Chen-Yu Tsai | 79d05ec | 2015-10-01 19:57:49 +0800 | [diff] [blame] | 601 | |
| 602 | r_rsb: rsb@01f03400 { |
| 603 | compatible = "allwinner,sun8i-a23-rsb"; |
| 604 | reg = <0x01f03400 0x400>; |
| 605 | interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; |
| 606 | clocks = <&apb0_gates 3>; |
| 607 | clock-frequency = <3000000>; |
| 608 | resets = <&apb0_rst 3>; |
| 609 | pinctrl-names = "default"; |
| 610 | pinctrl-0 = <&r_rsb_pins>; |
| 611 | status = "disabled"; |
| 612 | #address-cells = <1>; |
| 613 | #size-cells = <0>; |
| 614 | }; |
Vishnu Patekar | a0e9e9b | 2015-05-30 16:55:03 +0200 | [diff] [blame] | 615 | }; |
| 616 | }; |