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Jon Masonfce8a7b2012-11-16 19:27:12 -07001/*
2 * This file is provided under a dual BSD/GPLv2 license. When using or
3 * redistributing this file, you may do so under either license.
4 *
5 * GPL LICENSE SUMMARY
6 *
7 * Copyright(c) 2012 Intel Corporation. All rights reserved.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of version 2 of the GNU General Public License as
11 * published by the Free Software Foundation.
12 *
13 * BSD LICENSE
14 *
15 * Copyright(c) 2012 Intel Corporation. All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions
19 * are met:
20 *
21 * * Redistributions of source code must retain the above copyright
22 * notice, this list of conditions and the following disclaimer.
23 * * Redistributions in binary form must reproduce the above copy
24 * notice, this list of conditions and the following disclaimer in
25 * the documentation and/or other materials provided with the
26 * distribution.
27 * * Neither the name of Intel Corporation nor the names of its
28 * contributors may be used to endorse or promote products derived
29 * from this software without specific prior written permission.
30 *
31 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
32 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
33 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
34 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
35 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
36 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
37 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
38 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
39 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
40 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
41 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
42 *
43 * Intel PCIe NTB Linux driver
44 *
45 * Contact Information:
46 * Jon Mason <jon.mason@intel.com>
47 */
48
Jon Masonfce8a7b2012-11-16 19:27:12 -070049#define NTB_LINK_STATUS_ACTIVE 0x2000
50#define NTB_LINK_SPEED_MASK 0x000f
51#define NTB_LINK_WIDTH_MASK 0x03f0
52
53#define SNB_MSIX_CNT 4
Jon Mason87034512013-07-15 15:26:14 -070054#define SNB_MAX_B2B_SPADS 16
55#define SNB_MAX_COMPAT_SPADS 16
Jon Masonfce8a7b2012-11-16 19:27:12 -070056/* Reserve the uppermost bit for link interrupt */
57#define SNB_MAX_DB_BITS 15
Jon Masonc529aa32013-09-06 16:51:16 -070058#define SNB_LINK_DB 15
Jon Masonfce8a7b2012-11-16 19:27:12 -070059#define SNB_DB_BITS_PER_VEC 5
Dave Jiangab760a02014-08-28 13:53:23 -070060#define HSX_SPLITBAR_MAX_MW 3
Jon Mason948d3a62013-04-18 17:07:36 -070061#define SNB_MAX_MW 2
62#define SNB_ERRATA_MAX_MW 1
Jon Masonfce8a7b2012-11-16 19:27:12 -070063
64#define SNB_DB_HW_LINK 0x8000
65
Jon Mason6465d022014-04-07 10:55:47 -070066#define SNB_UNCERRSTS_OFFSET 0x014C
67#define SNB_CORERRSTS_OFFSET 0x0158
68#define SNB_LINK_STATUS_OFFSET 0x01A2
Jon Masonfce8a7b2012-11-16 19:27:12 -070069#define SNB_PCICMD_OFFSET 0x0504
70#define SNB_DEVCTRL_OFFSET 0x0598
Jon Mason6465d022014-04-07 10:55:47 -070071#define SNB_DEVSTS_OFFSET 0x059A
Jon Masoned6c24e2013-07-15 16:43:54 -070072#define SNB_SLINK_STATUS_OFFSET 0x05A2
Jon Masonfce8a7b2012-11-16 19:27:12 -070073
74#define SNB_PBAR2LMT_OFFSET 0x0000
75#define SNB_PBAR4LMT_OFFSET 0x0008
Dave Jiangab760a02014-08-28 13:53:23 -070076#define SNB_PBAR5LMT_OFFSET 0x000C
Jon Masonfce8a7b2012-11-16 19:27:12 -070077#define SNB_PBAR2XLAT_OFFSET 0x0010
78#define SNB_PBAR4XLAT_OFFSET 0x0018
Dave Jiangab760a02014-08-28 13:53:23 -070079#define SNB_PBAR5XLAT_OFFSET 0x001C
Jon Masonfce8a7b2012-11-16 19:27:12 -070080#define SNB_SBAR2LMT_OFFSET 0x0020
81#define SNB_SBAR4LMT_OFFSET 0x0028
Dave Jiangab760a02014-08-28 13:53:23 -070082#define SNB_SBAR5LMT_OFFSET 0x002C
Jon Masonfce8a7b2012-11-16 19:27:12 -070083#define SNB_SBAR2XLAT_OFFSET 0x0030
84#define SNB_SBAR4XLAT_OFFSET 0x0038
Dave Jiangab760a02014-08-28 13:53:23 -070085#define SNB_SBAR5XLAT_OFFSET 0x003C
Jon Masonfce8a7b2012-11-16 19:27:12 -070086#define SNB_SBAR0BASE_OFFSET 0x0040
87#define SNB_SBAR2BASE_OFFSET 0x0048
88#define SNB_SBAR4BASE_OFFSET 0x0050
Dave Jiangab760a02014-08-28 13:53:23 -070089#define SNB_SBAR5BASE_OFFSET 0x0054
Jon Masonfce8a7b2012-11-16 19:27:12 -070090#define SNB_NTBCNTL_OFFSET 0x0058
91#define SNB_SBDF_OFFSET 0x005C
92#define SNB_PDOORBELL_OFFSET 0x0060
93#define SNB_PDBMSK_OFFSET 0x0062
94#define SNB_SDOORBELL_OFFSET 0x0064
95#define SNB_SDBMSK_OFFSET 0x0066
Jon Mason6465d022014-04-07 10:55:47 -070096#define SNB_USMEMMISS_OFFSET 0x0070
Jon Masonfce8a7b2012-11-16 19:27:12 -070097#define SNB_SPAD_OFFSET 0x0080
98#define SNB_SPADSEMA4_OFFSET 0x00c0
99#define SNB_WCCNTRL_OFFSET 0x00e0
100#define SNB_B2B_SPAD_OFFSET 0x0100
101#define SNB_B2B_DOORBELL_OFFSET 0x0140
Jon Mason948d3a62013-04-18 17:07:36 -0700102#define SNB_B2B_XLAT_OFFSETL 0x0144
103#define SNB_B2B_XLAT_OFFSETU 0x0148
104
Dave Jiangab760a02014-08-28 13:53:23 -0700105/*
106 * The addresses are setup so the 32bit BARs can function. Thus
107 * the addresses are all in 32bit space
108 */
109#define SNB_MBAR01_USD_ADDR 0x000000002100000CULL
110#define SNB_MBAR23_USD_ADDR 0x000000004100000CULL
111#define SNB_MBAR4_USD_ADDR 0x000000008100000CULL
112#define SNB_MBAR5_USD_ADDR 0x00000000A100000CULL
113#define SNB_MBAR01_DSD_ADDR 0x000000002000000CULL
114#define SNB_MBAR23_DSD_ADDR 0x000000004000000CULL
115#define SNB_MBAR4_DSD_ADDR 0x000000008000000CULL
116#define SNB_MBAR5_DSD_ADDR 0x00000000A000000CULL
Jon Masonfce8a7b2012-11-16 19:27:12 -0700117
118#define BWD_MSIX_CNT 34
119#define BWD_MAX_SPADS 16
Jon Masonfce8a7b2012-11-16 19:27:12 -0700120#define BWD_MAX_DB_BITS 34
121#define BWD_DB_BITS_PER_VEC 1
Jon Mason948d3a62013-04-18 17:07:36 -0700122#define BWD_MAX_MW 2
Jon Masonfce8a7b2012-11-16 19:27:12 -0700123
124#define BWD_PCICMD_OFFSET 0xb004
125#define BWD_MBAR23_OFFSET 0xb018
126#define BWD_MBAR45_OFFSET 0xb020
127#define BWD_DEVCTRL_OFFSET 0xb048
128#define BWD_LINK_STATUS_OFFSET 0xb052
Jon Mason113bf1c2012-11-16 18:52:57 -0700129#define BWD_ERRCORSTS_OFFSET 0xb110
Jon Masonfce8a7b2012-11-16 19:27:12 -0700130
131#define BWD_SBAR2XLAT_OFFSET 0x0008
132#define BWD_SBAR4XLAT_OFFSET 0x0010
133#define BWD_PDOORBELL_OFFSET 0x0020
134#define BWD_PDBMSK_OFFSET 0x0028
135#define BWD_NTBCNTL_OFFSET 0x0060
136#define BWD_EBDF_OFFSET 0x0064
137#define BWD_SPAD_OFFSET 0x0080
138#define BWD_SPADSEMA_OFFSET 0x00c0
139#define BWD_STKYSPAD_OFFSET 0x00c4
140#define BWD_PBAR2XLAT_OFFSET 0x8008
141#define BWD_PBAR4XLAT_OFFSET 0x8010
142#define BWD_B2B_DOORBELL_OFFSET 0x8020
143#define BWD_B2B_SPAD_OFFSET 0x8080
144#define BWD_B2B_SPADSEMA_OFFSET 0x80c0
145#define BWD_B2B_STKYSPAD_OFFSET 0x80c4
146
Jon Mason113bf1c2012-11-16 18:52:57 -0700147#define BWD_MODPHY_PCSREG4 0x1c004
148#define BWD_MODPHY_PCSREG6 0x1c006
149
150#define BWD_IP_BASE 0xC000
151#define BWD_DESKEWSTS_OFFSET (BWD_IP_BASE + 0x3024)
152#define BWD_LTSSMERRSTS0_OFFSET (BWD_IP_BASE + 0x3180)
153#define BWD_LTSSMSTATEJMP_OFFSET (BWD_IP_BASE + 0x3040)
154#define BWD_IBSTERRRCRVSTS0_OFFSET (BWD_IP_BASE + 0x3324)
155
156#define BWD_DESKEWSTS_DBERR (1 << 15)
157#define BWD_LTSSMERRSTS0_UNEXPECTEDEI (1 << 20)
158#define BWD_LTSSMSTATEJMP_FORCEDETECT (1 << 2)
159#define BWD_IBIST_ERR_OFLOW 0x7FFF7FFF
160
Jon Mason78958432013-10-03 17:24:03 -0700161#define NTB_CNTL_CFG_LOCK (1 << 0)
162#define NTB_CNTL_LINK_DISABLE (1 << 1)
163#define NTB_CNTL_S2P_BAR23_SNOOP (1 << 2)
164#define NTB_CNTL_P2S_BAR23_SNOOP (1 << 4)
Dave Jiangab760a02014-08-28 13:53:23 -0700165#define NTB_CNTL_S2P_BAR4_SNOOP (1 << 6)
166#define NTB_CNTL_P2S_BAR4_SNOOP (1 << 8)
167#define NTB_CNTL_S2P_BAR5_SNOOP (1 << 12)
168#define NTB_CNTL_P2S_BAR5_SNOOP (1 << 14)
Jon Mason78958432013-10-03 17:24:03 -0700169#define BWD_CNTL_LINK_DOWN (1 << 16)
Jon Masonfce8a7b2012-11-16 19:27:12 -0700170
171#define NTB_PPD_OFFSET 0x00D4
172#define SNB_PPD_CONN_TYPE 0x0003
173#define SNB_PPD_DEV_TYPE 0x0010
Dave Jiangab760a02014-08-28 13:53:23 -0700174#define SNB_PPD_SPLIT_BAR (1 << 6)
Jon Masonfce8a7b2012-11-16 19:27:12 -0700175#define BWD_PPD_INIT_LINK 0x0008
176#define BWD_PPD_CONN_TYPE 0x0300
177#define BWD_PPD_DEV_TYPE 0x1000