Imran Khan | 04f0831 | 2017-03-30 15:07:43 +0530 | [diff] [blame] | 1 | /* Copyright (c) 2017, The Linux Foundation. All rights reserved. |
| 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | */ |
| 12 | |
| 13 | #include "skeleton64.dtsi" |
| 14 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
Odelu Kukatla | 1fe3a22 | 2017-06-01 16:24:59 +0530 | [diff] [blame] | 15 | #include <dt-bindings/clock/qcom,gcc-sdm845.h> |
| 16 | #include <dt-bindings/clock/qcom,camcc-sdm845.h> |
| 17 | #include <dt-bindings/clock/qcom,dispcc-sdm845.h> |
| 18 | #include <dt-bindings/clock/qcom,gpucc-sdm845.h> |
| 19 | #include <dt-bindings/clock/qcom,videocc-sdm845.h> |
| 20 | #include <dt-bindings/clock/qcom,cpucc-sdm845.h> |
| 21 | #include <dt-bindings/clock/qcom,rpmh.h> |
Tirupathi Reddy | 0cfe208 | 2017-06-08 14:24:13 +0530 | [diff] [blame] | 22 | #include <dt-bindings/regulator/qcom,rpmh-regulator.h> |
Imran Khan | 04f0831 | 2017-03-30 15:07:43 +0530 | [diff] [blame] | 23 | |
| 24 | / { |
| 25 | model = "Qualcomm Technologies, Inc. SDM670"; |
| 26 | compatible = "qcom,sdm670"; |
| 27 | qcom,msm-id = <336 0x0>; |
| 28 | interrupt-parent = <&intc>; |
| 29 | |
| 30 | aliases { }; |
| 31 | |
| 32 | cpus { |
| 33 | #address-cells = <2>; |
| 34 | #size-cells = <0>; |
| 35 | |
| 36 | CPU0: cpu@0 { |
| 37 | device_type = "cpu"; |
| 38 | compatible = "arm,armv8"; |
| 39 | reg = <0x0 0x0>; |
| 40 | enable-method = "psci"; |
| 41 | efficiency = <1024>; |
| 42 | cache-size = <0x8000>; |
| 43 | cpu-release-addr = <0x0 0x90000000>; |
| 44 | next-level-cache = <&L2_0>; |
| 45 | L2_0: l2-cache { |
| 46 | compatible = "arm,arch-cache"; |
| 47 | cache-size = <0x20000>; |
| 48 | cache-level = <2>; |
| 49 | next-level-cache = <&L3_0>; |
| 50 | L3_0: l3-cache { |
| 51 | compatible = "arm,arch-cache"; |
| 52 | cache-size = <0x100000>; |
| 53 | cache-level = <3>; |
| 54 | }; |
| 55 | }; |
| 56 | L1_I_0: l1-icache { |
| 57 | compatible = "arm,arch-cache"; |
| 58 | qcom,dump-size = <0x9000>; |
| 59 | }; |
| 60 | L1_D_0: l1-dcache { |
| 61 | compatible = "arm,arch-cache"; |
| 62 | qcom,dump-size = <0x9000>; |
| 63 | }; |
| 64 | }; |
| 65 | |
| 66 | CPU1: cpu@100 { |
| 67 | device_type = "cpu"; |
| 68 | compatible = "arm,armv8"; |
| 69 | reg = <0x0 0x100>; |
| 70 | enable-method = "psci"; |
| 71 | efficiency = <1024>; |
| 72 | cache-size = <0x8000>; |
| 73 | cpu-release-addr = <0x0 0x90000000>; |
| 74 | next-level-cache = <&L2_100>; |
| 75 | L2_100: l2-cache { |
| 76 | compatible = "arm,arch-cache"; |
| 77 | cache-size = <0x20000>; |
| 78 | cache-level = <2>; |
| 79 | next-level-cache = <&L3_0>; |
| 80 | }; |
| 81 | L1_I_100: l1-icache { |
| 82 | compatible = "arm,arch-cache"; |
| 83 | qcom,dump-size = <0x9000>; |
| 84 | }; |
| 85 | L1_D_100: l1-dcache { |
| 86 | compatible = "arm,arch-cache"; |
| 87 | qcom,dump-size = <0x9000>; |
| 88 | }; |
| 89 | }; |
| 90 | |
| 91 | CPU2: cpu@200 { |
| 92 | device_type = "cpu"; |
| 93 | compatible = "arm,armv8"; |
| 94 | reg = <0x0 0x200>; |
| 95 | enable-method = "psci"; |
| 96 | efficiency = <1024>; |
| 97 | cache-size = <0x8000>; |
| 98 | cpu-release-addr = <0x0 0x90000000>; |
| 99 | next-level-cache = <&L2_200>; |
| 100 | L2_200: l2-cache { |
| 101 | compatible = "arm,arch-cache"; |
| 102 | cache-size = <0x20000>; |
| 103 | cache-level = <2>; |
| 104 | next-level-cache = <&L3_0>; |
| 105 | }; |
| 106 | L1_I_200: l1-icache { |
| 107 | compatible = "arm,arch-cache"; |
| 108 | qcom,dump-size = <0x9000>; |
| 109 | }; |
| 110 | L1_D_200: l1-dcache { |
| 111 | compatible = "arm,arch-cache"; |
| 112 | qcom,dump-size = <0x9000>; |
| 113 | }; |
| 114 | }; |
| 115 | |
| 116 | CPU3: cpu@300 { |
| 117 | device_type = "cpu"; |
| 118 | compatible = "arm,armv8"; |
| 119 | reg = <0x0 0x300>; |
| 120 | enable-method = "psci"; |
| 121 | efficiency = <1024>; |
| 122 | cache-size = <0x8000>; |
| 123 | cpu-release-addr = <0x0 0x90000000>; |
| 124 | next-level-cache = <&L2_300>; |
| 125 | L2_300: l2-cache { |
| 126 | compatible = "arm,arch-cache"; |
| 127 | cache-size = <0x20000>; |
| 128 | cache-level = <2>; |
| 129 | next-level-cache = <&L3_0>; |
| 130 | }; |
| 131 | L1_I_300: l1-icache { |
| 132 | compatible = "arm,arch-cache"; |
| 133 | qcom,dump-size = <0x9000>; |
| 134 | }; |
| 135 | L1_D_300: l1-dcache { |
| 136 | compatible = "arm,arch-cache"; |
| 137 | qcom,dump-size = <0x9000>; |
| 138 | }; |
| 139 | }; |
| 140 | |
| 141 | CPU4: cpu@400 { |
| 142 | device_type = "cpu"; |
| 143 | compatible = "arm,armv8"; |
| 144 | reg = <0x0 0x400>; |
| 145 | enable-method = "psci"; |
| 146 | efficiency = <1024>; |
| 147 | cache-size = <0x8000>; |
| 148 | cpu-release-addr = <0x0 0x90000000>; |
| 149 | next-level-cache = <&L2_400>; |
| 150 | L2_400: l2-cache { |
| 151 | compatible = "arm,arch-cache"; |
| 152 | cache-size = <0x20000>; |
| 153 | cache-level = <2>; |
| 154 | next-level-cache = <&L3_0>; |
| 155 | }; |
| 156 | L1_I_400: l1-icache { |
| 157 | compatible = "arm,arch-cache"; |
| 158 | qcom,dump-size = <0x9000>; |
| 159 | }; |
| 160 | L1_D_400: l1-dcache { |
| 161 | compatible = "arm,arch-cache"; |
| 162 | qcom,dump-size = <0x9000>; |
| 163 | }; |
| 164 | }; |
| 165 | |
| 166 | CPU5: cpu@500 { |
| 167 | device_type = "cpu"; |
| 168 | compatible = "arm,armv8"; |
| 169 | reg = <0x0 0x500>; |
| 170 | enable-method = "psci"; |
| 171 | efficiency = <1024>; |
| 172 | cache-size = <0x8000>; |
| 173 | cpu-release-addr = <0x0 0x90000000>; |
| 174 | next-level-cache = <&L2_500>; |
| 175 | L2_500: l2-cache { |
| 176 | compatible = "arm,arch-cache"; |
| 177 | cache-size = <0x20000>; |
| 178 | cache-level = <2>; |
| 179 | next-level-cache = <&L3_0>; |
| 180 | }; |
| 181 | L1_I_500: l1-icache { |
| 182 | compatible = "arm,arch-cache"; |
| 183 | qcom,dump-size = <0x9000>; |
| 184 | }; |
| 185 | L1_D_500: l1-dcache { |
| 186 | compatible = "arm,arch-cache"; |
| 187 | qcom,dump-size = <0x9000>; |
| 188 | }; |
| 189 | }; |
| 190 | |
| 191 | CPU6: cpu@600 { |
| 192 | device_type = "cpu"; |
| 193 | compatible = "arm,armv8"; |
| 194 | reg = <0x0 0x600>; |
| 195 | enable-method = "psci"; |
| 196 | efficiency = <1740>; |
| 197 | cache-size = <0x10000>; |
| 198 | cpu-release-addr = <0x0 0x90000000>; |
| 199 | next-level-cache = <&L2_600>; |
| 200 | L2_600: l2-cache { |
| 201 | compatible = "arm,arch-cache"; |
| 202 | cache-size = <0x40000>; |
| 203 | cache-level = <2>; |
| 204 | next-level-cache = <&L3_0>; |
| 205 | }; |
| 206 | L1_I_600: l1-icache { |
| 207 | compatible = "arm,arch-cache"; |
| 208 | qcom,dump-size = <0x12000>; |
| 209 | }; |
| 210 | L1_D_600: l1-dcache { |
| 211 | compatible = "arm,arch-cache"; |
| 212 | qcom,dump-size = <0x12000>; |
| 213 | }; |
| 214 | }; |
| 215 | |
| 216 | CPU7: cpu@700 { |
| 217 | device_type = "cpu"; |
| 218 | compatible = "arm,armv8"; |
| 219 | reg = <0x0 0x700>; |
| 220 | enable-method = "psci"; |
| 221 | efficiency = <1740>; |
| 222 | cache-size = <0x10000>; |
| 223 | cpu-release-addr = <0x0 0x90000000>; |
| 224 | next-level-cache = <&L2_700>; |
| 225 | L2_700: l2-cache { |
| 226 | compatible = "arm,arch-cache"; |
| 227 | cache-size = <0x40000>; |
| 228 | cache-level = <2>; |
| 229 | next-level-cache = <&L3_0>; |
| 230 | }; |
| 231 | L1_I_700: l1-icache { |
| 232 | compatible = "arm,arch-cache"; |
| 233 | qcom,dump-size = <0x12000>; |
| 234 | }; |
| 235 | L1_D_700: l1-dcache { |
| 236 | compatible = "arm,arch-cache"; |
| 237 | qcom,dump-size = <0x12000>; |
| 238 | }; |
| 239 | }; |
| 240 | |
| 241 | cpu-map { |
| 242 | cluster0 { |
| 243 | core0 { |
| 244 | cpu = <&CPU0>; |
| 245 | }; |
| 246 | |
| 247 | core1 { |
| 248 | cpu = <&CPU1>; |
| 249 | }; |
| 250 | |
| 251 | core2 { |
| 252 | cpu = <&CPU2>; |
| 253 | }; |
| 254 | |
| 255 | core3 { |
| 256 | cpu = <&CPU3>; |
| 257 | }; |
| 258 | |
| 259 | core4 { |
| 260 | cpu = <&CPU4>; |
| 261 | }; |
| 262 | |
| 263 | core5 { |
| 264 | cpu = <&CPU5>; |
| 265 | }; |
| 266 | }; |
| 267 | cluster1 { |
| 268 | core0 { |
| 269 | cpu = <&CPU6>; |
| 270 | }; |
| 271 | |
| 272 | core1 { |
| 273 | cpu = <&CPU7>; |
| 274 | }; |
| 275 | }; |
| 276 | }; |
| 277 | }; |
| 278 | |
| 279 | psci { |
| 280 | compatible = "arm,psci-1.0"; |
| 281 | method = "smc"; |
| 282 | }; |
| 283 | |
| 284 | soc: soc { }; |
| 285 | |
| 286 | reserved-memory { |
| 287 | #address-cells = <2>; |
| 288 | #size-cells = <2>; |
| 289 | ranges; |
Vijayanand Jitta | a1ee786 | 2017-06-07 12:06:39 +0530 | [diff] [blame] | 290 | |
| 291 | removed_regions: removed_regions@85700000 { |
| 292 | compatible = "removed-dma-pool"; |
| 293 | no-map; |
| 294 | reg = <0 0x85700000 0 0x3800000>; |
| 295 | }; |
| 296 | |
| 297 | pil_camera_mem: camera_region@8ab00000 { |
| 298 | compatible = "removed-dma-pool"; |
| 299 | no-map; |
| 300 | reg = <0 0x8ab00000 0 0x500000>; |
| 301 | }; |
| 302 | |
| 303 | pil_modem_mem: modem_region@8b000000 { |
| 304 | compatible = "removed-dma-pool"; |
| 305 | no-map; |
| 306 | reg = <0 0x8b000000 0 0x7e00000>; |
| 307 | }; |
| 308 | |
| 309 | pil_video_mem: pil_video_region@92e00000 { |
| 310 | compatible = "removed-dma-pool"; |
| 311 | no-map; |
| 312 | reg = <0 0x92e00000 0 0x500000>; |
| 313 | }; |
| 314 | |
| 315 | pil_cdsp_mem: cdsp_regions@93300000 { |
| 316 | compatible = "removed-dma-pool"; |
| 317 | no-map; |
| 318 | reg = <0 0x93300000 0 0x600000>; |
| 319 | }; |
| 320 | |
| 321 | pil_mba_mem: pil_mba_region@0x93900000 { |
| 322 | compatible = "removed-dma-pool"; |
| 323 | no-map; |
| 324 | reg = <0 0x93900000 0 0x200000>; |
| 325 | }; |
| 326 | |
| 327 | pil_adsp_mem: pil_adsp_region@93b00000 { |
| 328 | compatible = "removed-dma-pool"; |
| 329 | no-map; |
| 330 | reg = <0 0x93b00000 0 0x1e00000>; |
| 331 | }; |
| 332 | |
| 333 | pil_ipa_fw_mem: pil_ipa_fw_region@95900000 { |
| 334 | compatible = "removed-dma-pool"; |
| 335 | no-map; |
| 336 | reg = <0 0x95900000 0 0x10000>; |
| 337 | }; |
| 338 | |
| 339 | pil_ipa_gsi_mem: pil_ipa_gsi_region@95910000 { |
| 340 | compatible = "removed-dma-pool"; |
| 341 | no-map; |
| 342 | reg = <0 0x95910000 0 0x5000>; |
| 343 | }; |
| 344 | |
| 345 | pil_gpu_mem: pil_gpu_region@95915000 { |
| 346 | compatible = "removed-dma-pool"; |
| 347 | no-map; |
| 348 | reg = <0 0x95915000 0 0x1000>; |
| 349 | }; |
| 350 | |
| 351 | adsp_mem: adsp_region { |
| 352 | compatible = "shared-dma-pool"; |
| 353 | alloc-ranges = <0 0x00000000 0 0xffffffff>; |
| 354 | reusable; |
| 355 | alignment = <0 0x400000>; |
| 356 | size = <0 0xc00000>; |
| 357 | }; |
| 358 | |
| 359 | qseecom_mem: qseecom_region { |
| 360 | compatible = "shared-dma-pool"; |
| 361 | alloc-ranges = <0 0x00000000 0 0xffffffff>; |
| 362 | reusable; |
| 363 | alignment = <0 0x400000>; |
| 364 | size = <0 0x1400000>; |
| 365 | }; |
| 366 | |
| 367 | sp_mem: sp_region { /* SPSS-HLOS ION shared mem */ |
| 368 | compatible = "shared-dma-pool"; |
| 369 | alloc-ranges = <0 0x00000000 0 0xffffffff>; /* 32-bit */ |
| 370 | reusable; |
| 371 | alignment = <0 0x400000>; |
| 372 | size = <0 0x800000>; |
| 373 | }; |
| 374 | |
| 375 | secure_display_memory: secure_display_region { |
| 376 | compatible = "shared-dma-pool"; |
| 377 | alloc-ranges = <0 0x00000000 0 0xffffffff>; |
| 378 | reusable; |
| 379 | alignment = <0 0x400000>; |
| 380 | size = <0 0x5c00000>; |
| 381 | }; |
| 382 | |
| 383 | /* global autoconfigured region for contiguous allocations */ |
| 384 | linux,cma { |
| 385 | compatible = "shared-dma-pool"; |
| 386 | alloc-ranges = <0 0x00000000 0 0xffffffff>; |
| 387 | reusable; |
| 388 | alignment = <0 0x400000>; |
| 389 | size = <0 0x2000000>; |
| 390 | linux,cma-default; |
| 391 | }; |
Imran Khan | 04f0831 | 2017-03-30 15:07:43 +0530 | [diff] [blame] | 392 | }; |
| 393 | }; |
| 394 | |
Vijayanand Jitta | a1ee786 | 2017-06-07 12:06:39 +0530 | [diff] [blame] | 395 | #include "sdm670-ion.dtsi" |
| 396 | |
Mukesh Kumar Savaliya | 065ca48 | 2017-06-06 14:44:45 +0530 | [diff] [blame] | 397 | #include "sdm670-qupv3.dtsi" |
| 398 | |
Imran Khan | 04f0831 | 2017-03-30 15:07:43 +0530 | [diff] [blame] | 399 | &soc { |
| 400 | #address-cells = <1>; |
| 401 | #size-cells = <1>; |
| 402 | ranges = <0 0 0 0xffffffff>; |
| 403 | compatible = "simple-bus"; |
| 404 | |
| 405 | intc: interrupt-controller@17a00000 { |
| 406 | compatible = "arm,gic-v3"; |
| 407 | #interrupt-cells = <3>; |
| 408 | interrupt-controller; |
| 409 | #redistributor-regions = <1>; |
| 410 | redistributor-stride = <0x0 0x20000>; |
| 411 | reg = <0x17a00000 0x10000>, /* GICD */ |
| 412 | <0x17a60000 0x100000>; /* GICR * 8 */ |
| 413 | interrupts = <1 9 4>; |
| 414 | }; |
| 415 | |
| 416 | timer { |
| 417 | compatible = "arm,armv8-timer"; |
| 418 | interrupts = <1 1 0xf08>, |
| 419 | <1 2 0xf08>, |
| 420 | <1 3 0xf08>, |
| 421 | <1 0 0xf08>; |
| 422 | clock-frequency = <19200000>; |
| 423 | }; |
| 424 | |
Lakshmi Sunkara | bbd6989 | 2017-06-09 13:17:10 +0530 | [diff] [blame] | 425 | qcom,sps { |
| 426 | compatible = "qcom,msm_sps_4k"; |
| 427 | qcom,pipe-attr-ee; |
| 428 | }; |
| 429 | |
Imran Khan | 04f0831 | 2017-03-30 15:07:43 +0530 | [diff] [blame] | 430 | timer@0x17c90000{ |
| 431 | #address-cells = <1>; |
| 432 | #size-cells = <1>; |
| 433 | ranges; |
| 434 | compatible = "arm,armv7-timer-mem"; |
| 435 | reg = <0x17c90000 0x1000>; |
| 436 | clock-frequency = <19200000>; |
| 437 | |
| 438 | frame@0x17ca0000 { |
| 439 | frame-number = <0>; |
| 440 | interrupts = <0 7 0x4>, |
| 441 | <0 6 0x4>; |
| 442 | reg = <0x17ca0000 0x1000>, |
| 443 | <0x17cb0000 0x1000>; |
| 444 | }; |
| 445 | |
| 446 | frame@17cc0000 { |
| 447 | frame-number = <1>; |
| 448 | interrupts = <0 8 0x4>; |
| 449 | reg = <0x17cc0000 0x1000>; |
| 450 | status = "disabled"; |
| 451 | }; |
| 452 | |
| 453 | frame@17cd0000 { |
| 454 | frame-number = <2>; |
| 455 | interrupts = <0 9 0x4>; |
| 456 | reg = <0x17cd0000 0x1000>; |
| 457 | status = "disabled"; |
| 458 | }; |
| 459 | |
| 460 | frame@17ce0000 { |
| 461 | frame-number = <3>; |
| 462 | interrupts = <0 10 0x4>; |
| 463 | reg = <0x17ce0000 0x1000>; |
| 464 | status = "disabled"; |
| 465 | }; |
| 466 | |
| 467 | frame@17cf0000 { |
| 468 | frame-number = <4>; |
| 469 | interrupts = <0 11 0x4>; |
| 470 | reg = <0x17cf0000 0x1000>; |
| 471 | status = "disabled"; |
| 472 | }; |
| 473 | |
| 474 | frame@17d00000 { |
| 475 | frame-number = <5>; |
| 476 | interrupts = <0 12 0x4>; |
| 477 | reg = <0x17d00000 0x1000>; |
| 478 | status = "disabled"; |
| 479 | }; |
| 480 | |
| 481 | frame@17d10000 { |
| 482 | frame-number = <6>; |
| 483 | interrupts = <0 13 0x4>; |
| 484 | reg = <0x17d10000 0x1000>; |
| 485 | status = "disabled"; |
| 486 | }; |
| 487 | }; |
| 488 | |
| 489 | restart@10ac000 { |
| 490 | compatible = "qcom,pshold"; |
| 491 | reg = <0xC264000 0x4>, |
| 492 | <0x1fd3000 0x4>; |
| 493 | reg-names = "pshold-base", "tcsr-boot-misc-detect"; |
| 494 | }; |
| 495 | |
Odelu Kukatla | 1fe3a22 | 2017-06-01 16:24:59 +0530 | [diff] [blame] | 496 | clock_rpmh: qcom,rpmhclk { |
| 497 | compatible = "qcom,dummycc"; |
| 498 | clock-output-names = "rpmh_clocks"; |
| 499 | #clock-cells = <1>; |
| 500 | }; |
| 501 | |
| 502 | clock_gcc: qcom,gcc@100000 { |
| 503 | compatible = "qcom,dummycc"; |
| 504 | clock-output-names = "gcc_clocks"; |
| 505 | #clock-cells = <1>; |
| 506 | #reset-cells = <1>; |
| 507 | }; |
| 508 | |
| 509 | clock_videocc: qcom,videocc@ab00000 { |
| 510 | compatible = "qcom,dummycc"; |
| 511 | clock-output-names = "videocc_clocks"; |
| 512 | #clock-cells = <1>; |
| 513 | #reset-cells = <1>; |
| 514 | }; |
| 515 | |
| 516 | clock_camcc: qcom,camcc@ad00000 { |
| 517 | compatible = "qcom,dummycc"; |
| 518 | clock-output-names = "camcc_clocks"; |
| 519 | #clock-cells = <1>; |
| 520 | #reset-cells = <1>; |
| 521 | }; |
| 522 | |
| 523 | clock_dispcc: qcom,dispcc@af00000 { |
| 524 | compatible = "qcom,dummycc"; |
| 525 | clock-output-names = "dispcc_clocks"; |
| 526 | #clock-cells = <1>; |
| 527 | #reset-cells = <1>; |
| 528 | }; |
| 529 | |
| 530 | clock_gpucc: qcom,gpucc@5090000 { |
| 531 | compatible = "qcom,dummycc"; |
| 532 | clock-output-names = "gpucc_clocks"; |
| 533 | #clock-cells = <1>; |
| 534 | #reset-cells = <1>; |
| 535 | }; |
| 536 | |
| 537 | clock_gfx: qcom,gfxcc@5090000 { |
| 538 | compatible = "qcom,dummycc"; |
| 539 | clock-output-names = "gfxcc_clocks"; |
| 540 | #clock-cells = <1>; |
| 541 | #reset-cells = <1>; |
| 542 | }; |
| 543 | |
Imran Khan | 04f0831 | 2017-03-30 15:07:43 +0530 | [diff] [blame] | 544 | clock_cpucc: qcom,cpucc { |
| 545 | compatible = "qcom,dummycc"; |
| 546 | clock-output-names = "cpucc_clocks"; |
| 547 | #clock-cells = <1>; |
| 548 | #reset-cells = <1>; |
| 549 | }; |
| 550 | |
| 551 | wdog: qcom,wdt@17980000{ |
| 552 | compatible = "qcom,msm-watchdog"; |
| 553 | reg = <0x17980000 0x1000>; |
| 554 | reg-names = "wdt-base"; |
| 555 | interrupts = <0 3 0>, <0 4 0>; |
| 556 | qcom,bark-time = <11000>; |
| 557 | qcom,pet-time = <10000>; |
| 558 | qcom,ipi-ping; |
| 559 | qcom,wakeup-enable; |
| 560 | }; |
| 561 | |
| 562 | qcom,msm-rtb { |
| 563 | compatible = "qcom,msm-rtb"; |
| 564 | qcom,rtb-size = <0x100000>; |
| 565 | }; |
| 566 | |
| 567 | qcom,msm-imem@146bf000 { |
| 568 | compatible = "qcom,msm-imem"; |
| 569 | reg = <0x146bf000 0x1000>; |
| 570 | ranges = <0x0 0x146bf000 0x1000>; |
| 571 | #address-cells = <1>; |
| 572 | #size-cells = <1>; |
| 573 | |
| 574 | mem_dump_table@10 { |
| 575 | compatible = "qcom,msm-imem-mem_dump_table"; |
| 576 | reg = <0x10 8>; |
| 577 | }; |
| 578 | |
| 579 | restart_reason@65c { |
| 580 | compatible = "qcom,msm-imem-restart_reason"; |
| 581 | reg = <0x65c 4>; |
| 582 | }; |
| 583 | |
| 584 | pil@94c { |
| 585 | compatible = "qcom,msm-imem-pil"; |
| 586 | reg = <0x94c 200>; |
| 587 | }; |
| 588 | |
| 589 | kaslr_offset@6d0 { |
| 590 | compatible = "qcom,msm-imem-kaslr_offset"; |
| 591 | reg = <0x6d0 12>; |
| 592 | }; |
| 593 | }; |
| 594 | |
| 595 | cpuss_dump { |
| 596 | compatible = "qcom,cpuss-dump"; |
| 597 | qcom,l1_i_cache0 { |
| 598 | qcom,dump-node = <&L1_I_0>; |
| 599 | qcom,dump-id = <0x60>; |
| 600 | }; |
| 601 | qcom,l1_i_cache1 { |
| 602 | qcom,dump-node = <&L1_I_100>; |
| 603 | qcom,dump-id = <0x61>; |
| 604 | }; |
| 605 | qcom,l1_i_cache2 { |
| 606 | qcom,dump-node = <&L1_I_200>; |
| 607 | qcom,dump-id = <0x62>; |
| 608 | }; |
| 609 | qcom,l1_i_cache3 { |
| 610 | qcom,dump-node = <&L1_I_300>; |
| 611 | qcom,dump-id = <0x63>; |
| 612 | }; |
| 613 | qcom,l1_i_cache100 { |
| 614 | qcom,dump-node = <&L1_I_400>; |
| 615 | qcom,dump-id = <0x64>; |
| 616 | }; |
| 617 | qcom,l1_i_cache101 { |
| 618 | qcom,dump-node = <&L1_I_500>; |
| 619 | qcom,dump-id = <0x65>; |
| 620 | }; |
| 621 | qcom,l1_i_cache102 { |
| 622 | qcom,dump-node = <&L1_I_600>; |
| 623 | qcom,dump-id = <0x66>; |
| 624 | }; |
| 625 | qcom,l1_i_cache103 { |
| 626 | qcom,dump-node = <&L1_I_700>; |
| 627 | qcom,dump-id = <0x67>; |
| 628 | }; |
| 629 | qcom,l1_d_cache0 { |
| 630 | qcom,dump-node = <&L1_D_0>; |
| 631 | qcom,dump-id = <0x80>; |
| 632 | }; |
| 633 | qcom,l1_d_cache1 { |
| 634 | qcom,dump-node = <&L1_D_100>; |
| 635 | qcom,dump-id = <0x81>; |
| 636 | }; |
| 637 | qcom,l1_d_cache2 { |
| 638 | qcom,dump-node = <&L1_D_200>; |
| 639 | qcom,dump-id = <0x82>; |
| 640 | }; |
| 641 | qcom,l1_d_cache3 { |
| 642 | qcom,dump-node = <&L1_D_300>; |
| 643 | qcom,dump-id = <0x83>; |
| 644 | }; |
| 645 | qcom,l1_d_cache100 { |
| 646 | qcom,dump-node = <&L1_D_400>; |
| 647 | qcom,dump-id = <0x84>; |
| 648 | }; |
| 649 | qcom,l1_d_cache101 { |
| 650 | qcom,dump-node = <&L1_D_500>; |
| 651 | qcom,dump-id = <0x85>; |
| 652 | }; |
| 653 | qcom,l1_d_cache102 { |
| 654 | qcom,dump-node = <&L1_D_600>; |
| 655 | qcom,dump-id = <0x86>; |
| 656 | }; |
| 657 | qcom,l1_d_cache103 { |
| 658 | qcom,dump-node = <&L1_D_700>; |
| 659 | qcom,dump-id = <0x87>; |
| 660 | }; |
Lingutla Chandrasekhar | ee4f187 | 2017-06-07 13:50:53 +0530 | [diff] [blame] | 661 | qcom,llcc1_d_cache { |
| 662 | qcom,dump-node = <&LLCC_1>; |
| 663 | qcom,dump-id = <0x140>; |
| 664 | }; |
| 665 | qcom,llcc2_d_cache { |
| 666 | qcom,dump-node = <&LLCC_2>; |
| 667 | qcom,dump-id = <0x141>; |
| 668 | }; |
Imran Khan | 04f0831 | 2017-03-30 15:07:43 +0530 | [diff] [blame] | 669 | }; |
| 670 | |
| 671 | kryo3xx-erp { |
| 672 | compatible = "arm,arm64-kryo3xx-cpu-erp"; |
| 673 | interrupts = <1 6 4>, |
| 674 | <1 7 4>, |
| 675 | <0 34 4>, |
| 676 | <0 35 4>; |
| 677 | |
| 678 | interrupt-names = "l1-l2-faultirq", |
| 679 | "l1-l2-errirq", |
| 680 | "l3-scu-errirq", |
| 681 | "l3-scu-faultirq"; |
| 682 | }; |
| 683 | |
Dhoat Harpal | a24cb2c | 2017-06-06 20:39:54 +0530 | [diff] [blame] | 684 | qcom,ipc-spinlock@1f40000 { |
| 685 | compatible = "qcom,ipc-spinlock-sfpb"; |
| 686 | reg = <0x1f40000 0x8000>; |
| 687 | qcom,num-locks = <8>; |
| 688 | }; |
| 689 | |
Dhoat Harpal | dd9bfaf | 2017-06-06 20:43:16 +0530 | [diff] [blame] | 690 | qcom,smem@86000000 { |
| 691 | compatible = "qcom,smem"; |
| 692 | reg = <0x86000000 0x200000>, |
| 693 | <0x17911008 0x4>, |
| 694 | <0x778000 0x7000>, |
| 695 | <0x1fd4000 0x8>; |
| 696 | reg-names = "smem", "irq-reg-base", "aux-mem1", |
| 697 | "smem_targ_info_reg"; |
| 698 | qcom,mpu-enabled; |
| 699 | }; |
| 700 | |
Dhoat Harpal | 466ffcc | 2017-06-06 20:54:51 +0530 | [diff] [blame] | 701 | qcom,glink-smem-native-xprt-modem@86000000 { |
| 702 | compatible = "qcom,glink-smem-native-xprt"; |
| 703 | reg = <0x86000000 0x200000>, |
| 704 | <0x1799000c 0x4>; |
| 705 | reg-names = "smem", "irq-reg-base"; |
| 706 | qcom,irq-mask = <0x1000>; |
| 707 | interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; |
| 708 | label = "mpss"; |
| 709 | }; |
| 710 | |
| 711 | qcom,glink-smem-native-xprt-adsp@86000000 { |
| 712 | compatible = "qcom,glink-smem-native-xprt"; |
| 713 | reg = <0x86000000 0x200000>, |
| 714 | <0x1799000c 0x4>; |
| 715 | reg-names = "smem", "irq-reg-base"; |
| 716 | qcom,irq-mask = <0x100>; |
| 717 | interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; |
| 718 | label = "lpass"; |
| 719 | qcom,qos-config = <&glink_qos_adsp>; |
| 720 | qcom,ramp-time = <0xaf>; |
| 721 | }; |
| 722 | |
| 723 | glink_qos_adsp: qcom,glink-qos-config-adsp { |
| 724 | compatible = "qcom,glink-qos-config"; |
| 725 | qcom,flow-info = <0x3c 0x0>, |
| 726 | <0x3c 0x0>, |
| 727 | <0x3c 0x0>, |
| 728 | <0x3c 0x0>; |
| 729 | qcom,mtu-size = <0x800>; |
| 730 | qcom,tput-stats-cycle = <0xa>; |
| 731 | }; |
| 732 | |
| 733 | glink_spi_xprt_wdsp: qcom,glink-spi-xprt-wdsp { |
| 734 | compatible = "qcom,glink-spi-xprt"; |
| 735 | label = "wdsp"; |
| 736 | qcom,remote-fifo-config = <&glink_fifo_wdsp>; |
| 737 | qcom,qos-config = <&glink_qos_wdsp>; |
| 738 | qcom,ramp-time = <0x10>, |
| 739 | <0x20>, |
| 740 | <0x30>, |
| 741 | <0x40>; |
| 742 | }; |
| 743 | |
| 744 | glink_fifo_wdsp: qcom,glink-fifo-config-wdsp { |
| 745 | compatible = "qcom,glink-fifo-config"; |
| 746 | qcom,out-read-idx-reg = <0x12000>; |
| 747 | qcom,out-write-idx-reg = <0x12004>; |
| 748 | qcom,in-read-idx-reg = <0x1200C>; |
| 749 | qcom,in-write-idx-reg = <0x12010>; |
| 750 | }; |
| 751 | |
| 752 | glink_qos_wdsp: qcom,glink-qos-config-wdsp { |
| 753 | compatible = "qcom,glink-qos-config"; |
| 754 | qcom,flow-info = <0x80 0x0>, |
| 755 | <0x70 0x1>, |
| 756 | <0x60 0x2>, |
| 757 | <0x50 0x3>; |
| 758 | qcom,mtu-size = <0x800>; |
| 759 | qcom,tput-stats-cycle = <0xa>; |
| 760 | }; |
| 761 | |
| 762 | qcom,glink-smem-native-xprt-cdsp@86000000 { |
| 763 | compatible = "qcom,glink-smem-native-xprt"; |
| 764 | reg = <0x86000000 0x200000>, |
| 765 | <0x1799000c 0x4>; |
| 766 | reg-names = "smem", "irq-reg-base"; |
| 767 | qcom,irq-mask = <0x10>; |
| 768 | interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>; |
| 769 | label = "cdsp"; |
| 770 | }; |
| 771 | |
Dhoat Harpal | 9cb73cc | 2017-06-06 20:58:14 +0530 | [diff] [blame^] | 772 | glink_mpss: qcom,glink-ssr-modem { |
| 773 | compatible = "qcom,glink_ssr"; |
| 774 | label = "modem"; |
| 775 | qcom,edge = "mpss"; |
| 776 | qcom,notify-edges = <&glink_lpass>, <&glink_cdsp>; |
| 777 | qcom,xprt = "smem"; |
| 778 | }; |
| 779 | |
| 780 | glink_lpass: qcom,glink-ssr-adsp { |
| 781 | compatible = "qcom,glink_ssr"; |
| 782 | label = "adsp"; |
| 783 | qcom,edge = "lpass"; |
| 784 | qcom,notify-edges = <&glink_mpss>, <&glink_cdsp>; |
| 785 | qcom,xprt = "smem"; |
| 786 | }; |
| 787 | |
| 788 | glink_cdsp: qcom,glink-ssr-cdsp { |
| 789 | compatible = "qcom,glink_ssr"; |
| 790 | label = "cdsp"; |
| 791 | qcom,edge = "cdsp"; |
| 792 | qcom,notify-edges = <&glink_mpss>, <&glink_lpass>; |
| 793 | qcom,xprt = "smem"; |
| 794 | }; |
| 795 | |
Imran Khan | 04f0831 | 2017-03-30 15:07:43 +0530 | [diff] [blame] | 796 | qcom,chd_sliver { |
| 797 | compatible = "qcom,core-hang-detect"; |
| 798 | label = "silver"; |
| 799 | qcom,threshold-arr = <0x17e00058 0x17e10058 0x17e20058 |
| 800 | 0x17e30058 0x17e40058 0x17e50058>; |
| 801 | qcom,config-arr = <0x17e00060 0x17e10060 0x17e20060 |
| 802 | 0x17e30060 0x17e40060 0x17e50060>; |
| 803 | }; |
| 804 | |
| 805 | qcom,chd_gold { |
| 806 | compatible = "qcom,core-hang-detect"; |
| 807 | label = "gold"; |
| 808 | qcom,threshold-arr = <0x17e60058 0x17e70058>; |
| 809 | qcom,config-arr = <0x17e60060 0x17e70060>; |
| 810 | }; |
| 811 | |
| 812 | qcom,ghd { |
| 813 | compatible = "qcom,gladiator-hang-detect-v2"; |
| 814 | qcom,threshold-arr = <0x1799041c 0x17990420>; |
| 815 | qcom,config-reg = <0x17990434>; |
| 816 | }; |
| 817 | |
| 818 | qcom,msm-gladiator-v3@17900000 { |
| 819 | compatible = "qcom,msm-gladiator-v3"; |
| 820 | reg = <0x17900000 0xd080>; |
| 821 | reg-names = "gladiator_base"; |
| 822 | interrupts = <0 17 0>; |
| 823 | }; |
| 824 | |
Lingutla Chandrasekhar | ee4f187 | 2017-06-07 13:50:53 +0530 | [diff] [blame] | 825 | qcom,llcc@1100000 { |
| 826 | compatible = "qcom,llcc-core", "syscon", "simple-mfd"; |
| 827 | reg = <0x1100000 0x250000>; |
| 828 | reg-names = "llcc_base"; |
| 829 | qcom,llcc-banks-off = <0x0 0x80000 >; |
| 830 | qcom,llcc-broadcast-off = <0x200000>; |
| 831 | |
| 832 | llcc: qcom,sdm670-llcc { |
| 833 | compatible = "qcom,sdm670-llcc"; |
| 834 | #cache-cells = <1>; |
| 835 | max-slices = <32>; |
| 836 | qcom,dump-size = <0x80000>; |
| 837 | }; |
| 838 | |
| 839 | qcom,llcc-erp { |
| 840 | compatible = "qcom,llcc-erp"; |
| 841 | interrupt-names = "ecc_irq"; |
| 842 | interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; |
| 843 | }; |
| 844 | |
| 845 | qcom,llcc-amon { |
| 846 | compatible = "qcom,llcc-amon"; |
| 847 | }; |
| 848 | |
| 849 | LLCC_1: llcc_1_dcache { |
| 850 | qcom,dump-size = <0xd8000>; |
| 851 | }; |
| 852 | |
| 853 | LLCC_2: llcc_2_dcache { |
| 854 | qcom,dump-size = <0xd8000>; |
| 855 | }; |
| 856 | }; |
| 857 | |
Imran Khan | 04f0831 | 2017-03-30 15:07:43 +0530 | [diff] [blame] | 858 | dcc: dcc_v2@10a2000 { |
| 859 | compatible = "qcom,dcc_v2"; |
| 860 | reg = <0x10a2000 0x1000>, |
| 861 | <0x10ae000 0x2000>; |
| 862 | reg-names = "dcc-base", "dcc-ram-base"; |
| 863 | }; |
| 864 | |
Tirupathi Reddy | 9ae4c89 | 2017-06-09 12:30:31 +0530 | [diff] [blame] | 865 | spmi_bus: qcom,spmi@c440000 { |
| 866 | compatible = "qcom,spmi-pmic-arb"; |
| 867 | reg = <0xc440000 0x1100>, |
| 868 | <0xc600000 0x2000000>, |
| 869 | <0xe600000 0x100000>, |
| 870 | <0xe700000 0xa0000>, |
| 871 | <0xc40a000 0x26000>; |
| 872 | reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; |
| 873 | interrupt-names = "periph_irq"; |
| 874 | interrupts = <GIC_SPI 481 IRQ_TYPE_NONE>; |
| 875 | qcom,ee = <0>; |
| 876 | qcom,channel = <0>; |
| 877 | #address-cells = <2>; |
| 878 | #size-cells = <0>; |
| 879 | interrupt-controller; |
| 880 | #interrupt-cells = <4>; |
| 881 | cell-index = <0>; |
| 882 | }; |
Imran Khan | 04f0831 | 2017-03-30 15:07:43 +0530 | [diff] [blame] | 883 | }; |
| 884 | |
| 885 | #include "sdm670-pinctrl.dtsi" |
Vijayanand Jitta | d48c408 | 2017-06-07 15:07:51 +0530 | [diff] [blame] | 886 | #include "msm-arm-smmu-sdm670.dtsi" |
Odelu Kukatla | 1fe3a22 | 2017-06-01 16:24:59 +0530 | [diff] [blame] | 887 | #include "msm-gdsc-sdm845.dtsi" |
| 888 | |
| 889 | &usb30_prim_gdsc { |
| 890 | status = "ok"; |
| 891 | }; |
| 892 | |
| 893 | &ufs_phy_gdsc { |
| 894 | status = "ok"; |
| 895 | }; |
| 896 | |
| 897 | &hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc { |
| 898 | status = "ok"; |
| 899 | }; |
| 900 | |
| 901 | &hlos1_vote_aggre_noc_mmu_tbu1_gdsc { |
| 902 | status = "ok"; |
| 903 | }; |
| 904 | |
| 905 | &hlos1_vote_aggre_noc_mmu_tbu2_gdsc { |
| 906 | status = "ok"; |
| 907 | }; |
| 908 | |
| 909 | &bps_gdsc { |
| 910 | status = "ok"; |
| 911 | }; |
| 912 | |
| 913 | &ife_0_gdsc { |
| 914 | status = "ok"; |
| 915 | }; |
| 916 | |
| 917 | &ife_1_gdsc { |
| 918 | status = "ok"; |
| 919 | }; |
| 920 | |
| 921 | &ipe_0_gdsc { |
| 922 | status = "ok"; |
| 923 | }; |
| 924 | |
| 925 | &ipe_1_gdsc { |
| 926 | status = "ok"; |
| 927 | }; |
| 928 | |
| 929 | &titan_top_gdsc { |
| 930 | status = "ok"; |
| 931 | }; |
| 932 | |
| 933 | &mdss_core_gdsc { |
| 934 | status = "ok"; |
| 935 | }; |
| 936 | |
| 937 | &gpu_cx_gdsc { |
| 938 | status = "ok"; |
| 939 | }; |
| 940 | |
| 941 | &gpu_gx_gdsc { |
| 942 | clock-names = "core_root_clk"; |
| 943 | clocks = <&clock_gfx GPU_CC_GX_GFX3D_CLK_SRC>; |
| 944 | qcom,force-enable-root-clk; |
| 945 | status = "ok"; |
| 946 | }; |
| 947 | |
| 948 | &vcodec0_gdsc { |
| 949 | qcom,support-hw-trigger; |
| 950 | status = "ok"; |
| 951 | }; |
| 952 | |
| 953 | &vcodec1_gdsc { |
| 954 | qcom,support-hw-trigger; |
| 955 | status = "ok"; |
| 956 | }; |
| 957 | |
| 958 | &venus_gdsc { |
| 959 | status = "ok"; |
| 960 | }; |
Tirupathi Reddy | 0cfe208 | 2017-06-08 14:24:13 +0530 | [diff] [blame] | 961 | |
Tirupathi Reddy | 242bd80 | 2017-06-09 11:31:05 +0530 | [diff] [blame] | 962 | #include "pm660.dtsi" |
| 963 | #include "pm660l.dtsi" |
Tirupathi Reddy | 0cfe208 | 2017-06-08 14:24:13 +0530 | [diff] [blame] | 964 | #include "sdm670-regulator.dtsi" |