blob: ca41b0ebf461b12a413d36627a73fff323f5d69a [file] [log] [blame]
Dinh Nguyen66314222012-07-18 16:07:18 -06001/*
2 * Copyright (C) 2012 Altera Corporation <www.altera.com>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
18/dts-v1/;
19/include/ "socfpga.dtsi"
20
21/ {
Dinh Nguyenc2ad2842013-02-11 17:30:30 -060022 soc {
Dinh Nguyen042000b2013-04-11 10:55:25 -050023 clkmgr@ffd04000 {
24 clocks {
25 osc1 {
26 clock-frequency = <25000000>;
27 };
28 };
29 };
30
Dinh Nguyen9b931362014-02-17 20:31:02 -060031 dwmmc0@ff704000 {
32 num-slots = <1>;
33 supports-highspeed;
34 broken-cd;
35
36 slot@0 {
37 reg = <0>;
38 bus-width = <4>;
39 };
40 };
41
Dinh Nguyen3d954cf2013-06-05 10:02:53 -050042 ethernet@ff702000 {
43 phy-mode = "rgmii";
44 phy-addr = <0xffffffff>; /* probe for phy addr */
45 status = "okay";
46 };
47
Dinh Nguyenc2ad2842013-02-11 17:30:30 -060048 timer0@ffc08000 {
49 clock-frequency = <100000000>;
50 };
51
52 timer1@ffc09000 {
53 clock-frequency = <100000000>;
54 };
55
56 timer2@ffd00000 {
57 clock-frequency = <25000000>;
58 };
59
60 timer3@ffd01000 {
61 clock-frequency = <25000000>;
62 };
63
64 serial0@ffc02000 {
65 clock-frequency = <100000000>;
66 };
67
68 serial1@ffc03000 {
69 clock-frequency = <100000000>;
70 };
Dinh Nguyend6dd7352013-02-11 17:30:33 -060071
72 sysmgr@ffd08000 {
73 cpu1-start-addr = <0xffd080c4>;
74 };
Dinh Nguyen66314222012-07-18 16:07:18 -060075 };
76};