Gavin Shan | 8747f36 | 2013-06-20 13:21:06 +0800 | [diff] [blame] | 1 | /* |
| 2 | * The file intends to implement the functions needed by EEH, which is |
| 3 | * built on IODA compliant chip. Actually, lots of functions related |
| 4 | * to EEH would be built based on the OPAL APIs. |
| 5 | * |
| 6 | * Copyright Benjamin Herrenschmidt & Gavin Shan, IBM Corporation 2013. |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; either version 2 of the License, or |
| 11 | * (at your option) any later version. |
| 12 | */ |
| 13 | |
| 14 | #include <linux/bootmem.h> |
| 15 | #include <linux/delay.h> |
| 16 | #include <linux/init.h> |
| 17 | #include <linux/io.h> |
| 18 | #include <linux/irq.h> |
| 19 | #include <linux/kernel.h> |
| 20 | #include <linux/msi.h> |
| 21 | #include <linux/pci.h> |
| 22 | #include <linux/string.h> |
| 23 | |
| 24 | #include <asm/eeh.h> |
| 25 | #include <asm/eeh_event.h> |
| 26 | #include <asm/io.h> |
| 27 | #include <asm/iommu.h> |
| 28 | #include <asm/msi_bitmap.h> |
| 29 | #include <asm/opal.h> |
| 30 | #include <asm/pci-bridge.h> |
| 31 | #include <asm/ppc-pci.h> |
| 32 | #include <asm/tce.h> |
| 33 | |
| 34 | #include "powernv.h" |
| 35 | #include "pci.h" |
| 36 | |
Gavin Shan | 73370c6 | 2013-06-20 13:21:07 +0800 | [diff] [blame] | 37 | /** |
| 38 | * ioda_eeh_post_init - Chip dependent post initialization |
| 39 | * @hose: PCI controller |
| 40 | * |
| 41 | * The function will be called after eeh PEs and devices |
| 42 | * have been built. That means the EEH is ready to supply |
| 43 | * service with I/O cache. |
| 44 | */ |
| 45 | static int ioda_eeh_post_init(struct pci_controller *hose) |
| 46 | { |
| 47 | struct pnv_phb *phb = hose->private_data; |
| 48 | |
| 49 | /* FIXME: Enable it for PHB3 later */ |
| 50 | if (phb->type == PNV_PHB_IODA1) |
| 51 | phb->eeh_enabled = 1; |
| 52 | |
| 53 | return 0; |
| 54 | } |
| 55 | |
Gavin Shan | eb00598 | 2013-06-20 13:21:08 +0800 | [diff] [blame] | 56 | /** |
| 57 | * ioda_eeh_set_option - Set EEH operation or I/O setting |
| 58 | * @pe: EEH PE |
| 59 | * @option: options |
| 60 | * |
| 61 | * Enable or disable EEH option for the indicated PE. The |
| 62 | * function also can be used to enable I/O or DMA for the |
| 63 | * PE. |
| 64 | */ |
| 65 | static int ioda_eeh_set_option(struct eeh_pe *pe, int option) |
| 66 | { |
| 67 | s64 ret; |
| 68 | u32 pe_no; |
| 69 | struct pci_controller *hose = pe->phb; |
| 70 | struct pnv_phb *phb = hose->private_data; |
| 71 | |
| 72 | /* Check on PE number */ |
| 73 | if (pe->addr < 0 || pe->addr >= phb->ioda.total_pe) { |
| 74 | pr_err("%s: PE address %x out of range [0, %x] " |
| 75 | "on PHB#%x\n", |
| 76 | __func__, pe->addr, phb->ioda.total_pe, |
| 77 | hose->global_number); |
| 78 | return -EINVAL; |
| 79 | } |
| 80 | |
| 81 | pe_no = pe->addr; |
| 82 | switch (option) { |
| 83 | case EEH_OPT_DISABLE: |
| 84 | ret = -EEXIST; |
| 85 | break; |
| 86 | case EEH_OPT_ENABLE: |
| 87 | ret = 0; |
| 88 | break; |
| 89 | case EEH_OPT_THAW_MMIO: |
| 90 | ret = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, |
| 91 | OPAL_EEH_ACTION_CLEAR_FREEZE_MMIO); |
| 92 | if (ret) { |
| 93 | pr_warning("%s: Failed to enable MMIO for " |
| 94 | "PHB#%x-PE#%x, err=%lld\n", |
| 95 | __func__, hose->global_number, pe_no, ret); |
| 96 | return -EIO; |
| 97 | } |
| 98 | |
| 99 | break; |
| 100 | case EEH_OPT_THAW_DMA: |
| 101 | ret = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, |
| 102 | OPAL_EEH_ACTION_CLEAR_FREEZE_DMA); |
| 103 | if (ret) { |
| 104 | pr_warning("%s: Failed to enable DMA for " |
| 105 | "PHB#%x-PE#%x, err=%lld\n", |
| 106 | __func__, hose->global_number, pe_no, ret); |
| 107 | return -EIO; |
| 108 | } |
| 109 | |
| 110 | break; |
| 111 | default: |
| 112 | pr_warning("%s: Invalid option %d\n", __func__, option); |
| 113 | return -EINVAL; |
| 114 | } |
| 115 | |
| 116 | return ret; |
| 117 | } |
| 118 | |
Gavin Shan | 8c41a7f | 2013-06-20 13:21:09 +0800 | [diff] [blame] | 119 | /** |
| 120 | * ioda_eeh_get_state - Retrieve the state of PE |
| 121 | * @pe: EEH PE |
| 122 | * |
| 123 | * The PE's state should be retrieved from the PEEV, PEST |
| 124 | * IODA tables. Since the OPAL has exported the function |
| 125 | * to do it, it'd better to use that. |
| 126 | */ |
| 127 | static int ioda_eeh_get_state(struct eeh_pe *pe) |
| 128 | { |
| 129 | s64 ret = 0; |
| 130 | u8 fstate; |
| 131 | u16 pcierr; |
| 132 | u32 pe_no; |
| 133 | int result; |
| 134 | struct pci_controller *hose = pe->phb; |
| 135 | struct pnv_phb *phb = hose->private_data; |
| 136 | |
| 137 | /* |
| 138 | * Sanity check on PE address. The PHB PE address should |
| 139 | * be zero. |
| 140 | */ |
| 141 | if (pe->addr < 0 || pe->addr >= phb->ioda.total_pe) { |
| 142 | pr_err("%s: PE address %x out of range [0, %x] " |
| 143 | "on PHB#%x\n", |
| 144 | __func__, pe->addr, phb->ioda.total_pe, |
| 145 | hose->global_number); |
| 146 | return EEH_STATE_NOT_SUPPORT; |
| 147 | } |
| 148 | |
| 149 | /* Retrieve PE status through OPAL */ |
| 150 | pe_no = pe->addr; |
| 151 | ret = opal_pci_eeh_freeze_status(phb->opal_id, pe_no, |
| 152 | &fstate, &pcierr, NULL); |
| 153 | if (ret) { |
| 154 | pr_err("%s: Failed to get EEH status on " |
| 155 | "PHB#%x-PE#%x\n, err=%lld\n", |
| 156 | __func__, hose->global_number, pe_no, ret); |
| 157 | return EEH_STATE_NOT_SUPPORT; |
| 158 | } |
| 159 | |
| 160 | /* Check PHB status */ |
| 161 | if (pe->type & EEH_PE_PHB) { |
| 162 | result = 0; |
| 163 | result &= ~EEH_STATE_RESET_ACTIVE; |
| 164 | |
| 165 | if (pcierr != OPAL_EEH_PHB_ERROR) { |
| 166 | result |= EEH_STATE_MMIO_ACTIVE; |
| 167 | result |= EEH_STATE_DMA_ACTIVE; |
| 168 | result |= EEH_STATE_MMIO_ENABLED; |
| 169 | result |= EEH_STATE_DMA_ENABLED; |
| 170 | } |
| 171 | |
| 172 | return result; |
| 173 | } |
| 174 | |
| 175 | /* Parse result out */ |
| 176 | result = 0; |
| 177 | switch (fstate) { |
| 178 | case OPAL_EEH_STOPPED_NOT_FROZEN: |
| 179 | result &= ~EEH_STATE_RESET_ACTIVE; |
| 180 | result |= EEH_STATE_MMIO_ACTIVE; |
| 181 | result |= EEH_STATE_DMA_ACTIVE; |
| 182 | result |= EEH_STATE_MMIO_ENABLED; |
| 183 | result |= EEH_STATE_DMA_ENABLED; |
| 184 | break; |
| 185 | case OPAL_EEH_STOPPED_MMIO_FREEZE: |
| 186 | result &= ~EEH_STATE_RESET_ACTIVE; |
| 187 | result |= EEH_STATE_DMA_ACTIVE; |
| 188 | result |= EEH_STATE_DMA_ENABLED; |
| 189 | break; |
| 190 | case OPAL_EEH_STOPPED_DMA_FREEZE: |
| 191 | result &= ~EEH_STATE_RESET_ACTIVE; |
| 192 | result |= EEH_STATE_MMIO_ACTIVE; |
| 193 | result |= EEH_STATE_MMIO_ENABLED; |
| 194 | break; |
| 195 | case OPAL_EEH_STOPPED_MMIO_DMA_FREEZE: |
| 196 | result &= ~EEH_STATE_RESET_ACTIVE; |
| 197 | break; |
| 198 | case OPAL_EEH_STOPPED_RESET: |
| 199 | result |= EEH_STATE_RESET_ACTIVE; |
| 200 | break; |
| 201 | case OPAL_EEH_STOPPED_TEMP_UNAVAIL: |
| 202 | result |= EEH_STATE_UNAVAILABLE; |
| 203 | break; |
| 204 | case OPAL_EEH_STOPPED_PERM_UNAVAIL: |
| 205 | result |= EEH_STATE_NOT_SUPPORT; |
| 206 | break; |
| 207 | default: |
| 208 | pr_warning("%s: Unexpected EEH status 0x%x " |
| 209 | "on PHB#%x-PE#%x\n", |
| 210 | __func__, fstate, hose->global_number, pe_no); |
| 211 | } |
| 212 | |
| 213 | return result; |
| 214 | } |
| 215 | |
Gavin Shan | 9d5cab0 | 2013-06-20 13:21:10 +0800 | [diff] [blame^] | 216 | static int ioda_eeh_pe_clear(struct eeh_pe *pe) |
| 217 | { |
| 218 | struct pci_controller *hose; |
| 219 | struct pnv_phb *phb; |
| 220 | u32 pe_no; |
| 221 | u8 fstate; |
| 222 | u16 pcierr; |
| 223 | s64 ret; |
| 224 | |
| 225 | pe_no = pe->addr; |
| 226 | hose = pe->phb; |
| 227 | phb = pe->phb->private_data; |
| 228 | |
| 229 | /* Clear the EEH error on the PE */ |
| 230 | ret = opal_pci_eeh_freeze_clear(phb->opal_id, |
| 231 | pe_no, OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); |
| 232 | if (ret) { |
| 233 | pr_err("%s: Failed to clear EEH error for " |
| 234 | "PHB#%x-PE#%x, err=%lld\n", |
| 235 | __func__, hose->global_number, pe_no, ret); |
| 236 | return -EIO; |
| 237 | } |
| 238 | |
| 239 | /* |
| 240 | * Read the PE state back and verify that the frozen |
| 241 | * state has been removed. |
| 242 | */ |
| 243 | ret = opal_pci_eeh_freeze_status(phb->opal_id, pe_no, |
| 244 | &fstate, &pcierr, NULL); |
| 245 | if (ret) { |
| 246 | pr_err("%s: Failed to get EEH status on " |
| 247 | "PHB#%x-PE#%x\n, err=%lld\n", |
| 248 | __func__, hose->global_number, pe_no, ret); |
| 249 | return -EIO; |
| 250 | } |
| 251 | |
| 252 | if (fstate != OPAL_EEH_STOPPED_NOT_FROZEN) { |
| 253 | pr_err("%s: Frozen state not cleared on " |
| 254 | "PHB#%x-PE#%x, sts=%x\n", |
| 255 | __func__, hose->global_number, pe_no, fstate); |
| 256 | return -EIO; |
| 257 | } |
| 258 | |
| 259 | return 0; |
| 260 | } |
| 261 | |
| 262 | static s64 ioda_eeh_phb_poll(struct pnv_phb *phb) |
| 263 | { |
| 264 | s64 rc = OPAL_HARDWARE; |
| 265 | |
| 266 | while (1) { |
| 267 | rc = opal_pci_poll(phb->opal_id); |
| 268 | if (rc <= 0) |
| 269 | break; |
| 270 | |
| 271 | msleep(rc); |
| 272 | } |
| 273 | |
| 274 | return rc; |
| 275 | } |
| 276 | |
| 277 | static int ioda_eeh_phb_reset(struct pci_controller *hose, int option) |
| 278 | { |
| 279 | struct pnv_phb *phb = hose->private_data; |
| 280 | s64 rc = OPAL_HARDWARE; |
| 281 | |
| 282 | pr_debug("%s: Reset PHB#%x, option=%d\n", |
| 283 | __func__, hose->global_number, option); |
| 284 | |
| 285 | /* Issue PHB complete reset request */ |
| 286 | if (option == EEH_RESET_FUNDAMENTAL || |
| 287 | option == EEH_RESET_HOT) |
| 288 | rc = opal_pci_reset(phb->opal_id, |
| 289 | OPAL_PHB_COMPLETE, |
| 290 | OPAL_ASSERT_RESET); |
| 291 | else if (option == EEH_RESET_DEACTIVATE) |
| 292 | rc = opal_pci_reset(phb->opal_id, |
| 293 | OPAL_PHB_COMPLETE, |
| 294 | OPAL_DEASSERT_RESET); |
| 295 | if (rc < 0) |
| 296 | goto out; |
| 297 | |
| 298 | /* |
| 299 | * Poll state of the PHB until the request is done |
| 300 | * successfully. |
| 301 | */ |
| 302 | rc = ioda_eeh_phb_poll(phb); |
| 303 | out: |
| 304 | if (rc != OPAL_SUCCESS) |
| 305 | return -EIO; |
| 306 | |
| 307 | return 0; |
| 308 | } |
| 309 | |
| 310 | static int ioda_eeh_root_reset(struct pci_controller *hose, int option) |
| 311 | { |
| 312 | struct pnv_phb *phb = hose->private_data; |
| 313 | s64 rc = OPAL_SUCCESS; |
| 314 | |
| 315 | pr_debug("%s: Reset PHB#%x, option=%d\n", |
| 316 | __func__, hose->global_number, option); |
| 317 | |
| 318 | /* |
| 319 | * During the reset deassert time, we needn't care |
| 320 | * the reset scope because the firmware does nothing |
| 321 | * for fundamental or hot reset during deassert phase. |
| 322 | */ |
| 323 | if (option == EEH_RESET_FUNDAMENTAL) |
| 324 | rc = opal_pci_reset(phb->opal_id, |
| 325 | OPAL_PCI_FUNDAMENTAL_RESET, |
| 326 | OPAL_ASSERT_RESET); |
| 327 | else if (option == EEH_RESET_HOT) |
| 328 | rc = opal_pci_reset(phb->opal_id, |
| 329 | OPAL_PCI_HOT_RESET, |
| 330 | OPAL_ASSERT_RESET); |
| 331 | else if (option == EEH_RESET_DEACTIVATE) |
| 332 | rc = opal_pci_reset(phb->opal_id, |
| 333 | OPAL_PCI_HOT_RESET, |
| 334 | OPAL_DEASSERT_RESET); |
| 335 | if (rc < 0) |
| 336 | goto out; |
| 337 | |
| 338 | /* Poll state of the PHB until the request is done */ |
| 339 | rc = ioda_eeh_phb_poll(phb); |
| 340 | out: |
| 341 | if (rc != OPAL_SUCCESS) |
| 342 | return -EIO; |
| 343 | |
| 344 | return 0; |
| 345 | } |
| 346 | |
| 347 | static int ioda_eeh_bridge_reset(struct pci_controller *hose, |
| 348 | struct pci_dev *dev, int option) |
| 349 | { |
| 350 | u16 ctrl; |
| 351 | |
| 352 | pr_debug("%s: Reset device %04x:%02x:%02x.%01x with option %d\n", |
| 353 | __func__, hose->global_number, dev->bus->number, |
| 354 | PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn), option); |
| 355 | |
| 356 | switch (option) { |
| 357 | case EEH_RESET_FUNDAMENTAL: |
| 358 | case EEH_RESET_HOT: |
| 359 | pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &ctrl); |
| 360 | ctrl |= PCI_BRIDGE_CTL_BUS_RESET; |
| 361 | pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl); |
| 362 | break; |
| 363 | case EEH_RESET_DEACTIVATE: |
| 364 | pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &ctrl); |
| 365 | ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET; |
| 366 | pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl); |
| 367 | break; |
| 368 | } |
| 369 | |
| 370 | return 0; |
| 371 | } |
| 372 | |
| 373 | /** |
| 374 | * ioda_eeh_reset - Reset the indicated PE |
| 375 | * @pe: EEH PE |
| 376 | * @option: reset option |
| 377 | * |
| 378 | * Do reset on the indicated PE. For PCI bus sensitive PE, |
| 379 | * we need to reset the parent p2p bridge. The PHB has to |
| 380 | * be reinitialized if the p2p bridge is root bridge. For |
| 381 | * PCI device sensitive PE, we will try to reset the device |
| 382 | * through FLR. For now, we don't have OPAL APIs to do HARD |
| 383 | * reset yet, so all reset would be SOFT (HOT) reset. |
| 384 | */ |
| 385 | static int ioda_eeh_reset(struct eeh_pe *pe, int option) |
| 386 | { |
| 387 | struct pci_controller *hose = pe->phb; |
| 388 | struct eeh_dev *edev; |
| 389 | struct pci_dev *dev; |
| 390 | int ret; |
| 391 | |
| 392 | /* |
| 393 | * Anyway, we have to clear the problematic state for the |
| 394 | * corresponding PE. However, we needn't do it if the PE |
| 395 | * is PHB associated. That means the PHB is having fatal |
| 396 | * errors and it needs reset. Further more, the AIB interface |
| 397 | * isn't reliable any more. |
| 398 | */ |
| 399 | if (!(pe->type & EEH_PE_PHB) && |
| 400 | (option == EEH_RESET_HOT || |
| 401 | option == EEH_RESET_FUNDAMENTAL)) { |
| 402 | ret = ioda_eeh_pe_clear(pe); |
| 403 | if (ret) |
| 404 | return -EIO; |
| 405 | } |
| 406 | |
| 407 | /* |
| 408 | * The rules applied to reset, either fundamental or hot reset: |
| 409 | * |
| 410 | * We always reset the direct upstream bridge of the PE. If the |
| 411 | * direct upstream bridge isn't root bridge, we always take hot |
| 412 | * reset no matter what option (fundamental or hot) is. Otherwise, |
| 413 | * we should do the reset according to the required option. |
| 414 | */ |
| 415 | if (pe->type & EEH_PE_PHB) { |
| 416 | ret = ioda_eeh_phb_reset(hose, option); |
| 417 | } else { |
| 418 | if (pe->type & EEH_PE_DEVICE) { |
| 419 | /* |
| 420 | * If it's device PE, we didn't refer to the parent |
| 421 | * PCI bus yet. So we have to figure it out indirectly. |
| 422 | */ |
| 423 | edev = list_first_entry(&pe->edevs, |
| 424 | struct eeh_dev, list); |
| 425 | dev = eeh_dev_to_pci_dev(edev); |
| 426 | dev = dev->bus->self; |
| 427 | } else { |
| 428 | /* |
| 429 | * If it's bus PE, the parent PCI bus is already there |
| 430 | * and just pick it up. |
| 431 | */ |
| 432 | dev = pe->bus->self; |
| 433 | } |
| 434 | |
| 435 | /* |
| 436 | * Do reset based on the fact that the direct upstream bridge |
| 437 | * is root bridge (port) or not. |
| 438 | */ |
| 439 | if (dev->bus->number == 0) |
| 440 | ret = ioda_eeh_root_reset(hose, option); |
| 441 | else |
| 442 | ret = ioda_eeh_bridge_reset(hose, dev, option); |
| 443 | } |
| 444 | |
| 445 | return ret; |
| 446 | } |
| 447 | |
Gavin Shan | 8747f36 | 2013-06-20 13:21:06 +0800 | [diff] [blame] | 448 | struct pnv_eeh_ops ioda_eeh_ops = { |
Gavin Shan | 73370c6 | 2013-06-20 13:21:07 +0800 | [diff] [blame] | 449 | .post_init = ioda_eeh_post_init, |
Gavin Shan | eb00598 | 2013-06-20 13:21:08 +0800 | [diff] [blame] | 450 | .set_option = ioda_eeh_set_option, |
Gavin Shan | 8c41a7f | 2013-06-20 13:21:09 +0800 | [diff] [blame] | 451 | .get_state = ioda_eeh_get_state, |
Gavin Shan | 9d5cab0 | 2013-06-20 13:21:10 +0800 | [diff] [blame^] | 452 | .reset = ioda_eeh_reset, |
Gavin Shan | 8747f36 | 2013-06-20 13:21:06 +0800 | [diff] [blame] | 453 | .get_log = NULL, |
| 454 | .configure_bridge = NULL, |
| 455 | .next_error = NULL |
| 456 | }; |