Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1 | #include "r8192U.h" |
| 2 | #include "r8192U_hw.h" |
| 3 | #include "r819xU_phy.h" |
| 4 | #include "r819xU_phyreg.h" |
| 5 | #include "r8190_rtl8256.h" |
| 6 | #include "r8192U_dm.h" |
| 7 | #include "r819xU_firmware_img.h" |
| 8 | |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 9 | #include "dot11d.h" |
Xenia Ragiadakou | 391c72a | 2013-06-15 07:29:01 +0300 | [diff] [blame] | 10 | #include <linux/bitops.h> |
| 11 | |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 12 | static u32 RF_CHANNEL_TABLE_ZEBRA[] = { |
| 13 | 0, |
| 14 | 0x085c, //2412 1 |
| 15 | 0x08dc, //2417 2 |
| 16 | 0x095c, //2422 3 |
| 17 | 0x09dc, //2427 4 |
| 18 | 0x0a5c, //2432 5 |
| 19 | 0x0adc, //2437 6 |
| 20 | 0x0b5c, //2442 7 |
| 21 | 0x0bdc, //2447 8 |
| 22 | 0x0c5c, //2452 9 |
| 23 | 0x0cdc, //2457 10 |
| 24 | 0x0d5c, //2462 11 |
| 25 | 0x0ddc, //2467 12 |
| 26 | 0x0e5c, //2472 13 |
| 27 | 0x0f72, //2484 |
| 28 | }; |
| 29 | |
| 30 | |
| 31 | #define rtl819XPHY_REG_1T2RArray Rtl8192UsbPHY_REG_1T2RArray |
| 32 | #define rtl819XMACPHY_Array_PG Rtl8192UsbMACPHY_Array_PG |
| 33 | #define rtl819XMACPHY_Array Rtl8192UsbMACPHY_Array |
| 34 | #define rtl819XRadioA_Array Rtl8192UsbRadioA_Array |
| 35 | #define rtl819XRadioB_Array Rtl8192UsbRadioB_Array |
| 36 | #define rtl819XRadioC_Array Rtl8192UsbRadioC_Array |
| 37 | #define rtl819XRadioD_Array Rtl8192UsbRadioD_Array |
| 38 | #define rtl819XAGCTAB_Array Rtl8192UsbAGCTAB_Array |
| 39 | |
| 40 | /****************************************************************************** |
| 41 | *function: This function read BB parameters from Header file we gen, |
| 42 | * and do register read/write |
| 43 | * input: u32 dwBitMask //taget bit pos in the addr to be modified |
| 44 | * output: none |
Justin P. Mattock | 589b3d0 | 2012-04-30 07:41:36 -0700 | [diff] [blame] | 45 | * return: u32 return the shift bit position of the mask |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 46 | * ****************************************************************************/ |
| 47 | u32 rtl8192_CalculateBitShift(u32 dwBitMask) |
| 48 | { |
| 49 | u32 i; |
Xenia Ragiadakou | 391c72a | 2013-06-15 07:29:01 +0300 | [diff] [blame] | 50 | i = ffs(dwBitMask) - 1; |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 51 | return i; |
| 52 | } |
| 53 | /****************************************************************************** |
| 54 | *function: This function check different RF type to execute legal judgement. If RF Path is illegal, we will return false. |
| 55 | * input: none |
| 56 | * output: none |
| 57 | * return: 0(illegal, false), 1(legal,true) |
| 58 | * ***************************************************************************/ |
Xenia Ragiadakou | 88d8fe2 | 2013-05-11 17:22:22 +0300 | [diff] [blame] | 59 | u8 rtl8192_phy_CheckIsLegalRFPath(struct net_device *dev, u32 eRFPath) |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 60 | { |
| 61 | u8 ret = 1; |
| 62 | struct r8192_priv *priv = ieee80211_priv(dev); |
Xenia Ragiadakou | 4a6094c | 2013-06-15 07:29:02 +0300 | [diff] [blame] | 63 | if (priv->rf_type == RF_2T4R) { |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 64 | ret = 0; |
Xenia Ragiadakou | 4a6094c | 2013-06-15 07:29:02 +0300 | [diff] [blame] | 65 | } else if (priv->rf_type == RF_1T2R) { |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 66 | if (eRFPath == RF90_PATH_A || eRFPath == RF90_PATH_B) |
| 67 | ret = 1; |
| 68 | else if (eRFPath == RF90_PATH_C || eRFPath == RF90_PATH_D) |
| 69 | ret = 0; |
| 70 | } |
| 71 | return ret; |
| 72 | } |
| 73 | /****************************************************************************** |
| 74 | *function: This function set specific bits to BB register |
| 75 | * input: net_device dev |
| 76 | * u32 dwRegAddr //target addr to be modified |
| 77 | * u32 dwBitMask //taget bit pos in the addr to be modified |
| 78 | * u32 dwData //value to be write |
| 79 | * output: none |
| 80 | * return: none |
| 81 | * notice: |
| 82 | * ****************************************************************************/ |
Xenia Ragiadakou | 442543d | 2013-06-15 07:29:08 +0300 | [diff] [blame] | 83 | void rtl8192_setBBreg(struct net_device *dev, u32 dwRegAddr, u32 dwBitMask, |
| 84 | u32 dwData) |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 85 | { |
| 86 | |
| 87 | u32 OriginalValue, BitShift, NewValue; |
| 88 | |
Xenia Ragiadakou | 9d8e79e | 2013-06-18 05:29:38 +0300 | [diff] [blame^] | 89 | if (dwBitMask != bMaskDWord) { //if not "double word" write |
Xenia Ragiadakou | b3d42bf | 2013-06-06 16:40:51 +0300 | [diff] [blame] | 90 | read_nic_dword(dev, dwRegAddr, &OriginalValue); |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 91 | BitShift = rtl8192_CalculateBitShift(dwBitMask); |
Mauro Carvalho Chehab | e406322 | 2009-11-03 07:42:46 -0200 | [diff] [blame] | 92 | NewValue = (((OriginalValue) & (~dwBitMask)) | (dwData << BitShift)); |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 93 | write_nic_dword(dev, dwRegAddr, NewValue); |
Xenia Ragiadakou | 4a6094c | 2013-06-15 07:29:02 +0300 | [diff] [blame] | 94 | } else { |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 95 | write_nic_dword(dev, dwRegAddr, dwData); |
Xenia Ragiadakou | 4a6094c | 2013-06-15 07:29:02 +0300 | [diff] [blame] | 96 | } |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 97 | return; |
| 98 | } |
| 99 | /****************************************************************************** |
| 100 | *function: This function reads specific bits from BB register |
| 101 | * input: net_device dev |
| 102 | * u32 dwRegAddr //target addr to be readback |
| 103 | * u32 dwBitMask //taget bit pos in the addr to be readback |
| 104 | * output: none |
| 105 | * return: u32 Data //the readback register value |
| 106 | * notice: |
| 107 | * ****************************************************************************/ |
Xenia Ragiadakou | 88d8fe2 | 2013-05-11 17:22:22 +0300 | [diff] [blame] | 108 | u32 rtl8192_QueryBBReg(struct net_device *dev, u32 dwRegAddr, u32 dwBitMask) |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 109 | { |
| 110 | u32 Ret = 0, OriginalValue, BitShift; |
| 111 | |
Xenia Ragiadakou | b3d42bf | 2013-06-06 16:40:51 +0300 | [diff] [blame] | 112 | read_nic_dword(dev, dwRegAddr, &OriginalValue); |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 113 | BitShift = rtl8192_CalculateBitShift(dwBitMask); |
Xenia Ragiadakou | ec5d319 | 2013-06-18 05:29:36 +0300 | [diff] [blame] | 114 | Ret = (OriginalValue & dwBitMask) >> BitShift; |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 115 | |
Xenia Ragiadakou | 4c8dd92 | 2013-06-15 07:29:03 +0300 | [diff] [blame] | 116 | return Ret; |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 117 | } |
Xenia Ragiadakou | 442543d | 2013-06-15 07:29:08 +0300 | [diff] [blame] | 118 | static u32 phy_FwRFSerialRead(struct net_device *dev, RF90_RADIO_PATH_E eRFPath, |
| 119 | u32 Offset); |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 120 | |
Xenia Ragiadakou | 442543d | 2013-06-15 07:29:08 +0300 | [diff] [blame] | 121 | static void phy_FwRFSerialWrite(struct net_device *dev, |
| 122 | RF90_RADIO_PATH_E eRFPath, u32 Offset, |
| 123 | u32 Data); |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 124 | |
| 125 | /****************************************************************************** |
| 126 | *function: This function read register from RF chip |
| 127 | * input: net_device dev |
Sebastian Hahn | 35997ff | 2012-12-05 21:40:18 +0100 | [diff] [blame] | 128 | * RF90_RADIO_PATH_E eRFPath //radio path of A/B/C/D |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 129 | * u32 Offset //target address to be read |
| 130 | * output: none |
Sebastian Hahn | 35997ff | 2012-12-05 21:40:18 +0100 | [diff] [blame] | 131 | * return: u32 readback value |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 132 | * notice: There are three types of serial operations:(1) Software serial write.(2)Hardware LSSI-Low Speed Serial Interface.(3)Hardware HSSI-High speed serial write. Driver here need to implement (1) and (2)---need more spec for this information. |
| 133 | * ****************************************************************************/ |
Xenia Ragiadakou | 442543d | 2013-06-15 07:29:08 +0300 | [diff] [blame] | 134 | u32 rtl8192_phy_RFSerialRead(struct net_device *dev, RF90_RADIO_PATH_E eRFPath, |
| 135 | u32 Offset) |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 136 | { |
| 137 | struct r8192_priv *priv = ieee80211_priv(dev); |
| 138 | u32 ret = 0; |
| 139 | u32 NewOffset = 0; |
Xenia Ragiadakou | 88d8fe2 | 2013-05-11 17:22:22 +0300 | [diff] [blame] | 140 | BB_REGISTER_DEFINITION_T *pPhyReg = &priv->PHYRegDef[eRFPath]; |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 141 | rtl8192_setBBreg(dev, pPhyReg->rfLSSIReadBack, bLSSIReadBackData, 0); |
| 142 | //make sure RF register offset is correct |
| 143 | Offset &= 0x3f; |
| 144 | |
| 145 | //switch page for 8256 RF IC |
Xenia Ragiadakou | 4a6094c | 2013-06-15 07:29:02 +0300 | [diff] [blame] | 146 | if (priv->rf_chip == RF_8256) { |
| 147 | if (Offset >= 31) { |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 148 | priv->RfReg0Value[eRFPath] |= 0x140; |
| 149 | //Switch to Reg_Mode2 for Reg 31-45 |
Xenia Ragiadakou | ceb5659 | 2013-06-15 07:29:07 +0300 | [diff] [blame] | 150 | rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, (priv->RfReg0Value[eRFPath]<<16)); |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 151 | //modify offset |
| 152 | NewOffset = Offset -30; |
Xenia Ragiadakou | 4a6094c | 2013-06-15 07:29:02 +0300 | [diff] [blame] | 153 | } else if (Offset >= 16) { |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 154 | priv->RfReg0Value[eRFPath] |= 0x100; |
| 155 | priv->RfReg0Value[eRFPath] &= (~0x40); |
| 156 | //Switch to Reg_Mode 1 for Reg16-30 |
Xenia Ragiadakou | ceb5659 | 2013-06-15 07:29:07 +0300 | [diff] [blame] | 157 | rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, (priv->RfReg0Value[eRFPath]<<16)); |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 158 | |
| 159 | NewOffset = Offset - 15; |
Xenia Ragiadakou | 4a6094c | 2013-06-15 07:29:02 +0300 | [diff] [blame] | 160 | } else { |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 161 | NewOffset = Offset; |
Xenia Ragiadakou | 4a6094c | 2013-06-15 07:29:02 +0300 | [diff] [blame] | 162 | } |
| 163 | } else { |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 164 | RT_TRACE((COMP_PHY|COMP_ERR), "check RF type here, need to be 8256\n"); |
| 165 | NewOffset = Offset; |
| 166 | } |
| 167 | //put desired read addr to LSSI control Register |
| 168 | rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadAddress, NewOffset); |
| 169 | //Issue a posedge trigger |
| 170 | // |
| 171 | rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x0); |
| 172 | rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x1); |
| 173 | |
| 174 | |
Justin P. Mattock | 8ef3a7e | 2012-04-30 14:39:21 -0700 | [diff] [blame] | 175 | // TODO: we should not delay such a long time. Ask for help from SD3 |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 176 | msleep(1); |
| 177 | |
| 178 | ret = rtl8192_QueryBBReg(dev, pPhyReg->rfLSSIReadBack, bLSSIReadBackData); |
| 179 | |
| 180 | |
| 181 | // Switch back to Reg_Mode0; |
Xenia Ragiadakou | 1111b87 | 2013-06-15 07:29:04 +0300 | [diff] [blame] | 182 | if (priv->rf_chip == RF_8256) { |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 183 | priv->RfReg0Value[eRFPath] &= 0xebf; |
| 184 | |
| 185 | rtl8192_setBBreg( |
| 186 | dev, |
| 187 | pPhyReg->rf3wireOffset, |
| 188 | bMaskDWord, |
| 189 | (priv->RfReg0Value[eRFPath] << 16)); |
| 190 | } |
| 191 | |
| 192 | return ret; |
| 193 | |
| 194 | } |
| 195 | |
| 196 | /****************************************************************************** |
| 197 | *function: This function write data to RF register |
| 198 | * input: net_device dev |
Sebastian Hahn | 35997ff | 2012-12-05 21:40:18 +0100 | [diff] [blame] | 199 | * RF90_RADIO_PATH_E eRFPath //radio path of A/B/C/D |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 200 | * u32 Offset //target address to be written |
| 201 | * u32 Data //The new register data to be written |
| 202 | * output: none |
| 203 | * return: none |
| 204 | * notice: For RF8256 only. |
| 205 | =========================================================== |
| 206 | *Reg Mode RegCTL[1] RegCTL[0] Note |
| 207 | * (Reg00[12]) (Reg00[10]) |
| 208 | *=========================================================== |
| 209 | *Reg_Mode0 0 x Reg 0 ~15(0x0 ~ 0xf) |
| 210 | *------------------------------------------------------------------ |
| 211 | *Reg_Mode1 1 0 Reg 16 ~30(0x1 ~ 0xf) |
| 212 | *------------------------------------------------------------------ |
| 213 | * Reg_Mode2 1 1 Reg 31 ~ 45(0x1 ~ 0xf) |
| 214 | *------------------------------------------------------------------ |
| 215 | * ****************************************************************************/ |
Xenia Ragiadakou | 442543d | 2013-06-15 07:29:08 +0300 | [diff] [blame] | 216 | void rtl8192_phy_RFSerialWrite(struct net_device *dev, |
| 217 | RF90_RADIO_PATH_E eRFPath, u32 Offset, u32 Data) |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 218 | { |
| 219 | struct r8192_priv *priv = ieee80211_priv(dev); |
| 220 | u32 DataAndAddr = 0, NewOffset = 0; |
| 221 | BB_REGISTER_DEFINITION_T *pPhyReg = &priv->PHYRegDef[eRFPath]; |
| 222 | |
| 223 | Offset &= 0x3f; |
Xenia Ragiadakou | 4a6094c | 2013-06-15 07:29:02 +0300 | [diff] [blame] | 224 | if (priv->rf_chip == RF_8256) { |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 225 | |
Xenia Ragiadakou | 4a6094c | 2013-06-15 07:29:02 +0300 | [diff] [blame] | 226 | if (Offset >= 31) { |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 227 | priv->RfReg0Value[eRFPath] |= 0x140; |
| 228 | rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, (priv->RfReg0Value[eRFPath] << 16)); |
| 229 | NewOffset = Offset - 30; |
Xenia Ragiadakou | 4a6094c | 2013-06-15 07:29:02 +0300 | [diff] [blame] | 230 | } else if (Offset >= 16) { |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 231 | priv->RfReg0Value[eRFPath] |= 0x100; |
| 232 | priv->RfReg0Value[eRFPath] &= (~0x40); |
| 233 | rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, (priv->RfReg0Value[eRFPath]<<16)); |
| 234 | NewOffset = Offset - 15; |
Xenia Ragiadakou | 4a6094c | 2013-06-15 07:29:02 +0300 | [diff] [blame] | 235 | } else { |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 236 | NewOffset = Offset; |
Xenia Ragiadakou | 4a6094c | 2013-06-15 07:29:02 +0300 | [diff] [blame] | 237 | } |
| 238 | } else { |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 239 | RT_TRACE((COMP_PHY|COMP_ERR), "check RF type here, need to be 8256\n"); |
| 240 | NewOffset = Offset; |
| 241 | } |
| 242 | |
Justin P. Mattock | 589b3d0 | 2012-04-30 07:41:36 -0700 | [diff] [blame] | 243 | // Put write addr in [5:0] and write data in [31:16] |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 244 | DataAndAddr = (Data<<16) | (NewOffset&0x3f); |
| 245 | |
| 246 | // Write Operation |
| 247 | rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr); |
| 248 | |
| 249 | |
Xenia Ragiadakou | 9d8e79e | 2013-06-18 05:29:38 +0300 | [diff] [blame^] | 250 | if (Offset == 0x0) |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 251 | priv->RfReg0Value[eRFPath] = Data; |
| 252 | |
| 253 | // Switch back to Reg_Mode0; |
Xenia Ragiadakou | 1111b87 | 2013-06-15 07:29:04 +0300 | [diff] [blame] | 254 | if (priv->rf_chip == RF_8256) { |
| 255 | if (Offset != 0) { |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 256 | priv->RfReg0Value[eRFPath] &= 0xebf; |
| 257 | rtl8192_setBBreg( |
| 258 | dev, |
| 259 | pPhyReg->rf3wireOffset, |
| 260 | bMaskDWord, |
| 261 | (priv->RfReg0Value[eRFPath] << 16)); |
| 262 | } |
| 263 | } |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 264 | return; |
| 265 | } |
| 266 | |
| 267 | /****************************************************************************** |
| 268 | *function: This function set specific bits to RF register |
| 269 | * input: net_device dev |
Sebastian Hahn | 35997ff | 2012-12-05 21:40:18 +0100 | [diff] [blame] | 270 | * RF90_RADIO_PATH_E eRFPath //radio path of A/B/C/D |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 271 | * u32 RegAddr //target addr to be modified |
| 272 | * u32 BitMask //taget bit pos in the addr to be modified |
| 273 | * u32 Data //value to be write |
| 274 | * output: none |
| 275 | * return: none |
| 276 | * notice: |
| 277 | * ****************************************************************************/ |
Xenia Ragiadakou | 442543d | 2013-06-15 07:29:08 +0300 | [diff] [blame] | 278 | void rtl8192_phy_SetRFReg(struct net_device *dev, RF90_RADIO_PATH_E eRFPath, |
| 279 | u32 RegAddr, u32 BitMask, u32 Data) |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 280 | { |
| 281 | struct r8192_priv *priv = ieee80211_priv(dev); |
| 282 | u32 Original_Value, BitShift, New_Value; |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 283 | |
| 284 | if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath)) |
| 285 | return; |
| 286 | |
Xenia Ragiadakou | 4a6094c | 2013-06-15 07:29:02 +0300 | [diff] [blame] | 287 | if (priv->Rf_Mode == RF_OP_By_FW) { |
| 288 | if (BitMask != bMask12Bits) { // RF data is 12 bits only |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 289 | Original_Value = phy_FwRFSerialRead(dev, eRFPath, RegAddr); |
| 290 | BitShift = rtl8192_CalculateBitShift(BitMask); |
| 291 | New_Value = ((Original_Value) & (~BitMask)) | (Data<< BitShift); |
| 292 | |
| 293 | phy_FwRFSerialWrite(dev, eRFPath, RegAddr, New_Value); |
Xenia Ragiadakou | 4a6094c | 2013-06-15 07:29:02 +0300 | [diff] [blame] | 294 | } else { |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 295 | phy_FwRFSerialWrite(dev, eRFPath, RegAddr, Data); |
Xenia Ragiadakou | 4a6094c | 2013-06-15 07:29:02 +0300 | [diff] [blame] | 296 | } |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 297 | |
| 298 | udelay(200); |
| 299 | |
Xenia Ragiadakou | 4a6094c | 2013-06-15 07:29:02 +0300 | [diff] [blame] | 300 | } else { |
| 301 | if (BitMask != bMask12Bits) { // RF data is 12 bits only |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 302 | Original_Value = rtl8192_phy_RFSerialRead(dev, eRFPath, RegAddr); |
Mauro Carvalho Chehab | e406322 | 2009-11-03 07:42:46 -0200 | [diff] [blame] | 303 | BitShift = rtl8192_CalculateBitShift(BitMask); |
| 304 | New_Value = (((Original_Value) & (~BitMask)) | (Data<< BitShift)); |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 305 | |
| 306 | rtl8192_phy_RFSerialWrite(dev, eRFPath, RegAddr, New_Value); |
Xenia Ragiadakou | 4a6094c | 2013-06-15 07:29:02 +0300 | [diff] [blame] | 307 | } else { |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 308 | rtl8192_phy_RFSerialWrite(dev, eRFPath, RegAddr, Data); |
Xenia Ragiadakou | 4a6094c | 2013-06-15 07:29:02 +0300 | [diff] [blame] | 309 | } |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 310 | } |
| 311 | return; |
| 312 | } |
| 313 | |
| 314 | /****************************************************************************** |
| 315 | *function: This function reads specific bits from RF register |
| 316 | * input: net_device dev |
| 317 | * u32 RegAddr //target addr to be readback |
| 318 | * u32 BitMask //taget bit pos in the addr to be readback |
| 319 | * output: none |
| 320 | * return: u32 Data //the readback register value |
| 321 | * notice: |
| 322 | * ****************************************************************************/ |
Xenia Ragiadakou | 442543d | 2013-06-15 07:29:08 +0300 | [diff] [blame] | 323 | u32 rtl8192_phy_QueryRFReg(struct net_device *dev, RF90_RADIO_PATH_E eRFPath, |
| 324 | u32 RegAddr, u32 BitMask) |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 325 | { |
| 326 | u32 Original_Value, Readback_Value, BitShift; |
| 327 | struct r8192_priv *priv = ieee80211_priv(dev); |
| 328 | |
| 329 | |
| 330 | if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath)) |
| 331 | return 0; |
Xenia Ragiadakou | 4a6094c | 2013-06-15 07:29:02 +0300 | [diff] [blame] | 332 | if (priv->Rf_Mode == RF_OP_By_FW) { |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 333 | Original_Value = phy_FwRFSerialRead(dev, eRFPath, RegAddr); |
| 334 | BitShift = rtl8192_CalculateBitShift(BitMask); |
| 335 | Readback_Value = (Original_Value & BitMask) >> BitShift; |
| 336 | udelay(200); |
Xenia Ragiadakou | 4c8dd92 | 2013-06-15 07:29:03 +0300 | [diff] [blame] | 337 | return Readback_Value; |
Xenia Ragiadakou | 4a6094c | 2013-06-15 07:29:02 +0300 | [diff] [blame] | 338 | } else { |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 339 | Original_Value = rtl8192_phy_RFSerialRead(dev, eRFPath, RegAddr); |
Mauro Carvalho Chehab | e406322 | 2009-11-03 07:42:46 -0200 | [diff] [blame] | 340 | BitShift = rtl8192_CalculateBitShift(BitMask); |
| 341 | Readback_Value = (Original_Value & BitMask) >> BitShift; |
Xenia Ragiadakou | 4c8dd92 | 2013-06-15 07:29:03 +0300 | [diff] [blame] | 342 | return Readback_Value; |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 343 | } |
| 344 | } |
| 345 | /****************************************************************************** |
| 346 | *function: We support firmware to execute RF-R/W. |
| 347 | * input: dev |
| 348 | * output: none |
| 349 | * return: none |
| 350 | * notice: |
| 351 | * ***************************************************************************/ |
Xenia Ragiadakou | 442543d | 2013-06-15 07:29:08 +0300 | [diff] [blame] | 352 | static u32 phy_FwRFSerialRead(struct net_device *dev, RF90_RADIO_PATH_E eRFPath, |
| 353 | u32 Offset) |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 354 | { |
| 355 | u32 retValue = 0; |
| 356 | u32 Data = 0; |
| 357 | u8 time = 0; |
Xenia Ragiadakou | b3d42bf | 2013-06-06 16:40:51 +0300 | [diff] [blame] | 358 | u32 tmp; |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 359 | /* 2007/11/02 MH Firmware RF Write control. By Francis' suggestion, we can |
| 360 | not execute the scheme in the initial step. Otherwise, RF-R/W will waste |
| 361 | much time. This is only for site survey. */ |
| 362 | // 1. Read operation need not insert data. bit 0-11 |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 363 | // 2. Write RF register address. Bit 12-19 |
| 364 | Data |= ((Offset&0xFF)<<12); |
| 365 | // 3. Write RF path. bit 20-21 |
| 366 | Data |= ((eRFPath&0x3)<<20); |
| 367 | // 4. Set RF read indicator. bit 22=0 |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 368 | // 5. Trigger Fw to operate the command. bit 31 |
| 369 | Data |= 0x80000000; |
| 370 | // 6. We can not execute read operation if bit 31 is 1. |
Xenia Ragiadakou | b3d42bf | 2013-06-06 16:40:51 +0300 | [diff] [blame] | 371 | read_nic_dword(dev, QPNR, &tmp); |
Xenia Ragiadakou | 4a6094c | 2013-06-15 07:29:02 +0300 | [diff] [blame] | 372 | while (tmp & 0x80000000) { |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 373 | // If FW can not finish RF-R/W for more than ?? times. We must reset FW. |
Xenia Ragiadakou | 4a6094c | 2013-06-15 07:29:02 +0300 | [diff] [blame] | 374 | if (time++ < 100) { |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 375 | udelay(10); |
Xenia Ragiadakou | b3d42bf | 2013-06-06 16:40:51 +0300 | [diff] [blame] | 376 | read_nic_dword(dev, QPNR, &tmp); |
Xenia Ragiadakou | 4a6094c | 2013-06-15 07:29:02 +0300 | [diff] [blame] | 377 | } else { |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 378 | break; |
Xenia Ragiadakou | 4a6094c | 2013-06-15 07:29:02 +0300 | [diff] [blame] | 379 | } |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 380 | } |
| 381 | // 7. Execute read operation. |
| 382 | write_nic_dword(dev, QPNR, Data); |
| 383 | // 8. Check if firmawre send back RF content. |
Xenia Ragiadakou | b3d42bf | 2013-06-06 16:40:51 +0300 | [diff] [blame] | 384 | read_nic_dword(dev, QPNR, &tmp); |
Xenia Ragiadakou | 4a6094c | 2013-06-15 07:29:02 +0300 | [diff] [blame] | 385 | while (tmp & 0x80000000) { |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 386 | // If FW can not finish RF-R/W for more than ?? times. We must reset FW. |
Xenia Ragiadakou | 4a6094c | 2013-06-15 07:29:02 +0300 | [diff] [blame] | 387 | if (time++ < 100) { |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 388 | udelay(10); |
Xenia Ragiadakou | b3d42bf | 2013-06-06 16:40:51 +0300 | [diff] [blame] | 389 | read_nic_dword(dev, QPNR, &tmp); |
Xenia Ragiadakou | 4a6094c | 2013-06-15 07:29:02 +0300 | [diff] [blame] | 390 | } else { |
Xenia Ragiadakou | 4c8dd92 | 2013-06-15 07:29:03 +0300 | [diff] [blame] | 391 | return 0; |
Xenia Ragiadakou | 4a6094c | 2013-06-15 07:29:02 +0300 | [diff] [blame] | 392 | } |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 393 | } |
Xenia Ragiadakou | b3d42bf | 2013-06-06 16:40:51 +0300 | [diff] [blame] | 394 | read_nic_dword(dev, RF_DATA, &retValue); |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 395 | |
Xenia Ragiadakou | 4c8dd92 | 2013-06-15 07:29:03 +0300 | [diff] [blame] | 396 | return retValue; |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 397 | |
| 398 | } /* phy_FwRFSerialRead */ |
| 399 | |
| 400 | /****************************************************************************** |
| 401 | *function: We support firmware to execute RF-R/W. |
| 402 | * input: dev |
| 403 | * output: none |
| 404 | * return: none |
| 405 | * notice: |
| 406 | * ***************************************************************************/ |
Xenia Ragiadakou | 442543d | 2013-06-15 07:29:08 +0300 | [diff] [blame] | 407 | static void phy_FwRFSerialWrite(struct net_device *dev, |
| 408 | RF90_RADIO_PATH_E eRFPath, u32 Offset, u32 Data) |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 409 | { |
| 410 | u8 time = 0; |
Xenia Ragiadakou | b3d42bf | 2013-06-06 16:40:51 +0300 | [diff] [blame] | 411 | u32 tmp; |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 412 | |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 413 | /* 2007/11/02 MH Firmware RF Write control. By Francis' suggestion, we can |
| 414 | not execute the scheme in the initial step. Otherwise, RF-R/W will waste |
| 415 | much time. This is only for site survey. */ |
| 416 | |
| 417 | // 1. Set driver write bit and 12 bit data. bit 0-11 |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 418 | // 2. Write RF register address. bit 12-19 |
| 419 | Data |= ((Offset&0xFF)<<12); |
| 420 | // 3. Write RF path. bit 20-21 |
| 421 | Data |= ((eRFPath&0x3)<<20); |
| 422 | // 4. Set RF write indicator. bit 22=1 |
| 423 | Data |= 0x400000; |
| 424 | // 5. Trigger Fw to operate the command. bit 31=1 |
| 425 | Data |= 0x80000000; |
| 426 | |
| 427 | // 6. Write operation. We can not write if bit 31 is 1. |
Xenia Ragiadakou | b3d42bf | 2013-06-06 16:40:51 +0300 | [diff] [blame] | 428 | read_nic_dword(dev, QPNR, &tmp); |
Xenia Ragiadakou | 4a6094c | 2013-06-15 07:29:02 +0300 | [diff] [blame] | 429 | while (tmp & 0x80000000) { |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 430 | // If FW can not finish RF-R/W for more than ?? times. We must reset FW. |
Xenia Ragiadakou | 4a6094c | 2013-06-15 07:29:02 +0300 | [diff] [blame] | 431 | if (time++ < 100) { |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 432 | udelay(10); |
Xenia Ragiadakou | b3d42bf | 2013-06-06 16:40:51 +0300 | [diff] [blame] | 433 | read_nic_dword(dev, QPNR, &tmp); |
Xenia Ragiadakou | 4a6094c | 2013-06-15 07:29:02 +0300 | [diff] [blame] | 434 | } else { |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 435 | break; |
Xenia Ragiadakou | 4a6094c | 2013-06-15 07:29:02 +0300 | [diff] [blame] | 436 | } |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 437 | } |
| 438 | // 7. No matter check bit. We always force the write. Because FW will |
| 439 | // not accept the command. |
| 440 | write_nic_dword(dev, QPNR, Data); |
| 441 | /* 2007/11/02 MH Acoording to test, we must delay 20us to wait firmware |
| 442 | to finish RF write operation. */ |
| 443 | /* 2008/01/17 MH We support delay in firmware side now. */ |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 444 | |
| 445 | } /* phy_FwRFSerialWrite */ |
| 446 | |
| 447 | |
| 448 | /****************************************************************************** |
| 449 | *function: This function read BB parameters from Header file we gen, |
| 450 | * and do register read/write |
| 451 | * input: dev |
| 452 | * output: none |
| 453 | * return: none |
| 454 | * notice: BB parameters may change all the time, so please make |
| 455 | * sure it has been synced with the newest. |
| 456 | * ***************************************************************************/ |
Xenia Ragiadakou | 88d8fe2 | 2013-05-11 17:22:22 +0300 | [diff] [blame] | 457 | void rtl8192_phy_configmac(struct net_device *dev) |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 458 | { |
| 459 | u32 dwArrayLen = 0, i; |
Xenia Ragiadakou | 88d8fe2 | 2013-05-11 17:22:22 +0300 | [diff] [blame] | 460 | u32 *pdwArray = NULL; |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 461 | struct r8192_priv *priv = ieee80211_priv(dev); |
| 462 | |
Xenia Ragiadakou | 1111b87 | 2013-06-15 07:29:04 +0300 | [diff] [blame] | 463 | if (priv->btxpowerdata_readfromEEPORM) { |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 464 | RT_TRACE(COMP_PHY, "Rtl819XMACPHY_Array_PG\n"); |
| 465 | dwArrayLen = MACPHY_Array_PGLength; |
| 466 | pdwArray = rtl819XMACPHY_Array_PG; |
| 467 | |
Xenia Ragiadakou | 4a6094c | 2013-06-15 07:29:02 +0300 | [diff] [blame] | 468 | } else { |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 469 | RT_TRACE(COMP_PHY, "Rtl819XMACPHY_Array\n"); |
| 470 | dwArrayLen = MACPHY_ArrayLength; |
| 471 | pdwArray = rtl819XMACPHY_Array; |
| 472 | } |
Xenia Ragiadakou | 9d8e79e | 2013-06-18 05:29:38 +0300 | [diff] [blame^] | 473 | for (i = 0; i < dwArrayLen; i = i+3) { |
Xenia Ragiadakou | 1111b87 | 2013-06-15 07:29:04 +0300 | [diff] [blame] | 474 | if (pdwArray[i] == 0x318) { |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 475 | pdwArray[i+2] = 0x00000800; |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 476 | } |
| 477 | |
| 478 | RT_TRACE(COMP_DBG, "The Rtl8190MACPHY_Array[0] is %x Rtl8190MACPHY_Array[1] is %x Rtl8190MACPHY_Array[2] is %x\n", |
| 479 | pdwArray[i], pdwArray[i+1], pdwArray[i+2]); |
| 480 | rtl8192_setBBreg(dev, pdwArray[i], pdwArray[i+1], pdwArray[i+2]); |
| 481 | } |
| 482 | return; |
| 483 | |
| 484 | } |
| 485 | |
| 486 | /****************************************************************************** |
Justin P. Mattock | 589b3d0 | 2012-04-30 07:41:36 -0700 | [diff] [blame] | 487 | *function: This function does dirty work |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 488 | * input: dev |
| 489 | * output: none |
| 490 | * return: none |
| 491 | * notice: BB parameters may change all the time, so please make |
| 492 | * sure it has been synced with the newest. |
| 493 | * ***************************************************************************/ |
| 494 | |
Xenia Ragiadakou | 88d8fe2 | 2013-05-11 17:22:22 +0300 | [diff] [blame] | 495 | void rtl8192_phyConfigBB(struct net_device *dev, u8 ConfigType) |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 496 | { |
| 497 | u32 i; |
| 498 | |
| 499 | #ifdef TO_DO_LIST |
| 500 | u32 *rtl8192PhyRegArrayTable = NULL, *rtl8192AgcTabArrayTable = NULL; |
Xenia Ragiadakou | 1111b87 | 2013-06-15 07:29:04 +0300 | [diff] [blame] | 501 | if (Adapter->bInHctTest) { |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 502 | PHY_REGArrayLen = PHY_REGArrayLengthDTM; |
| 503 | AGCTAB_ArrayLen = AGCTAB_ArrayLengthDTM; |
| 504 | Rtl8190PHY_REGArray_Table = Rtl819XPHY_REGArrayDTM; |
| 505 | Rtl8190AGCTAB_Array_Table = Rtl819XAGCTAB_ArrayDTM; |
| 506 | } |
| 507 | #endif |
Xenia Ragiadakou | 4a6094c | 2013-06-15 07:29:02 +0300 | [diff] [blame] | 508 | if (ConfigType == BaseBand_Config_PHY_REG) { |
Xenia Ragiadakou | 9d8e79e | 2013-06-18 05:29:38 +0300 | [diff] [blame^] | 509 | for (i = 0; i < PHY_REG_1T2RArrayLength; i += 2) { |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 510 | rtl8192_setBBreg(dev, rtl819XPHY_REG_1T2RArray[i], bMaskDWord, rtl819XPHY_REG_1T2RArray[i+1]); |
| 511 | RT_TRACE(COMP_DBG, "i: %x, The Rtl819xUsbPHY_REGArray[0] is %x Rtl819xUsbPHY_REGArray[1] is %x \n",i, rtl819XPHY_REG_1T2RArray[i], rtl819XPHY_REG_1T2RArray[i+1]); |
| 512 | } |
Xenia Ragiadakou | 4a6094c | 2013-06-15 07:29:02 +0300 | [diff] [blame] | 513 | } else if (ConfigType == BaseBand_Config_AGC_TAB) { |
Xenia Ragiadakou | 9d8e79e | 2013-06-18 05:29:38 +0300 | [diff] [blame^] | 514 | for (i = 0; i < AGCTAB_ArrayLength; i += 2) { |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 515 | rtl8192_setBBreg(dev, rtl819XAGCTAB_Array[i], bMaskDWord, rtl819XAGCTAB_Array[i+1]); |
| 516 | RT_TRACE(COMP_DBG, "i:%x, The rtl819XAGCTAB_Array[0] is %x rtl819XAGCTAB_Array[1] is %x \n",i, rtl819XAGCTAB_Array[i], rtl819XAGCTAB_Array[i+1]); |
| 517 | } |
| 518 | } |
| 519 | return; |
| 520 | |
| 521 | |
| 522 | } |
| 523 | /****************************************************************************** |
| 524 | *function: This function initialize Register definition offset for Radio Path |
| 525 | * A/B/C/D |
| 526 | * input: net_device dev |
| 527 | * output: none |
| 528 | * return: none |
| 529 | * notice: Initialization value here is constant and it should never be changed |
| 530 | * ***************************************************************************/ |
Xenia Ragiadakou | 88d8fe2 | 2013-05-11 17:22:22 +0300 | [diff] [blame] | 531 | void rtl8192_InitBBRFRegDef(struct net_device *dev) |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 532 | { |
| 533 | struct r8192_priv *priv = ieee80211_priv(dev); |
Justin P. Mattock | 589b3d0 | 2012-04-30 07:41:36 -0700 | [diff] [blame] | 534 | // RF Interface Software Control |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 535 | priv->PHYRegDef[RF90_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW; // 16 LSBs if read 32-bit from 0x870 |
| 536 | priv->PHYRegDef[RF90_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW; // 16 MSBs if read 32-bit from 0x870 (16-bit for 0x872) |
| 537 | priv->PHYRegDef[RF90_PATH_C].rfintfs = rFPGA0_XCD_RFInterfaceSW;// 16 LSBs if read 32-bit from 0x874 |
| 538 | priv->PHYRegDef[RF90_PATH_D].rfintfs = rFPGA0_XCD_RFInterfaceSW;// 16 MSBs if read 32-bit from 0x874 (16-bit for 0x876) |
| 539 | |
| 540 | // RF Interface Readback Value |
| 541 | priv->PHYRegDef[RF90_PATH_A].rfintfi = rFPGA0_XAB_RFInterfaceRB; // 16 LSBs if read 32-bit from 0x8E0 |
| 542 | priv->PHYRegDef[RF90_PATH_B].rfintfi = rFPGA0_XAB_RFInterfaceRB;// 16 MSBs if read 32-bit from 0x8E0 (16-bit for 0x8E2) |
| 543 | priv->PHYRegDef[RF90_PATH_C].rfintfi = rFPGA0_XCD_RFInterfaceRB;// 16 LSBs if read 32-bit from 0x8E4 |
| 544 | priv->PHYRegDef[RF90_PATH_D].rfintfi = rFPGA0_XCD_RFInterfaceRB;// 16 MSBs if read 32-bit from 0x8E4 (16-bit for 0x8E6) |
| 545 | |
| 546 | // RF Interface Output (and Enable) |
| 547 | priv->PHYRegDef[RF90_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE; // 16 LSBs if read 32-bit from 0x860 |
| 548 | priv->PHYRegDef[RF90_PATH_B].rfintfo = rFPGA0_XB_RFInterfaceOE; // 16 LSBs if read 32-bit from 0x864 |
| 549 | priv->PHYRegDef[RF90_PATH_C].rfintfo = rFPGA0_XC_RFInterfaceOE;// 16 LSBs if read 32-bit from 0x868 |
| 550 | priv->PHYRegDef[RF90_PATH_D].rfintfo = rFPGA0_XD_RFInterfaceOE;// 16 LSBs if read 32-bit from 0x86C |
| 551 | |
| 552 | // RF Interface (Output and) Enable |
| 553 | priv->PHYRegDef[RF90_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE; // 16 MSBs if read 32-bit from 0x860 (16-bit for 0x862) |
| 554 | priv->PHYRegDef[RF90_PATH_B].rfintfe = rFPGA0_XB_RFInterfaceOE; // 16 MSBs if read 32-bit from 0x864 (16-bit for 0x866) |
| 555 | priv->PHYRegDef[RF90_PATH_C].rfintfe = rFPGA0_XC_RFInterfaceOE;// 16 MSBs if read 32-bit from 0x86A (16-bit for 0x86A) |
| 556 | priv->PHYRegDef[RF90_PATH_D].rfintfe = rFPGA0_XD_RFInterfaceOE;// 16 MSBs if read 32-bit from 0x86C (16-bit for 0x86E) |
| 557 | |
Justin P. Mattock | 589b3d0 | 2012-04-30 07:41:36 -0700 | [diff] [blame] | 558 | //Addr of LSSI. Write RF register by driver |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 559 | priv->PHYRegDef[RF90_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter; //LSSI Parameter |
| 560 | priv->PHYRegDef[RF90_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter; |
| 561 | priv->PHYRegDef[RF90_PATH_C].rf3wireOffset = rFPGA0_XC_LSSIParameter; |
| 562 | priv->PHYRegDef[RF90_PATH_D].rf3wireOffset = rFPGA0_XD_LSSIParameter; |
| 563 | |
| 564 | // RF parameter |
| 565 | priv->PHYRegDef[RF90_PATH_A].rfLSSI_Select = rFPGA0_XAB_RFParameter; //BB Band Select |
| 566 | priv->PHYRegDef[RF90_PATH_B].rfLSSI_Select = rFPGA0_XAB_RFParameter; |
| 567 | priv->PHYRegDef[RF90_PATH_C].rfLSSI_Select = rFPGA0_XCD_RFParameter; |
| 568 | priv->PHYRegDef[RF90_PATH_D].rfLSSI_Select = rFPGA0_XCD_RFParameter; |
| 569 | |
| 570 | // Tx AGC Gain Stage (same for all path. Should we remove this?) |
| 571 | priv->PHYRegDef[RF90_PATH_A].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage |
| 572 | priv->PHYRegDef[RF90_PATH_B].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage |
| 573 | priv->PHYRegDef[RF90_PATH_C].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage |
| 574 | priv->PHYRegDef[RF90_PATH_D].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage |
| 575 | |
| 576 | // Tranceiver A~D HSSI Parameter-1 |
| 577 | priv->PHYRegDef[RF90_PATH_A].rfHSSIPara1 = rFPGA0_XA_HSSIParameter1; //wire control parameter1 |
| 578 | priv->PHYRegDef[RF90_PATH_B].rfHSSIPara1 = rFPGA0_XB_HSSIParameter1; //wire control parameter1 |
| 579 | priv->PHYRegDef[RF90_PATH_C].rfHSSIPara1 = rFPGA0_XC_HSSIParameter1; //wire control parameter1 |
| 580 | priv->PHYRegDef[RF90_PATH_D].rfHSSIPara1 = rFPGA0_XD_HSSIParameter1; //wire control parameter1 |
| 581 | |
| 582 | // Tranceiver A~D HSSI Parameter-2 |
| 583 | priv->PHYRegDef[RF90_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2; //wire control parameter2 |
| 584 | priv->PHYRegDef[RF90_PATH_B].rfHSSIPara2 = rFPGA0_XB_HSSIParameter2; //wire control parameter2 |
| 585 | priv->PHYRegDef[RF90_PATH_C].rfHSSIPara2 = rFPGA0_XC_HSSIParameter2; //wire control parameter2 |
| 586 | priv->PHYRegDef[RF90_PATH_D].rfHSSIPara2 = rFPGA0_XD_HSSIParameter2; //wire control parameter1 |
| 587 | |
| 588 | // RF switch Control |
| 589 | priv->PHYRegDef[RF90_PATH_A].rfSwitchControl = rFPGA0_XAB_SwitchControl; //TR/Ant switch control |
| 590 | priv->PHYRegDef[RF90_PATH_B].rfSwitchControl = rFPGA0_XAB_SwitchControl; |
| 591 | priv->PHYRegDef[RF90_PATH_C].rfSwitchControl = rFPGA0_XCD_SwitchControl; |
| 592 | priv->PHYRegDef[RF90_PATH_D].rfSwitchControl = rFPGA0_XCD_SwitchControl; |
| 593 | |
| 594 | // AGC control 1 |
| 595 | priv->PHYRegDef[RF90_PATH_A].rfAGCControl1 = rOFDM0_XAAGCCore1; |
| 596 | priv->PHYRegDef[RF90_PATH_B].rfAGCControl1 = rOFDM0_XBAGCCore1; |
| 597 | priv->PHYRegDef[RF90_PATH_C].rfAGCControl1 = rOFDM0_XCAGCCore1; |
| 598 | priv->PHYRegDef[RF90_PATH_D].rfAGCControl1 = rOFDM0_XDAGCCore1; |
| 599 | |
| 600 | // AGC control 2 |
| 601 | priv->PHYRegDef[RF90_PATH_A].rfAGCControl2 = rOFDM0_XAAGCCore2; |
| 602 | priv->PHYRegDef[RF90_PATH_B].rfAGCControl2 = rOFDM0_XBAGCCore2; |
| 603 | priv->PHYRegDef[RF90_PATH_C].rfAGCControl2 = rOFDM0_XCAGCCore2; |
| 604 | priv->PHYRegDef[RF90_PATH_D].rfAGCControl2 = rOFDM0_XDAGCCore2; |
| 605 | |
| 606 | // RX AFE control 1 |
| 607 | priv->PHYRegDef[RF90_PATH_A].rfRxIQImbalance = rOFDM0_XARxIQImbalance; |
| 608 | priv->PHYRegDef[RF90_PATH_B].rfRxIQImbalance = rOFDM0_XBRxIQImbalance; |
| 609 | priv->PHYRegDef[RF90_PATH_C].rfRxIQImbalance = rOFDM0_XCRxIQImbalance; |
| 610 | priv->PHYRegDef[RF90_PATH_D].rfRxIQImbalance = rOFDM0_XDRxIQImbalance; |
| 611 | |
| 612 | // RX AFE control 1 |
| 613 | priv->PHYRegDef[RF90_PATH_A].rfRxAFE = rOFDM0_XARxAFE; |
| 614 | priv->PHYRegDef[RF90_PATH_B].rfRxAFE = rOFDM0_XBRxAFE; |
| 615 | priv->PHYRegDef[RF90_PATH_C].rfRxAFE = rOFDM0_XCRxAFE; |
| 616 | priv->PHYRegDef[RF90_PATH_D].rfRxAFE = rOFDM0_XDRxAFE; |
| 617 | |
| 618 | // Tx AFE control 1 |
| 619 | priv->PHYRegDef[RF90_PATH_A].rfTxIQImbalance = rOFDM0_XATxIQImbalance; |
| 620 | priv->PHYRegDef[RF90_PATH_B].rfTxIQImbalance = rOFDM0_XBTxIQImbalance; |
| 621 | priv->PHYRegDef[RF90_PATH_C].rfTxIQImbalance = rOFDM0_XCTxIQImbalance; |
| 622 | priv->PHYRegDef[RF90_PATH_D].rfTxIQImbalance = rOFDM0_XDTxIQImbalance; |
| 623 | |
| 624 | // Tx AFE control 2 |
| 625 | priv->PHYRegDef[RF90_PATH_A].rfTxAFE = rOFDM0_XATxAFE; |
| 626 | priv->PHYRegDef[RF90_PATH_B].rfTxAFE = rOFDM0_XBTxAFE; |
| 627 | priv->PHYRegDef[RF90_PATH_C].rfTxAFE = rOFDM0_XCTxAFE; |
| 628 | priv->PHYRegDef[RF90_PATH_D].rfTxAFE = rOFDM0_XDTxAFE; |
| 629 | |
| 630 | // Tranceiver LSSI Readback |
| 631 | priv->PHYRegDef[RF90_PATH_A].rfLSSIReadBack = rFPGA0_XA_LSSIReadBack; |
| 632 | priv->PHYRegDef[RF90_PATH_B].rfLSSIReadBack = rFPGA0_XB_LSSIReadBack; |
| 633 | priv->PHYRegDef[RF90_PATH_C].rfLSSIReadBack = rFPGA0_XC_LSSIReadBack; |
| 634 | priv->PHYRegDef[RF90_PATH_D].rfLSSIReadBack = rFPGA0_XD_LSSIReadBack; |
| 635 | |
| 636 | } |
| 637 | /****************************************************************************** |
| 638 | *function: This function is to write register and then readback to make sure whether BB and RF is OK |
| 639 | * input: net_device dev |
Sebastian Hahn | 35997ff | 2012-12-05 21:40:18 +0100 | [diff] [blame] | 640 | * HW90_BLOCK_E CheckBlock |
| 641 | * RF90_RADIO_PATH_E eRFPath //only used when checkblock is HW90_BLOCK_RF |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 642 | * output: none |
| 643 | * return: return whether BB and RF is ok(0:OK; 1:Fail) |
| 644 | * notice: This function may be removed in the ASIC |
| 645 | * ***************************************************************************/ |
Xenia Ragiadakou | 442543d | 2013-06-15 07:29:08 +0300 | [diff] [blame] | 646 | u8 rtl8192_phy_checkBBAndRF(struct net_device *dev, HW90_BLOCK_E CheckBlock, |
| 647 | RF90_RADIO_PATH_E eRFPath) |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 648 | { |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 649 | u8 ret = 0; |
| 650 | u32 i, CheckTimes = 4, dwRegRead = 0; |
| 651 | u32 WriteAddr[4]; |
| 652 | u32 WriteData[] = {0xfffff027, 0xaa55a02f, 0x00000027, 0x55aa502f}; |
| 653 | // Initialize register address offset to be checked |
| 654 | WriteAddr[HW90_BLOCK_MAC] = 0x100; |
| 655 | WriteAddr[HW90_BLOCK_PHY0] = 0x900; |
| 656 | WriteAddr[HW90_BLOCK_PHY1] = 0x800; |
| 657 | WriteAddr[HW90_BLOCK_RF] = 0x3; |
| 658 | RT_TRACE(COMP_PHY, "=======>%s(), CheckBlock:%d\n", __FUNCTION__, CheckBlock); |
Xenia Ragiadakou | 111857c | 2013-06-18 05:29:37 +0300 | [diff] [blame] | 659 | for (i = 0; i < CheckTimes; i++) { |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 660 | |
| 661 | // |
| 662 | // Write Data to register and readback |
| 663 | // |
Xenia Ragiadakou | 4a6094c | 2013-06-15 07:29:02 +0300 | [diff] [blame] | 664 | switch (CheckBlock) { |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 665 | case HW90_BLOCK_MAC: |
| 666 | RT_TRACE(COMP_ERR, "PHY_CheckBBRFOK(): Never Write 0x100 here!"); |
| 667 | break; |
| 668 | |
| 669 | case HW90_BLOCK_PHY0: |
| 670 | case HW90_BLOCK_PHY1: |
| 671 | write_nic_dword(dev, WriteAddr[CheckBlock], WriteData[i]); |
Xenia Ragiadakou | b3d42bf | 2013-06-06 16:40:51 +0300 | [diff] [blame] | 672 | read_nic_dword(dev, WriteAddr[CheckBlock], &dwRegRead); |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 673 | break; |
| 674 | |
| 675 | case HW90_BLOCK_RF: |
| 676 | WriteData[i] &= 0xfff; |
| 677 | rtl8192_phy_SetRFReg(dev, eRFPath, WriteAddr[HW90_BLOCK_RF], bMask12Bits, WriteData[i]); |
| 678 | // TODO: we should not delay for such a long time. Ask SD3 |
| 679 | msleep(1); |
| 680 | dwRegRead = rtl8192_phy_QueryRFReg(dev, eRFPath, WriteAddr[HW90_BLOCK_RF], bMask12Bits); |
| 681 | msleep(1); |
| 682 | break; |
| 683 | |
| 684 | default: |
| 685 | ret = 1; |
| 686 | break; |
| 687 | } |
| 688 | |
| 689 | |
| 690 | // |
| 691 | // Check whether readback data is correct |
| 692 | // |
Xenia Ragiadakou | 1111b87 | 2013-06-15 07:29:04 +0300 | [diff] [blame] | 693 | if (dwRegRead != WriteData[i]) { |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 694 | RT_TRACE((COMP_PHY|COMP_ERR), "====>error=====dwRegRead: %x, WriteData: %x \n", dwRegRead, WriteData[i]); |
| 695 | ret = 1; |
| 696 | break; |
| 697 | } |
| 698 | } |
| 699 | |
| 700 | return ret; |
| 701 | } |
| 702 | |
| 703 | |
| 704 | /****************************************************************************** |
| 705 | *function: This function initialize BB&RF |
| 706 | * input: net_device dev |
| 707 | * output: none |
| 708 | * return: none |
| 709 | * notice: Initialization value may change all the time, so please make |
| 710 | * sure it has been synced with the newest. |
| 711 | * ***************************************************************************/ |
Xenia Ragiadakou | 88d8fe2 | 2013-05-11 17:22:22 +0300 | [diff] [blame] | 712 | void rtl8192_BB_Config_ParaFile(struct net_device *dev) |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 713 | { |
| 714 | struct r8192_priv *priv = ieee80211_priv(dev); |
| 715 | u8 bRegValue = 0, eCheckItem = 0, rtStatus = 0; |
| 716 | u32 dwRegValue = 0; |
| 717 | /************************************** |
| 718 | //<1>Initialize BaseBand |
| 719 | **************************************/ |
| 720 | |
| 721 | /*--set BB Global Reset--*/ |
Xenia Ragiadakou | b3d42bf | 2013-06-06 16:40:51 +0300 | [diff] [blame] | 722 | read_nic_byte(dev, BB_GLOBAL_RESET, &bRegValue); |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 723 | write_nic_byte(dev, BB_GLOBAL_RESET,(bRegValue|BB_GLOBAL_RESET_BIT)); |
| 724 | mdelay(50); |
| 725 | /*---set BB reset Active---*/ |
Xenia Ragiadakou | b3d42bf | 2013-06-06 16:40:51 +0300 | [diff] [blame] | 726 | read_nic_dword(dev, CPU_GEN, &dwRegValue); |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 727 | write_nic_dword(dev, CPU_GEN, (dwRegValue&(~CPU_GEN_BB_RST))); |
| 728 | |
| 729 | /*----Ckeck FPGAPHY0 and PHY1 board is OK----*/ |
| 730 | // TODO: this function should be removed on ASIC , Emily 2007.2.2 |
Xenia Ragiadakou | 9d8e79e | 2013-06-18 05:29:38 +0300 | [diff] [blame^] | 731 | for (eCheckItem = (HW90_BLOCK_E)HW90_BLOCK_PHY0; eCheckItem <= HW90_BLOCK_PHY1; eCheckItem++) { |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 732 | rtStatus = rtl8192_phy_checkBBAndRF(dev, (HW90_BLOCK_E)eCheckItem, (RF90_RADIO_PATH_E)0); //don't care RF path |
Xenia Ragiadakou | 1111b87 | 2013-06-15 07:29:04 +0300 | [diff] [blame] | 733 | if (rtStatus != 0) { |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 734 | RT_TRACE((COMP_ERR | COMP_PHY), "PHY_RF8256_Config():Check PHY%d Fail!!\n", eCheckItem-1); |
Xenia Ragiadakou | 111857c | 2013-06-18 05:29:37 +0300 | [diff] [blame] | 735 | return; |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 736 | } |
| 737 | } |
| 738 | /*---- Set CCK and OFDM Block "OFF"----*/ |
| 739 | rtl8192_setBBreg(dev, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0x0); |
| 740 | /*----BB Register Initilazation----*/ |
| 741 | //==m==>Set PHY REG From Header<==m== |
| 742 | rtl8192_phyConfigBB(dev, BaseBand_Config_PHY_REG); |
| 743 | |
| 744 | /*----Set BB reset de-Active----*/ |
Xenia Ragiadakou | b3d42bf | 2013-06-06 16:40:51 +0300 | [diff] [blame] | 745 | read_nic_dword(dev, CPU_GEN, &dwRegValue); |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 746 | write_nic_dword(dev, CPU_GEN, (dwRegValue|CPU_GEN_BB_RST)); |
| 747 | |
Mauro Carvalho Chehab | e406322 | 2009-11-03 07:42:46 -0200 | [diff] [blame] | 748 | /*----BB AGC table Initialization----*/ |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 749 | //==m==>Set PHY REG From Header<==m== |
| 750 | rtl8192_phyConfigBB(dev, BaseBand_Config_AGC_TAB); |
| 751 | |
| 752 | /*----Enable XSTAL ----*/ |
| 753 | write_nic_byte_E(dev, 0x5e, 0x00); |
Xenia Ragiadakou | 4a6094c | 2013-06-15 07:29:02 +0300 | [diff] [blame] | 754 | if (priv->card_8192_version == (u8)VERSION_819xU_A) { |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 755 | //Antenna gain offset from B/C/D to A |
| 756 | dwRegValue = (priv->AntennaTxPwDiff[1]<<4 | priv->AntennaTxPwDiff[0]); |
| 757 | rtl8192_setBBreg(dev, rFPGA0_TxGainStage, (bXBTxAGC|bXCTxAGC), dwRegValue); |
| 758 | |
| 759 | //XSTALLCap |
| 760 | dwRegValue = priv->CrystalCap & 0xf; |
| 761 | rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, bXtalCap, dwRegValue); |
| 762 | } |
| 763 | |
| 764 | // Check if the CCK HighPower is turned ON. |
| 765 | // This is used to calculate PWDB. |
| 766 | priv->bCckHighPower = (u8)(rtl8192_QueryBBReg(dev, rFPGA0_XA_HSSIParameter2, 0x200)); |
| 767 | return; |
| 768 | } |
| 769 | /****************************************************************************** |
| 770 | *function: This function initialize BB&RF |
| 771 | * input: net_device dev |
| 772 | * output: none |
| 773 | * return: none |
| 774 | * notice: Initialization value may change all the time, so please make |
| 775 | * sure it has been synced with the newest. |
| 776 | * ***************************************************************************/ |
Xenia Ragiadakou | 88d8fe2 | 2013-05-11 17:22:22 +0300 | [diff] [blame] | 777 | void rtl8192_BBConfig(struct net_device *dev) |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 778 | { |
| 779 | rtl8192_InitBBRFRegDef(dev); |
| 780 | //config BB&RF. As hardCode based initialization has not been well |
| 781 | //implemented, so use file first.FIXME:should implement it for hardcode? |
| 782 | rtl8192_BB_Config_ParaFile(dev); |
| 783 | return; |
| 784 | } |
| 785 | |
| 786 | /****************************************************************************** |
| 787 | *function: This function obtains the initialization value of Tx power Level offset |
| 788 | * input: net_device dev |
| 789 | * output: none |
| 790 | * return: none |
| 791 | * ***************************************************************************/ |
Xenia Ragiadakou | 88d8fe2 | 2013-05-11 17:22:22 +0300 | [diff] [blame] | 792 | void rtl8192_phy_getTxPower(struct net_device *dev) |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 793 | { |
| 794 | struct r8192_priv *priv = ieee80211_priv(dev); |
Xenia Ragiadakou | b3d42bf | 2013-06-06 16:40:51 +0300 | [diff] [blame] | 795 | u8 tmp; |
| 796 | read_nic_dword(dev, rTxAGC_Rate18_06, &priv->MCSTxPowerLevelOriginalOffset[0]); |
| 797 | read_nic_dword(dev, rTxAGC_Rate54_24, &priv->MCSTxPowerLevelOriginalOffset[1]); |
| 798 | read_nic_dword(dev, rTxAGC_Mcs03_Mcs00, &priv->MCSTxPowerLevelOriginalOffset[2]); |
| 799 | read_nic_dword(dev, rTxAGC_Mcs07_Mcs04, &priv->MCSTxPowerLevelOriginalOffset[3]); |
| 800 | read_nic_dword(dev, rTxAGC_Mcs11_Mcs08, &priv->MCSTxPowerLevelOriginalOffset[4]); |
| 801 | read_nic_dword(dev, rTxAGC_Mcs15_Mcs12, &priv->MCSTxPowerLevelOriginalOffset[5]); |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 802 | |
| 803 | // read rx initial gain |
Xenia Ragiadakou | b3d42bf | 2013-06-06 16:40:51 +0300 | [diff] [blame] | 804 | read_nic_byte(dev, rOFDM0_XAAGCCore1, &priv->DefaultInitialGain[0]); |
| 805 | read_nic_byte(dev, rOFDM0_XBAGCCore1, &priv->DefaultInitialGain[1]); |
| 806 | read_nic_byte(dev, rOFDM0_XCAGCCore1, &priv->DefaultInitialGain[2]); |
| 807 | read_nic_byte(dev, rOFDM0_XDAGCCore1, &priv->DefaultInitialGain[3]); |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 808 | RT_TRACE(COMP_INIT, "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x) \n", |
| 809 | priv->DefaultInitialGain[0], priv->DefaultInitialGain[1], |
| 810 | priv->DefaultInitialGain[2], priv->DefaultInitialGain[3]); |
| 811 | |
| 812 | // read framesync |
Xenia Ragiadakou | b3d42bf | 2013-06-06 16:40:51 +0300 | [diff] [blame] | 813 | read_nic_byte(dev, rOFDM0_RxDetector3, &priv->framesync); |
| 814 | read_nic_byte(dev, rOFDM0_RxDetector2, &tmp); |
| 815 | priv->framesyncC34 = tmp; |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 816 | RT_TRACE(COMP_INIT, "Default framesync (0x%x) = 0x%x \n", |
| 817 | rOFDM0_RxDetector3, priv->framesync); |
| 818 | |
| 819 | // read SIFS (save the value read fome MACPHY_REG.txt) |
Xenia Ragiadakou | b3d42bf | 2013-06-06 16:40:51 +0300 | [diff] [blame] | 820 | read_nic_word(dev, SIFS, &priv->SifsTime); |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 821 | |
| 822 | return; |
| 823 | } |
| 824 | |
| 825 | /****************************************************************************** |
| 826 | *function: This function obtains the initialization value of Tx power Level offset |
| 827 | * input: net_device dev |
| 828 | * output: none |
| 829 | * return: none |
| 830 | * ***************************************************************************/ |
Xenia Ragiadakou | 88d8fe2 | 2013-05-11 17:22:22 +0300 | [diff] [blame] | 831 | void rtl8192_phy_setTxPower(struct net_device *dev, u8 channel) |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 832 | { |
| 833 | struct r8192_priv *priv = ieee80211_priv(dev); |
| 834 | u8 powerlevel = priv->TxPowerLevelCCK[channel-1]; |
| 835 | u8 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G[channel-1]; |
| 836 | |
Xenia Ragiadakou | 4a6094c | 2013-06-15 07:29:02 +0300 | [diff] [blame] | 837 | switch (priv->rf_chip) { |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 838 | case RF_8256: |
| 839 | PHY_SetRF8256CCKTxPower(dev, powerlevel); //need further implement |
| 840 | PHY_SetRF8256OFDMTxPower(dev, powerlevelOFDM24G); |
| 841 | break; |
| 842 | default: |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 843 | RT_TRACE((COMP_PHY|COMP_ERR), "error RF chipID(8225 or 8258) in function %s()\n", __FUNCTION__); |
| 844 | break; |
| 845 | } |
| 846 | return; |
| 847 | } |
| 848 | |
| 849 | /****************************************************************************** |
| 850 | *function: This function check Rf chip to do RF config |
| 851 | * input: net_device dev |
| 852 | * output: none |
| 853 | * return: only 8256 is supported |
| 854 | * ***************************************************************************/ |
Xenia Ragiadakou | 88d8fe2 | 2013-05-11 17:22:22 +0300 | [diff] [blame] | 855 | void rtl8192_phy_RFConfig(struct net_device *dev) |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 856 | { |
| 857 | struct r8192_priv *priv = ieee80211_priv(dev); |
| 858 | |
Xenia Ragiadakou | 4a6094c | 2013-06-15 07:29:02 +0300 | [diff] [blame] | 859 | switch (priv->rf_chip) { |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 860 | case RF_8256: |
| 861 | PHY_RF8256_Config(dev); |
| 862 | break; |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 863 | default: |
| 864 | RT_TRACE(COMP_ERR, "error chip id\n"); |
| 865 | break; |
| 866 | } |
| 867 | return; |
| 868 | } |
| 869 | |
| 870 | /****************************************************************************** |
| 871 | *function: This function update Initial gain |
| 872 | * input: net_device dev |
| 873 | * output: none |
| 874 | * return: As Windows has not implemented this, wait for complement |
| 875 | * ***************************************************************************/ |
Xenia Ragiadakou | 88d8fe2 | 2013-05-11 17:22:22 +0300 | [diff] [blame] | 876 | void rtl8192_phy_updateInitGain(struct net_device *dev) |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 877 | { |
| 878 | return; |
| 879 | } |
| 880 | |
| 881 | /****************************************************************************** |
| 882 | *function: This function read RF parameters from general head file, and do RF 3-wire |
| 883 | * input: net_device dev |
| 884 | * output: none |
| 885 | * return: return code show if RF configuration is successful(0:pass, 1:fail) |
| 886 | * Note: Delay may be required for RF configuration |
| 887 | * ***************************************************************************/ |
Xenia Ragiadakou | 442543d | 2013-06-15 07:29:08 +0300 | [diff] [blame] | 888 | u8 rtl8192_phy_ConfigRFWithHeaderFile(struct net_device *dev, |
| 889 | RF90_RADIO_PATH_E eRFPath) |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 890 | { |
| 891 | |
| 892 | int i; |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 893 | u8 ret = 0; |
| 894 | |
Xenia Ragiadakou | 4a6094c | 2013-06-15 07:29:02 +0300 | [diff] [blame] | 895 | switch (eRFPath) { |
Sebastian Hahn | 24fbe87 | 2012-12-05 21:40:22 +0100 | [diff] [blame] | 896 | case RF90_PATH_A: |
Xenia Ragiadakou | 9d8e79e | 2013-06-18 05:29:38 +0300 | [diff] [blame^] | 897 | for (i = 0; i < RadioA_ArrayLength; i = i+2) { |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 898 | |
Xenia Ragiadakou | 1111b87 | 2013-06-15 07:29:04 +0300 | [diff] [blame] | 899 | if (rtl819XRadioA_Array[i] == 0xfe) { |
Sebastian Hahn | 24fbe87 | 2012-12-05 21:40:22 +0100 | [diff] [blame] | 900 | mdelay(100); |
| 901 | continue; |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 902 | } |
Sebastian Hahn | 24fbe87 | 2012-12-05 21:40:22 +0100 | [diff] [blame] | 903 | rtl8192_phy_SetRFReg(dev, eRFPath, rtl819XRadioA_Array[i], bMask12Bits, rtl819XRadioA_Array[i+1]); |
| 904 | mdelay(1); |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 905 | |
Sebastian Hahn | 24fbe87 | 2012-12-05 21:40:22 +0100 | [diff] [blame] | 906 | } |
| 907 | break; |
| 908 | case RF90_PATH_B: |
Xenia Ragiadakou | 9d8e79e | 2013-06-18 05:29:38 +0300 | [diff] [blame^] | 909 | for (i = 0; i < RadioB_ArrayLength; i = i+2) { |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 910 | |
Xenia Ragiadakou | 1111b87 | 2013-06-15 07:29:04 +0300 | [diff] [blame] | 911 | if (rtl819XRadioB_Array[i] == 0xfe) { |
Sebastian Hahn | 24fbe87 | 2012-12-05 21:40:22 +0100 | [diff] [blame] | 912 | mdelay(100); |
| 913 | continue; |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 914 | } |
Sebastian Hahn | 24fbe87 | 2012-12-05 21:40:22 +0100 | [diff] [blame] | 915 | rtl8192_phy_SetRFReg(dev, eRFPath, rtl819XRadioB_Array[i], bMask12Bits, rtl819XRadioB_Array[i+1]); |
| 916 | mdelay(1); |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 917 | |
Sebastian Hahn | 24fbe87 | 2012-12-05 21:40:22 +0100 | [diff] [blame] | 918 | } |
| 919 | break; |
| 920 | case RF90_PATH_C: |
Xenia Ragiadakou | 9d8e79e | 2013-06-18 05:29:38 +0300 | [diff] [blame^] | 921 | for (i = 0; i < RadioC_ArrayLength; i = i+2) { |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 922 | |
Xenia Ragiadakou | 1111b87 | 2013-06-15 07:29:04 +0300 | [diff] [blame] | 923 | if (rtl819XRadioC_Array[i] == 0xfe) { |
Sebastian Hahn | 24fbe87 | 2012-12-05 21:40:22 +0100 | [diff] [blame] | 924 | mdelay(100); |
| 925 | continue; |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 926 | } |
Sebastian Hahn | 24fbe87 | 2012-12-05 21:40:22 +0100 | [diff] [blame] | 927 | rtl8192_phy_SetRFReg(dev, eRFPath, rtl819XRadioC_Array[i], bMask12Bits, rtl819XRadioC_Array[i+1]); |
| 928 | mdelay(1); |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 929 | |
Sebastian Hahn | 24fbe87 | 2012-12-05 21:40:22 +0100 | [diff] [blame] | 930 | } |
| 931 | break; |
| 932 | case RF90_PATH_D: |
Xenia Ragiadakou | 9d8e79e | 2013-06-18 05:29:38 +0300 | [diff] [blame^] | 933 | for (i = 0; i < RadioD_ArrayLength; i = i+2) { |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 934 | |
Xenia Ragiadakou | 1111b87 | 2013-06-15 07:29:04 +0300 | [diff] [blame] | 935 | if (rtl819XRadioD_Array[i] == 0xfe) { |
Sebastian Hahn | 24fbe87 | 2012-12-05 21:40:22 +0100 | [diff] [blame] | 936 | mdelay(100); |
| 937 | continue; |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 938 | } |
Sebastian Hahn | 24fbe87 | 2012-12-05 21:40:22 +0100 | [diff] [blame] | 939 | rtl8192_phy_SetRFReg(dev, eRFPath, rtl819XRadioD_Array[i], bMask12Bits, rtl819XRadioD_Array[i+1]); |
| 940 | mdelay(1); |
| 941 | |
| 942 | } |
| 943 | break; |
| 944 | default: |
| 945 | break; |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 946 | } |
| 947 | |
Joe Perches | 859171c | 2010-11-14 19:04:48 -0800 | [diff] [blame] | 948 | return ret; |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 949 | |
| 950 | } |
| 951 | /****************************************************************************** |
| 952 | *function: This function set Tx Power of the channel |
| 953 | * input: struct net_device *dev |
Sebastian Hahn | 35997ff | 2012-12-05 21:40:18 +0100 | [diff] [blame] | 954 | * u8 channel |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 955 | * output: none |
| 956 | * return: none |
| 957 | * Note: |
| 958 | * ***************************************************************************/ |
| 959 | void rtl8192_SetTxPowerLevel(struct net_device *dev, u8 channel) |
| 960 | { |
| 961 | struct r8192_priv *priv = ieee80211_priv(dev); |
| 962 | u8 powerlevel = priv->TxPowerLevelCCK[channel-1]; |
| 963 | u8 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G[channel-1]; |
| 964 | |
Xenia Ragiadakou | 4a6094c | 2013-06-15 07:29:02 +0300 | [diff] [blame] | 965 | switch (priv->rf_chip) { |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 966 | case RF_8225: |
| 967 | #ifdef TO_DO_LIST |
| 968 | PHY_SetRF8225CckTxPower(Adapter, powerlevel); |
| 969 | PHY_SetRF8225OfdmTxPower(Adapter, powerlevelOFDM24G); |
| 970 | #endif |
| 971 | break; |
| 972 | |
| 973 | case RF_8256: |
| 974 | PHY_SetRF8256CCKTxPower(dev, powerlevel); |
| 975 | PHY_SetRF8256OFDMTxPower(dev, powerlevelOFDM24G); |
| 976 | break; |
| 977 | |
| 978 | case RF_8258: |
| 979 | break; |
| 980 | default: |
| 981 | RT_TRACE(COMP_ERR, "unknown rf chip ID in rtl8192_SetTxPowerLevel()\n"); |
| 982 | break; |
| 983 | } |
| 984 | return; |
| 985 | } |
| 986 | |
| 987 | /****************************************************************************** |
| 988 | *function: This function set RF state on or off |
| 989 | * input: struct net_device *dev |
Sebastian Hahn | 35997ff | 2012-12-05 21:40:18 +0100 | [diff] [blame] | 990 | * RT_RF_POWER_STATE eRFPowerState //Power State to set |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 991 | * output: none |
| 992 | * return: none |
| 993 | * Note: |
| 994 | * ***************************************************************************/ |
Xenia Ragiadakou | 442543d | 2013-06-15 07:29:08 +0300 | [diff] [blame] | 995 | bool rtl8192_SetRFPowerState(struct net_device *dev, |
| 996 | RT_RF_POWER_STATE eRFPowerState) |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 997 | { |
| 998 | bool bResult = true; |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 999 | struct r8192_priv *priv = ieee80211_priv(dev); |
| 1000 | |
Xenia Ragiadakou | 1111b87 | 2013-06-15 07:29:04 +0300 | [diff] [blame] | 1001 | if (eRFPowerState == priv->ieee80211->eRFPowerState) |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1002 | return false; |
| 1003 | |
Xenia Ragiadakou | 1111b87 | 2013-06-15 07:29:04 +0300 | [diff] [blame] | 1004 | if (priv->SetRFPowerStateInProgress == true) |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1005 | return false; |
| 1006 | |
| 1007 | priv->SetRFPowerStateInProgress = true; |
| 1008 | |
Xenia Ragiadakou | 4a6094c | 2013-06-15 07:29:02 +0300 | [diff] [blame] | 1009 | switch (priv->rf_chip) { |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1010 | case RF_8256: |
Xenia Ragiadakou | ceb5659 | 2013-06-15 07:29:07 +0300 | [diff] [blame] | 1011 | switch (eRFPowerState) { |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1012 | case eRfOn: |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1013 | //RF-A, RF-B |
| 1014 | //enable RF-Chip A/B |
| 1015 | rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT4, 0x1); // 0x860[4] |
| 1016 | //analog to digital on |
| 1017 | rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300, 0x3);// 0x88c[9:8] |
| 1018 | //digital to analog on |
| 1019 | rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x18, 0x3); // 0x880[4:3] |
| 1020 | //rx antenna on |
| 1021 | rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0x3, 0x3);// 0xc04[1:0] |
| 1022 | //rx antenna on |
| 1023 | rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0x3, 0x3);// 0xd04[1:0] |
| 1024 | //analog to digital part2 on |
| 1025 | rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x60, 0x3); // 0x880[6:5] |
| 1026 | |
| 1027 | break; |
| 1028 | |
| 1029 | case eRfSleep: |
| 1030 | |
| 1031 | break; |
| 1032 | |
| 1033 | case eRfOff: |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1034 | //RF-A, RF-B |
| 1035 | //disable RF-Chip A/B |
| 1036 | rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT4, 0x0); // 0x860[4] |
| 1037 | //analog to digital off, for power save |
| 1038 | rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0);// 0x88c[11:8] |
| 1039 | //digital to analog off, for power save |
| 1040 | rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x18, 0x0); // 0x880[4:3] |
| 1041 | //rx antenna off |
| 1042 | rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0xf, 0x0);// 0xc04[3:0] |
| 1043 | //rx antenna off |
| 1044 | rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0xf, 0x0);// 0xd04[3:0] |
| 1045 | //analog to digital part2 off, for power save |
| 1046 | rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x60, 0x0); // 0x880[6:5] |
| 1047 | |
| 1048 | break; |
| 1049 | |
| 1050 | default: |
| 1051 | bResult = false; |
| 1052 | RT_TRACE(COMP_ERR, "SetRFPowerState819xUsb(): unknow state to set: 0x%X!!!\n", eRFPowerState); |
| 1053 | break; |
| 1054 | } |
| 1055 | break; |
| 1056 | default: |
| 1057 | RT_TRACE(COMP_ERR, "Not support rf_chip(%x)\n", priv->rf_chip); |
| 1058 | break; |
| 1059 | } |
| 1060 | #ifdef TO_DO_LIST |
Xenia Ragiadakou | 1111b87 | 2013-06-15 07:29:04 +0300 | [diff] [blame] | 1061 | if (bResult) { |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1062 | // Update current RF state variable. |
| 1063 | pHalData->eRFPowerState = eRFPowerState; |
Xenia Ragiadakou | ceb5659 | 2013-06-15 07:29:07 +0300 | [diff] [blame] | 1064 | switch (pHalData->RFChipID) { |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1065 | case RF_8256: |
Xenia Ragiadakou | 4a6094c | 2013-06-15 07:29:02 +0300 | [diff] [blame] | 1066 | switch (pHalData->eRFPowerState) { |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1067 | case eRfOff: |
| 1068 | // |
| 1069 | //If Rf off reason is from IPS, Led should blink with no link, by Maddest 071015 |
| 1070 | // |
Xenia Ragiadakou | 9d8e79e | 2013-06-18 05:29:38 +0300 | [diff] [blame^] | 1071 | if (pMgntInfo->RfOffReason == RF_CHANGE_BY_IPS) |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1072 | Adapter->HalFunc.LedControlHandler(Adapter,LED_CTL_NO_LINK); |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1073 | else |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1074 | // Turn off LED if RF is not ON. |
| 1075 | Adapter->HalFunc.LedControlHandler(Adapter, LED_CTL_POWER_OFF); |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1076 | break; |
| 1077 | |
| 1078 | case eRfOn: |
| 1079 | // Turn on RF we are still linked, which might happen when |
| 1080 | // we quickly turn off and on HW RF. 2006.05.12, by rcnjko. |
Xenia Ragiadakou | ceb5659 | 2013-06-15 07:29:07 +0300 | [diff] [blame] | 1081 | if (pMgntInfo->bMediaConnect == TRUE) |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1082 | Adapter->HalFunc.LedControlHandler(Adapter, LED_CTL_LINK); |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1083 | else |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1084 | // Turn off LED if RF is not ON. |
| 1085 | Adapter->HalFunc.LedControlHandler(Adapter, LED_CTL_NO_LINK); |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1086 | break; |
| 1087 | |
| 1088 | default: |
| 1089 | // do nothing. |
| 1090 | break; |
| 1091 | }// Switch RF state |
| 1092 | break; |
| 1093 | |
| 1094 | default: |
| 1095 | RT_TRACE(COMP_RF, DBG_LOUD, ("SetRFPowerState8190(): Unknown RF type\n")); |
| 1096 | break; |
| 1097 | } |
| 1098 | |
| 1099 | } |
| 1100 | #endif |
| 1101 | priv->SetRFPowerStateInProgress = false; |
| 1102 | |
| 1103 | return bResult; |
| 1104 | } |
| 1105 | |
| 1106 | /**************************************************************************************** |
| 1107 | *function: This function set command table variable(struct SwChnlCmd). |
Sebastian Hahn | 35997ff | 2012-12-05 21:40:18 +0100 | [diff] [blame] | 1108 | * input: SwChnlCmd* CmdTable //table to be set. |
| 1109 | * u32 CmdTableIdx //variable index in table to be set |
| 1110 | * u32 CmdTableSz //table size. |
| 1111 | * SwChnlCmdID CmdID //command ID to set. |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1112 | * u32 Para1 |
| 1113 | * u32 Para2 |
| 1114 | * u32 msDelay |
| 1115 | * output: |
| 1116 | * return: true if finished, false otherwise |
| 1117 | * Note: |
| 1118 | * ************************************************************************************/ |
Xenia Ragiadakou | 442543d | 2013-06-15 07:29:08 +0300 | [diff] [blame] | 1119 | u8 rtl8192_phy_SetSwChnlCmdArray(SwChnlCmd *CmdTable, u32 CmdTableIdx, |
| 1120 | u32 CmdTableSz, SwChnlCmdID CmdID, u32 Para1, |
| 1121 | u32 Para2, u32 msDelay) |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1122 | { |
Xenia Ragiadakou | 88d8fe2 | 2013-05-11 17:22:22 +0300 | [diff] [blame] | 1123 | SwChnlCmd *pCmd; |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1124 | |
Xenia Ragiadakou | 1111b87 | 2013-06-15 07:29:04 +0300 | [diff] [blame] | 1125 | if (CmdTable == NULL) { |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1126 | RT_TRACE(COMP_ERR, "phy_SetSwChnlCmdArray(): CmdTable cannot be NULL.\n"); |
| 1127 | return false; |
| 1128 | } |
Xenia Ragiadakou | 1111b87 | 2013-06-15 07:29:04 +0300 | [diff] [blame] | 1129 | if (CmdTableIdx >= CmdTableSz) { |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1130 | RT_TRACE(COMP_ERR, "phy_SetSwChnlCmdArray(): Access invalid index, please check size of the table, CmdTableIdx:%d, CmdTableSz:%d\n", |
| 1131 | CmdTableIdx, CmdTableSz); |
| 1132 | return false; |
| 1133 | } |
| 1134 | |
| 1135 | pCmd = CmdTable + CmdTableIdx; |
| 1136 | pCmd->CmdID = CmdID; |
| 1137 | pCmd->Para1 = Para1; |
| 1138 | pCmd->Para2 = Para2; |
| 1139 | pCmd->msDelay = msDelay; |
| 1140 | |
| 1141 | return true; |
| 1142 | } |
| 1143 | /****************************************************************************** |
| 1144 | *function: This function set channel step by step |
| 1145 | * input: struct net_device *dev |
Sebastian Hahn | 35997ff | 2012-12-05 21:40:18 +0100 | [diff] [blame] | 1146 | * u8 channel |
| 1147 | * u8* stage //3 stages |
| 1148 | * u8* step // |
| 1149 | * u32* delay //whether need to delay |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1150 | * output: store new stage, step and delay for next step(combine with function above) |
| 1151 | * return: true if finished, false otherwise |
| 1152 | * Note: Wait for simpler function to replace it //wb |
| 1153 | * ***************************************************************************/ |
Xenia Ragiadakou | 442543d | 2013-06-15 07:29:08 +0300 | [diff] [blame] | 1154 | u8 rtl8192_phy_SwChnlStepByStep(struct net_device *dev, u8 channel, u8 *stage, |
| 1155 | u8 *step, u32 *delay) |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1156 | { |
| 1157 | struct r8192_priv *priv = ieee80211_priv(dev); |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1158 | SwChnlCmd PreCommonCmd[MAX_PRECMD_CNT]; |
| 1159 | u32 PreCommonCmdCnt; |
| 1160 | SwChnlCmd PostCommonCmd[MAX_POSTCMD_CNT]; |
| 1161 | u32 PostCommonCmdCnt; |
| 1162 | SwChnlCmd RfDependCmd[MAX_RFDEPENDCMD_CNT]; |
| 1163 | u32 RfDependCmdCnt; |
| 1164 | SwChnlCmd *CurrentCmd = NULL; |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1165 | u8 eRFPath; |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1166 | |
| 1167 | RT_TRACE(COMP_CH, "====>%s()====stage:%d, step:%d, channel:%d\n", __FUNCTION__, *stage, *step, channel); |
Xenia Ragiadakou | 4a6094c | 2013-06-15 07:29:02 +0300 | [diff] [blame] | 1168 | if (!IsLegalChannel(priv->ieee80211, channel)) { |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1169 | RT_TRACE(COMP_ERR, "=============>set to illegal channel:%d\n", channel); |
| 1170 | return true; //return true to tell upper caller function this channel setting is finished! Or it will in while loop. |
| 1171 | } |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1172 | //FIXME:need to check whether channel is legal or not here.WB |
| 1173 | |
| 1174 | |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1175 | // <1> Fill up pre common command. |
| 1176 | PreCommonCmdCnt = 0; |
| 1177 | rtl8192_phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++, MAX_PRECMD_CNT, |
| 1178 | CmdID_SetTxPowerLevel, 0, 0, 0); |
| 1179 | rtl8192_phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++, MAX_PRECMD_CNT, |
| 1180 | CmdID_End, 0, 0, 0); |
| 1181 | |
| 1182 | // <2> Fill up post common command. |
| 1183 | PostCommonCmdCnt = 0; |
| 1184 | |
| 1185 | rtl8192_phy_SetSwChnlCmdArray(PostCommonCmd, PostCommonCmdCnt++, MAX_POSTCMD_CNT, |
| 1186 | CmdID_End, 0, 0, 0); |
| 1187 | |
| 1188 | // <3> Fill up RF dependent command. |
| 1189 | RfDependCmdCnt = 0; |
Xenia Ragiadakou | ceb5659 | 2013-06-15 07:29:07 +0300 | [diff] [blame] | 1190 | switch (priv->rf_chip) { |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1191 | case RF_8225: |
Xenia Ragiadakou | 4a6094c | 2013-06-15 07:29:02 +0300 | [diff] [blame] | 1192 | if (!(channel >= 1 && channel <= 14)) { |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1193 | RT_TRACE(COMP_ERR, "illegal channel for Zebra 8225: %d\n", channel); |
| 1194 | return true; |
| 1195 | } |
| 1196 | rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT, |
| 1197 | CmdID_RF_WriteReg, rZebra1_Channel, RF_CHANNEL_TABLE_ZEBRA[channel], 10); |
| 1198 | rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT, |
| 1199 | CmdID_End, 0, 0, 0); |
| 1200 | break; |
| 1201 | |
| 1202 | case RF_8256: |
| 1203 | // TEST!! This is not the table for 8256!! |
Xenia Ragiadakou | 4a6094c | 2013-06-15 07:29:02 +0300 | [diff] [blame] | 1204 | if (!(channel >= 1 && channel <= 14)) { |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1205 | RT_TRACE(COMP_ERR, "illegal channel for Zebra 8256: %d\n", channel); |
| 1206 | return true; |
| 1207 | } |
| 1208 | rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT, |
| 1209 | CmdID_RF_WriteReg, rZebra1_Channel, channel, 10); |
| 1210 | rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT, |
| 1211 | CmdID_End, 0, 0, 0); |
| 1212 | break; |
| 1213 | |
| 1214 | case RF_8258: |
| 1215 | break; |
| 1216 | |
| 1217 | default: |
| 1218 | RT_TRACE(COMP_ERR, "Unknown RFChipID: %d\n", priv->rf_chip); |
| 1219 | return true; |
| 1220 | break; |
| 1221 | } |
| 1222 | |
| 1223 | |
Xenia Ragiadakou | 4a6094c | 2013-06-15 07:29:02 +0300 | [diff] [blame] | 1224 | do { |
| 1225 | switch (*stage) { |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1226 | case 0: |
Xenia Ragiadakou | ec5d319 | 2013-06-18 05:29:36 +0300 | [diff] [blame] | 1227 | CurrentCmd = &PreCommonCmd[*step]; |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1228 | break; |
| 1229 | case 1: |
Xenia Ragiadakou | ec5d319 | 2013-06-18 05:29:36 +0300 | [diff] [blame] | 1230 | CurrentCmd = &RfDependCmd[*step]; |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1231 | break; |
| 1232 | case 2: |
Xenia Ragiadakou | ec5d319 | 2013-06-18 05:29:36 +0300 | [diff] [blame] | 1233 | CurrentCmd = &PostCommonCmd[*step]; |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1234 | break; |
| 1235 | } |
| 1236 | |
Xenia Ragiadakou | 9d8e79e | 2013-06-18 05:29:38 +0300 | [diff] [blame^] | 1237 | if (CurrentCmd->CmdID == CmdID_End) { |
| 1238 | if ((*stage) == 2) { |
Xenia Ragiadakou | ec5d319 | 2013-06-18 05:29:36 +0300 | [diff] [blame] | 1239 | (*delay) = CurrentCmd->msDelay; |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1240 | return true; |
Xenia Ragiadakou | 4a6094c | 2013-06-15 07:29:02 +0300 | [diff] [blame] | 1241 | } else { |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1242 | (*stage)++; |
Xenia Ragiadakou | ec5d319 | 2013-06-18 05:29:36 +0300 | [diff] [blame] | 1243 | (*step) = 0; |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1244 | continue; |
| 1245 | } |
| 1246 | } |
| 1247 | |
Xenia Ragiadakou | 4a6094c | 2013-06-15 07:29:02 +0300 | [diff] [blame] | 1248 | switch (CurrentCmd->CmdID) { |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1249 | case CmdID_SetTxPowerLevel: |
Xenia Ragiadakou | 1111b87 | 2013-06-15 07:29:04 +0300 | [diff] [blame] | 1250 | if (priv->card_8192_version == (u8)VERSION_819xU_A) //xiong: consider it later! |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1251 | rtl8192_SetTxPowerLevel(dev,channel); |
| 1252 | break; |
| 1253 | case CmdID_WritePortUlong: |
| 1254 | write_nic_dword(dev, CurrentCmd->Para1, CurrentCmd->Para2); |
| 1255 | break; |
| 1256 | case CmdID_WritePortUshort: |
| 1257 | write_nic_word(dev, CurrentCmd->Para1, (u16)CurrentCmd->Para2); |
| 1258 | break; |
| 1259 | case CmdID_WritePortUchar: |
| 1260 | write_nic_byte(dev, CurrentCmd->Para1, (u8)CurrentCmd->Para2); |
| 1261 | break; |
| 1262 | case CmdID_RF_WriteReg: |
Xenia Ragiadakou | eadb188 | 2013-06-15 07:29:05 +0300 | [diff] [blame] | 1263 | for (eRFPath = 0; eRFPath < RF90_PATH_MAX; eRFPath++) { |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1264 | rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, CurrentCmd->Para1, bZebra1_ChannelNum, CurrentCmd->Para2); |
| 1265 | } |
| 1266 | break; |
| 1267 | default: |
| 1268 | break; |
| 1269 | } |
| 1270 | |
| 1271 | break; |
Xenia Ragiadakou | eadb188 | 2013-06-15 07:29:05 +0300 | [diff] [blame] | 1272 | } while (true); |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1273 | |
Xenia Ragiadakou | ec5d319 | 2013-06-18 05:29:36 +0300 | [diff] [blame] | 1274 | (*delay) = CurrentCmd->msDelay; |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1275 | (*step)++; |
| 1276 | return false; |
| 1277 | } |
| 1278 | |
| 1279 | /****************************************************************************** |
Justin P. Mattock | 589b3d0 | 2012-04-30 07:41:36 -0700 | [diff] [blame] | 1280 | *function: This function does actually set channel work |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1281 | * input: struct net_device *dev |
Sebastian Hahn | 35997ff | 2012-12-05 21:40:18 +0100 | [diff] [blame] | 1282 | * u8 channel |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1283 | * output: none |
| 1284 | * return: noin |
| 1285 | * Note: We should not call this function directly |
| 1286 | * ***************************************************************************/ |
| 1287 | void rtl8192_phy_FinishSwChnlNow(struct net_device *dev, u8 channel) |
| 1288 | { |
| 1289 | struct r8192_priv *priv = ieee80211_priv(dev); |
| 1290 | u32 delay = 0; |
| 1291 | |
Xenia Ragiadakou | eadb188 | 2013-06-15 07:29:05 +0300 | [diff] [blame] | 1292 | while (!rtl8192_phy_SwChnlStepByStep(dev,channel,&priv->SwChnlStage,&priv->SwChnlStep,&delay)) { |
Xenia Ragiadakou | 1111b87 | 2013-06-15 07:29:04 +0300 | [diff] [blame] | 1293 | if (!priv->up) |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1294 | break; |
| 1295 | } |
| 1296 | } |
| 1297 | /****************************************************************************** |
| 1298 | *function: Callback routine of the work item for switch channel. |
| 1299 | * input: |
| 1300 | * |
| 1301 | * output: none |
| 1302 | * return: noin |
| 1303 | * ***************************************************************************/ |
| 1304 | void rtl8192_SwChnl_WorkItem(struct net_device *dev) |
| 1305 | { |
| 1306 | |
| 1307 | struct r8192_priv *priv = ieee80211_priv(dev); |
| 1308 | |
| 1309 | RT_TRACE(COMP_CH, "==> SwChnlCallback819xUsbWorkItem(), chan:%d\n", priv->chan); |
| 1310 | |
| 1311 | |
| 1312 | rtl8192_phy_FinishSwChnlNow(dev , priv->chan); |
| 1313 | |
| 1314 | RT_TRACE(COMP_CH, "<== SwChnlCallback819xUsbWorkItem()\n"); |
| 1315 | } |
| 1316 | |
| 1317 | /****************************************************************************** |
Justin P. Mattock | 8ef3a7e | 2012-04-30 14:39:21 -0700 | [diff] [blame] | 1318 | *function: This function scheduled actual work item to set channel |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1319 | * input: net_device dev |
Sebastian Hahn | 35997ff | 2012-12-05 21:40:18 +0100 | [diff] [blame] | 1320 | * u8 channel //channel to set |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1321 | * output: none |
| 1322 | * return: return code show if workitem is scheduled(1:pass, 0:fail) |
| 1323 | * Note: Delay may be required for RF configuration |
| 1324 | * ***************************************************************************/ |
Xenia Ragiadakou | 88d8fe2 | 2013-05-11 17:22:22 +0300 | [diff] [blame] | 1325 | u8 rtl8192_phy_SwChnl(struct net_device *dev, u8 channel) |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1326 | { |
| 1327 | struct r8192_priv *priv = ieee80211_priv(dev); |
| 1328 | RT_TRACE(COMP_CH, "=====>%s(), SwChnlInProgress:%d\n", __FUNCTION__, priv->SwChnlInProgress); |
Xenia Ragiadakou | 1111b87 | 2013-06-15 07:29:04 +0300 | [diff] [blame] | 1329 | if (!priv->up) |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1330 | return false; |
Xenia Ragiadakou | 1111b87 | 2013-06-15 07:29:04 +0300 | [diff] [blame] | 1331 | if (priv->SwChnlInProgress) |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1332 | return false; |
| 1333 | |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1334 | //-------------------------------------------- |
Xenia Ragiadakou | 4a6094c | 2013-06-15 07:29:02 +0300 | [diff] [blame] | 1335 | switch (priv->ieee80211->mode) { |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1336 | case WIRELESS_MODE_A: |
| 1337 | case WIRELESS_MODE_N_5G: |
Xenia Ragiadakou | 9d8e79e | 2013-06-18 05:29:38 +0300 | [diff] [blame^] | 1338 | if (channel <= 14) { |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1339 | RT_TRACE(COMP_ERR, "WIRELESS_MODE_A but channel<=14"); |
| 1340 | return false; |
| 1341 | } |
| 1342 | break; |
| 1343 | case WIRELESS_MODE_B: |
Xenia Ragiadakou | 9d8e79e | 2013-06-18 05:29:38 +0300 | [diff] [blame^] | 1344 | if (channel > 14) { |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1345 | RT_TRACE(COMP_ERR, "WIRELESS_MODE_B but channel>14"); |
| 1346 | return false; |
| 1347 | } |
| 1348 | break; |
| 1349 | case WIRELESS_MODE_G: |
| 1350 | case WIRELESS_MODE_N_24G: |
Xenia Ragiadakou | 9d8e79e | 2013-06-18 05:29:38 +0300 | [diff] [blame^] | 1351 | if (channel > 14) { |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1352 | RT_TRACE(COMP_ERR, "WIRELESS_MODE_G but channel>14"); |
| 1353 | return false; |
| 1354 | } |
| 1355 | break; |
| 1356 | } |
| 1357 | //-------------------------------------------- |
| 1358 | |
| 1359 | priv->SwChnlInProgress = true; |
Xenia Ragiadakou | 1111b87 | 2013-06-15 07:29:04 +0300 | [diff] [blame] | 1360 | if (channel == 0) |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1361 | channel = 1; |
| 1362 | |
Xenia Ragiadakou | ec5d319 | 2013-06-18 05:29:36 +0300 | [diff] [blame] | 1363 | priv->chan = channel; |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1364 | |
Xenia Ragiadakou | ec5d319 | 2013-06-18 05:29:36 +0300 | [diff] [blame] | 1365 | priv->SwChnlStage = 0; |
| 1366 | priv->SwChnlStep = 0; |
Xenia Ragiadakou | d75340e | 2013-06-15 07:29:06 +0300 | [diff] [blame] | 1367 | if (priv->up) |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1368 | rtl8192_SwChnl_WorkItem(dev); |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1369 | |
| 1370 | priv->SwChnlInProgress = false; |
| 1371 | return true; |
| 1372 | } |
| 1373 | |
| 1374 | |
| 1375 | // |
| 1376 | /****************************************************************************** |
| 1377 | *function: Callback routine of the work item for set bandwidth mode. |
| 1378 | * input: struct net_device *dev |
Sebastian Hahn | 35997ff | 2012-12-05 21:40:18 +0100 | [diff] [blame] | 1379 | * HT_CHANNEL_WIDTH Bandwidth //20M or 40M |
| 1380 | * HT_EXTCHNL_OFFSET Offset //Upper, Lower, or Don't care |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1381 | * output: none |
| 1382 | * return: none |
| 1383 | * Note: I doubt whether SetBWModeInProgress flag is necessary as we can |
Sebastian Hahn | 35997ff | 2012-12-05 21:40:18 +0100 | [diff] [blame] | 1384 | * test whether current work in the queue or not.//do I? |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1385 | * ***************************************************************************/ |
| 1386 | void rtl8192_SetBWModeWorkItem(struct net_device *dev) |
| 1387 | { |
| 1388 | |
| 1389 | struct r8192_priv *priv = ieee80211_priv(dev); |
| 1390 | u8 regBwOpMode; |
| 1391 | |
| 1392 | RT_TRACE(COMP_SWBW, "==>rtl8192_SetBWModeWorkItem() Switch to %s bandwidth\n", \ |
Xenia Ragiadakou | 4a8d113 | 2013-06-09 14:38:43 +0300 | [diff] [blame] | 1393 | priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20?"20MHz":"40MHz"); |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1394 | |
| 1395 | |
Xenia Ragiadakou | 1111b87 | 2013-06-15 07:29:04 +0300 | [diff] [blame] | 1396 | if (priv->rf_chip == RF_PSEUDO_11N) { |
Xenia Ragiadakou | ec5d319 | 2013-06-18 05:29:36 +0300 | [diff] [blame] | 1397 | priv->SetBWModeInProgress = false; |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1398 | return; |
| 1399 | } |
| 1400 | |
| 1401 | //<1>Set MAC register |
Xenia Ragiadakou | b3d42bf | 2013-06-06 16:40:51 +0300 | [diff] [blame] | 1402 | read_nic_byte(dev, BW_OPMODE, ®BwOpMode); |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1403 | |
Xenia Ragiadakou | 4a6094c | 2013-06-15 07:29:02 +0300 | [diff] [blame] | 1404 | switch (priv->CurrentChannelBW) { |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1405 | case HT_CHANNEL_WIDTH_20: |
| 1406 | regBwOpMode |= BW_OPMODE_20MHZ; |
Lucas De Marchi | 25985ed | 2011-03-30 22:57:33 -0300 | [diff] [blame] | 1407 | // 2007/02/07 Mark by Emily because we have not verify whether this register works |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1408 | write_nic_byte(dev, BW_OPMODE, regBwOpMode); |
| 1409 | break; |
| 1410 | |
| 1411 | case HT_CHANNEL_WIDTH_20_40: |
| 1412 | regBwOpMode &= ~BW_OPMODE_20MHZ; |
Lucas De Marchi | 25985ed | 2011-03-30 22:57:33 -0300 | [diff] [blame] | 1413 | // 2007/02/07 Mark by Emily because we have not verify whether this register works |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1414 | write_nic_byte(dev, BW_OPMODE, regBwOpMode); |
| 1415 | break; |
| 1416 | |
| 1417 | default: |
| 1418 | RT_TRACE(COMP_ERR, "SetChannelBandwidth819xUsb(): unknown Bandwidth: %#X\n",priv->CurrentChannelBW); |
| 1419 | break; |
| 1420 | } |
| 1421 | |
| 1422 | //<2>Set PHY related register |
Xenia Ragiadakou | 4a6094c | 2013-06-15 07:29:02 +0300 | [diff] [blame] | 1423 | switch (priv->CurrentChannelBW) { |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1424 | case HT_CHANNEL_WIDTH_20: |
| 1425 | // Add by Vivi 20071119 |
| 1426 | rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x0); |
| 1427 | rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x0); |
| 1428 | rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 1); |
| 1429 | |
| 1430 | // Correct the tx power for CCK rate in 20M. Suggest by YN, 20071207 |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1431 | priv->cck_present_attentuation = |
| 1432 | priv->cck_present_attentuation_20Mdefault + priv->cck_present_attentuation_difference; |
| 1433 | |
Xenia Ragiadakou | 1111b87 | 2013-06-15 07:29:04 +0300 | [diff] [blame] | 1434 | if (priv->cck_present_attentuation > 22) |
Xenia Ragiadakou | ec5d319 | 2013-06-18 05:29:36 +0300 | [diff] [blame] | 1435 | priv->cck_present_attentuation = 22; |
Xenia Ragiadakou | 9d8e79e | 2013-06-18 05:29:38 +0300 | [diff] [blame^] | 1436 | if (priv->cck_present_attentuation < 0) |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1437 | priv->cck_present_attentuation = 0; |
| 1438 | RT_TRACE(COMP_INIT, "20M, pHalData->CCKPresentAttentuation = %d\n", priv->cck_present_attentuation); |
| 1439 | |
Xenia Ragiadakou | 1111b87 | 2013-06-15 07:29:04 +0300 | [diff] [blame] | 1440 | if (priv->chan == 14 && !priv->bcck_in_ch14) { |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1441 | priv->bcck_in_ch14 = TRUE; |
| 1442 | dm_cck_txpower_adjust(dev,priv->bcck_in_ch14); |
Xenia Ragiadakou | 1111b87 | 2013-06-15 07:29:04 +0300 | [diff] [blame] | 1443 | } else if (priv->chan != 14 && priv->bcck_in_ch14) { |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1444 | priv->bcck_in_ch14 = FALSE; |
| 1445 | dm_cck_txpower_adjust(dev,priv->bcck_in_ch14); |
Xenia Ragiadakou | 4a6094c | 2013-06-15 07:29:02 +0300 | [diff] [blame] | 1446 | } else { |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1447 | dm_cck_txpower_adjust(dev,priv->bcck_in_ch14); |
Xenia Ragiadakou | 4a6094c | 2013-06-15 07:29:02 +0300 | [diff] [blame] | 1448 | } |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1449 | |
| 1450 | break; |
| 1451 | case HT_CHANNEL_WIDTH_20_40: |
| 1452 | // Add by Vivi 20071119 |
| 1453 | rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x1); |
| 1454 | rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x1); |
| 1455 | rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand, (priv->nCur40MhzPrimeSC>>1)); |
Mauro Carvalho Chehab | e406322 | 2009-11-03 07:42:46 -0200 | [diff] [blame] | 1456 | rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 0); |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1457 | rtl8192_setBBreg(dev, rOFDM1_LSTF, 0xC00, priv->nCur40MhzPrimeSC); |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1458 | priv->cck_present_attentuation = |
| 1459 | priv->cck_present_attentuation_40Mdefault + priv->cck_present_attentuation_difference; |
| 1460 | |
Xenia Ragiadakou | 1111b87 | 2013-06-15 07:29:04 +0300 | [diff] [blame] | 1461 | if (priv->cck_present_attentuation > 22) |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1462 | priv->cck_present_attentuation = 22; |
Xenia Ragiadakou | 1111b87 | 2013-06-15 07:29:04 +0300 | [diff] [blame] | 1463 | if (priv->cck_present_attentuation < 0) |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1464 | priv->cck_present_attentuation = 0; |
| 1465 | |
| 1466 | RT_TRACE(COMP_INIT, "40M, pHalData->CCKPresentAttentuation = %d\n", priv->cck_present_attentuation); |
Xenia Ragiadakou | 1111b87 | 2013-06-15 07:29:04 +0300 | [diff] [blame] | 1467 | if (priv->chan == 14 && !priv->bcck_in_ch14) { |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1468 | priv->bcck_in_ch14 = true; |
| 1469 | dm_cck_txpower_adjust(dev,priv->bcck_in_ch14); |
Xenia Ragiadakou | 9d8e79e | 2013-06-18 05:29:38 +0300 | [diff] [blame^] | 1470 | } else if (priv->chan != 14 && priv->bcck_in_ch14) { |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1471 | priv->bcck_in_ch14 = false; |
| 1472 | dm_cck_txpower_adjust(dev,priv->bcck_in_ch14); |
Xenia Ragiadakou | 4a6094c | 2013-06-15 07:29:02 +0300 | [diff] [blame] | 1473 | } else { |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1474 | dm_cck_txpower_adjust(dev,priv->bcck_in_ch14); |
Xenia Ragiadakou | 4a6094c | 2013-06-15 07:29:02 +0300 | [diff] [blame] | 1475 | } |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1476 | |
| 1477 | break; |
| 1478 | default: |
| 1479 | RT_TRACE(COMP_ERR, "SetChannelBandwidth819xUsb(): unknown Bandwidth: %#X\n" ,priv->CurrentChannelBW); |
| 1480 | break; |
| 1481 | |
| 1482 | } |
| 1483 | //Skip over setting of J-mode in BB register here. Default value is "None J mode". Emily 20070315 |
| 1484 | |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1485 | //<3>Set RF related register |
Xenia Ragiadakou | ceb5659 | 2013-06-15 07:29:07 +0300 | [diff] [blame] | 1486 | switch (priv->rf_chip) { |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1487 | case RF_8225: |
| 1488 | #ifdef TO_DO_LIST |
| 1489 | PHY_SetRF8225Bandwidth(Adapter, pHalData->CurrentChannelBW); |
| 1490 | #endif |
| 1491 | break; |
| 1492 | |
| 1493 | case RF_8256: |
| 1494 | PHY_SetRF8256Bandwidth(dev, priv->CurrentChannelBW); |
| 1495 | break; |
| 1496 | |
| 1497 | case RF_8258: |
| 1498 | // PHY_SetRF8258Bandwidth(); |
| 1499 | break; |
| 1500 | |
| 1501 | case RF_PSEUDO_11N: |
| 1502 | // Do Nothing |
| 1503 | break; |
| 1504 | |
| 1505 | default: |
| 1506 | RT_TRACE(COMP_ERR, "Unknown RFChipID: %d\n", priv->rf_chip); |
| 1507 | break; |
| 1508 | } |
Xenia Ragiadakou | ec5d319 | 2013-06-18 05:29:36 +0300 | [diff] [blame] | 1509 | priv->SetBWModeInProgress = false; |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1510 | |
Xenia Ragiadakou | ceb5659 | 2013-06-15 07:29:07 +0300 | [diff] [blame] | 1511 | RT_TRACE(COMP_SWBW, "<==SetBWMode819xUsb(), %d", atomic_read(&(priv->ieee80211->atm_swbw))); |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1512 | } |
| 1513 | |
| 1514 | /****************************************************************************** |
Lucas De Marchi | 25985ed | 2011-03-30 22:57:33 -0300 | [diff] [blame] | 1515 | *function: This function schedules bandwidth switch work. |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1516 | * input: struct net_device *dev |
Sebastian Hahn | 35997ff | 2012-12-05 21:40:18 +0100 | [diff] [blame] | 1517 | * HT_CHANNEL_WIDTH Bandwidth //20M or 40M |
| 1518 | * HT_EXTCHNL_OFFSET Offset //Upper, Lower, or Don't care |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1519 | * output: none |
| 1520 | * return: none |
| 1521 | * Note: I doubt whether SetBWModeInProgress flag is necessary as we can |
Sebastian Hahn | 35997ff | 2012-12-05 21:40:18 +0100 | [diff] [blame] | 1522 | * test whether current work in the queue or not.//do I? |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1523 | * ***************************************************************************/ |
Xenia Ragiadakou | 442543d | 2013-06-15 07:29:08 +0300 | [diff] [blame] | 1524 | void rtl8192_SetBWMode(struct net_device *dev, HT_CHANNEL_WIDTH Bandwidth, |
| 1525 | HT_EXTCHNL_OFFSET Offset) |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1526 | { |
| 1527 | struct r8192_priv *priv = ieee80211_priv(dev); |
| 1528 | |
Xenia Ragiadakou | 1111b87 | 2013-06-15 07:29:04 +0300 | [diff] [blame] | 1529 | if (priv->SetBWModeInProgress) |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1530 | return; |
Xenia Ragiadakou | ec5d319 | 2013-06-18 05:29:36 +0300 | [diff] [blame] | 1531 | priv->SetBWModeInProgress = true; |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1532 | |
| 1533 | priv->CurrentChannelBW = Bandwidth; |
| 1534 | |
Xenia Ragiadakou | 9d8e79e | 2013-06-18 05:29:38 +0300 | [diff] [blame^] | 1535 | if (Offset == HT_EXTCHNL_OFFSET_LOWER) |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1536 | priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_UPPER; |
Xenia Ragiadakou | 9d8e79e | 2013-06-18 05:29:38 +0300 | [diff] [blame^] | 1537 | else if (Offset == HT_EXTCHNL_OFFSET_UPPER) |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1538 | priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_LOWER; |
| 1539 | else |
| 1540 | priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_DONT_CARE; |
| 1541 | |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1542 | rtl8192_SetBWModeWorkItem(dev); |
| 1543 | |
| 1544 | } |
| 1545 | |
| 1546 | void InitialGain819xUsb(struct net_device *dev, u8 Operation) |
| 1547 | { |
| 1548 | struct r8192_priv *priv = ieee80211_priv(dev); |
| 1549 | |
| 1550 | priv->InitialGainOperateType = Operation; |
| 1551 | |
Xenia Ragiadakou | 1111b87 | 2013-06-15 07:29:04 +0300 | [diff] [blame] | 1552 | if (priv->up) |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1553 | queue_delayed_work(priv->priv_wq,&priv->initialgain_operate_wq,0); |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1554 | } |
| 1555 | |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1556 | extern void InitialGainOperateWorkItemCallBack(struct work_struct *work) |
| 1557 | { |
| 1558 | struct delayed_work *dwork = container_of(work,struct delayed_work,work); |
| 1559 | struct r8192_priv *priv = container_of(dwork,struct r8192_priv,initialgain_operate_wq); |
| 1560 | struct net_device *dev = priv->ieee80211->dev; |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1561 | #define SCAN_RX_INITIAL_GAIN 0x17 |
| 1562 | #define POWER_DETECTION_TH 0x08 |
| 1563 | u32 BitMask; |
| 1564 | u8 initial_gain; |
| 1565 | u8 Operation; |
| 1566 | |
| 1567 | Operation = priv->InitialGainOperateType; |
| 1568 | |
Xenia Ragiadakou | 4a6094c | 2013-06-15 07:29:02 +0300 | [diff] [blame] | 1569 | switch (Operation) { |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1570 | case IG_Backup: |
| 1571 | RT_TRACE(COMP_SCAN, "IG_Backup, backup the initial gain.\n"); |
Xenia Ragiadakou | d75340e | 2013-06-15 07:29:06 +0300 | [diff] [blame] | 1572 | initial_gain = SCAN_RX_INITIAL_GAIN; |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1573 | BitMask = bMaskByte0; |
Xenia Ragiadakou | 1111b87 | 2013-06-15 07:29:04 +0300 | [diff] [blame] | 1574 | if (dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM) |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1575 | rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); // FW DIG OFF |
| 1576 | priv->initgain_backup.xaagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XAAGCCore1, BitMask); |
| 1577 | priv->initgain_backup.xbagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XBAGCCore1, BitMask); |
| 1578 | priv->initgain_backup.xcagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XCAGCCore1, BitMask); |
| 1579 | priv->initgain_backup.xdagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XDAGCCore1, BitMask); |
| 1580 | BitMask = bMaskByte2; |
| 1581 | priv->initgain_backup.cca = (u8)rtl8192_QueryBBReg(dev, rCCK0_CCA, BitMask); |
| 1582 | |
| 1583 | RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc50 is %x\n",priv->initgain_backup.xaagccore1); |
| 1584 | RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc58 is %x\n",priv->initgain_backup.xbagccore1); |
| 1585 | RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc60 is %x\n",priv->initgain_backup.xcagccore1); |
| 1586 | RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc68 is %x\n",priv->initgain_backup.xdagccore1); |
| 1587 | RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xa0a is %x\n",priv->initgain_backup.cca); |
| 1588 | |
| 1589 | RT_TRACE(COMP_SCAN, "Write scan initial gain = 0x%x \n", initial_gain); |
| 1590 | write_nic_byte(dev, rOFDM0_XAAGCCore1, initial_gain); |
| 1591 | write_nic_byte(dev, rOFDM0_XBAGCCore1, initial_gain); |
| 1592 | write_nic_byte(dev, rOFDM0_XCAGCCore1, initial_gain); |
| 1593 | write_nic_byte(dev, rOFDM0_XDAGCCore1, initial_gain); |
| 1594 | RT_TRACE(COMP_SCAN, "Write scan 0xa0a = 0x%x \n", POWER_DETECTION_TH); |
| 1595 | write_nic_byte(dev, 0xa0a, POWER_DETECTION_TH); |
| 1596 | break; |
| 1597 | case IG_Restore: |
| 1598 | RT_TRACE(COMP_SCAN, "IG_Restore, restore the initial gain.\n"); |
| 1599 | BitMask = 0x7f; //Bit0~ Bit6 |
Xenia Ragiadakou | 1111b87 | 2013-06-15 07:29:04 +0300 | [diff] [blame] | 1600 | if (dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM) |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1601 | rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); // FW DIG OFF |
| 1602 | |
| 1603 | rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, BitMask, (u32)priv->initgain_backup.xaagccore1); |
| 1604 | rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, BitMask, (u32)priv->initgain_backup.xbagccore1); |
| 1605 | rtl8192_setBBreg(dev, rOFDM0_XCAGCCore1, BitMask, (u32)priv->initgain_backup.xcagccore1); |
| 1606 | rtl8192_setBBreg(dev, rOFDM0_XDAGCCore1, BitMask, (u32)priv->initgain_backup.xdagccore1); |
| 1607 | BitMask = bMaskByte2; |
| 1608 | rtl8192_setBBreg(dev, rCCK0_CCA, BitMask, (u32)priv->initgain_backup.cca); |
| 1609 | |
| 1610 | RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc50 is %x\n",priv->initgain_backup.xaagccore1); |
| 1611 | RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc58 is %x\n",priv->initgain_backup.xbagccore1); |
| 1612 | RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc60 is %x\n",priv->initgain_backup.xcagccore1); |
| 1613 | RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc68 is %x\n",priv->initgain_backup.xdagccore1); |
| 1614 | RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xa0a is %x\n",priv->initgain_backup.cca); |
| 1615 | |
| 1616 | #ifdef RTL8190P |
| 1617 | SetTxPowerLevel8190(Adapter,priv->CurrentChannel); |
| 1618 | #endif |
| 1619 | #ifdef RTL8192E |
| 1620 | SetTxPowerLevel8190(Adapter,priv->CurrentChannel); |
| 1621 | #endif |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1622 | rtl8192_phy_setTxPower(dev,priv->ieee80211->current_network.channel); |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1623 | |
Xenia Ragiadakou | 1111b87 | 2013-06-15 07:29:04 +0300 | [diff] [blame] | 1624 | if (dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM) |
Jerry Chuang | 8fc8598 | 2009-11-03 07:17:11 -0200 | [diff] [blame] | 1625 | rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1); // FW DIG ON |
| 1626 | break; |
| 1627 | default: |
| 1628 | RT_TRACE(COMP_SCAN, "Unknown IG Operation. \n"); |
| 1629 | break; |
| 1630 | } |
| 1631 | } |