Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2007 Stephane Marchesin |
| 3 | * All Rights Reserved. |
| 4 | * |
| 5 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 6 | * copy of this software and associated documentation files (the "Software"), |
| 7 | * to deal in the Software without restriction, including without limitation |
| 8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 9 | * and/or sell copies of the Software, and to permit persons to whom the |
| 10 | * Software is furnished to do so, subject to the following conditions: |
| 11 | * |
| 12 | * The above copyright notice and this permission notice (including the next |
| 13 | * paragraph) shall be included in all copies or substantial portions of the |
| 14 | * Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 19 | * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
| 22 | * DEALINGS IN THE SOFTWARE. |
| 23 | */ |
| 24 | |
| 25 | #include "drmP.h" |
| 26 | #include "drm.h" |
| 27 | #include "nouveau_drm.h" |
| 28 | #include "nouveau_drv.h" |
| 29 | |
| 30 | static uint32_t nv04_graph_ctx_regs[] = { |
| 31 | NV04_PGRAPH_CTX_SWITCH1, |
| 32 | NV04_PGRAPH_CTX_SWITCH2, |
| 33 | NV04_PGRAPH_CTX_SWITCH3, |
| 34 | NV04_PGRAPH_CTX_SWITCH4, |
| 35 | NV04_PGRAPH_CTX_CACHE1, |
| 36 | NV04_PGRAPH_CTX_CACHE2, |
| 37 | NV04_PGRAPH_CTX_CACHE3, |
| 38 | NV04_PGRAPH_CTX_CACHE4, |
| 39 | 0x00400184, |
| 40 | 0x004001a4, |
| 41 | 0x004001c4, |
| 42 | 0x004001e4, |
| 43 | 0x00400188, |
| 44 | 0x004001a8, |
| 45 | 0x004001c8, |
| 46 | 0x004001e8, |
| 47 | 0x0040018c, |
| 48 | 0x004001ac, |
| 49 | 0x004001cc, |
| 50 | 0x004001ec, |
| 51 | 0x00400190, |
| 52 | 0x004001b0, |
| 53 | 0x004001d0, |
| 54 | 0x004001f0, |
| 55 | 0x00400194, |
| 56 | 0x004001b4, |
| 57 | 0x004001d4, |
| 58 | 0x004001f4, |
| 59 | 0x00400198, |
| 60 | 0x004001b8, |
| 61 | 0x004001d8, |
| 62 | 0x004001f8, |
| 63 | 0x0040019c, |
| 64 | 0x004001bc, |
| 65 | 0x004001dc, |
| 66 | 0x004001fc, |
| 67 | 0x00400174, |
| 68 | NV04_PGRAPH_DMA_START_0, |
| 69 | NV04_PGRAPH_DMA_START_1, |
| 70 | NV04_PGRAPH_DMA_LENGTH, |
| 71 | NV04_PGRAPH_DMA_MISC, |
| 72 | NV04_PGRAPH_DMA_PITCH, |
| 73 | NV04_PGRAPH_BOFFSET0, |
| 74 | NV04_PGRAPH_BBASE0, |
| 75 | NV04_PGRAPH_BLIMIT0, |
| 76 | NV04_PGRAPH_BOFFSET1, |
| 77 | NV04_PGRAPH_BBASE1, |
| 78 | NV04_PGRAPH_BLIMIT1, |
| 79 | NV04_PGRAPH_BOFFSET2, |
| 80 | NV04_PGRAPH_BBASE2, |
| 81 | NV04_PGRAPH_BLIMIT2, |
| 82 | NV04_PGRAPH_BOFFSET3, |
| 83 | NV04_PGRAPH_BBASE3, |
| 84 | NV04_PGRAPH_BLIMIT3, |
| 85 | NV04_PGRAPH_BOFFSET4, |
| 86 | NV04_PGRAPH_BBASE4, |
| 87 | NV04_PGRAPH_BLIMIT4, |
| 88 | NV04_PGRAPH_BOFFSET5, |
| 89 | NV04_PGRAPH_BBASE5, |
| 90 | NV04_PGRAPH_BLIMIT5, |
| 91 | NV04_PGRAPH_BPITCH0, |
| 92 | NV04_PGRAPH_BPITCH1, |
| 93 | NV04_PGRAPH_BPITCH2, |
| 94 | NV04_PGRAPH_BPITCH3, |
| 95 | NV04_PGRAPH_BPITCH4, |
| 96 | NV04_PGRAPH_SURFACE, |
| 97 | NV04_PGRAPH_STATE, |
| 98 | NV04_PGRAPH_BSWIZZLE2, |
| 99 | NV04_PGRAPH_BSWIZZLE5, |
| 100 | NV04_PGRAPH_BPIXEL, |
| 101 | NV04_PGRAPH_NOTIFY, |
| 102 | NV04_PGRAPH_PATT_COLOR0, |
| 103 | NV04_PGRAPH_PATT_COLOR1, |
| 104 | NV04_PGRAPH_PATT_COLORRAM+0x00, |
| 105 | NV04_PGRAPH_PATT_COLORRAM+0x01, |
| 106 | NV04_PGRAPH_PATT_COLORRAM+0x02, |
| 107 | NV04_PGRAPH_PATT_COLORRAM+0x03, |
| 108 | NV04_PGRAPH_PATT_COLORRAM+0x04, |
| 109 | NV04_PGRAPH_PATT_COLORRAM+0x05, |
| 110 | NV04_PGRAPH_PATT_COLORRAM+0x06, |
| 111 | NV04_PGRAPH_PATT_COLORRAM+0x07, |
| 112 | NV04_PGRAPH_PATT_COLORRAM+0x08, |
| 113 | NV04_PGRAPH_PATT_COLORRAM+0x09, |
| 114 | NV04_PGRAPH_PATT_COLORRAM+0x0A, |
| 115 | NV04_PGRAPH_PATT_COLORRAM+0x0B, |
| 116 | NV04_PGRAPH_PATT_COLORRAM+0x0C, |
| 117 | NV04_PGRAPH_PATT_COLORRAM+0x0D, |
| 118 | NV04_PGRAPH_PATT_COLORRAM+0x0E, |
| 119 | NV04_PGRAPH_PATT_COLORRAM+0x0F, |
| 120 | NV04_PGRAPH_PATT_COLORRAM+0x10, |
| 121 | NV04_PGRAPH_PATT_COLORRAM+0x11, |
| 122 | NV04_PGRAPH_PATT_COLORRAM+0x12, |
| 123 | NV04_PGRAPH_PATT_COLORRAM+0x13, |
| 124 | NV04_PGRAPH_PATT_COLORRAM+0x14, |
| 125 | NV04_PGRAPH_PATT_COLORRAM+0x15, |
| 126 | NV04_PGRAPH_PATT_COLORRAM+0x16, |
| 127 | NV04_PGRAPH_PATT_COLORRAM+0x17, |
| 128 | NV04_PGRAPH_PATT_COLORRAM+0x18, |
| 129 | NV04_PGRAPH_PATT_COLORRAM+0x19, |
| 130 | NV04_PGRAPH_PATT_COLORRAM+0x1A, |
| 131 | NV04_PGRAPH_PATT_COLORRAM+0x1B, |
| 132 | NV04_PGRAPH_PATT_COLORRAM+0x1C, |
| 133 | NV04_PGRAPH_PATT_COLORRAM+0x1D, |
| 134 | NV04_PGRAPH_PATT_COLORRAM+0x1E, |
| 135 | NV04_PGRAPH_PATT_COLORRAM+0x1F, |
| 136 | NV04_PGRAPH_PATT_COLORRAM+0x20, |
| 137 | NV04_PGRAPH_PATT_COLORRAM+0x21, |
| 138 | NV04_PGRAPH_PATT_COLORRAM+0x22, |
| 139 | NV04_PGRAPH_PATT_COLORRAM+0x23, |
| 140 | NV04_PGRAPH_PATT_COLORRAM+0x24, |
| 141 | NV04_PGRAPH_PATT_COLORRAM+0x25, |
| 142 | NV04_PGRAPH_PATT_COLORRAM+0x26, |
| 143 | NV04_PGRAPH_PATT_COLORRAM+0x27, |
| 144 | NV04_PGRAPH_PATT_COLORRAM+0x28, |
| 145 | NV04_PGRAPH_PATT_COLORRAM+0x29, |
| 146 | NV04_PGRAPH_PATT_COLORRAM+0x2A, |
| 147 | NV04_PGRAPH_PATT_COLORRAM+0x2B, |
| 148 | NV04_PGRAPH_PATT_COLORRAM+0x2C, |
| 149 | NV04_PGRAPH_PATT_COLORRAM+0x2D, |
| 150 | NV04_PGRAPH_PATT_COLORRAM+0x2E, |
| 151 | NV04_PGRAPH_PATT_COLORRAM+0x2F, |
| 152 | NV04_PGRAPH_PATT_COLORRAM+0x30, |
| 153 | NV04_PGRAPH_PATT_COLORRAM+0x31, |
| 154 | NV04_PGRAPH_PATT_COLORRAM+0x32, |
| 155 | NV04_PGRAPH_PATT_COLORRAM+0x33, |
| 156 | NV04_PGRAPH_PATT_COLORRAM+0x34, |
| 157 | NV04_PGRAPH_PATT_COLORRAM+0x35, |
| 158 | NV04_PGRAPH_PATT_COLORRAM+0x36, |
| 159 | NV04_PGRAPH_PATT_COLORRAM+0x37, |
| 160 | NV04_PGRAPH_PATT_COLORRAM+0x38, |
| 161 | NV04_PGRAPH_PATT_COLORRAM+0x39, |
| 162 | NV04_PGRAPH_PATT_COLORRAM+0x3A, |
| 163 | NV04_PGRAPH_PATT_COLORRAM+0x3B, |
| 164 | NV04_PGRAPH_PATT_COLORRAM+0x3C, |
| 165 | NV04_PGRAPH_PATT_COLORRAM+0x3D, |
| 166 | NV04_PGRAPH_PATT_COLORRAM+0x3E, |
| 167 | NV04_PGRAPH_PATT_COLORRAM+0x3F, |
| 168 | NV04_PGRAPH_PATTERN, |
| 169 | 0x0040080c, |
| 170 | NV04_PGRAPH_PATTERN_SHAPE, |
| 171 | 0x00400600, |
| 172 | NV04_PGRAPH_ROP3, |
| 173 | NV04_PGRAPH_CHROMA, |
| 174 | NV04_PGRAPH_BETA_AND, |
| 175 | NV04_PGRAPH_BETA_PREMULT, |
| 176 | NV04_PGRAPH_CONTROL0, |
| 177 | NV04_PGRAPH_CONTROL1, |
| 178 | NV04_PGRAPH_CONTROL2, |
| 179 | NV04_PGRAPH_BLEND, |
| 180 | NV04_PGRAPH_STORED_FMT, |
| 181 | NV04_PGRAPH_SOURCE_COLOR, |
| 182 | 0x00400560, |
| 183 | 0x00400568, |
| 184 | 0x00400564, |
| 185 | 0x0040056c, |
| 186 | 0x00400400, |
| 187 | 0x00400480, |
| 188 | 0x00400404, |
| 189 | 0x00400484, |
| 190 | 0x00400408, |
| 191 | 0x00400488, |
| 192 | 0x0040040c, |
| 193 | 0x0040048c, |
| 194 | 0x00400410, |
| 195 | 0x00400490, |
| 196 | 0x00400414, |
| 197 | 0x00400494, |
| 198 | 0x00400418, |
| 199 | 0x00400498, |
| 200 | 0x0040041c, |
| 201 | 0x0040049c, |
| 202 | 0x00400420, |
| 203 | 0x004004a0, |
| 204 | 0x00400424, |
| 205 | 0x004004a4, |
| 206 | 0x00400428, |
| 207 | 0x004004a8, |
| 208 | 0x0040042c, |
| 209 | 0x004004ac, |
| 210 | 0x00400430, |
| 211 | 0x004004b0, |
| 212 | 0x00400434, |
| 213 | 0x004004b4, |
| 214 | 0x00400438, |
| 215 | 0x004004b8, |
| 216 | 0x0040043c, |
| 217 | 0x004004bc, |
| 218 | 0x00400440, |
| 219 | 0x004004c0, |
| 220 | 0x00400444, |
| 221 | 0x004004c4, |
| 222 | 0x00400448, |
| 223 | 0x004004c8, |
| 224 | 0x0040044c, |
| 225 | 0x004004cc, |
| 226 | 0x00400450, |
| 227 | 0x004004d0, |
| 228 | 0x00400454, |
| 229 | 0x004004d4, |
| 230 | 0x00400458, |
| 231 | 0x004004d8, |
| 232 | 0x0040045c, |
| 233 | 0x004004dc, |
| 234 | 0x00400460, |
| 235 | 0x004004e0, |
| 236 | 0x00400464, |
| 237 | 0x004004e4, |
| 238 | 0x00400468, |
| 239 | 0x004004e8, |
| 240 | 0x0040046c, |
| 241 | 0x004004ec, |
| 242 | 0x00400470, |
| 243 | 0x004004f0, |
| 244 | 0x00400474, |
| 245 | 0x004004f4, |
| 246 | 0x00400478, |
| 247 | 0x004004f8, |
| 248 | 0x0040047c, |
| 249 | 0x004004fc, |
| 250 | 0x0040053c, |
| 251 | 0x00400544, |
| 252 | 0x00400540, |
| 253 | 0x00400548, |
| 254 | 0x00400560, |
| 255 | 0x00400568, |
| 256 | 0x00400564, |
| 257 | 0x0040056c, |
| 258 | 0x00400534, |
| 259 | 0x00400538, |
| 260 | 0x00400514, |
| 261 | 0x00400518, |
| 262 | 0x0040051c, |
| 263 | 0x00400520, |
| 264 | 0x00400524, |
| 265 | 0x00400528, |
| 266 | 0x0040052c, |
| 267 | 0x00400530, |
| 268 | 0x00400d00, |
| 269 | 0x00400d40, |
| 270 | 0x00400d80, |
| 271 | 0x00400d04, |
| 272 | 0x00400d44, |
| 273 | 0x00400d84, |
| 274 | 0x00400d08, |
| 275 | 0x00400d48, |
| 276 | 0x00400d88, |
| 277 | 0x00400d0c, |
| 278 | 0x00400d4c, |
| 279 | 0x00400d8c, |
| 280 | 0x00400d10, |
| 281 | 0x00400d50, |
| 282 | 0x00400d90, |
| 283 | 0x00400d14, |
| 284 | 0x00400d54, |
| 285 | 0x00400d94, |
| 286 | 0x00400d18, |
| 287 | 0x00400d58, |
| 288 | 0x00400d98, |
| 289 | 0x00400d1c, |
| 290 | 0x00400d5c, |
| 291 | 0x00400d9c, |
| 292 | 0x00400d20, |
| 293 | 0x00400d60, |
| 294 | 0x00400da0, |
| 295 | 0x00400d24, |
| 296 | 0x00400d64, |
| 297 | 0x00400da4, |
| 298 | 0x00400d28, |
| 299 | 0x00400d68, |
| 300 | 0x00400da8, |
| 301 | 0x00400d2c, |
| 302 | 0x00400d6c, |
| 303 | 0x00400dac, |
| 304 | 0x00400d30, |
| 305 | 0x00400d70, |
| 306 | 0x00400db0, |
| 307 | 0x00400d34, |
| 308 | 0x00400d74, |
| 309 | 0x00400db4, |
| 310 | 0x00400d38, |
| 311 | 0x00400d78, |
| 312 | 0x00400db8, |
| 313 | 0x00400d3c, |
| 314 | 0x00400d7c, |
| 315 | 0x00400dbc, |
| 316 | 0x00400590, |
| 317 | 0x00400594, |
| 318 | 0x00400598, |
| 319 | 0x0040059c, |
| 320 | 0x004005a8, |
| 321 | 0x004005ac, |
| 322 | 0x004005b0, |
| 323 | 0x004005b4, |
| 324 | 0x004005c0, |
| 325 | 0x004005c4, |
| 326 | 0x004005c8, |
| 327 | 0x004005cc, |
| 328 | 0x004005d0, |
| 329 | 0x004005d4, |
| 330 | 0x004005d8, |
| 331 | 0x004005dc, |
| 332 | 0x004005e0, |
| 333 | NV04_PGRAPH_PASSTHRU_0, |
| 334 | NV04_PGRAPH_PASSTHRU_1, |
| 335 | NV04_PGRAPH_PASSTHRU_2, |
| 336 | NV04_PGRAPH_DVD_COLORFMT, |
| 337 | NV04_PGRAPH_SCALED_FORMAT, |
| 338 | NV04_PGRAPH_MISC24_0, |
| 339 | NV04_PGRAPH_MISC24_1, |
| 340 | NV04_PGRAPH_MISC24_2, |
| 341 | 0x00400500, |
| 342 | 0x00400504, |
| 343 | NV04_PGRAPH_VALID1, |
| 344 | NV04_PGRAPH_VALID2 |
| 345 | |
| 346 | |
| 347 | }; |
| 348 | |
| 349 | struct graph_state { |
| 350 | int nv04[ARRAY_SIZE(nv04_graph_ctx_regs)]; |
| 351 | }; |
| 352 | |
| 353 | struct nouveau_channel * |
| 354 | nv04_graph_channel(struct drm_device *dev) |
| 355 | { |
| 356 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
| 357 | int chid = dev_priv->engine.fifo.channels; |
| 358 | |
| 359 | if (nv_rd32(dev, NV04_PGRAPH_CTX_CONTROL) & 0x00010000) |
| 360 | chid = nv_rd32(dev, NV04_PGRAPH_CTX_USER) >> 24; |
| 361 | |
| 362 | if (chid >= dev_priv->engine.fifo.channels) |
| 363 | return NULL; |
| 364 | |
| 365 | return dev_priv->fifos[chid]; |
| 366 | } |
| 367 | |
| 368 | void |
| 369 | nv04_graph_context_switch(struct drm_device *dev) |
| 370 | { |
| 371 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
| 372 | struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph; |
| 373 | struct nouveau_channel *chan = NULL; |
| 374 | int chid; |
| 375 | |
| 376 | pgraph->fifo_access(dev, false); |
| 377 | nouveau_wait_for_idle(dev); |
| 378 | |
| 379 | /* If previous context is valid, we need to save it */ |
| 380 | pgraph->unload_context(dev); |
| 381 | |
| 382 | /* Load context for next channel */ |
| 383 | chid = dev_priv->engine.fifo.channel_id(dev); |
| 384 | chan = dev_priv->fifos[chid]; |
| 385 | if (chan) |
| 386 | nv04_graph_load_context(chan); |
| 387 | |
| 388 | pgraph->fifo_access(dev, true); |
| 389 | } |
| 390 | |
| 391 | int nv04_graph_create_context(struct nouveau_channel *chan) |
| 392 | { |
| 393 | struct graph_state *pgraph_ctx; |
| 394 | NV_DEBUG(chan->dev, "nv04_graph_context_create %d\n", chan->id); |
| 395 | |
| 396 | chan->pgraph_ctx = pgraph_ctx = kzalloc(sizeof(*pgraph_ctx), |
| 397 | GFP_KERNEL); |
| 398 | if (pgraph_ctx == NULL) |
| 399 | return -ENOMEM; |
| 400 | |
| 401 | /* dev_priv->fifos[channel].pgraph_ctx_user = channel << 24; */ |
| 402 | pgraph_ctx->nv04[0] = 0x0001ffff; |
| 403 | /* is it really needed ??? */ |
| 404 | #if 0 |
| 405 | dev_priv->fifos[channel].pgraph_ctx[1] = |
| 406 | nv_rd32(dev, NV_PGRAPH_DEBUG_4); |
| 407 | dev_priv->fifos[channel].pgraph_ctx[2] = |
| 408 | nv_rd32(dev, 0x004006b0); |
| 409 | #endif |
| 410 | return 0; |
| 411 | } |
| 412 | |
| 413 | void nv04_graph_destroy_context(struct nouveau_channel *chan) |
| 414 | { |
| 415 | struct graph_state *pgraph_ctx = chan->pgraph_ctx; |
| 416 | |
| 417 | kfree(pgraph_ctx); |
| 418 | chan->pgraph_ctx = NULL; |
| 419 | } |
| 420 | |
| 421 | int nv04_graph_load_context(struct nouveau_channel *chan) |
| 422 | { |
| 423 | struct drm_device *dev = chan->dev; |
| 424 | struct graph_state *pgraph_ctx = chan->pgraph_ctx; |
| 425 | uint32_t tmp; |
| 426 | int i; |
| 427 | |
| 428 | for (i = 0; i < ARRAY_SIZE(nv04_graph_ctx_regs); i++) |
| 429 | nv_wr32(dev, nv04_graph_ctx_regs[i], pgraph_ctx->nv04[i]); |
| 430 | |
| 431 | nv_wr32(dev, NV04_PGRAPH_CTX_CONTROL, 0x10010100); |
| 432 | nv_wr32(dev, NV04_PGRAPH_CTX_USER, chan->id << 24); |
| 433 | tmp = nv_rd32(dev, NV04_PGRAPH_FFINTFC_ST2); |
| 434 | nv_wr32(dev, NV04_PGRAPH_FFINTFC_ST2, tmp & 0x000fffff); |
| 435 | return 0; |
| 436 | } |
| 437 | |
| 438 | int |
| 439 | nv04_graph_unload_context(struct drm_device *dev) |
| 440 | { |
| 441 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
| 442 | struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph; |
| 443 | struct nouveau_channel *chan = NULL; |
| 444 | struct graph_state *ctx; |
| 445 | uint32_t tmp; |
| 446 | int i; |
| 447 | |
| 448 | chan = pgraph->channel(dev); |
| 449 | if (!chan) |
| 450 | return 0; |
| 451 | ctx = chan->pgraph_ctx; |
| 452 | |
| 453 | for (i = 0; i < ARRAY_SIZE(nv04_graph_ctx_regs); i++) |
| 454 | ctx->nv04[i] = nv_rd32(dev, nv04_graph_ctx_regs[i]); |
| 455 | |
| 456 | nv_wr32(dev, NV04_PGRAPH_CTX_CONTROL, 0x10000000); |
| 457 | tmp = nv_rd32(dev, NV04_PGRAPH_CTX_USER) & 0x00ffffff; |
| 458 | tmp |= (dev_priv->engine.fifo.channels - 1) << 24; |
| 459 | nv_wr32(dev, NV04_PGRAPH_CTX_USER, tmp); |
| 460 | return 0; |
| 461 | } |
| 462 | |
| 463 | int nv04_graph_init(struct drm_device *dev) |
| 464 | { |
| 465 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
| 466 | uint32_t tmp; |
| 467 | |
| 468 | nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) & |
| 469 | ~NV_PMC_ENABLE_PGRAPH); |
| 470 | nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) | |
| 471 | NV_PMC_ENABLE_PGRAPH); |
| 472 | |
| 473 | /* Enable PGRAPH interrupts */ |
| 474 | nv_wr32(dev, NV03_PGRAPH_INTR, 0xFFFFFFFF); |
| 475 | nv_wr32(dev, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF); |
| 476 | |
| 477 | nv_wr32(dev, NV04_PGRAPH_VALID1, 0); |
| 478 | nv_wr32(dev, NV04_PGRAPH_VALID2, 0); |
| 479 | /*nv_wr32(dev, NV04_PGRAPH_DEBUG_0, 0x000001FF); |
| 480 | nv_wr32(dev, NV04_PGRAPH_DEBUG_0, 0x001FFFFF);*/ |
| 481 | nv_wr32(dev, NV04_PGRAPH_DEBUG_0, 0x1231c000); |
| 482 | /*1231C000 blob, 001 haiku*/ |
| 483 | //*V_WRITE(NV04_PGRAPH_DEBUG_1, 0xf2d91100);*/ |
| 484 | nv_wr32(dev, NV04_PGRAPH_DEBUG_1, 0x72111100); |
| 485 | /*0x72111100 blob , 01 haiku*/ |
| 486 | /*nv_wr32(dev, NV04_PGRAPH_DEBUG_2, 0x11d5f870);*/ |
| 487 | nv_wr32(dev, NV04_PGRAPH_DEBUG_2, 0x11d5f071); |
| 488 | /*haiku same*/ |
| 489 | |
| 490 | /*nv_wr32(dev, NV04_PGRAPH_DEBUG_3, 0xfad4ff31);*/ |
| 491 | nv_wr32(dev, NV04_PGRAPH_DEBUG_3, 0xf0d4ff31); |
| 492 | /*haiku and blob 10d4*/ |
| 493 | |
| 494 | nv_wr32(dev, NV04_PGRAPH_STATE , 0xFFFFFFFF); |
| 495 | nv_wr32(dev, NV04_PGRAPH_CTX_CONTROL , 0x10000100); |
| 496 | tmp = nv_rd32(dev, NV04_PGRAPH_CTX_USER) & 0x00ffffff; |
| 497 | tmp |= dev_priv->engine.fifo.channels << 24; |
| 498 | nv_wr32(dev, NV04_PGRAPH_CTX_USER, tmp); |
| 499 | |
| 500 | /* These don't belong here, they're part of a per-channel context */ |
| 501 | nv_wr32(dev, NV04_PGRAPH_PATTERN_SHAPE, 0x00000000); |
| 502 | nv_wr32(dev, NV04_PGRAPH_BETA_AND , 0xFFFFFFFF); |
| 503 | |
| 504 | return 0; |
| 505 | } |
| 506 | |
| 507 | void nv04_graph_takedown(struct drm_device *dev) |
| 508 | { |
| 509 | } |
| 510 | |
| 511 | void |
| 512 | nv04_graph_fifo_access(struct drm_device *dev, bool enabled) |
| 513 | { |
| 514 | if (enabled) |
| 515 | nv_wr32(dev, NV04_PGRAPH_FIFO, |
| 516 | nv_rd32(dev, NV04_PGRAPH_FIFO) | 1); |
| 517 | else |
| 518 | nv_wr32(dev, NV04_PGRAPH_FIFO, |
| 519 | nv_rd32(dev, NV04_PGRAPH_FIFO) & ~1); |
| 520 | } |
| 521 | |
| 522 | static int |
| 523 | nv04_graph_mthd_set_ref(struct nouveau_channel *chan, int grclass, |
| 524 | int mthd, uint32_t data) |
| 525 | { |
| 526 | chan->fence.last_sequence_irq = data; |
| 527 | nouveau_fence_handler(chan->dev, chan->id); |
| 528 | return 0; |
| 529 | } |
| 530 | |
| 531 | static int |
| 532 | nv04_graph_mthd_set_operation(struct nouveau_channel *chan, int grclass, |
| 533 | int mthd, uint32_t data) |
| 534 | { |
| 535 | struct drm_device *dev = chan->dev; |
| 536 | uint32_t instance = nv_rd32(dev, NV04_PGRAPH_CTX_SWITCH4) & 0xffff; |
| 537 | int subc = (nv_rd32(dev, NV04_PGRAPH_TRAPPED_ADDR) >> 13) & 0x7; |
| 538 | uint32_t tmp; |
| 539 | |
| 540 | tmp = nv_ri32(dev, instance); |
| 541 | tmp &= ~0x00038000; |
| 542 | tmp |= ((data & 7) << 15); |
| 543 | |
| 544 | nv_wi32(dev, instance, tmp); |
| 545 | nv_wr32(dev, NV04_PGRAPH_CTX_SWITCH1, tmp); |
| 546 | nv_wr32(dev, NV04_PGRAPH_CTX_CACHE1 + subc, tmp); |
| 547 | return 0; |
| 548 | } |
| 549 | |
| 550 | static struct nouveau_pgraph_object_method nv04_graph_mthds_m2mf[] = { |
| 551 | { 0x0150, nv04_graph_mthd_set_ref }, |
| 552 | {} |
| 553 | }; |
| 554 | |
| 555 | static struct nouveau_pgraph_object_method nv04_graph_mthds_set_operation[] = { |
| 556 | { 0x02fc, nv04_graph_mthd_set_operation }, |
| 557 | {}, |
| 558 | }; |
| 559 | |
| 560 | struct nouveau_pgraph_object_class nv04_graph_grclass[] = { |
| 561 | { 0x0039, false, nv04_graph_mthds_m2mf }, |
| 562 | { 0x004a, false, nv04_graph_mthds_set_operation }, /* gdirect */ |
| 563 | { 0x005f, false, nv04_graph_mthds_set_operation }, /* imageblit */ |
| 564 | { 0x0061, false, nv04_graph_mthds_set_operation }, /* ifc */ |
| 565 | { 0x0077, false, nv04_graph_mthds_set_operation }, /* sifm */ |
| 566 | { 0x0030, false, NULL }, /* null */ |
| 567 | { 0x0042, false, NULL }, /* surf2d */ |
| 568 | { 0x0043, false, NULL }, /* rop */ |
| 569 | { 0x0012, false, NULL }, /* beta1 */ |
| 570 | { 0x0072, false, NULL }, /* beta4 */ |
| 571 | { 0x0019, false, NULL }, /* cliprect */ |
| 572 | { 0x0044, false, NULL }, /* pattern */ |
| 573 | { 0x0052, false, NULL }, /* swzsurf */ |
| 574 | { 0x0053, false, NULL }, /* surf3d */ |
| 575 | { 0x0054, false, NULL }, /* tex_tri */ |
| 576 | { 0x0055, false, NULL }, /* multitex_tri */ |
| 577 | {} |
| 578 | }; |
| 579 | |