Rob Herring | b3f7ed0 | 2011-09-28 21:27:52 -0500 | [diff] [blame] | 1 | * ARM Generic Interrupt Controller |
| 2 | |
| 3 | ARM SMP cores are often associated with a GIC, providing per processor |
| 4 | interrupts (PPI), shared processor interrupts (SPI) and software |
| 5 | generated interrupts (SGI). |
| 6 | |
| 7 | Primary GIC is attached directly to the CPU and typically has PPIs and SGIs. |
| 8 | Secondary GICs are cascaded into the upward interrupt controller and do not |
| 9 | have PPIs or SGIs. |
| 10 | |
| 11 | Main node required properties: |
| 12 | |
| 13 | - compatible : should be one of: |
Rob Herring | 3ab72f9 | 2013-11-07 20:56:50 -0600 | [diff] [blame] | 14 | "arm,gic-400" |
Marc Zyngier | 0a68214 | 2012-05-09 18:57:57 +0100 | [diff] [blame] | 15 | "arm,cortex-a15-gic" |
Rob Herring | b3f7ed0 | 2011-09-28 21:27:52 -0500 | [diff] [blame] | 16 | "arm,cortex-a9-gic" |
Marc Zyngier | 0a68214 | 2012-05-09 18:57:57 +0100 | [diff] [blame] | 17 | "arm,cortex-a7-gic" |
Rob Herring | b3f7ed0 | 2011-09-28 21:27:52 -0500 | [diff] [blame] | 18 | "arm,arm11mp-gic" |
Marc Carino | f80b713 | 2013-09-06 13:44:19 -0700 | [diff] [blame] | 19 | "brcm,brahma-b15-gic" |
Linus Walleij | f123a66 | 2014-10-01 09:30:45 +0200 | [diff] [blame] | 20 | "arm,arm1176jzf-devchip-gic" |
Rob Herring | b3f7ed0 | 2011-09-28 21:27:52 -0500 | [diff] [blame] | 21 | - interrupt-controller : Identifies the node as an interrupt controller |
| 22 | - #interrupt-cells : Specifies the number of cells needed to encode an |
| 23 | interrupt source. The type shall be a <u32> and the value shall be 3. |
| 24 | |
| 25 | The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI |
| 26 | interrupts. |
| 27 | |
| 28 | The 2nd cell contains the interrupt number for the interrupt type. |
| 29 | SPI interrupts are in the range [0-987]. PPI interrupts are in the |
| 30 | range [0-15]. |
| 31 | |
| 32 | The 3rd cell is the flags, encoded as follows: |
| 33 | bits[3:0] trigger type and level flags. |
| 34 | 1 = low-to-high edge triggered |
| 35 | 2 = high-to-low edge triggered |
| 36 | 4 = active high level-sensitive |
| 37 | 8 = active low level-sensitive |
| 38 | bits[15:8] PPI interrupt cpu mask. Each bit corresponds to each of |
| 39 | the 8 possible cpus attached to the GIC. A bit set to '1' indicated |
| 40 | the interrupt is wired to that CPU. Only valid for PPI interrupts. |
| 41 | |
| 42 | - reg : Specifies base physical address(s) and size of the GIC registers. The |
| 43 | first region is the GIC distributor register base and size. The 2nd region is |
| 44 | the GIC cpu interface register base and size. |
| 45 | |
| 46 | Optional |
Marc Zyngier | 0a68214 | 2012-05-09 18:57:57 +0100 | [diff] [blame] | 47 | - interrupts : Interrupt source of the parent interrupt controller on |
Masanari Iida | f21ccfa | 2013-01-14 15:14:56 +0900 | [diff] [blame] | 48 | secondary GICs, or VGIC maintenance interrupt on primary GIC (see |
Marc Zyngier | 0a68214 | 2012-05-09 18:57:57 +0100 | [diff] [blame] | 49 | below). |
Rob Herring | b3f7ed0 | 2011-09-28 21:27:52 -0500 | [diff] [blame] | 50 | |
Marc Zyngier | db0d4db | 2011-11-12 16:09:49 +0000 | [diff] [blame] | 51 | - cpu-offset : per-cpu offset within the distributor and cpu interface |
| 52 | regions, used when the GIC doesn't have banked registers. The offset is |
| 53 | cpu-offset * cpu-nr. |
| 54 | |
Sricharan R | 006e983 | 2013-12-03 15:57:22 +0530 | [diff] [blame] | 55 | - arm,routable-irqs : Total number of gic irq inputs which are not directly |
| 56 | connected from the peripherals, but are routed dynamically |
| 57 | by a crossbar/multiplexer preceding the GIC. The GIC irq |
| 58 | input line is assigned dynamically when the corresponding |
| 59 | peripheral's crossbar line is mapped. |
Rob Herring | b3f7ed0 | 2011-09-28 21:27:52 -0500 | [diff] [blame] | 60 | Example: |
| 61 | |
| 62 | intc: interrupt-controller@fff11000 { |
| 63 | compatible = "arm,cortex-a9-gic"; |
| 64 | #interrupt-cells = <3>; |
| 65 | #address-cells = <1>; |
| 66 | interrupt-controller; |
Sricharan R | 006e983 | 2013-12-03 15:57:22 +0530 | [diff] [blame] | 67 | arm,routable-irqs = <160>; |
Rob Herring | b3f7ed0 | 2011-09-28 21:27:52 -0500 | [diff] [blame] | 68 | reg = <0xfff11000 0x1000>, |
| 69 | <0xfff10100 0x100>; |
| 70 | }; |
| 71 | |
Marc Zyngier | 0a68214 | 2012-05-09 18:57:57 +0100 | [diff] [blame] | 72 | |
| 73 | * GIC virtualization extensions (VGIC) |
| 74 | |
| 75 | For ARM cores that support the virtualization extensions, additional |
| 76 | properties must be described (they only exist if the GIC is the |
| 77 | primary interrupt controller). |
| 78 | |
| 79 | Required properties: |
| 80 | |
| 81 | - reg : Additional regions specifying the base physical address and |
| 82 | size of the VGIC registers. The first additional region is the GIC |
| 83 | virtual interface control register base and size. The 2nd additional |
| 84 | region is the GIC virtual cpu interface register base and size. |
| 85 | |
Masanari Iida | f21ccfa | 2013-01-14 15:14:56 +0900 | [diff] [blame] | 86 | - interrupts : VGIC maintenance interrupt. |
Marc Zyngier | 0a68214 | 2012-05-09 18:57:57 +0100 | [diff] [blame] | 87 | |
| 88 | Example: |
| 89 | |
| 90 | interrupt-controller@2c001000 { |
| 91 | compatible = "arm,cortex-a15-gic"; |
| 92 | #interrupt-cells = <3>; |
| 93 | interrupt-controller; |
| 94 | reg = <0x2c001000 0x1000>, |
| 95 | <0x2c002000 0x1000>, |
| 96 | <0x2c004000 0x2000>, |
| 97 | <0x2c006000 0x2000>; |
| 98 | interrupts = <1 9 0xf04>; |
| 99 | }; |