Paul Walmsley | 0d619a8 | 2011-07-09 19:14:07 -0600 | [diff] [blame] | 1 | /* |
| 2 | * omap_hwmod_2xxx_3xxx_ipblock_data.c - common IP block data for OMAP2/3 |
| 3 | * |
| 4 | * Copyright (C) 2011 Nokia Corporation |
Paul Walmsley | 03d830e | 2012-05-08 11:34:27 -0600 | [diff] [blame] | 5 | * Copyright (C) 2012 Texas Instruments, Inc. |
Paul Walmsley | 0d619a8 | 2011-07-09 19:14:07 -0600 | [diff] [blame] | 6 | * Paul Walmsley |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License version 2 as |
| 10 | * published by the Free Software Foundation. |
| 11 | */ |
Tony Lindgren | 2a296c8 | 2012-10-02 17:41:35 -0700 | [diff] [blame] | 12 | |
Tony Lindgren | 45c3eb7 | 2012-11-30 08:41:50 -0800 | [diff] [blame] | 13 | #include <linux/dmaengine.h> |
| 14 | #include <linux/omap-dma.h> |
Tony Lindgren | 2a296c8 | 2012-10-02 17:41:35 -0700 | [diff] [blame] | 15 | |
Tony Lindgren | 2a296c8 | 2012-10-02 17:41:35 -0700 | [diff] [blame] | 16 | #include "omap_hwmod.h" |
Tony Lindgren | a0b30ca | 2012-09-20 11:41:48 -0700 | [diff] [blame] | 17 | #include "hdq1w.h" |
Paul Walmsley | 0d619a8 | 2011-07-09 19:14:07 -0600 | [diff] [blame] | 18 | |
Paul Walmsley | 0d619a8 | 2011-07-09 19:14:07 -0600 | [diff] [blame] | 19 | #include "omap_hwmod_common_data.h" |
| 20 | |
Paul Walmsley | 273b946 | 2011-07-09 19:14:08 -0600 | [diff] [blame] | 21 | /* UART */ |
| 22 | |
| 23 | static struct omap_hwmod_class_sysconfig omap2_uart_sysc = { |
| 24 | .rev_offs = 0x50, |
| 25 | .sysc_offs = 0x54, |
| 26 | .syss_offs = 0x58, |
| 27 | .sysc_flags = (SYSC_HAS_SIDLEMODE | |
| 28 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | |
| 29 | SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), |
| 30 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), |
| 31 | .sysc_fields = &omap_hwmod_sysc_type1, |
| 32 | }; |
| 33 | |
| 34 | struct omap_hwmod_class omap2_uart_class = { |
| 35 | .name = "uart", |
| 36 | .sysc = &omap2_uart_sysc, |
| 37 | }; |
| 38 | |
| 39 | /* |
Paul Walmsley | 273b946 | 2011-07-09 19:14:08 -0600 | [diff] [blame] | 40 | * 'venc' class |
| 41 | * video encoder |
| 42 | */ |
| 43 | |
| 44 | struct omap_hwmod_class omap2_venc_hwmod_class = { |
| 45 | .name = "venc", |
| 46 | }; |
| 47 | |
| 48 | |
| 49 | /* Common DMA request line data */ |
| 50 | struct omap_hwmod_dma_info omap2_uart1_sdma_reqs[] = { |
Jarkko Nikula | 0fd8824 | 2013-06-15 11:31:04 +0300 | [diff] [blame] | 51 | { .name = "rx", .dma_req = 50, }, |
| 52 | { .name = "tx", .dma_req = 49, }, |
Paul Walmsley | 273b946 | 2011-07-09 19:14:08 -0600 | [diff] [blame] | 53 | { .dma_req = -1 } |
| 54 | }; |
| 55 | |
| 56 | struct omap_hwmod_dma_info omap2_uart2_sdma_reqs[] = { |
Jarkko Nikula | 0fd8824 | 2013-06-15 11:31:04 +0300 | [diff] [blame] | 57 | { .name = "rx", .dma_req = 52, }, |
| 58 | { .name = "tx", .dma_req = 51, }, |
Paul Walmsley | 273b946 | 2011-07-09 19:14:08 -0600 | [diff] [blame] | 59 | { .dma_req = -1 } |
| 60 | }; |
| 61 | |
| 62 | struct omap_hwmod_dma_info omap2_uart3_sdma_reqs[] = { |
Jarkko Nikula | 0fd8824 | 2013-06-15 11:31:04 +0300 | [diff] [blame] | 63 | { .name = "rx", .dma_req = 54, }, |
| 64 | { .name = "tx", .dma_req = 53, }, |
Paul Walmsley | 273b946 | 2011-07-09 19:14:08 -0600 | [diff] [blame] | 65 | { .dma_req = -1 } |
| 66 | }; |
| 67 | |
| 68 | struct omap_hwmod_dma_info omap2_i2c1_sdma_reqs[] = { |
Jarkko Nikula | 0fd8824 | 2013-06-15 11:31:04 +0300 | [diff] [blame] | 69 | { .name = "tx", .dma_req = 27 }, |
| 70 | { .name = "rx", .dma_req = 28 }, |
Paul Walmsley | 273b946 | 2011-07-09 19:14:08 -0600 | [diff] [blame] | 71 | { .dma_req = -1 } |
| 72 | }; |
| 73 | |
| 74 | struct omap_hwmod_dma_info omap2_i2c2_sdma_reqs[] = { |
Jarkko Nikula | 0fd8824 | 2013-06-15 11:31:04 +0300 | [diff] [blame] | 75 | { .name = "tx", .dma_req = 29 }, |
| 76 | { .name = "rx", .dma_req = 30 }, |
Paul Walmsley | 273b946 | 2011-07-09 19:14:08 -0600 | [diff] [blame] | 77 | { .dma_req = -1 } |
| 78 | }; |
| 79 | |
| 80 | struct omap_hwmod_dma_info omap2_mcspi1_sdma_reqs[] = { |
| 81 | { .name = "tx0", .dma_req = 35 }, /* DMA_SPI1_TX0 */ |
| 82 | { .name = "rx0", .dma_req = 36 }, /* DMA_SPI1_RX0 */ |
| 83 | { .name = "tx1", .dma_req = 37 }, /* DMA_SPI1_TX1 */ |
| 84 | { .name = "rx1", .dma_req = 38 }, /* DMA_SPI1_RX1 */ |
| 85 | { .name = "tx2", .dma_req = 39 }, /* DMA_SPI1_TX2 */ |
| 86 | { .name = "rx2", .dma_req = 40 }, /* DMA_SPI1_RX2 */ |
| 87 | { .name = "tx3", .dma_req = 41 }, /* DMA_SPI1_TX3 */ |
| 88 | { .name = "rx3", .dma_req = 42 }, /* DMA_SPI1_RX3 */ |
| 89 | { .dma_req = -1 } |
| 90 | }; |
| 91 | |
| 92 | struct omap_hwmod_dma_info omap2_mcspi2_sdma_reqs[] = { |
| 93 | { .name = "tx0", .dma_req = 43 }, /* DMA_SPI2_TX0 */ |
| 94 | { .name = "rx0", .dma_req = 44 }, /* DMA_SPI2_RX0 */ |
| 95 | { .name = "tx1", .dma_req = 45 }, /* DMA_SPI2_TX1 */ |
| 96 | { .name = "rx1", .dma_req = 46 }, /* DMA_SPI2_RX1 */ |
| 97 | { .dma_req = -1 } |
| 98 | }; |
| 99 | |
| 100 | struct omap_hwmod_dma_info omap2_mcbsp1_sdma_reqs[] = { |
| 101 | { .name = "rx", .dma_req = 32 }, |
| 102 | { .name = "tx", .dma_req = 31 }, |
| 103 | { .dma_req = -1 } |
| 104 | }; |
| 105 | |
| 106 | struct omap_hwmod_dma_info omap2_mcbsp2_sdma_reqs[] = { |
| 107 | { .name = "rx", .dma_req = 34 }, |
| 108 | { .name = "tx", .dma_req = 33 }, |
| 109 | { .dma_req = -1 } |
| 110 | }; |
| 111 | |
| 112 | struct omap_hwmod_dma_info omap2_mcbsp3_sdma_reqs[] = { |
| 113 | { .name = "rx", .dma_req = 18 }, |
| 114 | { .name = "tx", .dma_req = 17 }, |
| 115 | { .dma_req = -1 } |
| 116 | }; |
| 117 | |
| 118 | /* Other IP block data */ |
| 119 | |
Paul Walmsley | d826ebf | 2011-07-09 19:14:07 -0600 | [diff] [blame] | 120 | |
| 121 | /* |
| 122 | * omap_hwmod class data |
| 123 | */ |
| 124 | |
| 125 | struct omap_hwmod_class l3_hwmod_class = { |
| 126 | .name = "l3" |
| 127 | }; |
| 128 | |
| 129 | struct omap_hwmod_class l4_hwmod_class = { |
| 130 | .name = "l4" |
| 131 | }; |
| 132 | |
| 133 | struct omap_hwmod_class mpu_hwmod_class = { |
| 134 | .name = "mpu" |
| 135 | }; |
| 136 | |
| 137 | struct omap_hwmod_class iva_hwmod_class = { |
| 138 | .name = "iva" |
| 139 | }; |
| 140 | |
| 141 | /* Common MPU IRQ line data */ |
| 142 | |
Paul Walmsley | 0d619a8 | 2011-07-09 19:14:07 -0600 | [diff] [blame] | 143 | struct omap_hwmod_irq_info omap2_timer1_mpu_irqs[] = { |
Tony Lindgren | 7d7e1eb | 2012-08-27 17:43:01 -0700 | [diff] [blame] | 144 | { .irq = 37 + OMAP_INTC_START, }, |
| 145 | { .irq = -1 }, |
Paul Walmsley | 0d619a8 | 2011-07-09 19:14:07 -0600 | [diff] [blame] | 146 | }; |
| 147 | |
| 148 | struct omap_hwmod_irq_info omap2_timer2_mpu_irqs[] = { |
Tony Lindgren | 7d7e1eb | 2012-08-27 17:43:01 -0700 | [diff] [blame] | 149 | { .irq = 38 + OMAP_INTC_START, }, |
| 150 | { .irq = -1 }, |
Paul Walmsley | 0d619a8 | 2011-07-09 19:14:07 -0600 | [diff] [blame] | 151 | }; |
| 152 | |
| 153 | struct omap_hwmod_irq_info omap2_timer3_mpu_irqs[] = { |
Tony Lindgren | 7d7e1eb | 2012-08-27 17:43:01 -0700 | [diff] [blame] | 154 | { .irq = 39 + OMAP_INTC_START, }, |
| 155 | { .irq = -1 }, |
Paul Walmsley | 0d619a8 | 2011-07-09 19:14:07 -0600 | [diff] [blame] | 156 | }; |
| 157 | |
| 158 | struct omap_hwmod_irq_info omap2_timer4_mpu_irqs[] = { |
Tony Lindgren | 7d7e1eb | 2012-08-27 17:43:01 -0700 | [diff] [blame] | 159 | { .irq = 40 + OMAP_INTC_START, }, |
| 160 | { .irq = -1 }, |
Paul Walmsley | 0d619a8 | 2011-07-09 19:14:07 -0600 | [diff] [blame] | 161 | }; |
| 162 | |
| 163 | struct omap_hwmod_irq_info omap2_timer5_mpu_irqs[] = { |
Tony Lindgren | 7d7e1eb | 2012-08-27 17:43:01 -0700 | [diff] [blame] | 164 | { .irq = 41 + OMAP_INTC_START, }, |
| 165 | { .irq = -1 }, |
Paul Walmsley | 0d619a8 | 2011-07-09 19:14:07 -0600 | [diff] [blame] | 166 | }; |
| 167 | |
| 168 | struct omap_hwmod_irq_info omap2_timer6_mpu_irqs[] = { |
Tony Lindgren | 7d7e1eb | 2012-08-27 17:43:01 -0700 | [diff] [blame] | 169 | { .irq = 42 + OMAP_INTC_START, }, |
| 170 | { .irq = -1 }, |
Paul Walmsley | 0d619a8 | 2011-07-09 19:14:07 -0600 | [diff] [blame] | 171 | }; |
| 172 | |
| 173 | struct omap_hwmod_irq_info omap2_timer7_mpu_irqs[] = { |
Tony Lindgren | 7d7e1eb | 2012-08-27 17:43:01 -0700 | [diff] [blame] | 174 | { .irq = 43 + OMAP_INTC_START, }, |
| 175 | { .irq = -1 }, |
Paul Walmsley | 0d619a8 | 2011-07-09 19:14:07 -0600 | [diff] [blame] | 176 | }; |
| 177 | |
| 178 | struct omap_hwmod_irq_info omap2_timer8_mpu_irqs[] = { |
Tony Lindgren | 7d7e1eb | 2012-08-27 17:43:01 -0700 | [diff] [blame] | 179 | { .irq = 44 + OMAP_INTC_START, }, |
| 180 | { .irq = -1 }, |
Paul Walmsley | 0d619a8 | 2011-07-09 19:14:07 -0600 | [diff] [blame] | 181 | }; |
| 182 | |
| 183 | struct omap_hwmod_irq_info omap2_timer9_mpu_irqs[] = { |
Tony Lindgren | 7d7e1eb | 2012-08-27 17:43:01 -0700 | [diff] [blame] | 184 | { .irq = 45 + OMAP_INTC_START, }, |
| 185 | { .irq = -1 }, |
Paul Walmsley | 0d619a8 | 2011-07-09 19:14:07 -0600 | [diff] [blame] | 186 | }; |
| 187 | |
| 188 | struct omap_hwmod_irq_info omap2_timer10_mpu_irqs[] = { |
Tony Lindgren | 7d7e1eb | 2012-08-27 17:43:01 -0700 | [diff] [blame] | 189 | { .irq = 46 + OMAP_INTC_START, }, |
| 190 | { .irq = -1 }, |
Paul Walmsley | 0d619a8 | 2011-07-09 19:14:07 -0600 | [diff] [blame] | 191 | }; |
| 192 | |
| 193 | struct omap_hwmod_irq_info omap2_timer11_mpu_irqs[] = { |
Tony Lindgren | 7d7e1eb | 2012-08-27 17:43:01 -0700 | [diff] [blame] | 194 | { .irq = 47 + OMAP_INTC_START, }, |
| 195 | { .irq = -1 }, |
Paul Walmsley | 0d619a8 | 2011-07-09 19:14:07 -0600 | [diff] [blame] | 196 | }; |
| 197 | |
| 198 | struct omap_hwmod_irq_info omap2_uart1_mpu_irqs[] = { |
Tony Lindgren | 7d7e1eb | 2012-08-27 17:43:01 -0700 | [diff] [blame] | 199 | { .irq = 72 + OMAP_INTC_START, }, |
| 200 | { .irq = -1 }, |
Paul Walmsley | 0d619a8 | 2011-07-09 19:14:07 -0600 | [diff] [blame] | 201 | }; |
| 202 | |
| 203 | struct omap_hwmod_irq_info omap2_uart2_mpu_irqs[] = { |
Tony Lindgren | 7d7e1eb | 2012-08-27 17:43:01 -0700 | [diff] [blame] | 204 | { .irq = 73 + OMAP_INTC_START, }, |
| 205 | { .irq = -1 }, |
Paul Walmsley | 0d619a8 | 2011-07-09 19:14:07 -0600 | [diff] [blame] | 206 | }; |
| 207 | |
| 208 | struct omap_hwmod_irq_info omap2_uart3_mpu_irqs[] = { |
Tony Lindgren | 7d7e1eb | 2012-08-27 17:43:01 -0700 | [diff] [blame] | 209 | { .irq = 74 + OMAP_INTC_START, }, |
| 210 | { .irq = -1 }, |
Paul Walmsley | 0d619a8 | 2011-07-09 19:14:07 -0600 | [diff] [blame] | 211 | }; |
| 212 | |
| 213 | struct omap_hwmod_irq_info omap2_dispc_irqs[] = { |
Tony Lindgren | 7d7e1eb | 2012-08-27 17:43:01 -0700 | [diff] [blame] | 214 | { .irq = 25 + OMAP_INTC_START, }, |
| 215 | { .irq = -1 }, |
Paul Walmsley | 0d619a8 | 2011-07-09 19:14:07 -0600 | [diff] [blame] | 216 | }; |
| 217 | |
| 218 | struct omap_hwmod_irq_info omap2_i2c1_mpu_irqs[] = { |
Tony Lindgren | 7d7e1eb | 2012-08-27 17:43:01 -0700 | [diff] [blame] | 219 | { .irq = 56 + OMAP_INTC_START, }, |
| 220 | { .irq = -1 }, |
Paul Walmsley | 0d619a8 | 2011-07-09 19:14:07 -0600 | [diff] [blame] | 221 | }; |
| 222 | |
| 223 | struct omap_hwmod_irq_info omap2_i2c2_mpu_irqs[] = { |
Tony Lindgren | 7d7e1eb | 2012-08-27 17:43:01 -0700 | [diff] [blame] | 224 | { .irq = 57 + OMAP_INTC_START, }, |
| 225 | { .irq = -1 }, |
Paul Walmsley | 0d619a8 | 2011-07-09 19:14:07 -0600 | [diff] [blame] | 226 | }; |
| 227 | |
| 228 | struct omap_hwmod_irq_info omap2_gpio1_irqs[] = { |
Tony Lindgren | 7d7e1eb | 2012-08-27 17:43:01 -0700 | [diff] [blame] | 229 | { .irq = 29 + OMAP_INTC_START, }, /* INT_24XX_GPIO_BANK1 */ |
| 230 | { .irq = -1 }, |
Paul Walmsley | 0d619a8 | 2011-07-09 19:14:07 -0600 | [diff] [blame] | 231 | }; |
| 232 | |
| 233 | struct omap_hwmod_irq_info omap2_gpio2_irqs[] = { |
Tony Lindgren | 7d7e1eb | 2012-08-27 17:43:01 -0700 | [diff] [blame] | 234 | { .irq = 30 + OMAP_INTC_START, }, /* INT_24XX_GPIO_BANK2 */ |
| 235 | { .irq = -1 }, |
Paul Walmsley | 0d619a8 | 2011-07-09 19:14:07 -0600 | [diff] [blame] | 236 | }; |
| 237 | |
| 238 | struct omap_hwmod_irq_info omap2_gpio3_irqs[] = { |
Tony Lindgren | 7d7e1eb | 2012-08-27 17:43:01 -0700 | [diff] [blame] | 239 | { .irq = 31 + OMAP_INTC_START, }, /* INT_24XX_GPIO_BANK3 */ |
| 240 | { .irq = -1 }, |
Paul Walmsley | 0d619a8 | 2011-07-09 19:14:07 -0600 | [diff] [blame] | 241 | }; |
| 242 | |
| 243 | struct omap_hwmod_irq_info omap2_gpio4_irqs[] = { |
Tony Lindgren | 7d7e1eb | 2012-08-27 17:43:01 -0700 | [diff] [blame] | 244 | { .irq = 32 + OMAP_INTC_START, }, /* INT_24XX_GPIO_BANK4 */ |
| 245 | { .irq = -1 }, |
Paul Walmsley | 0d619a8 | 2011-07-09 19:14:07 -0600 | [diff] [blame] | 246 | }; |
| 247 | |
| 248 | struct omap_hwmod_irq_info omap2_dma_system_irqs[] = { |
Tony Lindgren | 7d7e1eb | 2012-08-27 17:43:01 -0700 | [diff] [blame] | 249 | { .name = "0", .irq = 12 + OMAP_INTC_START, }, /* INT_24XX_SDMA_IRQ0 */ |
| 250 | { .name = "1", .irq = 13 + OMAP_INTC_START, }, /* INT_24XX_SDMA_IRQ1 */ |
| 251 | { .name = "2", .irq = 14 + OMAP_INTC_START, }, /* INT_24XX_SDMA_IRQ2 */ |
| 252 | { .name = "3", .irq = 15 + OMAP_INTC_START, }, /* INT_24XX_SDMA_IRQ3 */ |
| 253 | { .irq = -1 }, |
Paul Walmsley | 0d619a8 | 2011-07-09 19:14:07 -0600 | [diff] [blame] | 254 | }; |
| 255 | |
| 256 | struct omap_hwmod_irq_info omap2_mcspi1_mpu_irqs[] = { |
Tony Lindgren | 7d7e1eb | 2012-08-27 17:43:01 -0700 | [diff] [blame] | 257 | { .irq = 65 + OMAP_INTC_START, }, |
| 258 | { .irq = -1 }, |
Paul Walmsley | 0d619a8 | 2011-07-09 19:14:07 -0600 | [diff] [blame] | 259 | }; |
| 260 | |
| 261 | struct omap_hwmod_irq_info omap2_mcspi2_mpu_irqs[] = { |
Tony Lindgren | 7d7e1eb | 2012-08-27 17:43:01 -0700 | [diff] [blame] | 262 | { .irq = 66 + OMAP_INTC_START, }, |
| 263 | { .irq = -1 }, |
Paul Walmsley | 0d619a8 | 2011-07-09 19:14:07 -0600 | [diff] [blame] | 264 | }; |
| 265 | |
Paul Walmsley | 03d830e | 2012-05-08 11:34:27 -0600 | [diff] [blame] | 266 | struct omap_hwmod_class_sysconfig omap2_hdq1w_sysc = { |
| 267 | .rev_offs = 0x0, |
| 268 | .sysc_offs = 0x14, |
| 269 | .syss_offs = 0x18, |
| 270 | .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | |
| 271 | SYSS_HAS_RESET_STATUS), |
| 272 | .sysc_fields = &omap_hwmod_sysc_type1, |
| 273 | }; |
| 274 | |
| 275 | struct omap_hwmod_class omap2_hdq1w_class = { |
| 276 | .name = "hdq1w", |
| 277 | .sysc = &omap2_hdq1w_sysc, |
| 278 | .reset = &omap_hdq1w_reset, |
| 279 | }; |
| 280 | |
| 281 | struct omap_hwmod_irq_info omap2_hdq1w_mpu_irqs[] = { |
Tony Lindgren | 7d7e1eb | 2012-08-27 17:43:01 -0700 | [diff] [blame] | 282 | { .irq = 58 + OMAP_INTC_START, }, |
| 283 | { .irq = -1 }, |
Paul Walmsley | 03d830e | 2012-05-08 11:34:27 -0600 | [diff] [blame] | 284 | }; |
| 285 | |