blob: 01aa6228f88b044d4e02a578e18508c86bdfb3dd [file] [log] [blame]
Andre Przywara83215812014-06-07 00:53:08 +02001/*
2 * Copyright (C) 2012-2014 ARM Ltd.
3 * Author: Marc Zyngier <marc.zyngier@arm.com>
4 *
5 * Derived from virt/kvm/arm/vgic.c
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20#ifndef __KVM_VGIC_H__
21#define __KVM_VGIC_H__
22
23#define VGIC_ADDR_UNDEF (-1)
24#define IS_VGIC_ADDR_UNDEF(_x) ((_x) == VGIC_ADDR_UNDEF)
25
26#define PRODUCT_ID_KVM 0x4b /* ASCII code K */
27#define IMPLEMENTER_ARM 0x43b
28
29#define ACCESS_READ_VALUE (1 << 0)
30#define ACCESS_READ_RAZ (0 << 0)
31#define ACCESS_READ_MASK(x) ((x) & (1 << 0))
32#define ACCESS_WRITE_IGNORED (0 << 1)
33#define ACCESS_WRITE_SETBIT (1 << 1)
34#define ACCESS_WRITE_CLEARBIT (2 << 1)
35#define ACCESS_WRITE_VALUE (3 << 1)
36#define ACCESS_WRITE_MASK(x) ((x) & (3 << 1))
37
Andre Przywaraa0675c22014-06-07 00:54:51 +020038#define VCPU_NOT_ALLOCATED ((u8)-1)
39
Andre Przywara83215812014-06-07 00:53:08 +020040unsigned long *vgic_bitmap_get_shared_map(struct vgic_bitmap *x);
41
42void vgic_update_state(struct kvm *kvm);
43int vgic_init_common_maps(struct kvm *kvm);
44
45u32 *vgic_bitmap_get_reg(struct vgic_bitmap *x, int cpuid, u32 offset);
46u32 *vgic_bytemap_get_reg(struct vgic_bytemap *x, int cpuid, u32 offset);
47
48void vgic_dist_irq_set_pending(struct kvm_vcpu *vcpu, int irq);
49void vgic_dist_irq_clear_pending(struct kvm_vcpu *vcpu, int irq);
50void vgic_cpu_irq_clear(struct kvm_vcpu *vcpu, int irq);
51void vgic_bitmap_set_irq_val(struct vgic_bitmap *x, int cpuid,
52 int irq, int val);
53
54void vgic_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
55void vgic_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
56
57bool vgic_queue_irq(struct kvm_vcpu *vcpu, u8 sgi_source_id, int irq);
58void vgic_unqueue_irqs(struct kvm_vcpu *vcpu);
59
60void vgic_reg_access(struct kvm_exit_mmio *mmio, u32 *reg,
61 phys_addr_t offset, int mode);
62bool handle_mmio_raz_wi(struct kvm_vcpu *vcpu, struct kvm_exit_mmio *mmio,
63 phys_addr_t offset);
64
65static inline
66u32 mmio_data_read(struct kvm_exit_mmio *mmio, u32 mask)
67{
68 return le32_to_cpu(*((u32 *)mmio->data)) & mask;
69}
70
71static inline
72void mmio_data_write(struct kvm_exit_mmio *mmio, u32 mask, u32 value)
73{
74 *((u32 *)mmio->data) = cpu_to_le32(value) & mask;
75}
76
Andre Przywaracf50a1e2015-03-26 14:39:32 +000077struct vgic_io_range {
Andre Przywara83215812014-06-07 00:53:08 +020078 phys_addr_t base;
79 unsigned long len;
80 int bits_per_irq;
81 bool (*handle_mmio)(struct kvm_vcpu *vcpu, struct kvm_exit_mmio *mmio,
82 phys_addr_t offset);
83};
84
85static inline bool is_in_range(phys_addr_t addr, unsigned long len,
86 phys_addr_t baseaddr, unsigned long size)
87{
88 return (addr >= baseaddr) && (addr + len <= baseaddr + size);
89}
90
91const
Andre Przywaracf50a1e2015-03-26 14:39:32 +000092struct vgic_io_range *vgic_find_range(const struct vgic_io_range *ranges,
Andre Przywara9f199d02015-03-26 14:39:33 +000093 int len, gpa_t offset);
Andre Przywara83215812014-06-07 00:53:08 +020094
95bool vgic_handle_mmio_range(struct kvm_vcpu *vcpu, struct kvm_run *run,
96 struct kvm_exit_mmio *mmio,
Andre Przywaracf50a1e2015-03-26 14:39:32 +000097 const struct vgic_io_range *ranges,
Andre Przywara83215812014-06-07 00:53:08 +020098 unsigned long mmio_base);
99
100bool vgic_handle_enable_reg(struct kvm *kvm, struct kvm_exit_mmio *mmio,
101 phys_addr_t offset, int vcpu_id, int access);
102
103bool vgic_handle_set_pending_reg(struct kvm *kvm, struct kvm_exit_mmio *mmio,
104 phys_addr_t offset, int vcpu_id);
105
106bool vgic_handle_clear_pending_reg(struct kvm *kvm, struct kvm_exit_mmio *mmio,
107 phys_addr_t offset, int vcpu_id);
108
Christoffer Dall47a98b12015-03-13 17:02:54 +0000109bool vgic_handle_set_active_reg(struct kvm *kvm,
110 struct kvm_exit_mmio *mmio,
111 phys_addr_t offset, int vcpu_id);
112
113bool vgic_handle_clear_active_reg(struct kvm *kvm,
114 struct kvm_exit_mmio *mmio,
115 phys_addr_t offset, int vcpu_id);
116
Andre Przywara83215812014-06-07 00:53:08 +0200117bool vgic_handle_cfg_reg(u32 *reg, struct kvm_exit_mmio *mmio,
118 phys_addr_t offset);
119
120void vgic_kick_vcpus(struct kvm *kvm);
121
Andre Przywaracf50a1e2015-03-26 14:39:32 +0000122int vgic_has_attr_regs(const struct vgic_io_range *ranges, phys_addr_t offset);
Andre Przywara83215812014-06-07 00:53:08 +0200123int vgic_set_common_attr(struct kvm_device *dev, struct kvm_device_attr *attr);
124int vgic_get_common_attr(struct kvm_device *dev, struct kvm_device_attr *attr);
125
126int vgic_init(struct kvm *kvm);
127void vgic_v2_init_emulation(struct kvm *kvm);
Andre Przywaraa0675c22014-06-07 00:54:51 +0200128void vgic_v3_init_emulation(struct kvm *kvm);
Andre Przywara83215812014-06-07 00:53:08 +0200129
130#endif