Stepan Moskovchenko | d9c8279 | 2010-08-24 19:51:15 -0700 | [diff] [blame] | 1 | /* Copyright (c) 2010, Code Aurora Forum. All rights reserved. |
| 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | * |
| 12 | * You should have received a copy of the GNU General Public License |
| 13 | * along with this program; if not, write to the Free Software |
| 14 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA |
| 15 | * 02110-1301, USA. |
| 16 | */ |
| 17 | |
| 18 | #include <linux/kernel.h> |
| 19 | #include <linux/platform_device.h> |
| 20 | #include <linux/bootmem.h> |
| 21 | |
| 22 | #include <mach/msm_iomap-8x60.h> |
| 23 | #include <mach/irqs-8x60.h> |
| 24 | #include <mach/iommu.h> |
| 25 | |
| 26 | static struct resource msm_iommu_jpegd_resources[] = { |
| 27 | { |
| 28 | .start = MSM_IOMMU_JPEGD_PHYS, |
| 29 | .end = MSM_IOMMU_JPEGD_PHYS + MSM_IOMMU_JPEGD_SIZE - 1, |
| 30 | .name = "physbase", |
| 31 | .flags = IORESOURCE_MEM, |
| 32 | }, |
| 33 | { |
| 34 | .name = "nonsecure_irq", |
| 35 | .start = SMMU_JPEGD_CB_SC_NON_SECURE_IRQ, |
| 36 | .end = SMMU_JPEGD_CB_SC_NON_SECURE_IRQ, |
| 37 | .flags = IORESOURCE_IRQ, |
| 38 | }, |
| 39 | { |
| 40 | .name = "secure_irq", |
| 41 | .start = SMMU_JPEGD_CB_SC_SECURE_IRQ, |
| 42 | .end = SMMU_JPEGD_CB_SC_SECURE_IRQ, |
| 43 | .flags = IORESOURCE_IRQ, |
| 44 | }, |
| 45 | }; |
| 46 | |
| 47 | static struct resource msm_iommu_vpe_resources[] = { |
| 48 | { |
| 49 | .start = MSM_IOMMU_VPE_PHYS, |
| 50 | .end = MSM_IOMMU_VPE_PHYS + MSM_IOMMU_VPE_SIZE - 1, |
| 51 | .name = "physbase", |
| 52 | .flags = IORESOURCE_MEM, |
| 53 | }, |
| 54 | { |
| 55 | .name = "nonsecure_irq", |
| 56 | .start = SMMU_VPE_CB_SC_NON_SECURE_IRQ, |
| 57 | .end = SMMU_VPE_CB_SC_NON_SECURE_IRQ, |
| 58 | .flags = IORESOURCE_IRQ, |
| 59 | }, |
| 60 | { |
| 61 | .name = "secure_irq", |
| 62 | .start = SMMU_VPE_CB_SC_SECURE_IRQ, |
| 63 | .end = SMMU_VPE_CB_SC_SECURE_IRQ, |
| 64 | .flags = IORESOURCE_IRQ, |
| 65 | }, |
| 66 | }; |
| 67 | |
| 68 | static struct resource msm_iommu_mdp0_resources[] = { |
| 69 | { |
| 70 | .start = MSM_IOMMU_MDP0_PHYS, |
| 71 | .end = MSM_IOMMU_MDP0_PHYS + MSM_IOMMU_MDP0_SIZE - 1, |
| 72 | .name = "physbase", |
| 73 | .flags = IORESOURCE_MEM, |
| 74 | }, |
| 75 | { |
| 76 | .name = "nonsecure_irq", |
| 77 | .start = SMMU_MDP0_CB_SC_NON_SECURE_IRQ, |
| 78 | .end = SMMU_MDP0_CB_SC_NON_SECURE_IRQ, |
| 79 | .flags = IORESOURCE_IRQ, |
| 80 | }, |
| 81 | { |
| 82 | .name = "secure_irq", |
| 83 | .start = SMMU_MDP0_CB_SC_SECURE_IRQ, |
| 84 | .end = SMMU_MDP0_CB_SC_SECURE_IRQ, |
| 85 | .flags = IORESOURCE_IRQ, |
| 86 | }, |
| 87 | }; |
| 88 | |
| 89 | static struct resource msm_iommu_mdp1_resources[] = { |
| 90 | { |
| 91 | .start = MSM_IOMMU_MDP1_PHYS, |
| 92 | .end = MSM_IOMMU_MDP1_PHYS + MSM_IOMMU_MDP1_SIZE - 1, |
| 93 | .name = "physbase", |
| 94 | .flags = IORESOURCE_MEM, |
| 95 | }, |
| 96 | { |
| 97 | .name = "nonsecure_irq", |
| 98 | .start = SMMU_MDP1_CB_SC_NON_SECURE_IRQ, |
| 99 | .end = SMMU_MDP1_CB_SC_NON_SECURE_IRQ, |
| 100 | .flags = IORESOURCE_IRQ, |
| 101 | }, |
| 102 | { |
| 103 | .name = "secure_irq", |
| 104 | .start = SMMU_MDP1_CB_SC_SECURE_IRQ, |
| 105 | .end = SMMU_MDP1_CB_SC_SECURE_IRQ, |
| 106 | .flags = IORESOURCE_IRQ, |
| 107 | }, |
| 108 | }; |
| 109 | |
| 110 | static struct resource msm_iommu_rot_resources[] = { |
| 111 | { |
| 112 | .start = MSM_IOMMU_ROT_PHYS, |
| 113 | .end = MSM_IOMMU_ROT_PHYS + MSM_IOMMU_ROT_SIZE - 1, |
| 114 | .name = "physbase", |
| 115 | .flags = IORESOURCE_MEM, |
| 116 | }, |
| 117 | { |
| 118 | .name = "nonsecure_irq", |
| 119 | .start = SMMU_ROT_CB_SC_NON_SECURE_IRQ, |
| 120 | .end = SMMU_ROT_CB_SC_NON_SECURE_IRQ, |
| 121 | .flags = IORESOURCE_IRQ, |
| 122 | }, |
| 123 | { |
| 124 | .name = "secure_irq", |
| 125 | .start = SMMU_ROT_CB_SC_SECURE_IRQ, |
| 126 | .end = SMMU_ROT_CB_SC_SECURE_IRQ, |
| 127 | .flags = IORESOURCE_IRQ, |
| 128 | }, |
| 129 | }; |
| 130 | |
| 131 | static struct resource msm_iommu_ijpeg_resources[] = { |
| 132 | { |
| 133 | .start = MSM_IOMMU_IJPEG_PHYS, |
| 134 | .end = MSM_IOMMU_IJPEG_PHYS + MSM_IOMMU_IJPEG_SIZE - 1, |
| 135 | .name = "physbase", |
| 136 | .flags = IORESOURCE_MEM, |
| 137 | }, |
| 138 | { |
| 139 | .name = "nonsecure_irq", |
| 140 | .start = SMMU_IJPEG_CB_SC_NON_SECURE_IRQ, |
| 141 | .end = SMMU_IJPEG_CB_SC_NON_SECURE_IRQ, |
| 142 | .flags = IORESOURCE_IRQ, |
| 143 | }, |
| 144 | { |
| 145 | .name = "secure_irq", |
| 146 | .start = SMMU_IJPEG_CB_SC_SECURE_IRQ, |
| 147 | .end = SMMU_IJPEG_CB_SC_SECURE_IRQ, |
| 148 | .flags = IORESOURCE_IRQ, |
| 149 | }, |
| 150 | }; |
| 151 | |
| 152 | static struct resource msm_iommu_vfe_resources[] = { |
| 153 | { |
| 154 | .start = MSM_IOMMU_VFE_PHYS, |
| 155 | .end = MSM_IOMMU_VFE_PHYS + MSM_IOMMU_VFE_SIZE - 1, |
| 156 | .name = "physbase", |
| 157 | .flags = IORESOURCE_MEM, |
| 158 | }, |
| 159 | { |
| 160 | .name = "nonsecure_irq", |
| 161 | .start = SMMU_VFE_CB_SC_NON_SECURE_IRQ, |
| 162 | .end = SMMU_VFE_CB_SC_NON_SECURE_IRQ, |
| 163 | .flags = IORESOURCE_IRQ, |
| 164 | }, |
| 165 | { |
| 166 | .name = "secure_irq", |
| 167 | .start = SMMU_VFE_CB_SC_SECURE_IRQ, |
| 168 | .end = SMMU_VFE_CB_SC_SECURE_IRQ, |
| 169 | .flags = IORESOURCE_IRQ, |
| 170 | }, |
| 171 | }; |
| 172 | |
| 173 | static struct resource msm_iommu_vcodec_a_resources[] = { |
| 174 | { |
| 175 | .start = MSM_IOMMU_VCODEC_A_PHYS, |
| 176 | .end = MSM_IOMMU_VCODEC_A_PHYS + MSM_IOMMU_VCODEC_A_SIZE - 1, |
| 177 | .name = "physbase", |
| 178 | .flags = IORESOURCE_MEM, |
| 179 | }, |
| 180 | { |
| 181 | .name = "nonsecure_irq", |
| 182 | .start = SMMU_VCODEC_A_CB_SC_NON_SECURE_IRQ, |
| 183 | .end = SMMU_VCODEC_A_CB_SC_NON_SECURE_IRQ, |
| 184 | .flags = IORESOURCE_IRQ, |
| 185 | }, |
| 186 | { |
| 187 | .name = "secure_irq", |
| 188 | .start = SMMU_VCODEC_A_CB_SC_SECURE_IRQ, |
| 189 | .end = SMMU_VCODEC_A_CB_SC_SECURE_IRQ, |
| 190 | .flags = IORESOURCE_IRQ, |
| 191 | }, |
| 192 | }; |
| 193 | |
| 194 | static struct resource msm_iommu_vcodec_b_resources[] = { |
| 195 | { |
| 196 | .start = MSM_IOMMU_VCODEC_B_PHYS, |
| 197 | .end = MSM_IOMMU_VCODEC_B_PHYS + MSM_IOMMU_VCODEC_B_SIZE - 1, |
| 198 | .name = "physbase", |
| 199 | .flags = IORESOURCE_MEM, |
| 200 | }, |
| 201 | { |
| 202 | .name = "nonsecure_irq", |
| 203 | .start = SMMU_VCODEC_B_CB_SC_NON_SECURE_IRQ, |
| 204 | .end = SMMU_VCODEC_B_CB_SC_NON_SECURE_IRQ, |
| 205 | .flags = IORESOURCE_IRQ, |
| 206 | }, |
| 207 | { |
| 208 | .name = "secure_irq", |
| 209 | .start = SMMU_VCODEC_B_CB_SC_SECURE_IRQ, |
| 210 | .end = SMMU_VCODEC_B_CB_SC_SECURE_IRQ, |
| 211 | .flags = IORESOURCE_IRQ, |
| 212 | }, |
| 213 | }; |
| 214 | |
| 215 | static struct resource msm_iommu_gfx3d_resources[] = { |
| 216 | { |
| 217 | .start = MSM_IOMMU_GFX3D_PHYS, |
| 218 | .end = MSM_IOMMU_GFX3D_PHYS + MSM_IOMMU_GFX3D_SIZE - 1, |
| 219 | .name = "physbase", |
| 220 | .flags = IORESOURCE_MEM, |
| 221 | }, |
| 222 | { |
| 223 | .name = "nonsecure_irq", |
| 224 | .start = SMMU_GFX3D_CB_SC_NON_SECURE_IRQ, |
| 225 | .end = SMMU_GFX3D_CB_SC_NON_SECURE_IRQ, |
| 226 | .flags = IORESOURCE_IRQ, |
| 227 | }, |
| 228 | { |
| 229 | .name = "secure_irq", |
| 230 | .start = SMMU_GFX3D_CB_SC_SECURE_IRQ, |
| 231 | .end = SMMU_GFX3D_CB_SC_SECURE_IRQ, |
| 232 | .flags = IORESOURCE_IRQ, |
| 233 | }, |
| 234 | }; |
| 235 | |
| 236 | static struct resource msm_iommu_gfx2d0_resources[] = { |
| 237 | { |
| 238 | .start = MSM_IOMMU_GFX2D0_PHYS, |
| 239 | .end = MSM_IOMMU_GFX2D0_PHYS + MSM_IOMMU_GFX2D0_SIZE - 1, |
| 240 | .name = "physbase", |
| 241 | .flags = IORESOURCE_MEM, |
| 242 | }, |
| 243 | { |
| 244 | .name = "nonsecure_irq", |
| 245 | .start = SMMU_GFX2D0_CB_SC_NON_SECURE_IRQ, |
| 246 | .end = SMMU_GFX2D0_CB_SC_NON_SECURE_IRQ, |
| 247 | .flags = IORESOURCE_IRQ, |
| 248 | }, |
| 249 | { |
| 250 | .name = "secure_irq", |
| 251 | .start = SMMU_GFX2D0_CB_SC_SECURE_IRQ, |
| 252 | .end = SMMU_GFX2D0_CB_SC_SECURE_IRQ, |
| 253 | .flags = IORESOURCE_IRQ, |
| 254 | }, |
| 255 | }; |
| 256 | |
| 257 | static struct platform_device msm_root_iommu_dev = { |
| 258 | .name = "msm_iommu", |
| 259 | .id = -1, |
| 260 | }; |
| 261 | |
| 262 | static struct msm_iommu_dev jpegd_smmu = { |
| 263 | .name = "jpegd", |
| 264 | .clk_rate = -1 |
| 265 | }; |
| 266 | |
| 267 | static struct msm_iommu_dev vpe_smmu = { |
| 268 | .name = "vpe" |
| 269 | }; |
| 270 | |
| 271 | static struct msm_iommu_dev mdp0_smmu = { |
| 272 | .name = "mdp0" |
| 273 | }; |
| 274 | |
| 275 | static struct msm_iommu_dev mdp1_smmu = { |
| 276 | .name = "mdp1" |
| 277 | }; |
| 278 | |
| 279 | static struct msm_iommu_dev rot_smmu = { |
| 280 | .name = "rot" |
| 281 | }; |
| 282 | |
| 283 | static struct msm_iommu_dev ijpeg_smmu = { |
| 284 | .name = "ijpeg" |
| 285 | }; |
| 286 | |
| 287 | static struct msm_iommu_dev vfe_smmu = { |
| 288 | .name = "vfe", |
| 289 | .clk_rate = -1 |
| 290 | }; |
| 291 | |
| 292 | static struct msm_iommu_dev vcodec_a_smmu = { |
| 293 | .name = "vcodec_a" |
| 294 | }; |
| 295 | |
| 296 | static struct msm_iommu_dev vcodec_b_smmu = { |
| 297 | .name = "vcodec_b" |
| 298 | }; |
| 299 | |
| 300 | static struct msm_iommu_dev gfx3d_smmu = { |
| 301 | .name = "gfx3d", |
| 302 | .clk_rate = 27000000 |
| 303 | }; |
| 304 | |
| 305 | static struct msm_iommu_dev gfx2d0_smmu = { |
| 306 | .name = "gfx2d0", |
| 307 | .clk_rate = 27000000 |
| 308 | }; |
| 309 | |
| 310 | static struct platform_device msm_device_smmu_jpegd = { |
| 311 | .name = "msm_iommu", |
| 312 | .id = 0, |
| 313 | .dev = { |
| 314 | .parent = &msm_root_iommu_dev.dev, |
| 315 | }, |
| 316 | .num_resources = ARRAY_SIZE(msm_iommu_jpegd_resources), |
| 317 | .resource = msm_iommu_jpegd_resources, |
| 318 | }; |
| 319 | |
| 320 | static struct platform_device msm_device_smmu_vpe = { |
| 321 | .name = "msm_iommu", |
| 322 | .id = 1, |
| 323 | .dev = { |
| 324 | .parent = &msm_root_iommu_dev.dev, |
| 325 | }, |
| 326 | .num_resources = ARRAY_SIZE(msm_iommu_vpe_resources), |
| 327 | .resource = msm_iommu_vpe_resources, |
| 328 | }; |
| 329 | |
| 330 | static struct platform_device msm_device_smmu_mdp0 = { |
| 331 | .name = "msm_iommu", |
| 332 | .id = 2, |
| 333 | .dev = { |
| 334 | .parent = &msm_root_iommu_dev.dev, |
| 335 | }, |
| 336 | .num_resources = ARRAY_SIZE(msm_iommu_mdp0_resources), |
| 337 | .resource = msm_iommu_mdp0_resources, |
| 338 | }; |
| 339 | |
| 340 | static struct platform_device msm_device_smmu_mdp1 = { |
| 341 | .name = "msm_iommu", |
| 342 | .id = 3, |
| 343 | .dev = { |
| 344 | .parent = &msm_root_iommu_dev.dev, |
| 345 | }, |
| 346 | .num_resources = ARRAY_SIZE(msm_iommu_mdp1_resources), |
| 347 | .resource = msm_iommu_mdp1_resources, |
| 348 | }; |
| 349 | |
| 350 | static struct platform_device msm_device_smmu_rot = { |
| 351 | .name = "msm_iommu", |
| 352 | .id = 4, |
| 353 | .dev = { |
| 354 | .parent = &msm_root_iommu_dev.dev, |
| 355 | }, |
| 356 | .num_resources = ARRAY_SIZE(msm_iommu_rot_resources), |
| 357 | .resource = msm_iommu_rot_resources, |
| 358 | }; |
| 359 | |
| 360 | static struct platform_device msm_device_smmu_ijpeg = { |
| 361 | .name = "msm_iommu", |
| 362 | .id = 5, |
| 363 | .dev = { |
| 364 | .parent = &msm_root_iommu_dev.dev, |
| 365 | }, |
| 366 | .num_resources = ARRAY_SIZE(msm_iommu_ijpeg_resources), |
| 367 | .resource = msm_iommu_ijpeg_resources, |
| 368 | }; |
| 369 | |
| 370 | static struct platform_device msm_device_smmu_vfe = { |
| 371 | .name = "msm_iommu", |
| 372 | .id = 6, |
| 373 | .dev = { |
| 374 | .parent = &msm_root_iommu_dev.dev, |
| 375 | }, |
| 376 | .num_resources = ARRAY_SIZE(msm_iommu_vfe_resources), |
| 377 | .resource = msm_iommu_vfe_resources, |
| 378 | }; |
| 379 | |
| 380 | static struct platform_device msm_device_smmu_vcodec_a = { |
| 381 | .name = "msm_iommu", |
| 382 | .id = 7, |
| 383 | .dev = { |
| 384 | .parent = &msm_root_iommu_dev.dev, |
| 385 | }, |
| 386 | .num_resources = ARRAY_SIZE(msm_iommu_vcodec_a_resources), |
| 387 | .resource = msm_iommu_vcodec_a_resources, |
| 388 | }; |
| 389 | |
| 390 | static struct platform_device msm_device_smmu_vcodec_b = { |
| 391 | .name = "msm_iommu", |
| 392 | .id = 8, |
| 393 | .dev = { |
| 394 | .parent = &msm_root_iommu_dev.dev, |
| 395 | }, |
| 396 | .num_resources = ARRAY_SIZE(msm_iommu_vcodec_b_resources), |
| 397 | .resource = msm_iommu_vcodec_b_resources, |
| 398 | }; |
| 399 | |
| 400 | static struct platform_device msm_device_smmu_gfx3d = { |
| 401 | .name = "msm_iommu", |
| 402 | .id = 9, |
| 403 | .dev = { |
| 404 | .parent = &msm_root_iommu_dev.dev, |
| 405 | }, |
| 406 | .num_resources = ARRAY_SIZE(msm_iommu_gfx3d_resources), |
| 407 | .resource = msm_iommu_gfx3d_resources, |
| 408 | }; |
| 409 | |
| 410 | static struct platform_device msm_device_smmu_gfx2d0 = { |
| 411 | .name = "msm_iommu", |
| 412 | .id = 10, |
| 413 | .dev = { |
| 414 | .parent = &msm_root_iommu_dev.dev, |
| 415 | }, |
| 416 | .num_resources = ARRAY_SIZE(msm_iommu_gfx2d0_resources), |
| 417 | .resource = msm_iommu_gfx2d0_resources, |
| 418 | }; |
| 419 | |
| 420 | static struct msm_iommu_ctx_dev jpegd_src_ctx = { |
| 421 | .name = "jpegd_src", |
| 422 | .num = 0, |
| 423 | .mids = {0, -1} |
| 424 | }; |
| 425 | |
| 426 | static struct msm_iommu_ctx_dev jpegd_dst_ctx = { |
| 427 | .name = "jpegd_dst", |
| 428 | .num = 1, |
| 429 | .mids = {1, -1} |
| 430 | }; |
| 431 | |
| 432 | static struct msm_iommu_ctx_dev vpe_src_ctx = { |
| 433 | .name = "vpe_src", |
| 434 | .num = 0, |
| 435 | .mids = {0, -1} |
| 436 | }; |
| 437 | |
| 438 | static struct msm_iommu_ctx_dev vpe_dst_ctx = { |
| 439 | .name = "vpe_dst", |
| 440 | .num = 1, |
| 441 | .mids = {1, -1} |
| 442 | }; |
| 443 | |
| 444 | static struct msm_iommu_ctx_dev mdp_vg1_ctx = { |
| 445 | .name = "mdp_vg1", |
| 446 | .num = 0, |
| 447 | .mids = {0, 2, -1} |
| 448 | }; |
| 449 | |
| 450 | static struct msm_iommu_ctx_dev mdp_rgb1_ctx = { |
| 451 | .name = "mdp_rgb1", |
| 452 | .num = 1, |
| 453 | .mids = {1, 3, 4, 5, 6, 7, 8, 9, 10, -1} |
| 454 | }; |
| 455 | |
| 456 | static struct msm_iommu_ctx_dev mdp_vg2_ctx = { |
| 457 | .name = "mdp_vg2", |
| 458 | .num = 0, |
| 459 | .mids = {0, 2, -1} |
| 460 | }; |
| 461 | |
| 462 | static struct msm_iommu_ctx_dev mdp_rgb2_ctx = { |
| 463 | .name = "mdp_rgb2", |
| 464 | .num = 1, |
| 465 | .mids = {1, 3, 4, 5, 6, 7, 8, 9, 10, -1} |
| 466 | }; |
| 467 | |
| 468 | static struct msm_iommu_ctx_dev rot_src_ctx = { |
| 469 | .name = "rot_src", |
| 470 | .num = 0, |
| 471 | .mids = {0, -1} |
| 472 | }; |
| 473 | |
| 474 | static struct msm_iommu_ctx_dev rot_dst_ctx = { |
| 475 | .name = "rot_dst", |
| 476 | .num = 1, |
| 477 | .mids = {1, -1} |
| 478 | }; |
| 479 | |
| 480 | static struct msm_iommu_ctx_dev ijpeg_src_ctx = { |
| 481 | .name = "ijpeg_src", |
| 482 | .num = 0, |
| 483 | .mids = {0, -1} |
| 484 | }; |
| 485 | |
| 486 | static struct msm_iommu_ctx_dev ijpeg_dst_ctx = { |
| 487 | .name = "ijpeg_dst", |
| 488 | .num = 1, |
| 489 | .mids = {1, -1} |
| 490 | }; |
| 491 | |
| 492 | static struct msm_iommu_ctx_dev vfe_imgwr_ctx = { |
| 493 | .name = "vfe_imgwr", |
| 494 | .num = 0, |
| 495 | .mids = {2, 3, 4, 5, 6, 7, 8, -1} |
| 496 | }; |
| 497 | |
| 498 | static struct msm_iommu_ctx_dev vfe_misc_ctx = { |
| 499 | .name = "vfe_misc", |
| 500 | .num = 1, |
| 501 | .mids = {0, 1, 9, -1} |
| 502 | }; |
| 503 | |
| 504 | static struct msm_iommu_ctx_dev vcodec_a_stream_ctx = { |
| 505 | .name = "vcodec_a_stream", |
| 506 | .num = 0, |
| 507 | .mids = {2, 5, -1} |
| 508 | }; |
| 509 | |
| 510 | static struct msm_iommu_ctx_dev vcodec_a_mm1_ctx = { |
| 511 | .name = "vcodec_a_mm1", |
| 512 | .num = 1, |
| 513 | .mids = {0, 1, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, -1} |
| 514 | }; |
| 515 | |
| 516 | static struct msm_iommu_ctx_dev vcodec_b_mm2_ctx = { |
| 517 | .name = "vcodec_b_mm2", |
| 518 | .num = 0, |
| 519 | .mids = {0, 1, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, -1} |
| 520 | }; |
| 521 | |
| 522 | static struct msm_iommu_ctx_dev gfx3d_rbpa_ctx = { |
| 523 | .name = "gfx3d_rbpa", |
| 524 | .num = 0, |
| 525 | .mids = {-1} |
| 526 | }; |
| 527 | |
| 528 | static struct msm_iommu_ctx_dev gfx3d_cpvgttc_ctx = { |
| 529 | .name = "gfx3d_cpvgttc", |
| 530 | .num = 1, |
| 531 | .mids = {0, 1, 2, 3, 4, 5, 6, 7, -1} |
| 532 | }; |
| 533 | |
| 534 | static struct msm_iommu_ctx_dev gfx3d_smmu_ctx = { |
| 535 | .name = "gfx3d_smmu", |
| 536 | .num = 2, |
| 537 | .mids = {8, 9, 10, 11, 12, -1} |
| 538 | }; |
| 539 | |
| 540 | static struct msm_iommu_ctx_dev gfx2d0_pixv1_ctx = { |
| 541 | .name = "gfx2d0_pixv1_smmu", |
| 542 | .num = 0, |
| 543 | .mids = {0, 3, 4, -1} |
| 544 | }; |
| 545 | |
| 546 | static struct msm_iommu_ctx_dev gfx2d0_texv3_ctx = { |
| 547 | .name = "gfx2d0_texv3_smmu", |
| 548 | .num = 1, |
| 549 | .mids = {1, 6, 7, -1} |
| 550 | }; |
| 551 | |
| 552 | static struct platform_device msm_device_jpegd_src_ctx = { |
| 553 | .name = "msm_iommu_ctx", |
| 554 | .id = 0, |
| 555 | .dev = { |
| 556 | .parent = &msm_device_smmu_jpegd.dev, |
| 557 | }, |
| 558 | }; |
| 559 | |
| 560 | static struct platform_device msm_device_jpegd_dst_ctx = { |
| 561 | .name = "msm_iommu_ctx", |
| 562 | .id = 1, |
| 563 | .dev = { |
| 564 | .parent = &msm_device_smmu_jpegd.dev, |
| 565 | }, |
| 566 | }; |
| 567 | |
| 568 | static struct platform_device msm_device_vpe_src_ctx = { |
| 569 | .name = "msm_iommu_ctx", |
| 570 | .id = 2, |
| 571 | .dev = { |
| 572 | .parent = &msm_device_smmu_vpe.dev, |
| 573 | }, |
| 574 | }; |
| 575 | |
| 576 | static struct platform_device msm_device_vpe_dst_ctx = { |
| 577 | .name = "msm_iommu_ctx", |
| 578 | .id = 3, |
| 579 | .dev = { |
| 580 | .parent = &msm_device_smmu_vpe.dev, |
| 581 | }, |
| 582 | }; |
| 583 | |
| 584 | static struct platform_device msm_device_mdp_vg1_ctx = { |
| 585 | .name = "msm_iommu_ctx", |
| 586 | .id = 4, |
| 587 | .dev = { |
| 588 | .parent = &msm_device_smmu_mdp0.dev, |
| 589 | }, |
| 590 | }; |
| 591 | |
| 592 | static struct platform_device msm_device_mdp_rgb1_ctx = { |
| 593 | .name = "msm_iommu_ctx", |
| 594 | .id = 5, |
| 595 | .dev = { |
| 596 | .parent = &msm_device_smmu_mdp0.dev, |
| 597 | }, |
| 598 | }; |
| 599 | |
| 600 | static struct platform_device msm_device_mdp_vg2_ctx = { |
| 601 | .name = "msm_iommu_ctx", |
| 602 | .id = 6, |
| 603 | .dev = { |
| 604 | .parent = &msm_device_smmu_mdp1.dev, |
| 605 | }, |
| 606 | }; |
| 607 | |
| 608 | static struct platform_device msm_device_mdp_rgb2_ctx = { |
| 609 | .name = "msm_iommu_ctx", |
| 610 | .id = 7, |
| 611 | .dev = { |
| 612 | .parent = &msm_device_smmu_mdp1.dev, |
| 613 | }, |
| 614 | }; |
| 615 | |
| 616 | static struct platform_device msm_device_rot_src_ctx = { |
| 617 | .name = "msm_iommu_ctx", |
| 618 | .id = 8, |
| 619 | .dev = { |
| 620 | .parent = &msm_device_smmu_rot.dev, |
| 621 | }, |
| 622 | }; |
| 623 | |
| 624 | static struct platform_device msm_device_rot_dst_ctx = { |
| 625 | .name = "msm_iommu_ctx", |
| 626 | .id = 9, |
| 627 | .dev = { |
| 628 | .parent = &msm_device_smmu_rot.dev, |
| 629 | }, |
| 630 | }; |
| 631 | |
| 632 | static struct platform_device msm_device_ijpeg_src_ctx = { |
| 633 | .name = "msm_iommu_ctx", |
| 634 | .id = 10, |
| 635 | .dev = { |
| 636 | .parent = &msm_device_smmu_ijpeg.dev, |
| 637 | }, |
| 638 | }; |
| 639 | |
| 640 | static struct platform_device msm_device_ijpeg_dst_ctx = { |
| 641 | .name = "msm_iommu_ctx", |
| 642 | .id = 11, |
| 643 | .dev = { |
| 644 | .parent = &msm_device_smmu_ijpeg.dev, |
| 645 | }, |
| 646 | }; |
| 647 | |
| 648 | static struct platform_device msm_device_vfe_imgwr_ctx = { |
| 649 | .name = "msm_iommu_ctx", |
| 650 | .id = 12, |
| 651 | .dev = { |
| 652 | .parent = &msm_device_smmu_vfe.dev, |
| 653 | }, |
| 654 | }; |
| 655 | |
| 656 | static struct platform_device msm_device_vfe_misc_ctx = { |
| 657 | .name = "msm_iommu_ctx", |
| 658 | .id = 13, |
| 659 | .dev = { |
| 660 | .parent = &msm_device_smmu_vfe.dev, |
| 661 | }, |
| 662 | }; |
| 663 | |
| 664 | static struct platform_device msm_device_vcodec_a_stream_ctx = { |
| 665 | .name = "msm_iommu_ctx", |
| 666 | .id = 14, |
| 667 | .dev = { |
| 668 | .parent = &msm_device_smmu_vcodec_a.dev, |
| 669 | }, |
| 670 | }; |
| 671 | |
| 672 | static struct platform_device msm_device_vcodec_a_mm1_ctx = { |
| 673 | .name = "msm_iommu_ctx", |
| 674 | .id = 15, |
| 675 | .dev = { |
| 676 | .parent = &msm_device_smmu_vcodec_a.dev, |
| 677 | }, |
| 678 | }; |
| 679 | |
| 680 | static struct platform_device msm_device_vcodec_b_mm2_ctx = { |
| 681 | .name = "msm_iommu_ctx", |
| 682 | .id = 16, |
| 683 | .dev = { |
| 684 | .parent = &msm_device_smmu_vcodec_b.dev, |
| 685 | }, |
| 686 | }; |
| 687 | |
| 688 | static struct platform_device msm_device_gfx3d_rbpa_ctx = { |
| 689 | .name = "msm_iommu_ctx", |
| 690 | .id = 17, |
| 691 | .dev = { |
| 692 | .parent = &msm_device_smmu_gfx3d.dev, |
| 693 | }, |
| 694 | }; |
| 695 | |
| 696 | static struct platform_device msm_device_gfx3d_cpvgttc_ctx = { |
| 697 | .name = "msm_iommu_ctx", |
| 698 | .id = 18, |
| 699 | .dev = { |
| 700 | .parent = &msm_device_smmu_gfx3d.dev, |
| 701 | }, |
| 702 | }; |
| 703 | |
| 704 | static struct platform_device msm_device_gfx3d_smmu_ctx = { |
| 705 | .name = "msm_iommu_ctx", |
| 706 | .id = 19, |
| 707 | .dev = { |
| 708 | .parent = &msm_device_smmu_gfx3d.dev, |
| 709 | }, |
| 710 | }; |
| 711 | |
| 712 | static struct platform_device msm_device_gfx2d0_pixv1_ctx = { |
| 713 | .name = "msm_iommu_ctx", |
| 714 | .id = 20, |
| 715 | .dev = { |
| 716 | .parent = &msm_device_smmu_gfx2d0.dev, |
| 717 | }, |
| 718 | }; |
| 719 | |
| 720 | static struct platform_device msm_device_gfx2d0_texv3_ctx = { |
| 721 | .name = "msm_iommu_ctx", |
| 722 | .id = 21, |
| 723 | .dev = { |
| 724 | .parent = &msm_device_smmu_gfx2d0.dev, |
| 725 | }, |
| 726 | }; |
| 727 | |
| 728 | static struct platform_device *msm_iommu_devs[] = { |
| 729 | &msm_device_smmu_jpegd, |
| 730 | &msm_device_smmu_vpe, |
| 731 | &msm_device_smmu_mdp0, |
| 732 | &msm_device_smmu_mdp1, |
| 733 | &msm_device_smmu_rot, |
| 734 | &msm_device_smmu_ijpeg, |
| 735 | &msm_device_smmu_vfe, |
| 736 | &msm_device_smmu_vcodec_a, |
| 737 | &msm_device_smmu_vcodec_b, |
| 738 | &msm_device_smmu_gfx3d, |
| 739 | &msm_device_smmu_gfx2d0, |
| 740 | }; |
| 741 | |
| 742 | static struct msm_iommu_dev *msm_iommu_data[] = { |
| 743 | &jpegd_smmu, |
| 744 | &vpe_smmu, |
| 745 | &mdp0_smmu, |
| 746 | &mdp1_smmu, |
| 747 | &rot_smmu, |
| 748 | &ijpeg_smmu, |
| 749 | &vfe_smmu, |
| 750 | &vcodec_a_smmu, |
| 751 | &vcodec_b_smmu, |
| 752 | &gfx3d_smmu, |
| 753 | &gfx2d0_smmu, |
| 754 | }; |
| 755 | |
| 756 | static struct platform_device *msm_iommu_ctx_devs[] = { |
| 757 | &msm_device_jpegd_src_ctx, |
| 758 | &msm_device_jpegd_dst_ctx, |
| 759 | &msm_device_vpe_src_ctx, |
| 760 | &msm_device_vpe_dst_ctx, |
| 761 | &msm_device_mdp_vg1_ctx, |
| 762 | &msm_device_mdp_rgb1_ctx, |
| 763 | &msm_device_mdp_vg2_ctx, |
| 764 | &msm_device_mdp_rgb2_ctx, |
| 765 | &msm_device_rot_src_ctx, |
| 766 | &msm_device_rot_dst_ctx, |
| 767 | &msm_device_ijpeg_src_ctx, |
| 768 | &msm_device_ijpeg_dst_ctx, |
| 769 | &msm_device_vfe_imgwr_ctx, |
| 770 | &msm_device_vfe_misc_ctx, |
| 771 | &msm_device_vcodec_a_stream_ctx, |
| 772 | &msm_device_vcodec_a_mm1_ctx, |
| 773 | &msm_device_vcodec_b_mm2_ctx, |
| 774 | &msm_device_gfx3d_rbpa_ctx, |
| 775 | &msm_device_gfx3d_cpvgttc_ctx, |
| 776 | &msm_device_gfx3d_smmu_ctx, |
| 777 | &msm_device_gfx2d0_pixv1_ctx, |
| 778 | &msm_device_gfx2d0_texv3_ctx, |
| 779 | }; |
| 780 | |
| 781 | static struct msm_iommu_ctx_dev *msm_iommu_ctx_data[] = { |
| 782 | &jpegd_src_ctx, |
| 783 | &jpegd_dst_ctx, |
| 784 | &vpe_src_ctx, |
| 785 | &vpe_dst_ctx, |
| 786 | &mdp_vg1_ctx, |
| 787 | &mdp_rgb1_ctx, |
| 788 | &mdp_vg2_ctx, |
| 789 | &mdp_rgb2_ctx, |
| 790 | &rot_src_ctx, |
| 791 | &rot_dst_ctx, |
| 792 | &ijpeg_src_ctx, |
| 793 | &ijpeg_dst_ctx, |
| 794 | &vfe_imgwr_ctx, |
| 795 | &vfe_misc_ctx, |
| 796 | &vcodec_a_stream_ctx, |
| 797 | &vcodec_a_mm1_ctx, |
| 798 | &vcodec_b_mm2_ctx, |
| 799 | &gfx3d_rbpa_ctx, |
| 800 | &gfx3d_cpvgttc_ctx, |
| 801 | &gfx3d_smmu_ctx, |
| 802 | &gfx2d0_pixv1_ctx, |
| 803 | &gfx2d0_texv3_ctx, |
| 804 | }; |
| 805 | |
| 806 | static int msm8x60_iommu_init(void) |
| 807 | { |
| 808 | int ret, i; |
| 809 | |
| 810 | ret = platform_device_register(&msm_root_iommu_dev); |
| 811 | if (ret != 0) { |
| 812 | pr_err("Failed to register root IOMMU device!\n"); |
| 813 | goto failure; |
| 814 | } |
| 815 | |
| 816 | for (i = 0; i < ARRAY_SIZE(msm_iommu_devs); i++) { |
| 817 | ret = platform_device_add_data(msm_iommu_devs[i], |
| 818 | msm_iommu_data[i], |
| 819 | sizeof(struct msm_iommu_dev)); |
| 820 | if (ret != 0) { |
| 821 | pr_err("platform_device_add_data failed, " |
| 822 | "i = %d\n", i); |
| 823 | goto failure_unwind; |
| 824 | } |
| 825 | |
| 826 | ret = platform_device_register(msm_iommu_devs[i]); |
| 827 | |
| 828 | if (ret != 0) { |
| 829 | pr_err("platform_device_register smmu failed, " |
| 830 | "i = %d\n", i); |
| 831 | goto failure_unwind; |
| 832 | } |
| 833 | } |
| 834 | |
| 835 | for (i = 0; i < ARRAY_SIZE(msm_iommu_ctx_devs); i++) { |
| 836 | ret = platform_device_add_data(msm_iommu_ctx_devs[i], |
| 837 | msm_iommu_ctx_data[i], |
| 838 | sizeof(*msm_iommu_ctx_devs[i])); |
| 839 | if (ret != 0) { |
| 840 | pr_err("platform_device_add_data smmu failed, " |
| 841 | "i = %d\n", i); |
| 842 | goto failure_unwind2; |
| 843 | } |
| 844 | |
| 845 | ret = platform_device_register(msm_iommu_ctx_devs[i]); |
| 846 | if (ret != 0) { |
| 847 | pr_err("platform_device_register ctx failed, " |
| 848 | "i = %d\n", i); |
| 849 | goto failure_unwind2; |
| 850 | } |
| 851 | } |
| 852 | return 0; |
| 853 | |
| 854 | failure_unwind2: |
| 855 | while (--i >= 0) |
| 856 | platform_device_unregister(msm_iommu_ctx_devs[i]); |
| 857 | failure_unwind: |
| 858 | while (--i >= 0) |
| 859 | platform_device_unregister(msm_iommu_devs[i]); |
| 860 | |
| 861 | platform_device_unregister(&msm_root_iommu_dev); |
| 862 | failure: |
| 863 | return ret; |
| 864 | } |
| 865 | |
| 866 | static void msm8x60_iommu_exit(void) |
| 867 | { |
| 868 | int i; |
| 869 | |
| 870 | for (i = 0; i < ARRAY_SIZE(msm_iommu_ctx_devs); i++) |
| 871 | platform_device_unregister(msm_iommu_ctx_devs[i]); |
| 872 | |
| 873 | for (i = 0; i < ARRAY_SIZE(msm_iommu_devs); ++i) |
| 874 | platform_device_unregister(msm_iommu_devs[i]); |
| 875 | |
| 876 | platform_device_unregister(&msm_root_iommu_dev); |
| 877 | } |
| 878 | |
| 879 | subsys_initcall(msm8x60_iommu_init); |
| 880 | module_exit(msm8x60_iommu_exit); |
| 881 | |
| 882 | MODULE_LICENSE("GPL v2"); |
| 883 | MODULE_AUTHOR("Stepan Moskovchenko <stepanm@codeaurora.org>"); |