Santosh Shilimkar | b2b9762 | 2010-06-16 22:19:48 +0530 | [diff] [blame] | 1 | /* |
| 2 | * OMAP MPUSS low power code |
| 3 | * |
| 4 | * Copyright (C) 2011 Texas Instruments, Inc. |
| 5 | * Santosh Shilimkar <santosh.shilimkar@ti.com> |
| 6 | * |
| 7 | * OMAP4430 MPUSS mainly consists of dual Cortex-A9 with per-CPU |
| 8 | * Local timer and Watchdog, GIC, SCU, PL310 L2 cache controller, |
| 9 | * CPU0 and CPU1 LPRM modules. |
| 10 | * CPU0, CPU1 and MPUSS each have there own power domain and |
| 11 | * hence multiple low power combinations of MPUSS are possible. |
| 12 | * |
| 13 | * The CPU0 and CPU1 can't support Closed switch Retention (CSWR) |
| 14 | * because the mode is not supported by hw constraints of dormant |
| 15 | * mode. While waking up from the dormant mode, a reset signal |
| 16 | * to the Cortex-A9 processor must be asserted by the external |
| 17 | * power controller. |
| 18 | * |
| 19 | * With architectural inputs and hardware recommendations, only |
| 20 | * below modes are supported from power gain vs latency point of view. |
| 21 | * |
| 22 | * CPU0 CPU1 MPUSS |
| 23 | * ---------------------------------------------- |
| 24 | * ON ON ON |
| 25 | * ON(Inactive) OFF ON(Inactive) |
| 26 | * OFF OFF CSWR |
Santosh Shilimkar | 3ba2a73 | 2011-06-06 14:33:29 +0530 | [diff] [blame] | 27 | * OFF OFF OSWR |
| 28 | * OFF OFF OFF(Device OFF *TBD) |
Santosh Shilimkar | b2b9762 | 2010-06-16 22:19:48 +0530 | [diff] [blame] | 29 | * ---------------------------------------------- |
| 30 | * |
| 31 | * Note: CPU0 is the master core and it is the last CPU to go down |
| 32 | * and first to wake-up when MPUSS low power states are excercised |
| 33 | * |
| 34 | * |
| 35 | * This program is free software; you can redistribute it and/or modify |
| 36 | * it under the terms of the GNU General Public License version 2 as |
| 37 | * published by the Free Software Foundation. |
| 38 | */ |
| 39 | |
| 40 | #include <linux/kernel.h> |
| 41 | #include <linux/io.h> |
| 42 | #include <linux/errno.h> |
| 43 | #include <linux/linkage.h> |
| 44 | #include <linux/smp.h> |
| 45 | |
| 46 | #include <asm/cacheflush.h> |
| 47 | #include <asm/tlbflush.h> |
| 48 | #include <asm/smp_scu.h> |
Santosh Shilimkar | b2b9762 | 2010-06-16 22:19:48 +0530 | [diff] [blame] | 49 | #include <asm/pgalloc.h> |
| 50 | #include <asm/suspend.h> |
Santosh Shilimkar | 5e94c6e3 | 2011-01-09 02:59:09 +0530 | [diff] [blame] | 51 | #include <asm/hardware/cache-l2x0.h> |
Santosh Shilimkar | b2b9762 | 2010-06-16 22:19:48 +0530 | [diff] [blame] | 52 | |
| 53 | #include <plat/omap44xx.h> |
| 54 | |
| 55 | #include "common.h" |
| 56 | #include "omap4-sar-layout.h" |
| 57 | #include "pm.h" |
Santosh Shilimkar | 3ba2a73 | 2011-06-06 14:33:29 +0530 | [diff] [blame] | 58 | #include "prcm_mpu44xx.h" |
| 59 | #include "prminst44xx.h" |
| 60 | #include "prcm44xx.h" |
| 61 | #include "prm44xx.h" |
| 62 | #include "prm-regbits-44xx.h" |
Santosh Shilimkar | b2b9762 | 2010-06-16 22:19:48 +0530 | [diff] [blame] | 63 | |
| 64 | #ifdef CONFIG_SMP |
| 65 | |
| 66 | struct omap4_cpu_pm_info { |
| 67 | struct powerdomain *pwrdm; |
| 68 | void __iomem *scu_sar_addr; |
| 69 | void __iomem *wkup_sar_addr; |
Santosh Shilimkar | 5e94c6e3 | 2011-01-09 02:59:09 +0530 | [diff] [blame] | 70 | void __iomem *l2x0_sar_addr; |
Santosh Shilimkar | b2b9762 | 2010-06-16 22:19:48 +0530 | [diff] [blame] | 71 | }; |
| 72 | |
| 73 | static DEFINE_PER_CPU(struct omap4_cpu_pm_info, omap4_pm_info); |
Santosh Shilimkar | e44f9a7 | 2010-06-16 22:19:49 +0530 | [diff] [blame] | 74 | static struct powerdomain *mpuss_pd; |
Santosh Shilimkar | 5e94c6e3 | 2011-01-09 02:59:09 +0530 | [diff] [blame] | 75 | static void __iomem *sar_base; |
Santosh Shilimkar | b2b9762 | 2010-06-16 22:19:48 +0530 | [diff] [blame] | 76 | |
| 77 | /* |
| 78 | * Program the wakeup routine address for the CPU0 and CPU1 |
| 79 | * used for OFF or DORMANT wakeup. |
| 80 | */ |
| 81 | static inline void set_cpu_wakeup_addr(unsigned int cpu_id, u32 addr) |
| 82 | { |
| 83 | struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id); |
| 84 | |
| 85 | __raw_writel(addr, pm_info->wkup_sar_addr); |
| 86 | } |
| 87 | |
| 88 | /* |
| 89 | * Set the CPUx powerdomain's previous power state |
| 90 | */ |
| 91 | static inline void set_cpu_next_pwrst(unsigned int cpu_id, |
| 92 | unsigned int power_state) |
| 93 | { |
| 94 | struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id); |
| 95 | |
| 96 | pwrdm_set_next_pwrst(pm_info->pwrdm, power_state); |
| 97 | } |
| 98 | |
| 99 | /* |
| 100 | * Read CPU's previous power state |
| 101 | */ |
| 102 | static inline unsigned int read_cpu_prev_pwrst(unsigned int cpu_id) |
| 103 | { |
| 104 | struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id); |
| 105 | |
| 106 | return pwrdm_read_prev_pwrst(pm_info->pwrdm); |
| 107 | } |
| 108 | |
| 109 | /* |
| 110 | * Clear the CPUx powerdomain's previous power state |
| 111 | */ |
| 112 | static inline void clear_cpu_prev_pwrst(unsigned int cpu_id) |
| 113 | { |
| 114 | struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id); |
| 115 | |
| 116 | pwrdm_clear_all_prev_pwrst(pm_info->pwrdm); |
| 117 | } |
| 118 | |
| 119 | /* |
| 120 | * Store the SCU power status value to scratchpad memory |
| 121 | */ |
| 122 | static void scu_pwrst_prepare(unsigned int cpu_id, unsigned int cpu_state) |
| 123 | { |
| 124 | struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id); |
| 125 | u32 scu_pwr_st; |
| 126 | |
| 127 | switch (cpu_state) { |
| 128 | case PWRDM_POWER_RET: |
| 129 | scu_pwr_st = SCU_PM_DORMANT; |
| 130 | break; |
| 131 | case PWRDM_POWER_OFF: |
| 132 | scu_pwr_st = SCU_PM_POWEROFF; |
| 133 | break; |
| 134 | case PWRDM_POWER_ON: |
| 135 | case PWRDM_POWER_INACTIVE: |
| 136 | default: |
| 137 | scu_pwr_st = SCU_PM_NORMAL; |
| 138 | break; |
| 139 | } |
| 140 | |
| 141 | __raw_writel(scu_pwr_st, pm_info->scu_sar_addr); |
| 142 | } |
| 143 | |
Santosh Shilimkar | 3ba2a73 | 2011-06-06 14:33:29 +0530 | [diff] [blame] | 144 | /* Helper functions for MPUSS OSWR */ |
| 145 | static inline void mpuss_clear_prev_logic_pwrst(void) |
| 146 | { |
| 147 | u32 reg; |
| 148 | |
| 149 | reg = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION, |
| 150 | OMAP4430_PRM_MPU_INST, OMAP4_RM_MPU_MPU_CONTEXT_OFFSET); |
| 151 | omap4_prminst_write_inst_reg(reg, OMAP4430_PRM_PARTITION, |
| 152 | OMAP4430_PRM_MPU_INST, OMAP4_RM_MPU_MPU_CONTEXT_OFFSET); |
| 153 | } |
| 154 | |
| 155 | static inline void cpu_clear_prev_logic_pwrst(unsigned int cpu_id) |
| 156 | { |
| 157 | u32 reg; |
| 158 | |
| 159 | if (cpu_id) { |
| 160 | reg = omap4_prcm_mpu_read_inst_reg(OMAP4430_PRCM_MPU_CPU1_INST, |
| 161 | OMAP4_RM_CPU1_CPU1_CONTEXT_OFFSET); |
| 162 | omap4_prcm_mpu_write_inst_reg(reg, OMAP4430_PRCM_MPU_CPU1_INST, |
| 163 | OMAP4_RM_CPU1_CPU1_CONTEXT_OFFSET); |
| 164 | } else { |
| 165 | reg = omap4_prcm_mpu_read_inst_reg(OMAP4430_PRCM_MPU_CPU0_INST, |
| 166 | OMAP4_RM_CPU0_CPU0_CONTEXT_OFFSET); |
| 167 | omap4_prcm_mpu_write_inst_reg(reg, OMAP4430_PRCM_MPU_CPU0_INST, |
| 168 | OMAP4_RM_CPU0_CPU0_CONTEXT_OFFSET); |
| 169 | } |
| 170 | } |
| 171 | |
| 172 | /** |
| 173 | * omap4_mpuss_read_prev_context_state: |
| 174 | * Function returns the MPUSS previous context state |
| 175 | */ |
| 176 | u32 omap4_mpuss_read_prev_context_state(void) |
| 177 | { |
| 178 | u32 reg; |
| 179 | |
| 180 | reg = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION, |
| 181 | OMAP4430_PRM_MPU_INST, OMAP4_RM_MPU_MPU_CONTEXT_OFFSET); |
| 182 | reg &= OMAP4430_LOSTCONTEXT_DFF_MASK; |
| 183 | return reg; |
| 184 | } |
| 185 | |
Santosh Shilimkar | 5e94c6e3 | 2011-01-09 02:59:09 +0530 | [diff] [blame] | 186 | /* |
| 187 | * Store the CPU cluster state for L2X0 low power operations. |
| 188 | */ |
| 189 | static void l2x0_pwrst_prepare(unsigned int cpu_id, unsigned int save_state) |
| 190 | { |
| 191 | struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id); |
| 192 | |
| 193 | __raw_writel(save_state, pm_info->l2x0_sar_addr); |
| 194 | } |
| 195 | |
| 196 | /* |
| 197 | * Save the L2X0 AUXCTRL and POR value to SAR memory. Its used to |
| 198 | * in every restore MPUSS OFF path. |
| 199 | */ |
| 200 | #ifdef CONFIG_CACHE_L2X0 |
| 201 | static void save_l2x0_context(void) |
| 202 | { |
| 203 | u32 val; |
| 204 | void __iomem *l2x0_base = omap4_get_l2cache_base(); |
| 205 | |
| 206 | val = __raw_readl(l2x0_base + L2X0_AUX_CTRL); |
| 207 | __raw_writel(val, sar_base + L2X0_AUXCTRL_OFFSET); |
| 208 | val = __raw_readl(l2x0_base + L2X0_PREFETCH_CTRL); |
| 209 | __raw_writel(val, sar_base + L2X0_PREFETCH_CTRL_OFFSET); |
| 210 | } |
| 211 | #else |
| 212 | static void save_l2x0_context(void) |
| 213 | {} |
| 214 | #endif |
| 215 | |
Santosh Shilimkar | b2b9762 | 2010-06-16 22:19:48 +0530 | [diff] [blame] | 216 | /** |
| 217 | * omap4_enter_lowpower: OMAP4 MPUSS Low Power Entry Function |
| 218 | * The purpose of this function is to manage low power programming |
| 219 | * of OMAP4 MPUSS subsystem |
| 220 | * @cpu : CPU ID |
| 221 | * @power_state: Low power state. |
Santosh Shilimkar | e44f9a7 | 2010-06-16 22:19:49 +0530 | [diff] [blame] | 222 | * |
| 223 | * MPUSS states for the context save: |
| 224 | * save_state = |
| 225 | * 0 - Nothing lost and no need to save: MPUSS INACTIVE |
| 226 | * 1 - CPUx L1 and logic lost: MPUSS CSWR |
| 227 | * 2 - CPUx L1 and logic lost + GIC lost: MPUSS OSWR |
| 228 | * 3 - CPUx L1 and logic lost + GIC + L2 lost: DEVICE OFF |
Santosh Shilimkar | b2b9762 | 2010-06-16 22:19:48 +0530 | [diff] [blame] | 229 | */ |
| 230 | int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state) |
| 231 | { |
| 232 | unsigned int save_state = 0; |
| 233 | unsigned int wakeup_cpu; |
| 234 | |
| 235 | if (omap_rev() == OMAP4430_REV_ES1_0) |
| 236 | return -ENXIO; |
| 237 | |
| 238 | switch (power_state) { |
| 239 | case PWRDM_POWER_ON: |
| 240 | case PWRDM_POWER_INACTIVE: |
| 241 | save_state = 0; |
| 242 | break; |
| 243 | case PWRDM_POWER_OFF: |
| 244 | save_state = 1; |
| 245 | break; |
| 246 | case PWRDM_POWER_RET: |
| 247 | default: |
| 248 | /* |
| 249 | * CPUx CSWR is invalid hardware state. Also CPUx OSWR |
| 250 | * doesn't make much scense, since logic is lost and $L1 |
| 251 | * needs to be cleaned because of coherency. This makes |
| 252 | * CPUx OSWR equivalent to CPUX OFF and hence not supported |
| 253 | */ |
| 254 | WARN_ON(1); |
| 255 | return -ENXIO; |
| 256 | } |
| 257 | |
Santosh Shilimkar | 49404dd | 2011-01-10 01:02:15 +0530 | [diff] [blame] | 258 | pwrdm_pre_transition(); |
| 259 | |
Santosh Shilimkar | 3ba2a73 | 2011-06-06 14:33:29 +0530 | [diff] [blame] | 260 | /* |
| 261 | * Check MPUSS next state and save interrupt controller if needed. |
| 262 | * In MPUSS OSWR or device OFF, interrupt controller contest is lost. |
| 263 | */ |
| 264 | mpuss_clear_prev_logic_pwrst(); |
Santosh Shilimkar | e44f9a7 | 2010-06-16 22:19:49 +0530 | [diff] [blame] | 265 | pwrdm_clear_all_prev_pwrst(mpuss_pd); |
Santosh Shilimkar | 3ba2a73 | 2011-06-06 14:33:29 +0530 | [diff] [blame] | 266 | if ((pwrdm_read_next_pwrst(mpuss_pd) == PWRDM_POWER_RET) && |
| 267 | (pwrdm_read_logic_retst(mpuss_pd) == PWRDM_POWER_OFF)) |
| 268 | save_state = 2; |
| 269 | |
Santosh Shilimkar | b2b9762 | 2010-06-16 22:19:48 +0530 | [diff] [blame] | 270 | clear_cpu_prev_pwrst(cpu); |
Santosh Shilimkar | 3ba2a73 | 2011-06-06 14:33:29 +0530 | [diff] [blame] | 271 | cpu_clear_prev_logic_pwrst(cpu); |
Santosh Shilimkar | b2b9762 | 2010-06-16 22:19:48 +0530 | [diff] [blame] | 272 | set_cpu_next_pwrst(cpu, power_state); |
| 273 | set_cpu_wakeup_addr(cpu, virt_to_phys(omap4_cpu_resume)); |
| 274 | scu_pwrst_prepare(cpu, power_state); |
Santosh Shilimkar | 5e94c6e3 | 2011-01-09 02:59:09 +0530 | [diff] [blame] | 275 | l2x0_pwrst_prepare(cpu, save_state); |
Santosh Shilimkar | b2b9762 | 2010-06-16 22:19:48 +0530 | [diff] [blame] | 276 | |
| 277 | /* |
| 278 | * Call low level function with targeted low power state. |
| 279 | */ |
| 280 | cpu_suspend(save_state, omap4_finish_suspend); |
| 281 | |
| 282 | /* |
| 283 | * Restore the CPUx power state to ON otherwise CPUx |
| 284 | * power domain can transitions to programmed low power |
| 285 | * state while doing WFI outside the low powe code. On |
| 286 | * secure devices, CPUx does WFI which can result in |
| 287 | * domain transition |
| 288 | */ |
| 289 | wakeup_cpu = smp_processor_id(); |
| 290 | set_cpu_next_pwrst(wakeup_cpu, PWRDM_POWER_ON); |
| 291 | |
Santosh Shilimkar | 49404dd | 2011-01-10 01:02:15 +0530 | [diff] [blame] | 292 | pwrdm_post_transition(); |
| 293 | |
Santosh Shilimkar | b2b9762 | 2010-06-16 22:19:48 +0530 | [diff] [blame] | 294 | return 0; |
| 295 | } |
| 296 | |
Santosh Shilimkar | b5b4f28 | 2010-06-16 22:19:48 +0530 | [diff] [blame] | 297 | /** |
| 298 | * omap4_hotplug_cpu: OMAP4 CPU hotplug entry |
| 299 | * @cpu : CPU ID |
| 300 | * @power_state: CPU low power state. |
| 301 | */ |
| 302 | int omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state) |
| 303 | { |
| 304 | unsigned int cpu_state = 0; |
| 305 | |
| 306 | if (omap_rev() == OMAP4430_REV_ES1_0) |
| 307 | return -ENXIO; |
| 308 | |
| 309 | if (power_state == PWRDM_POWER_OFF) |
| 310 | cpu_state = 1; |
| 311 | |
| 312 | clear_cpu_prev_pwrst(cpu); |
| 313 | set_cpu_next_pwrst(cpu, power_state); |
| 314 | set_cpu_wakeup_addr(cpu, virt_to_phys(omap_secondary_startup)); |
| 315 | scu_pwrst_prepare(cpu, power_state); |
| 316 | |
| 317 | /* |
| 318 | * CPU never retuns back if targetted power state is OFF mode. |
| 319 | * CPU ONLINE follows normal CPU ONLINE ptah via |
| 320 | * omap_secondary_startup(). |
| 321 | */ |
| 322 | omap4_finish_suspend(cpu_state); |
| 323 | |
| 324 | set_cpu_next_pwrst(cpu, PWRDM_POWER_ON); |
| 325 | return 0; |
| 326 | } |
| 327 | |
| 328 | |
Santosh Shilimkar | b2b9762 | 2010-06-16 22:19:48 +0530 | [diff] [blame] | 329 | /* |
| 330 | * Initialise OMAP4 MPUSS |
| 331 | */ |
| 332 | int __init omap4_mpuss_init(void) |
| 333 | { |
| 334 | struct omap4_cpu_pm_info *pm_info; |
Santosh Shilimkar | b2b9762 | 2010-06-16 22:19:48 +0530 | [diff] [blame] | 335 | |
| 336 | if (omap_rev() == OMAP4430_REV_ES1_0) { |
| 337 | WARN(1, "Power Management not supported on OMAP4430 ES1.0\n"); |
| 338 | return -ENODEV; |
| 339 | } |
| 340 | |
Santosh Shilimkar | 5e94c6e3 | 2011-01-09 02:59:09 +0530 | [diff] [blame] | 341 | sar_base = omap4_get_sar_ram_base(); |
| 342 | |
Santosh Shilimkar | b2b9762 | 2010-06-16 22:19:48 +0530 | [diff] [blame] | 343 | /* Initilaise per CPU PM information */ |
| 344 | pm_info = &per_cpu(omap4_pm_info, 0x0); |
| 345 | pm_info->scu_sar_addr = sar_base + SCU_OFFSET0; |
| 346 | pm_info->wkup_sar_addr = sar_base + CPU0_WAKEUP_NS_PA_ADDR_OFFSET; |
Santosh Shilimkar | 5e94c6e3 | 2011-01-09 02:59:09 +0530 | [diff] [blame] | 347 | pm_info->l2x0_sar_addr = sar_base + L2X0_SAVE_OFFSET0; |
Santosh Shilimkar | b2b9762 | 2010-06-16 22:19:48 +0530 | [diff] [blame] | 348 | pm_info->pwrdm = pwrdm_lookup("cpu0_pwrdm"); |
| 349 | if (!pm_info->pwrdm) { |
| 350 | pr_err("Lookup failed for CPU0 pwrdm\n"); |
| 351 | return -ENODEV; |
| 352 | } |
| 353 | |
| 354 | /* Clear CPU previous power domain state */ |
| 355 | pwrdm_clear_all_prev_pwrst(pm_info->pwrdm); |
Santosh Shilimkar | 3ba2a73 | 2011-06-06 14:33:29 +0530 | [diff] [blame] | 356 | cpu_clear_prev_logic_pwrst(0); |
Santosh Shilimkar | b2b9762 | 2010-06-16 22:19:48 +0530 | [diff] [blame] | 357 | |
| 358 | /* Initialise CPU0 power domain state to ON */ |
| 359 | pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON); |
| 360 | |
| 361 | pm_info = &per_cpu(omap4_pm_info, 0x1); |
| 362 | pm_info->scu_sar_addr = sar_base + SCU_OFFSET1; |
| 363 | pm_info->wkup_sar_addr = sar_base + CPU1_WAKEUP_NS_PA_ADDR_OFFSET; |
Santosh Shilimkar | 5e94c6e3 | 2011-01-09 02:59:09 +0530 | [diff] [blame] | 364 | pm_info->l2x0_sar_addr = sar_base + L2X0_SAVE_OFFSET1; |
Santosh Shilimkar | b2b9762 | 2010-06-16 22:19:48 +0530 | [diff] [blame] | 365 | pm_info->pwrdm = pwrdm_lookup("cpu1_pwrdm"); |
| 366 | if (!pm_info->pwrdm) { |
| 367 | pr_err("Lookup failed for CPU1 pwrdm\n"); |
| 368 | return -ENODEV; |
| 369 | } |
| 370 | |
| 371 | /* Clear CPU previous power domain state */ |
| 372 | pwrdm_clear_all_prev_pwrst(pm_info->pwrdm); |
Santosh Shilimkar | 3ba2a73 | 2011-06-06 14:33:29 +0530 | [diff] [blame] | 373 | cpu_clear_prev_logic_pwrst(1); |
Santosh Shilimkar | b2b9762 | 2010-06-16 22:19:48 +0530 | [diff] [blame] | 374 | |
| 375 | /* Initialise CPU1 power domain state to ON */ |
| 376 | pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON); |
| 377 | |
Santosh Shilimkar | e44f9a7 | 2010-06-16 22:19:49 +0530 | [diff] [blame] | 378 | mpuss_pd = pwrdm_lookup("mpu_pwrdm"); |
| 379 | if (!mpuss_pd) { |
| 380 | pr_err("Failed to lookup MPUSS power domain\n"); |
| 381 | return -ENODEV; |
| 382 | } |
| 383 | pwrdm_clear_all_prev_pwrst(mpuss_pd); |
Santosh Shilimkar | 3ba2a73 | 2011-06-06 14:33:29 +0530 | [diff] [blame] | 384 | mpuss_clear_prev_logic_pwrst(); |
Santosh Shilimkar | e44f9a7 | 2010-06-16 22:19:49 +0530 | [diff] [blame] | 385 | |
Santosh Shilimkar | b2b9762 | 2010-06-16 22:19:48 +0530 | [diff] [blame] | 386 | /* Save device type on scratchpad for low level code to use */ |
| 387 | if (omap_type() != OMAP2_DEVICE_TYPE_GP) |
| 388 | __raw_writel(1, sar_base + OMAP_TYPE_OFFSET); |
| 389 | else |
| 390 | __raw_writel(0, sar_base + OMAP_TYPE_OFFSET); |
| 391 | |
Santosh Shilimkar | 5e94c6e3 | 2011-01-09 02:59:09 +0530 | [diff] [blame] | 392 | save_l2x0_context(); |
| 393 | |
Santosh Shilimkar | b2b9762 | 2010-06-16 22:19:48 +0530 | [diff] [blame] | 394 | return 0; |
| 395 | } |
| 396 | |
| 397 | #endif |