Veera Sundaram Sankaran | 02dd6ac | 2016-12-22 15:08:29 -0800 | [diff] [blame] | 1 | /* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved. |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | */ |
| 12 | |
| 13 | #ifndef _SDE_HW_SSPP_H |
| 14 | #define _SDE_HW_SSPP_H |
| 15 | |
| 16 | #include "sde_hw_catalog.h" |
| 17 | #include "sde_hw_mdss.h" |
Clarence Ip | c475b08 | 2016-06-26 09:27:23 -0400 | [diff] [blame] | 18 | #include "sde_hw_util.h" |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 19 | #include "sde_formats.h" |
Benet Clark | d009b1d | 2016-06-27 14:45:59 -0700 | [diff] [blame] | 20 | #include "sde_color_processing.h" |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 21 | |
| 22 | struct sde_hw_pipe; |
| 23 | |
| 24 | /** |
| 25 | * Flags |
| 26 | */ |
| 27 | #define SDE_SSPP_SECURE_OVERLAY_SESSION 0x1 |
| 28 | #define SDE_SSPP_FLIP_LR 0x2 |
| 29 | #define SDE_SSPP_FLIP_UD 0x4 |
| 30 | #define SDE_SSPP_SOURCE_ROTATED_90 0x8 |
| 31 | #define SDE_SSPP_ROT_90 0x10 |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 32 | #define SDE_SSPP_SOLID_FILL 0x20 |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 33 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 34 | /** |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 35 | * Define all scaler feature bits in catalog |
| 36 | */ |
| 37 | #define SDE_SSPP_SCALER ((1UL << SDE_SSPP_SCALER_RGB) | \ |
| 38 | (1UL << SDE_SSPP_SCALER_QSEED2) | \ |
| 39 | (1UL << SDE_SSPP_SCALER_QSEED3)) |
| 40 | |
| 41 | /** |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 42 | * Component indices |
| 43 | */ |
| 44 | enum { |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 45 | SDE_SSPP_COMP_0, |
| 46 | SDE_SSPP_COMP_1_2, |
| 47 | SDE_SSPP_COMP_2, |
| 48 | SDE_SSPP_COMP_3, |
| 49 | |
| 50 | SDE_SSPP_COMP_MAX |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 51 | }; |
| 52 | |
Jeykumar Sankaran | 2e65503 | 2017-02-04 14:05:45 -0800 | [diff] [blame] | 53 | /** |
| 54 | * SDE_SSPP_RECT_SOLO - multirect disabled |
| 55 | * SDE_SSPP_RECT_0 - rect0 of a multirect pipe |
| 56 | * SDE_SSPP_RECT_1 - rect1 of a multirect pipe |
| 57 | * |
| 58 | * Note: HW supports multirect with either RECT0 or |
| 59 | * RECT1. Considering no benefit of such configs over |
| 60 | * SOLO mode and to keep the plane management simple, |
| 61 | * we dont support single rect multirect configs. |
| 62 | */ |
| 63 | enum sde_sspp_multirect_index { |
| 64 | SDE_SSPP_RECT_SOLO = 0, |
| 65 | SDE_SSPP_RECT_0, |
| 66 | SDE_SSPP_RECT_1, |
| 67 | }; |
| 68 | |
| 69 | enum sde_sspp_multirect_mode { |
| 70 | SDE_SSPP_MULTIRECT_NONE = 0, |
| 71 | SDE_SSPP_MULTIRECT_PARALLEL, |
| 72 | SDE_SSPP_MULTIRECT_TIME_MX, |
| 73 | }; |
| 74 | |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 75 | enum { |
Lloyd Atkinson | 9a67349 | 2016-07-05 11:41:57 -0400 | [diff] [blame] | 76 | SDE_FRAME_LINEAR, |
| 77 | SDE_FRAME_TILE_A4X, |
| 78 | SDE_FRAME_TILE_A5X, |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 79 | }; |
| 80 | |
| 81 | enum sde_hw_filter { |
Lloyd Atkinson | 9a67349 | 2016-07-05 11:41:57 -0400 | [diff] [blame] | 82 | SDE_SCALE_FILTER_NEAREST = 0, |
| 83 | SDE_SCALE_FILTER_BIL, |
| 84 | SDE_SCALE_FILTER_PCMN, |
| 85 | SDE_SCALE_FILTER_CA, |
| 86 | SDE_SCALE_FILTER_MAX |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 87 | }; |
| 88 | |
Gopikrishnaiah Anandan | f4c3429 | 2016-10-20 15:42:04 -0700 | [diff] [blame] | 89 | enum sde_hw_filter_alpa { |
| 90 | SDE_SCALE_ALPHA_PIXEL_REP, |
| 91 | SDE_SCALE_ALPHA_BIL |
| 92 | }; |
| 93 | |
| 94 | enum sde_hw_filter_yuv { |
| 95 | SDE_SCALE_2D_4X4, |
| 96 | SDE_SCALE_2D_CIR, |
| 97 | SDE_SCALE_1D_SEP, |
| 98 | SDE_SCALE_BIL |
| 99 | }; |
| 100 | |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 101 | struct sde_hw_sharp_cfg { |
| 102 | u32 strength; |
| 103 | u32 edge_thr; |
| 104 | u32 smooth_thr; |
| 105 | u32 noise_thr; |
| 106 | }; |
| 107 | |
| 108 | struct sde_hw_pixel_ext { |
| 109 | /* scaling factors are enabled for this input layer */ |
| 110 | uint8_t enable_pxl_ext; |
| 111 | |
| 112 | int init_phase_x[SDE_MAX_PLANES]; |
| 113 | int phase_step_x[SDE_MAX_PLANES]; |
| 114 | int init_phase_y[SDE_MAX_PLANES]; |
| 115 | int phase_step_y[SDE_MAX_PLANES]; |
| 116 | |
| 117 | /* |
| 118 | * Number of pixels extension in left, right, top and bottom direction |
| 119 | * for all color components. This pixel value for each color component |
| 120 | * should be sum of fetch + repeat pixels. |
| 121 | */ |
| 122 | int num_ext_pxls_left[SDE_MAX_PLANES]; |
| 123 | int num_ext_pxls_right[SDE_MAX_PLANES]; |
| 124 | int num_ext_pxls_top[SDE_MAX_PLANES]; |
| 125 | int num_ext_pxls_btm[SDE_MAX_PLANES]; |
| 126 | |
| 127 | /* |
| 128 | * Number of pixels needs to be overfetched in left, right, top and |
| 129 | * bottom directions from source image for scaling. |
| 130 | */ |
| 131 | int left_ftch[SDE_MAX_PLANES]; |
| 132 | int right_ftch[SDE_MAX_PLANES]; |
| 133 | int top_ftch[SDE_MAX_PLANES]; |
| 134 | int btm_ftch[SDE_MAX_PLANES]; |
| 135 | |
| 136 | /* |
| 137 | * Number of pixels needs to be repeated in left, right, top and |
| 138 | * bottom directions for scaling. |
| 139 | */ |
| 140 | int left_rpt[SDE_MAX_PLANES]; |
| 141 | int right_rpt[SDE_MAX_PLANES]; |
| 142 | int top_rpt[SDE_MAX_PLANES]; |
| 143 | int btm_rpt[SDE_MAX_PLANES]; |
| 144 | |
| 145 | uint32_t roi_w[SDE_MAX_PLANES]; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 146 | uint32_t roi_h[SDE_MAX_PLANES]; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 147 | |
| 148 | /* |
| 149 | * Filter type to be used for scaling in horizontal and vertical |
| 150 | * directions |
| 151 | */ |
| 152 | enum sde_hw_filter horz_filter[SDE_MAX_PLANES]; |
| 153 | enum sde_hw_filter vert_filter[SDE_MAX_PLANES]; |
| 154 | |
| 155 | }; |
| 156 | |
abeykun | 48f407a | 2016-08-25 12:06:44 -0400 | [diff] [blame] | 157 | /** |
| 158 | * struct sde_hw_scaler3_de_cfg : QSEEDv3 detail enhancer configuration |
| 159 | * @enable: detail enhancer enable/disable |
| 160 | * @sharpen_level1: sharpening strength for noise |
| 161 | * @sharpen_level2: sharpening strength for signal |
| 162 | * @ clip: clip shift |
| 163 | * @ limit: limit value |
| 164 | * @ thr_quiet: quiet threshold |
| 165 | * @ thr_dieout: dieout threshold |
| 166 | * @ thr_high: low threshold |
| 167 | * @ thr_high: high threshold |
| 168 | * @ prec_shift: precision shift |
| 169 | * @ adjust_a: A-coefficients for mapping curve |
| 170 | * @ adjust_b: B-coefficients for mapping curve |
| 171 | * @ adjust_c: C-coefficients for mapping curve |
| 172 | */ |
| 173 | struct sde_hw_scaler3_de_cfg { |
| 174 | u32 enable; |
| 175 | int16_t sharpen_level1; |
| 176 | int16_t sharpen_level2; |
| 177 | uint16_t clip; |
| 178 | uint16_t limit; |
| 179 | uint16_t thr_quiet; |
| 180 | uint16_t thr_dieout; |
| 181 | uint16_t thr_low; |
| 182 | uint16_t thr_high; |
| 183 | uint16_t prec_shift; |
| 184 | int16_t adjust_a[SDE_MAX_DE_CURVES]; |
| 185 | int16_t adjust_b[SDE_MAX_DE_CURVES]; |
| 186 | int16_t adjust_c[SDE_MAX_DE_CURVES]; |
| 187 | }; |
| 188 | |
| 189 | /** |
| 190 | * struct sde_hw_scaler3_cfg : QSEEDv3 configuration |
| 191 | * @enable: scaler enable |
| 192 | * @dir_en: direction detection block enable |
| 193 | * @ init_phase_x: horizontal initial phase |
| 194 | * @ phase_step_x: horizontal phase step |
| 195 | * @ init_phase_y: vertical initial phase |
| 196 | * @ phase_step_y: vertical phase step |
| 197 | * @ preload_x: horizontal preload value |
| 198 | * @ preload_y: vertical preload value |
| 199 | * @ src_width: source width |
| 200 | * @ src_height: source height |
| 201 | * @ dst_width: destination width |
| 202 | * @ dst_height: destination height |
| 203 | * @ y_rgb_filter_cfg: y/rgb plane filter configuration |
| 204 | * @ uv_filter_cfg: uv plane filter configuration |
| 205 | * @ alpha_filter_cfg: alpha filter configuration |
| 206 | * @ blend_cfg: blend coefficients configuration |
| 207 | * @ lut_flag: scaler LUT update flags |
| 208 | * 0x1 swap LUT bank |
| 209 | * 0x2 update 2D filter LUT |
| 210 | * 0x4 update y circular filter LUT |
| 211 | * 0x8 update uv circular filter LUT |
| 212 | * 0x10 update y separable filter LUT |
| 213 | * 0x20 update uv separable filter LUT |
| 214 | * @ dir_lut_idx: 2D filter LUT index |
| 215 | * @ y_rgb_cir_lut_idx: y circular filter LUT index |
| 216 | * @ uv_cir_lut_idx: uv circular filter LUT index |
| 217 | * @ y_rgb_sep_lut_idx: y circular filter LUT index |
| 218 | * @ uv_sep_lut_idx: uv separable filter LUT index |
| 219 | * @ dir_lut: pointer to 2D LUT |
| 220 | * @ cir_lut: pointer to circular filter LUT |
| 221 | * @ sep_lut: pointer to separable filter LUT |
| 222 | * @ de: detail enhancer configuration |
| 223 | */ |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 224 | struct sde_hw_scaler3_cfg { |
abeykun | 48f407a | 2016-08-25 12:06:44 -0400 | [diff] [blame] | 225 | u32 enable; |
| 226 | u32 dir_en; |
| 227 | int32_t init_phase_x[SDE_MAX_PLANES]; |
| 228 | int32_t phase_step_x[SDE_MAX_PLANES]; |
| 229 | int32_t init_phase_y[SDE_MAX_PLANES]; |
| 230 | int32_t phase_step_y[SDE_MAX_PLANES]; |
| 231 | |
| 232 | u32 preload_x[SDE_MAX_PLANES]; |
| 233 | u32 preload_y[SDE_MAX_PLANES]; |
| 234 | u32 src_width[SDE_MAX_PLANES]; |
| 235 | u32 src_height[SDE_MAX_PLANES]; |
| 236 | |
| 237 | u32 dst_width; |
| 238 | u32 dst_height; |
| 239 | |
| 240 | u32 y_rgb_filter_cfg; |
| 241 | u32 uv_filter_cfg; |
| 242 | u32 alpha_filter_cfg; |
| 243 | u32 blend_cfg; |
| 244 | |
| 245 | u32 lut_flag; |
| 246 | u32 dir_lut_idx; |
| 247 | |
| 248 | u32 y_rgb_cir_lut_idx; |
| 249 | u32 uv_cir_lut_idx; |
| 250 | u32 y_rgb_sep_lut_idx; |
| 251 | u32 uv_sep_lut_idx; |
| 252 | u32 *dir_lut; |
| 253 | size_t dir_len; |
| 254 | u32 *cir_lut; |
| 255 | size_t cir_len; |
| 256 | u32 *sep_lut; |
| 257 | size_t sep_len; |
| 258 | |
| 259 | /* |
| 260 | * Detail enhancer settings |
| 261 | */ |
| 262 | struct sde_hw_scaler3_de_cfg de; |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 263 | }; |
| 264 | |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 265 | /** |
| 266 | * struct sde_hw_pipe_cfg : Pipe description |
Lloyd Atkinson | fa2489c | 2016-05-25 15:16:03 -0400 | [diff] [blame] | 267 | * @layout: format layout information for programming buffer to hardware |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 268 | * @src_rect: src ROI, caller takes into account the different operations |
| 269 | * such as decimation, flip etc to program this field |
| 270 | * @dest_rect: destination ROI. |
| 271 | * @ horz_decimation : horizontal decimation factor( 0, 2, 4, 8, 16) |
| 272 | * @ vert_decimation : vertical decimation factor( 0, 2, 4, 8, 16) |
| 273 | * 2: Read 1 line/pixel drop 1 line/pixel |
| 274 | * 4: Read 1 line/pixel drop 3 lines/pixels |
| 275 | * 8: Read 1 line/pixel drop 7 lines/pixels |
| 276 | * 16: Read 1 line/pixel drop 15 line/pixels |
Jeykumar Sankaran | 2e65503 | 2017-02-04 14:05:45 -0800 | [diff] [blame] | 277 | * @index: index of the rectangle of SSPP |
| 278 | * @mode: parallel or time multiplex multirect mode |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 279 | */ |
| 280 | struct sde_hw_pipe_cfg { |
Lloyd Atkinson | fa2489c | 2016-05-25 15:16:03 -0400 | [diff] [blame] | 281 | struct sde_hw_fmt_layout layout; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 282 | struct sde_rect src_rect; |
| 283 | struct sde_rect dst_rect; |
| 284 | u8 horz_decimation; |
| 285 | u8 vert_decimation; |
Jeykumar Sankaran | 2e65503 | 2017-02-04 14:05:45 -0800 | [diff] [blame] | 286 | enum sde_sspp_multirect_index index; |
| 287 | enum sde_sspp_multirect_mode mode; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 288 | }; |
| 289 | |
| 290 | /** |
Alan Kwong | 1a00e4d | 2016-07-18 09:42:30 -0400 | [diff] [blame] | 291 | * struct sde_hw_pipe_qos_cfg : Source pipe QoS configuration |
| 292 | * @danger_lut: LUT for generate danger level based on fill level |
| 293 | * @safe_lut: LUT for generate safe level based on fill level |
| 294 | * @creq_lut: LUT for generate creq level based on fill level |
| 295 | * @creq_vblank: creq value generated to vbif during vertical blanking |
| 296 | * @danger_vblank: danger value generated during vertical blanking |
| 297 | * @vblank_en: enable creq_vblank and danger_vblank during vblank |
| 298 | * @danger_safe_en: enable danger safe generation |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 299 | */ |
Alan Kwong | 1a00e4d | 2016-07-18 09:42:30 -0400 | [diff] [blame] | 300 | struct sde_hw_pipe_qos_cfg { |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 301 | u32 danger_lut; |
| 302 | u32 safe_lut; |
Alan Kwong | 1a00e4d | 2016-07-18 09:42:30 -0400 | [diff] [blame] | 303 | u32 creq_lut; |
| 304 | u32 creq_vblank; |
| 305 | u32 danger_vblank; |
| 306 | bool vblank_en; |
| 307 | bool danger_safe_en; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 308 | }; |
| 309 | |
| 310 | /** |
| 311 | * struct sde_hw_sspp_ops - interface to the SSPP Hw driver functions |
| 312 | * Caller must call the init function to get the pipe context for each pipe |
| 313 | * Assumption is these functions will be called after clocks are enabled |
| 314 | */ |
| 315 | struct sde_hw_sspp_ops { |
| 316 | /** |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 317 | * setup_format - setup pixel format cropping rectangle, flip |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 318 | * @ctx: Pointer to pipe context |
| 319 | * @cfg: Pointer to pipe config structure |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 320 | * @flags: Extra flags for format config |
Jeykumar Sankaran | 2e65503 | 2017-02-04 14:05:45 -0800 | [diff] [blame] | 321 | * @index: rectangle index in multirect |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 322 | */ |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 323 | void (*setup_format)(struct sde_hw_pipe *ctx, |
Jeykumar Sankaran | 2e65503 | 2017-02-04 14:05:45 -0800 | [diff] [blame] | 324 | const struct sde_format *fmt, u32 flags, |
| 325 | enum sde_sspp_multirect_index index); |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 326 | |
| 327 | /** |
| 328 | * setup_rects - setup pipe ROI rectangles |
| 329 | * @ctx: Pointer to pipe context |
| 330 | * @cfg: Pointer to pipe config structure |
Jeykumar Sankaran | 2e65503 | 2017-02-04 14:05:45 -0800 | [diff] [blame] | 331 | * @index: rectangle index in multirect |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 332 | */ |
| 333 | void (*setup_rects)(struct sde_hw_pipe *ctx, |
| 334 | struct sde_hw_pipe_cfg *cfg, |
Jeykumar Sankaran | 9fcfa48 | 2017-02-16 16:03:14 -0800 | [diff] [blame^] | 335 | enum sde_sspp_multirect_index index); |
| 336 | |
| 337 | /** |
| 338 | * setup_pe - setup pipe pixel extension |
| 339 | * @ctx: Pointer to pipe context |
| 340 | * @pe_ext: Pointer to pixel ext settings |
| 341 | */ |
| 342 | void (*setup_pe)(struct sde_hw_pipe *ctx, |
| 343 | struct sde_hw_pixel_ext *pe_ext); |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 344 | |
| 345 | /** |
Veera Sundaram Sankaran | 02dd6ac | 2016-12-22 15:08:29 -0800 | [diff] [blame] | 346 | * setup_excl_rect - setup pipe exclusion rectangle |
| 347 | * @ctx: Pointer to pipe context |
| 348 | * @excl_rect: Pointer to exclclusion rect structure |
Jeykumar Sankaran | 2e65503 | 2017-02-04 14:05:45 -0800 | [diff] [blame] | 349 | * @index: rectangle index in multirect |
Veera Sundaram Sankaran | 02dd6ac | 2016-12-22 15:08:29 -0800 | [diff] [blame] | 350 | */ |
| 351 | void (*setup_excl_rect)(struct sde_hw_pipe *ctx, |
Jeykumar Sankaran | 2e65503 | 2017-02-04 14:05:45 -0800 | [diff] [blame] | 352 | struct sde_rect *excl_rect, |
| 353 | enum sde_sspp_multirect_index index); |
Veera Sundaram Sankaran | 02dd6ac | 2016-12-22 15:08:29 -0800 | [diff] [blame] | 354 | |
| 355 | /** |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 356 | * setup_sourceaddress - setup pipe source addresses |
| 357 | * @ctx: Pointer to pipe context |
| 358 | * @cfg: Pointer to pipe config structure |
Jeykumar Sankaran | 2e65503 | 2017-02-04 14:05:45 -0800 | [diff] [blame] | 359 | * @index: rectangle index in multirect |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 360 | */ |
| 361 | void (*setup_sourceaddress)(struct sde_hw_pipe *ctx, |
Jeykumar Sankaran | 2e65503 | 2017-02-04 14:05:45 -0800 | [diff] [blame] | 362 | struct sde_hw_pipe_cfg *cfg, |
| 363 | enum sde_sspp_multirect_index index); |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 364 | |
| 365 | /** |
| 366 | * setup_csc - setup color space coversion |
| 367 | * @ctx: Pointer to pipe context |
| 368 | * @data: Pointer to config structure |
| 369 | */ |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 370 | void (*setup_csc)(struct sde_hw_pipe *ctx, struct sde_csc_cfg *data); |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 371 | |
| 372 | /** |
| 373 | * setup_solidfill - enable/disable colorfill |
| 374 | * @ctx: Pointer to pipe context |
| 375 | * @const_color: Fill color value |
| 376 | * @flags: Pipe flags |
Jeykumar Sankaran | 2e65503 | 2017-02-04 14:05:45 -0800 | [diff] [blame] | 377 | * @index: rectangle index in multirect |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 378 | */ |
Jeykumar Sankaran | 2e65503 | 2017-02-04 14:05:45 -0800 | [diff] [blame] | 379 | void (*setup_solidfill)(struct sde_hw_pipe *ctx, u32 color, |
| 380 | enum sde_sspp_multirect_index index); |
| 381 | |
| 382 | /** |
| 383 | * setup_multirect - setup multirect configuration |
| 384 | * @ctx: Pointer to pipe context |
| 385 | * @index: rectangle index in multirect |
| 386 | * @mode: parallel fetch / time multiplex multirect mode |
| 387 | */ |
| 388 | |
| 389 | void (*setup_multirect)(struct sde_hw_pipe *ctx, |
| 390 | enum sde_sspp_multirect_index index, |
| 391 | enum sde_sspp_multirect_mode mode); |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 392 | |
| 393 | /** |
| 394 | * setup_sharpening - setup sharpening |
| 395 | * @ctx: Pointer to pipe context |
| 396 | * @cfg: Pointer to config structure |
| 397 | */ |
| 398 | void (*setup_sharpening)(struct sde_hw_pipe *ctx, |
| 399 | struct sde_hw_sharp_cfg *cfg); |
| 400 | |
Benet Clark | eb1b446 | 2016-06-27 14:43:06 -0700 | [diff] [blame] | 401 | |
| 402 | /** |
| 403 | * setup_pa_hue(): Setup source hue adjustment |
| 404 | * @ctx: Pointer to pipe context |
| 405 | * @cfg: Pointer to hue data |
| 406 | */ |
| 407 | void (*setup_pa_hue)(struct sde_hw_pipe *ctx, void *cfg); |
| 408 | |
| 409 | /** |
| 410 | * setup_pa_sat(): Setup source saturation adjustment |
| 411 | * @ctx: Pointer to pipe context |
| 412 | * @cfg: Pointer to saturation data |
| 413 | */ |
| 414 | void (*setup_pa_sat)(struct sde_hw_pipe *ctx, void *cfg); |
| 415 | |
| 416 | /** |
| 417 | * setup_pa_val(): Setup source value adjustment |
| 418 | * @ctx: Pointer to pipe context |
| 419 | * @cfg: Pointer to value data |
| 420 | */ |
| 421 | void (*setup_pa_val)(struct sde_hw_pipe *ctx, void *cfg); |
| 422 | |
| 423 | /** |
| 424 | * setup_pa_cont(): Setup source contrast adjustment |
| 425 | * @ctx: Pointer to pipe context |
| 426 | * @cfg: Pointer contrast data |
| 427 | */ |
| 428 | void (*setup_pa_cont)(struct sde_hw_pipe *ctx, void *cfg); |
| 429 | |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 430 | /** |
| 431 | * setup_pa_memcolor - setup source color processing |
| 432 | * @ctx: Pointer to pipe context |
Benet Clark | d009b1d | 2016-06-27 14:45:59 -0700 | [diff] [blame] | 433 | * @type: Memcolor type (Skin, sky or foliage) |
| 434 | * @cfg: Pointer to memory color config data |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 435 | */ |
| 436 | void (*setup_pa_memcolor)(struct sde_hw_pipe *ctx, |
Benet Clark | d009b1d | 2016-06-27 14:45:59 -0700 | [diff] [blame] | 437 | enum sde_memcolor_type type, void *cfg); |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 438 | |
| 439 | /** |
| 440 | * setup_igc - setup inverse gamma correction |
| 441 | * @ctx: Pointer to pipe context |
| 442 | */ |
| 443 | void (*setup_igc)(struct sde_hw_pipe *ctx); |
| 444 | |
| 445 | /** |
Alan Kwong | 1a00e4d | 2016-07-18 09:42:30 -0400 | [diff] [blame] | 446 | * setup_danger_safe_lut - setup danger safe LUTs |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 447 | * @ctx: Pointer to pipe context |
Alan Kwong | 1a00e4d | 2016-07-18 09:42:30 -0400 | [diff] [blame] | 448 | * @cfg: Pointer to pipe QoS configuration |
| 449 | * |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 450 | */ |
Alan Kwong | 1a00e4d | 2016-07-18 09:42:30 -0400 | [diff] [blame] | 451 | void (*setup_danger_safe_lut)(struct sde_hw_pipe *ctx, |
| 452 | struct sde_hw_pipe_qos_cfg *cfg); |
| 453 | |
| 454 | /** |
| 455 | * setup_creq_lut - setup CREQ LUT |
| 456 | * @ctx: Pointer to pipe context |
| 457 | * @cfg: Pointer to pipe QoS configuration |
| 458 | * |
| 459 | */ |
| 460 | void (*setup_creq_lut)(struct sde_hw_pipe *ctx, |
| 461 | struct sde_hw_pipe_qos_cfg *cfg); |
| 462 | |
| 463 | /** |
| 464 | * setup_qos_ctrl - setup QoS control |
| 465 | * @ctx: Pointer to pipe context |
| 466 | * @cfg: Pointer to pipe QoS configuration |
| 467 | * |
| 468 | */ |
| 469 | void (*setup_qos_ctrl)(struct sde_hw_pipe *ctx, |
| 470 | struct sde_hw_pipe_qos_cfg *cfg); |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 471 | |
| 472 | /** |
| 473 | * setup_histogram - setup histograms |
| 474 | * @ctx: Pointer to pipe context |
| 475 | * @cfg: Pointer to histogram configuration |
| 476 | */ |
| 477 | void (*setup_histogram)(struct sde_hw_pipe *ctx, |
| 478 | void *cfg); |
abeykun | 48f407a | 2016-08-25 12:06:44 -0400 | [diff] [blame] | 479 | |
| 480 | /** |
| 481 | * setup_scaler - setup scaler |
| 482 | * @ctx: Pointer to pipe context |
| 483 | * @pipe_cfg: Pointer to pipe configuration |
| 484 | * @pe_cfg: Pointer to pixel extension configuration |
| 485 | * @scaler_cfg: Pointer to scaler configuration |
| 486 | */ |
| 487 | void (*setup_scaler)(struct sde_hw_pipe *ctx, |
| 488 | struct sde_hw_pipe_cfg *pipe_cfg, |
| 489 | struct sde_hw_pixel_ext *pe_cfg, |
| 490 | void *scaler_cfg); |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 491 | }; |
| 492 | |
| 493 | /** |
| 494 | * struct sde_hw_pipe - pipe description |
| 495 | * @base_off: mdp register mapped offset |
| 496 | * @blk_off: pipe offset relative to mdss offset |
| 497 | * @length length of register block offset |
| 498 | * @hwversion mdss hw version number |
| 499 | * @idx: pipe index |
| 500 | * @type : pipe type, VIG/DMA/RGB/CURSOR, certain operations are not |
| 501 | * supported for each pipe type |
| 502 | * @pipe_hw_cap: pointer to layer_cfg |
| 503 | * @highest_bank_bit: |
| 504 | * @ops: pointer to operations possible for this pipe |
| 505 | */ |
| 506 | struct sde_hw_pipe { |
| 507 | /* base */ |
| 508 | struct sde_hw_blk_reg_map hw; |
| 509 | |
| 510 | /* Pipe */ |
| 511 | enum sde_sspp idx; |
| 512 | const struct sde_sspp_cfg *cap; |
| 513 | u32 highest_bank_bit; |
| 514 | |
| 515 | /* Ops */ |
| 516 | struct sde_hw_sspp_ops ops; |
| 517 | }; |
| 518 | |
| 519 | /** |
| 520 | * sde_hw_sspp_init - initializes the sspp hw driver object. |
| 521 | * Should be called once before accessing every pipe. |
| 522 | * @idx: Pipe index for which driver object is required |
| 523 | * @addr: Mapped register io address of MDP |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 524 | * @catalog : Pointer to mdss catalog data |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 525 | */ |
| 526 | struct sde_hw_pipe *sde_hw_sspp_init(enum sde_sspp idx, |
| 527 | void __iomem *addr, |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 528 | struct sde_mdss_cfg *catalog); |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 529 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 530 | /** |
| 531 | * sde_hw_sspp_destroy(): Destroys SSPP driver context |
| 532 | * should be called during Hw pipe cleanup. |
| 533 | * @ctx: Pointer to SSPP driver context returned by sde_hw_sspp_init |
| 534 | */ |
| 535 | void sde_hw_sspp_destroy(struct sde_hw_pipe *ctx); |
| 536 | |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 537 | #endif /*_SDE_HW_SSPP_H */ |
| 538 | |