Tuomas Tynkkynen | d8d7a08 | 2015-05-13 17:58:36 +0300 | [diff] [blame] | 1 | /* |
| 2 | * clk-dfll.h - prototypes and macros for the Tegra DFLL clocksource driver |
| 3 | * Copyright (C) 2013 NVIDIA Corporation. All rights reserved. |
| 4 | * |
| 5 | * Aleksandr Frid <afrid@nvidia.com> |
| 6 | * Paul Walmsley <pwalmsley@nvidia.com> |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License version 2 as |
| 10 | * published by the Free Software Foundation. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, but WITHOUT |
| 13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 15 | * more details. |
| 16 | */ |
| 17 | |
| 18 | #ifndef __DRIVERS_CLK_TEGRA_CLK_DFLL_H |
| 19 | #define __DRIVERS_CLK_TEGRA_CLK_DFLL_H |
| 20 | |
| 21 | #include <linux/platform_device.h> |
| 22 | #include <linux/reset.h> |
| 23 | #include <linux/types.h> |
| 24 | |
| 25 | /** |
| 26 | * struct tegra_dfll_soc_data - SoC-specific hooks/integration for the DFLL driver |
Thierry Reding | 8eaaae9 | 2016-04-08 14:57:09 +0200 | [diff] [blame] | 27 | * @dev: struct device * that holds the OPP table for the DFLL |
Thierry Reding | f7c42d9 | 2016-04-08 15:16:28 +0200 | [diff] [blame] | 28 | * @max_freq: maximum frequency supported on this SoC |
Thierry Reding | 27ed2f7 | 2016-04-08 15:02:06 +0200 | [diff] [blame] | 29 | * @cvb: CPU frequency table for this SoC |
Thierry Reding | 8eaaae9 | 2016-04-08 14:57:09 +0200 | [diff] [blame] | 30 | * @init_clock_trimmers: callback to initialize clock trimmers |
| 31 | * @set_clock_trimmers_high: callback to tune clock trimmers for high voltage |
| 32 | * @set_clock_trimmers_low: callback to tune clock trimmers for low voltage |
Tuomas Tynkkynen | d8d7a08 | 2015-05-13 17:58:36 +0300 | [diff] [blame] | 33 | */ |
| 34 | struct tegra_dfll_soc_data { |
Tuomas Tynkkynen | 62a8a09 | 2015-05-13 17:58:41 +0300 | [diff] [blame] | 35 | struct device *dev; |
Thierry Reding | f7c42d9 | 2016-04-08 15:16:28 +0200 | [diff] [blame] | 36 | unsigned long max_freq; |
Thierry Reding | 27ed2f7 | 2016-04-08 15:02:06 +0200 | [diff] [blame] | 37 | const struct cvb_table *cvb; |
Thierry Reding | 8eaaae9 | 2016-04-08 14:57:09 +0200 | [diff] [blame] | 38 | |
Tuomas Tynkkynen | d8d7a08 | 2015-05-13 17:58:36 +0300 | [diff] [blame] | 39 | void (*init_clock_trimmers)(void); |
| 40 | void (*set_clock_trimmers_high)(void); |
| 41 | void (*set_clock_trimmers_low)(void); |
| 42 | }; |
| 43 | |
| 44 | int tegra_dfll_register(struct platform_device *pdev, |
| 45 | struct tegra_dfll_soc_data *soc); |
| 46 | int tegra_dfll_unregister(struct platform_device *pdev); |
| 47 | int tegra_dfll_runtime_suspend(struct device *dev); |
| 48 | int tegra_dfll_runtime_resume(struct device *dev); |
| 49 | |
| 50 | #endif /* __DRIVERS_CLK_TEGRA_CLK_DFLL_H */ |