blob: fe0110074902dea0c03f3cd20d36208b62d0042d [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1994 - 2003 by Ralf Baechle
7 */
8#include <linux/config.h>
9#include <linux/init.h>
10#include <linux/kernel.h>
11#include <linux/module.h>
12#include <linux/sched.h>
13#include <linux/mm.h>
14
15#include <asm/cacheflush.h>
16#include <asm/processor.h>
17#include <asm/cpu.h>
18#include <asm/cpu-features.h>
19
20/* Cache operations. */
21void (*flush_cache_all)(void);
22void (*__flush_cache_all)(void);
23void (*flush_cache_mm)(struct mm_struct *mm);
24void (*flush_cache_range)(struct vm_area_struct *vma, unsigned long start,
25 unsigned long end);
26void (*flush_cache_page)(struct vm_area_struct *vma, unsigned long page, unsigned long pfn);
Ralf Baechlefe00f942005-03-01 19:22:29 +000027void (*flush_icache_range)(unsigned long __user start,
28 unsigned long __user end);
Linus Torvalds1da177e2005-04-16 15:20:36 -070029void (*flush_icache_page)(struct vm_area_struct *vma, struct page *page);
30
31/* MIPS specific cache operations */
32void (*flush_cache_sigtramp)(unsigned long addr);
33void (*flush_data_cache_page)(unsigned long addr);
34void (*flush_icache_all)(void);
35
Ralf Baechle9ff77c42005-03-08 14:39:39 +000036EXPORT_SYMBOL(flush_data_cache_page);
37
Linus Torvalds1da177e2005-04-16 15:20:36 -070038#ifdef CONFIG_DMA_NONCOHERENT
39
40/* DMA cache operations. */
41void (*_dma_cache_wback_inv)(unsigned long start, unsigned long size);
42void (*_dma_cache_wback)(unsigned long start, unsigned long size);
43void (*_dma_cache_inv)(unsigned long start, unsigned long size);
44
45EXPORT_SYMBOL(_dma_cache_wback_inv);
46EXPORT_SYMBOL(_dma_cache_wback);
47EXPORT_SYMBOL(_dma_cache_inv);
48
49#endif /* CONFIG_DMA_NONCOHERENT */
50
51/*
52 * We could optimize the case where the cache argument is not BCACHE but
53 * that seems very atypical use ...
54 */
Ralf Baechlefe00f942005-03-01 19:22:29 +000055asmlinkage int sys_cacheflush(unsigned long __user addr,
56 unsigned long bytes, unsigned int cache)
Linus Torvalds1da177e2005-04-16 15:20:36 -070057{
Ralf Baechlefe00f942005-03-01 19:22:29 +000058 if (!access_ok(VERIFY_WRITE, (void __user *) addr, bytes))
Linus Torvalds1da177e2005-04-16 15:20:36 -070059 return -EFAULT;
60
61 flush_icache_range(addr, addr + bytes);
62
63 return 0;
64}
65
66void __flush_dcache_page(struct page *page)
67{
68 struct address_space *mapping = page_mapping(page);
69 unsigned long addr;
70
71 if (mapping && !mapping_mapped(mapping)) {
72 SetPageDcacheDirty(page);
73 return;
74 }
75
76 /*
77 * We could delay the flush for the !page_mapping case too. But that
78 * case is for exec env/arg pages and those are %99 certainly going to
79 * get faulted into the tlb (and thus flushed) anyways.
80 */
81 addr = (unsigned long) page_address(page);
82 flush_data_cache_page(addr);
83}
84
85EXPORT_SYMBOL(__flush_dcache_page);
86
87void __update_cache(struct vm_area_struct *vma, unsigned long address,
88 pte_t pte)
89{
90 struct page *page;
91 unsigned long pfn, addr;
92
93 pfn = pte_pfn(pte);
94 if (pfn_valid(pfn) && (page = pfn_to_page(pfn), page_mapping(page)) &&
95 Page_dcache_dirty(page)) {
96 if (pages_do_alias((unsigned long)page_address(page),
97 address & PAGE_MASK)) {
98 addr = (unsigned long) page_address(page);
99 flush_data_cache_page(addr);
100 }
101
102 ClearPageDcacheDirty(page);
103 }
104}
105
106extern void ld_mmu_r23000(void);
107extern void ld_mmu_r4xx0(void);
108extern void ld_mmu_tx39(void);
109extern void ld_mmu_r6000(void);
110extern void ld_mmu_tfp(void);
111extern void ld_mmu_andes(void);
112extern void ld_mmu_sb1(void);
113
114void __init cpu_cache_init(void)
115{
116 if (cpu_has_4ktlb) {
117#if defined(CONFIG_CPU_R4X00) || defined(CONFIG_CPU_VR41XX) || \
118 defined(CONFIG_CPU_R4300) || defined(CONFIG_CPU_R5000) || \
119 defined(CONFIG_CPU_NEVADA) || defined(CONFIG_CPU_R5432) || \
120 defined(CONFIG_CPU_R5500) || defined(CONFIG_CPU_MIPS32) || \
121 defined(CONFIG_CPU_MIPS64) || defined(CONFIG_CPU_TX49XX) || \
122 defined(CONFIG_CPU_RM7000) || defined(CONFIG_CPU_RM9000)
123 ld_mmu_r4xx0();
124#endif
125 } else switch (current_cpu_data.cputype) {
126#ifdef CONFIG_CPU_R3000
127 case CPU_R2000:
128 case CPU_R3000:
129 case CPU_R3000A:
130 case CPU_R3081E:
131 ld_mmu_r23000();
132 break;
133#endif
134#ifdef CONFIG_CPU_TX39XX
135 case CPU_TX3912:
136 case CPU_TX3922:
137 case CPU_TX3927:
138 ld_mmu_tx39();
139 break;
140#endif
141#ifdef CONFIG_CPU_R10000
142 case CPU_R10000:
143 case CPU_R12000:
144 ld_mmu_r4xx0();
145 break;
146#endif
147#ifdef CONFIG_CPU_SB1
148 case CPU_SB1:
149 ld_mmu_sb1();
150 break;
151#endif
152
153 case CPU_R8000:
154 panic("R8000 is unsupported");
155 break;
156
157 default:
158 panic("Yeee, unsupported cache architecture.");
159 }
160}