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Tony Lindgren5e1c5ff2005-07-10 19:58:15 +01001/*
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +01002 * Support functions for OMAP GPIO
3 *
Tony Lindgren92105bb2005-09-07 17:20:26 +01004 * Copyright (C) 2003-2005 Nokia Corporation
Jan Engelhardt96de0e22007-10-19 23:21:04 +02005 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +01006 *
Santosh Shilimkar44169072009-05-28 14:16:04 -07007 * Copyright (C) 2009 Texas Instruments
8 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
9 *
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +010010 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +010015#include <linux/init.h>
16#include <linux/module.h>
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +010017#include <linux/interrupt.h>
Rafael J. Wysocki3c437ff2011-04-22 22:02:46 +020018#include <linux/syscore_ops.h>
Tony Lindgren92105bb2005-09-07 17:20:26 +010019#include <linux/err.h>
Russell Kingf8ce2542006-01-07 16:15:52 +000020#include <linux/clk.h>
Russell Kingfced80c2008-09-06 12:10:45 +010021#include <linux/io.h>
Benoit Cousson96751fc2012-02-01 16:01:39 +010022#include <linux/device.h>
Varadarajan, Charulatha77640aa2010-12-07 16:26:57 -080023#include <linux/pm_runtime.h>
Tarun Kanti DebBarma55b93c32011-09-29 07:23:22 +053024#include <linux/pm.h>
Benoit Cousson384ebe12011-08-16 11:53:02 +020025#include <linux/of.h>
26#include <linux/of_device.h>
Tony Lindgren4b254082012-08-30 15:37:24 -070027#include <linux/gpio.h>
Yegor Yefremov93700842014-04-24 08:57:39 +020028#include <linux/bitops.h>
Tony Lindgren4b254082012-08-30 15:37:24 -070029#include <linux/platform_data/gpio-omap.h>
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +010030
Tarun Kanti DebBarma2dc983c2011-11-24 02:44:29 +053031#define OFF_MODE 1
Grygorii Strashkoe85ec6c2015-08-18 14:10:54 +030032#define OMAP4_GPIO_DEBOUNCINGTIME_MASK 0xFF
Tarun Kanti DebBarma2dc983c2011-11-24 02:44:29 +053033
Charulatha V03e128c2011-05-05 19:58:01 +053034static LIST_HEAD(omap_gpio_list);
35
Charulatha V6d62e212011-04-18 15:06:51 +000036struct gpio_regs {
37 u32 irqenable1;
38 u32 irqenable2;
39 u32 wake_en;
40 u32 ctrl;
41 u32 oe;
42 u32 leveldetect0;
43 u32 leveldetect1;
44 u32 risingdetect;
45 u32 fallingdetect;
46 u32 dataout;
Nishanth Menonae547352011-09-09 19:08:58 +053047 u32 debounce;
48 u32 debounce_en;
Charulatha V6d62e212011-04-18 15:06:51 +000049};
50
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +010051struct gpio_bank {
Charulatha V03e128c2011-05-05 19:58:01 +053052 struct list_head node;
Tony Lindgren92105bb2005-09-07 17:20:26 +010053 void __iomem *base;
Grygorii Strashko30cefea2015-09-25 12:06:02 -070054 int irq;
Juha Yrjola3ac4fa92006-12-06 17:13:52 -080055 u32 non_wakeup_gpios;
56 u32 enabled_non_wakeup_gpios;
Charulatha V6d62e212011-04-18 15:06:51 +000057 struct gpio_regs context;
Juha Yrjola3ac4fa92006-12-06 17:13:52 -080058 u32 saved_datain;
Kevin Hilmanb144ff62008-01-16 21:56:15 -080059 u32 level_mask;
Cory Maccarrone4318f362010-01-08 10:29:04 -080060 u32 toggle_mask;
Sebastian Andrzej Siewior4dbada22015-07-21 18:26:51 +020061 raw_spinlock_t lock;
Grygorii Strashko450fa542015-09-25 12:28:03 -070062 raw_spinlock_t wa_lock;
David Brownell52e31342008-03-03 12:43:23 -080063 struct gpio_chip chip;
Jouni Hogander89db9482008-12-10 17:35:24 -080064 struct clk *dbck;
Charulatha V058af1e2009-11-22 10:11:25 -080065 u32 mod_usage;
Javier Martinez Canillasfa365e42013-09-25 02:36:52 +020066 u32 irq_usage;
Kevin Hilman8865b9b2009-01-27 11:15:34 -080067 u32 dbck_enable_mask;
Tarun Kanti DebBarma72f83af92011-11-24 03:03:28 +053068 bool dbck_enabled;
Charulatha Vd0d665a2011-08-31 00:02:21 +053069 bool is_mpuio;
Varadarajan, Charulatha77640aa2010-12-07 16:26:57 -080070 bool dbck_flag;
Charulatha V0cde8d02011-05-05 20:15:16 +053071 bool loses_context;
Jon Hunter352a2d52013-04-15 13:06:54 -050072 bool context_valid;
Tony Lindgren5de62b82010-12-07 16:26:58 -080073 int stride;
Kevin Hilmand5f46242011-04-21 09:23:00 -070074 u32 width;
Tarun Kanti DebBarma60a34372011-09-29 04:47:25 +053075 int context_loss_count;
Tarun Kanti DebBarma2dc983c2011-11-24 02:44:29 +053076 int power_mode;
77 bool workaround_enabled;
Kevin Hilmanfa87931a2011-04-20 16:31:23 -070078
Grygorii Strashko04ebcbd2015-03-23 14:18:24 +020079 void (*set_dataout)(struct gpio_bank *bank, unsigned gpio, int enable);
Tarun Kanti DebBarma60a34372011-09-29 04:47:25 +053080 int (*get_context_loss_count)(struct device *dev);
Kevin Hilmanfa87931a2011-04-20 16:31:23 -070081
82 struct omap_gpio_reg_offs *regs;
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +010083};
84
Charulatha Vc8eef652011-05-02 15:21:42 +053085#define GPIO_MOD_CTRL_BIT BIT(0)
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +010086
Javier Martinez Canillasfa365e42013-09-25 02:36:52 +020087#define BANK_USED(bank) (bank->mod_usage || bank->irq_usage)
Javier Martinez Canillasb1e9fec2014-04-27 02:00:49 +020088#define LINE_USED(line, offset) (line & (BIT(offset)))
Javier Martinez Canillasfa365e42013-09-25 02:36:52 +020089
Tony Lindgren3d009c82015-01-16 14:50:50 -080090static void omap_gpio_unmask_irq(struct irq_data *d);
91
Javier Martinez Canillasa0e827c2014-06-27 22:17:37 +020092static inline struct gpio_bank *omap_irq_data_get_bank(struct irq_data *d)
Jon Hunterede4d7a2013-03-01 11:22:47 -060093{
Javier Martinez Canillasfb655f52014-04-06 16:58:16 +020094 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
Linus Walleijd99f7ae2015-12-07 11:16:00 +010095 return gpiochip_get_data(chip);
Benoit Cousson25db7112012-02-23 21:50:10 +010096}
97
Javier Martinez Canillasa0e827c2014-06-27 22:17:37 +020098static void omap_set_gpio_direction(struct gpio_bank *bank, int gpio,
99 int is_input)
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100100{
Tony Lindgren92105bb2005-09-07 17:20:26 +0100101 void __iomem *reg = bank->base;
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100102 u32 l;
103
Kevin Hilmanfa87931a2011-04-20 16:31:23 -0700104 reg += bank->regs->direction;
Victor Kamensky661553b2013-11-16 02:01:04 +0200105 l = readl_relaxed(reg);
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100106 if (is_input)
Javier Martinez Canillasb1e9fec2014-04-27 02:00:49 +0200107 l |= BIT(gpio);
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100108 else
Javier Martinez Canillasb1e9fec2014-04-27 02:00:49 +0200109 l &= ~(BIT(gpio));
Victor Kamensky661553b2013-11-16 02:01:04 +0200110 writel_relaxed(l, reg);
Tarun Kanti DebBarma41d87cb2011-11-15 12:52:38 +0530111 bank->context.oe = l;
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100112}
113
Kevin Hilmanfa87931a2011-04-20 16:31:23 -0700114
115/* set data out value using dedicate set/clear register */
Grygorii Strashko04ebcbd2015-03-23 14:18:24 +0200116static void omap_set_gpio_dataout_reg(struct gpio_bank *bank, unsigned offset,
Javier Martinez Canillasa0e827c2014-06-27 22:17:37 +0200117 int enable)
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100118{
Tony Lindgren92105bb2005-09-07 17:20:26 +0100119 void __iomem *reg = bank->base;
Grygorii Strashko04ebcbd2015-03-23 14:18:24 +0200120 u32 l = BIT(offset);
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100121
Tarun Kanti DebBarma2c836f72012-03-02 12:52:52 +0530122 if (enable) {
Kevin Hilmanfa87931a2011-04-20 16:31:23 -0700123 reg += bank->regs->set_dataout;
Tarun Kanti DebBarma2c836f72012-03-02 12:52:52 +0530124 bank->context.dataout |= l;
125 } else {
Kevin Hilmanfa87931a2011-04-20 16:31:23 -0700126 reg += bank->regs->clr_dataout;
Tarun Kanti DebBarma2c836f72012-03-02 12:52:52 +0530127 bank->context.dataout &= ~l;
128 }
Kevin Hilmanfa87931a2011-04-20 16:31:23 -0700129
Victor Kamensky661553b2013-11-16 02:01:04 +0200130 writel_relaxed(l, reg);
Kevin Hilmanfa87931a2011-04-20 16:31:23 -0700131}
132
133/* set data out value using mask register */
Grygorii Strashko04ebcbd2015-03-23 14:18:24 +0200134static void omap_set_gpio_dataout_mask(struct gpio_bank *bank, unsigned offset,
Javier Martinez Canillasa0e827c2014-06-27 22:17:37 +0200135 int enable)
Kevin Hilmanfa87931a2011-04-20 16:31:23 -0700136{
137 void __iomem *reg = bank->base + bank->regs->dataout;
Grygorii Strashko04ebcbd2015-03-23 14:18:24 +0200138 u32 gpio_bit = BIT(offset);
Kevin Hilmanfa87931a2011-04-20 16:31:23 -0700139 u32 l;
140
Victor Kamensky661553b2013-11-16 02:01:04 +0200141 l = readl_relaxed(reg);
Kevin Hilmanfa87931a2011-04-20 16:31:23 -0700142 if (enable)
143 l |= gpio_bit;
144 else
145 l &= ~gpio_bit;
Victor Kamensky661553b2013-11-16 02:01:04 +0200146 writel_relaxed(l, reg);
Tarun Kanti DebBarma41d87cb2011-11-15 12:52:38 +0530147 bank->context.dataout = l;
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100148}
149
Javier Martinez Canillasa0e827c2014-06-27 22:17:37 +0200150static int omap_get_gpio_datain(struct gpio_bank *bank, int offset)
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100151{
Kevin Hilmanfa87931a2011-04-20 16:31:23 -0700152 void __iomem *reg = bank->base + bank->regs->datain;
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100153
Javier Martinez Canillasb1e9fec2014-04-27 02:00:49 +0200154 return (readl_relaxed(reg) & (BIT(offset))) != 0;
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100155}
156
Javier Martinez Canillasa0e827c2014-06-27 22:17:37 +0200157static int omap_get_gpio_dataout(struct gpio_bank *bank, int offset)
Roger Quadrosb37c45b2009-08-05 16:53:24 +0300158{
Kevin Hilmanfa87931a2011-04-20 16:31:23 -0700159 void __iomem *reg = bank->base + bank->regs->dataout;
Roger Quadrosb37c45b2009-08-05 16:53:24 +0300160
Javier Martinez Canillasb1e9fec2014-04-27 02:00:49 +0200161 return (readl_relaxed(reg) & (BIT(offset))) != 0;
Roger Quadrosb37c45b2009-08-05 16:53:24 +0300162}
163
Javier Martinez Canillasa0e827c2014-06-27 22:17:37 +0200164static inline void omap_gpio_rmw(void __iomem *base, u32 reg, u32 mask, bool set)
Kevin Hilmanece95282011-07-12 08:18:15 -0700165{
Victor Kamensky661553b2013-11-16 02:01:04 +0200166 int l = readl_relaxed(base + reg);
Kevin Hilmanece95282011-07-12 08:18:15 -0700167
Benoit Cousson862ff642012-02-01 15:58:56 +0100168 if (set)
Kevin Hilmanece95282011-07-12 08:18:15 -0700169 l |= mask;
170 else
171 l &= ~mask;
172
Victor Kamensky661553b2013-11-16 02:01:04 +0200173 writel_relaxed(l, base + reg);
Kevin Hilmanece95282011-07-12 08:18:15 -0700174}
Tony Lindgren92105bb2005-09-07 17:20:26 +0100175
Javier Martinez Canillasa0e827c2014-06-27 22:17:37 +0200176static inline void omap_gpio_dbck_enable(struct gpio_bank *bank)
Tarun Kanti DebBarma72f83af92011-11-24 03:03:28 +0530177{
178 if (bank->dbck_enable_mask && !bank->dbck_enabled) {
Grygorii Strashko5d9452e2015-08-18 14:10:56 +0300179 clk_enable(bank->dbck);
Tarun Kanti DebBarma72f83af92011-11-24 03:03:28 +0530180 bank->dbck_enabled = true;
Grazvydas Ignotas9e303f22012-06-16 22:01:25 +0300181
Victor Kamensky661553b2013-11-16 02:01:04 +0200182 writel_relaxed(bank->dbck_enable_mask,
Grazvydas Ignotas9e303f22012-06-16 22:01:25 +0300183 bank->base + bank->regs->debounce_en);
Tarun Kanti DebBarma72f83af92011-11-24 03:03:28 +0530184 }
185}
186
Javier Martinez Canillasa0e827c2014-06-27 22:17:37 +0200187static inline void omap_gpio_dbck_disable(struct gpio_bank *bank)
Tarun Kanti DebBarma72f83af92011-11-24 03:03:28 +0530188{
189 if (bank->dbck_enable_mask && bank->dbck_enabled) {
Grazvydas Ignotas9e303f22012-06-16 22:01:25 +0300190 /*
191 * Disable debounce before cutting it's clock. If debounce is
192 * enabled but the clock is not, GPIO module seems to be unable
193 * to detect events and generate interrupts at least on OMAP3.
194 */
Victor Kamensky661553b2013-11-16 02:01:04 +0200195 writel_relaxed(0, bank->base + bank->regs->debounce_en);
Grazvydas Ignotas9e303f22012-06-16 22:01:25 +0300196
Grygorii Strashko5d9452e2015-08-18 14:10:56 +0300197 clk_disable(bank->dbck);
Tarun Kanti DebBarma72f83af92011-11-24 03:03:28 +0530198 bank->dbck_enabled = false;
199 }
200}
201
Felipe Balbi168ef3d2010-05-26 14:42:23 -0700202/**
Javier Martinez Canillasa0e827c2014-06-27 22:17:37 +0200203 * omap2_set_gpio_debounce - low level gpio debounce time
Felipe Balbi168ef3d2010-05-26 14:42:23 -0700204 * @bank: the gpio bank we're acting upon
Grygorii Strashko4a58d222015-03-23 14:18:25 +0200205 * @offset: the gpio number on this @bank
Felipe Balbi168ef3d2010-05-26 14:42:23 -0700206 * @debounce: debounce time to use
207 *
Grygorii Strashkoe85ec6c2015-08-18 14:10:54 +0300208 * OMAP's debounce time is in 31us steps
209 * <debounce time> = (GPIO_DEBOUNCINGTIME[7:0].DEBOUNCETIME + 1) x 31
210 * so we need to convert and round up to the closest unit.
David Rivshin198ab402017-04-24 18:56:50 -0400211 *
212 * Return: 0 on success, negative error otherwise.
Felipe Balbi168ef3d2010-05-26 14:42:23 -0700213 */
David Rivshin198ab402017-04-24 18:56:50 -0400214static int omap2_set_gpio_debounce(struct gpio_bank *bank, unsigned offset,
215 unsigned debounce)
Felipe Balbi168ef3d2010-05-26 14:42:23 -0700216{
Kevin Hilman9942da02011-04-22 12:02:05 -0700217 void __iomem *reg;
Felipe Balbi168ef3d2010-05-26 14:42:23 -0700218 u32 val;
219 u32 l;
Grygorii Strashkoe85ec6c2015-08-18 14:10:54 +0300220 bool enable = !!debounce;
Felipe Balbi168ef3d2010-05-26 14:42:23 -0700221
Varadarajan, Charulatha77640aa2010-12-07 16:26:57 -0800222 if (!bank->dbck_flag)
David Rivshin198ab402017-04-24 18:56:50 -0400223 return -ENOTSUPP;
Varadarajan, Charulatha77640aa2010-12-07 16:26:57 -0800224
Grygorii Strashkoe85ec6c2015-08-18 14:10:54 +0300225 if (enable) {
226 debounce = DIV_ROUND_UP(debounce, 31) - 1;
David Rivshin198ab402017-04-24 18:56:50 -0400227 if ((debounce & OMAP4_GPIO_DEBOUNCINGTIME_MASK) != debounce)
228 return -EINVAL;
Grygorii Strashkoe85ec6c2015-08-18 14:10:54 +0300229 }
Felipe Balbi168ef3d2010-05-26 14:42:23 -0700230
Grygorii Strashko4a58d222015-03-23 14:18:25 +0200231 l = BIT(offset);
Felipe Balbi168ef3d2010-05-26 14:42:23 -0700232
Grygorii Strashko5d9452e2015-08-18 14:10:56 +0300233 clk_enable(bank->dbck);
Kevin Hilman9942da02011-04-22 12:02:05 -0700234 reg = bank->base + bank->regs->debounce;
Victor Kamensky661553b2013-11-16 02:01:04 +0200235 writel_relaxed(debounce, reg);
Felipe Balbi168ef3d2010-05-26 14:42:23 -0700236
Kevin Hilman9942da02011-04-22 12:02:05 -0700237 reg = bank->base + bank->regs->debounce_en;
Victor Kamensky661553b2013-11-16 02:01:04 +0200238 val = readl_relaxed(reg);
Felipe Balbi168ef3d2010-05-26 14:42:23 -0700239
Grygorii Strashkoe85ec6c2015-08-18 14:10:54 +0300240 if (enable)
Felipe Balbi168ef3d2010-05-26 14:42:23 -0700241 val |= l;
Tarun Kanti DebBarma6fd9c422011-11-24 03:58:54 +0530242 else
Felipe Balbi168ef3d2010-05-26 14:42:23 -0700243 val &= ~l;
Kevin Hilmanf7ec0b02010-06-09 13:53:07 +0300244 bank->dbck_enable_mask = val;
Felipe Balbi168ef3d2010-05-26 14:42:23 -0700245
Victor Kamensky661553b2013-11-16 02:01:04 +0200246 writel_relaxed(val, reg);
Grygorii Strashko5d9452e2015-08-18 14:10:56 +0300247 clk_disable(bank->dbck);
Tarun Kanti DebBarma6fd9c422011-11-24 03:58:54 +0530248 /*
249 * Enable debounce clock per module.
250 * This call is mandatory because in omap_gpio_request() when
251 * *_runtime_get_sync() is called, _gpio_dbck_enable() within
252 * runtime callbck fails to turn on dbck because dbck_enable_mask
253 * used within _gpio_dbck_enable() is still not initialized at
254 * that point. Therefore we have to enable dbck here.
255 */
Javier Martinez Canillasa0e827c2014-06-27 22:17:37 +0200256 omap_gpio_dbck_enable(bank);
Nishanth Menonae547352011-09-09 19:08:58 +0530257 if (bank->dbck_enable_mask) {
258 bank->context.debounce = debounce;
259 bank->context.debounce_en = val;
260 }
David Rivshin198ab402017-04-24 18:56:50 -0400261
262 return 0;
Felipe Balbi168ef3d2010-05-26 14:42:23 -0700263}
264
Jon Hunterc9c55d92012-10-26 14:26:04 -0500265/**
Javier Martinez Canillasa0e827c2014-06-27 22:17:37 +0200266 * omap_clear_gpio_debounce - clear debounce settings for a gpio
Jon Hunterc9c55d92012-10-26 14:26:04 -0500267 * @bank: the gpio bank we're acting upon
Grygorii Strashko4a58d222015-03-23 14:18:25 +0200268 * @offset: the gpio number on this @bank
Jon Hunterc9c55d92012-10-26 14:26:04 -0500269 *
270 * If a gpio is using debounce, then clear the debounce enable bit and if
271 * this is the only gpio in this bank using debounce, then clear the debounce
272 * time too. The debounce clock will also be disabled when calling this function
273 * if this is the only gpio in the bank using debounce.
274 */
Grygorii Strashko4a58d222015-03-23 14:18:25 +0200275static void omap_clear_gpio_debounce(struct gpio_bank *bank, unsigned offset)
Jon Hunterc9c55d92012-10-26 14:26:04 -0500276{
Grygorii Strashko4a58d222015-03-23 14:18:25 +0200277 u32 gpio_bit = BIT(offset);
Jon Hunterc9c55d92012-10-26 14:26:04 -0500278
279 if (!bank->dbck_flag)
280 return;
281
282 if (!(bank->dbck_enable_mask & gpio_bit))
283 return;
284
285 bank->dbck_enable_mask &= ~gpio_bit;
286 bank->context.debounce_en &= ~gpio_bit;
Victor Kamensky661553b2013-11-16 02:01:04 +0200287 writel_relaxed(bank->context.debounce_en,
Jon Hunterc9c55d92012-10-26 14:26:04 -0500288 bank->base + bank->regs->debounce_en);
289
290 if (!bank->dbck_enable_mask) {
291 bank->context.debounce = 0;
Victor Kamensky661553b2013-11-16 02:01:04 +0200292 writel_relaxed(bank->context.debounce, bank->base +
Jon Hunterc9c55d92012-10-26 14:26:04 -0500293 bank->regs->debounce);
Grygorii Strashko5d9452e2015-08-18 14:10:56 +0300294 clk_disable(bank->dbck);
Jon Hunterc9c55d92012-10-26 14:26:04 -0500295 bank->dbck_enabled = false;
296 }
297}
298
Javier Martinez Canillasa0e827c2014-06-27 22:17:37 +0200299static inline void omap_set_gpio_trigger(struct gpio_bank *bank, int gpio,
Tarun Kanti DebBarma00ece7e2011-11-25 15:41:06 +0530300 unsigned trigger)
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100301{
Juha Yrjola3ac4fa92006-12-06 17:13:52 -0800302 void __iomem *base = bank->base;
Javier Martinez Canillasb1e9fec2014-04-27 02:00:49 +0200303 u32 gpio_bit = BIT(gpio);
Tony Lindgren92105bb2005-09-07 17:20:26 +0100304
Javier Martinez Canillasa0e827c2014-06-27 22:17:37 +0200305 omap_gpio_rmw(base, bank->regs->leveldetect0, gpio_bit,
306 trigger & IRQ_TYPE_LEVEL_LOW);
307 omap_gpio_rmw(base, bank->regs->leveldetect1, gpio_bit,
308 trigger & IRQ_TYPE_LEVEL_HIGH);
309 omap_gpio_rmw(base, bank->regs->risingdetect, gpio_bit,
310 trigger & IRQ_TYPE_EDGE_RISING);
311 omap_gpio_rmw(base, bank->regs->fallingdetect, gpio_bit,
312 trigger & IRQ_TYPE_EDGE_FALLING);
Tarun Kanti DebBarma5e571f32011-09-13 15:02:14 +0530313
Tarun Kanti DebBarma41d87cb2011-11-15 12:52:38 +0530314 bank->context.leveldetect0 =
Victor Kamensky661553b2013-11-16 02:01:04 +0200315 readl_relaxed(bank->base + bank->regs->leveldetect0);
Tarun Kanti DebBarma41d87cb2011-11-15 12:52:38 +0530316 bank->context.leveldetect1 =
Victor Kamensky661553b2013-11-16 02:01:04 +0200317 readl_relaxed(bank->base + bank->regs->leveldetect1);
Tarun Kanti DebBarma41d87cb2011-11-15 12:52:38 +0530318 bank->context.risingdetect =
Victor Kamensky661553b2013-11-16 02:01:04 +0200319 readl_relaxed(bank->base + bank->regs->risingdetect);
Tarun Kanti DebBarma41d87cb2011-11-15 12:52:38 +0530320 bank->context.fallingdetect =
Victor Kamensky661553b2013-11-16 02:01:04 +0200321 readl_relaxed(bank->base + bank->regs->fallingdetect);
Tarun Kanti DebBarma41d87cb2011-11-15 12:52:38 +0530322
323 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
Javier Martinez Canillasa0e827c2014-06-27 22:17:37 +0200324 omap_gpio_rmw(base, bank->regs->wkup_en, gpio_bit, trigger != 0);
Tarun Kanti DebBarma41d87cb2011-11-15 12:52:38 +0530325 bank->context.wake_en =
Victor Kamensky661553b2013-11-16 02:01:04 +0200326 readl_relaxed(bank->base + bank->regs->wkup_en);
Tarun Kanti DebBarma41d87cb2011-11-15 12:52:38 +0530327 }
Tarun Kanti DebBarma5e571f32011-09-13 15:02:14 +0530328
Ambresh K55b220c2011-06-15 13:40:45 -0700329 /* This part needs to be executed always for OMAP{34xx, 44xx} */
Tarun Kanti DebBarma5e571f32011-09-13 15:02:14 +0530330 if (!bank->regs->irqctrl) {
331 /* On omap24xx proceed only when valid GPIO bit is set */
332 if (bank->non_wakeup_gpios) {
333 if (!(bank->non_wakeup_gpios & gpio_bit))
334 goto exit;
335 }
336
Chunqiu Wang699117a62009-06-24 17:13:39 +0000337 /*
338 * Log the edge gpio and manually trigger the IRQ
339 * after resume if the input level changes
340 * to avoid irq lost during PER RET/OFF mode
341 * Applies for omap2 non-wakeup gpio and all omap3 gpios
342 */
343 if (trigger & IRQ_TYPE_EDGE_BOTH)
Juha Yrjola3ac4fa92006-12-06 17:13:52 -0800344 bank->enabled_non_wakeup_gpios |= gpio_bit;
345 else
346 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
347 }
Kevin Hilman5eb3bb92007-05-05 11:40:29 -0700348
Tarun Kanti DebBarma5e571f32011-09-13 15:02:14 +0530349exit:
Tarun Kanti DebBarma9ea14d82011-08-30 15:05:44 +0530350 bank->level_mask =
Victor Kamensky661553b2013-11-16 02:01:04 +0200351 readl_relaxed(bank->base + bank->regs->leveldetect0) |
352 readl_relaxed(bank->base + bank->regs->leveldetect1);
Tony Lindgren92105bb2005-09-07 17:20:26 +0100353}
354
Uwe Kleine-König9198bcd2010-01-29 14:20:05 -0800355#ifdef CONFIG_ARCH_OMAP1
Cory Maccarrone4318f362010-01-08 10:29:04 -0800356/*
357 * This only applies to chips that can't do both rising and falling edge
358 * detection at once. For all other chips, this function is a noop.
359 */
Javier Martinez Canillasa0e827c2014-06-27 22:17:37 +0200360static void omap_toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
Cory Maccarrone4318f362010-01-08 10:29:04 -0800361{
362 void __iomem *reg = bank->base;
363 u32 l = 0;
364
Tarun Kanti DebBarma5e571f32011-09-13 15:02:14 +0530365 if (!bank->regs->irqctrl)
Cory Maccarrone4318f362010-01-08 10:29:04 -0800366 return;
Tarun Kanti DebBarma5e571f32011-09-13 15:02:14 +0530367
368 reg += bank->regs->irqctrl;
Cory Maccarrone4318f362010-01-08 10:29:04 -0800369
Victor Kamensky661553b2013-11-16 02:01:04 +0200370 l = readl_relaxed(reg);
Cory Maccarrone4318f362010-01-08 10:29:04 -0800371 if ((l >> gpio) & 1)
Javier Martinez Canillasb1e9fec2014-04-27 02:00:49 +0200372 l &= ~(BIT(gpio));
Cory Maccarrone4318f362010-01-08 10:29:04 -0800373 else
Javier Martinez Canillasb1e9fec2014-04-27 02:00:49 +0200374 l |= BIT(gpio);
Cory Maccarrone4318f362010-01-08 10:29:04 -0800375
Victor Kamensky661553b2013-11-16 02:01:04 +0200376 writel_relaxed(l, reg);
Cory Maccarrone4318f362010-01-08 10:29:04 -0800377}
Tarun Kanti DebBarma5e571f32011-09-13 15:02:14 +0530378#else
Javier Martinez Canillasa0e827c2014-06-27 22:17:37 +0200379static void omap_toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) {}
Uwe Kleine-König9198bcd2010-01-29 14:20:05 -0800380#endif
Cory Maccarrone4318f362010-01-08 10:29:04 -0800381
Javier Martinez Canillasa0e827c2014-06-27 22:17:37 +0200382static int omap_set_gpio_triggering(struct gpio_bank *bank, int gpio,
383 unsigned trigger)
Tony Lindgren92105bb2005-09-07 17:20:26 +0100384{
385 void __iomem *reg = bank->base;
Tarun Kanti DebBarma5e571f32011-09-13 15:02:14 +0530386 void __iomem *base = bank->base;
Tony Lindgren92105bb2005-09-07 17:20:26 +0100387 u32 l = 0;
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100388
Tarun Kanti DebBarma5e571f32011-09-13 15:02:14 +0530389 if (bank->regs->leveldetect0 && bank->regs->wkup_en) {
Javier Martinez Canillasa0e827c2014-06-27 22:17:37 +0200390 omap_set_gpio_trigger(bank, gpio, trigger);
Tarun Kanti DebBarma5e571f32011-09-13 15:02:14 +0530391 } else if (bank->regs->irqctrl) {
392 reg += bank->regs->irqctrl;
393
Victor Kamensky661553b2013-11-16 02:01:04 +0200394 l = readl_relaxed(reg);
Janusz Krzysztofik29501572010-04-05 11:38:06 +0000395 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
Javier Martinez Canillasb1e9fec2014-04-27 02:00:49 +0200396 bank->toggle_mask |= BIT(gpio);
Dmitry Baryshkov6cab4862008-07-27 04:23:31 +0100397 if (trigger & IRQ_TYPE_EDGE_RISING)
Javier Martinez Canillasb1e9fec2014-04-27 02:00:49 +0200398 l |= BIT(gpio);
Dmitry Baryshkov6cab4862008-07-27 04:23:31 +0100399 else if (trigger & IRQ_TYPE_EDGE_FALLING)
Javier Martinez Canillasb1e9fec2014-04-27 02:00:49 +0200400 l &= ~(BIT(gpio));
Tony Lindgren92105bb2005-09-07 17:20:26 +0100401 else
Tarun Kanti DebBarma5e571f32011-09-13 15:02:14 +0530402 return -EINVAL;
403
Victor Kamensky661553b2013-11-16 02:01:04 +0200404 writel_relaxed(l, reg);
Tarun Kanti DebBarma5e571f32011-09-13 15:02:14 +0530405 } else if (bank->regs->edgectrl1) {
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100406 if (gpio & 0x08)
Tarun Kanti DebBarma5e571f32011-09-13 15:02:14 +0530407 reg += bank->regs->edgectrl2;
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100408 else
Tarun Kanti DebBarma5e571f32011-09-13 15:02:14 +0530409 reg += bank->regs->edgectrl1;
410
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100411 gpio &= 0x07;
Victor Kamensky661553b2013-11-16 02:01:04 +0200412 l = readl_relaxed(reg);
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100413 l &= ~(3 << (gpio << 1));
Dmitry Baryshkov6cab4862008-07-27 04:23:31 +0100414 if (trigger & IRQ_TYPE_EDGE_RISING)
Tony Lindgren6e60e792006-04-02 17:46:23 +0100415 l |= 2 << (gpio << 1);
Dmitry Baryshkov6cab4862008-07-27 04:23:31 +0100416 if (trigger & IRQ_TYPE_EDGE_FALLING)
Javier Martinez Canillasb1e9fec2014-04-27 02:00:49 +0200417 l |= BIT(gpio << 1);
Tarun Kanti DebBarma5e571f32011-09-13 15:02:14 +0530418
419 /* Enable wake-up during idle for dynamic tick */
Javier Martinez Canillasa0e827c2014-06-27 22:17:37 +0200420 omap_gpio_rmw(base, bank->regs->wkup_en, BIT(gpio), trigger);
Tarun Kanti DebBarma41d87cb2011-11-15 12:52:38 +0530421 bank->context.wake_en =
Victor Kamensky661553b2013-11-16 02:01:04 +0200422 readl_relaxed(bank->base + bank->regs->wkup_en);
423 writel_relaxed(l, reg);
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100424 }
Tony Lindgren92105bb2005-09-07 17:20:26 +0100425 return 0;
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100426}
427
Javier Martinez Canillasa0e827c2014-06-27 22:17:37 +0200428static void omap_enable_gpio_module(struct gpio_bank *bank, unsigned offset)
Javier Martinez Canillasfac7fa12013-09-25 02:36:54 +0200429{
430 if (bank->regs->pinctrl) {
431 void __iomem *reg = bank->base + bank->regs->pinctrl;
432
433 /* Claim the pin for MPU */
Javier Martinez Canillasb1e9fec2014-04-27 02:00:49 +0200434 writel_relaxed(readl_relaxed(reg) | (BIT(offset)), reg);
Javier Martinez Canillasfac7fa12013-09-25 02:36:54 +0200435 }
436
437 if (bank->regs->ctrl && !BANK_USED(bank)) {
438 void __iomem *reg = bank->base + bank->regs->ctrl;
439 u32 ctrl;
440
Victor Kamensky661553b2013-11-16 02:01:04 +0200441 ctrl = readl_relaxed(reg);
Javier Martinez Canillasfac7fa12013-09-25 02:36:54 +0200442 /* Module is enabled, clocks are not gated */
443 ctrl &= ~GPIO_MOD_CTRL_BIT;
Victor Kamensky661553b2013-11-16 02:01:04 +0200444 writel_relaxed(ctrl, reg);
Javier Martinez Canillasfac7fa12013-09-25 02:36:54 +0200445 bank->context.ctrl = ctrl;
446 }
447}
448
Javier Martinez Canillasa0e827c2014-06-27 22:17:37 +0200449static void omap_disable_gpio_module(struct gpio_bank *bank, unsigned offset)
Javier Martinez Canillasfac7fa12013-09-25 02:36:54 +0200450{
451 void __iomem *base = bank->base;
452
453 if (bank->regs->wkup_en &&
454 !LINE_USED(bank->mod_usage, offset) &&
455 !LINE_USED(bank->irq_usage, offset)) {
456 /* Disable wake-up during idle for dynamic tick */
Javier Martinez Canillasa0e827c2014-06-27 22:17:37 +0200457 omap_gpio_rmw(base, bank->regs->wkup_en, BIT(offset), 0);
Javier Martinez Canillasfac7fa12013-09-25 02:36:54 +0200458 bank->context.wake_en =
Victor Kamensky661553b2013-11-16 02:01:04 +0200459 readl_relaxed(bank->base + bank->regs->wkup_en);
Javier Martinez Canillasfac7fa12013-09-25 02:36:54 +0200460 }
461
462 if (bank->regs->ctrl && !BANK_USED(bank)) {
463 void __iomem *reg = bank->base + bank->regs->ctrl;
464 u32 ctrl;
465
Victor Kamensky661553b2013-11-16 02:01:04 +0200466 ctrl = readl_relaxed(reg);
Javier Martinez Canillasfac7fa12013-09-25 02:36:54 +0200467 /* Module is disabled, clocks are gated */
468 ctrl |= GPIO_MOD_CTRL_BIT;
Victor Kamensky661553b2013-11-16 02:01:04 +0200469 writel_relaxed(ctrl, reg);
Javier Martinez Canillasfac7fa12013-09-25 02:36:54 +0200470 bank->context.ctrl = ctrl;
471 }
472}
473
Grygorii Strashkob2b20042015-03-23 14:18:23 +0200474static int omap_gpio_is_input(struct gpio_bank *bank, unsigned offset)
Javier Martinez Canillasfa365e42013-09-25 02:36:52 +0200475{
476 void __iomem *reg = bank->base + bank->regs->direction;
477
Grygorii Strashkob2b20042015-03-23 14:18:23 +0200478 return readl_relaxed(reg) & BIT(offset);
Javier Martinez Canillasfa365e42013-09-25 02:36:52 +0200479}
480
Grygorii Strashko37e14ec2015-03-23 14:18:26 +0200481static void omap_gpio_init_irq(struct gpio_bank *bank, unsigned offset)
Tony Lindgren3d009c82015-01-16 14:50:50 -0800482{
483 if (!LINE_USED(bank->mod_usage, offset)) {
484 omap_enable_gpio_module(bank, offset);
485 omap_set_gpio_direction(bank, offset, 1);
486 }
Grygorii Strashko37e14ec2015-03-23 14:18:26 +0200487 bank->irq_usage |= BIT(offset);
Tony Lindgren3d009c82015-01-16 14:50:50 -0800488}
489
Javier Martinez Canillasa0e827c2014-06-27 22:17:37 +0200490static int omap_gpio_irq_type(struct irq_data *d, unsigned type)
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100491{
Javier Martinez Canillasa0e827c2014-06-27 22:17:37 +0200492 struct gpio_bank *bank = omap_irq_data_get_bank(d);
Tony Lindgren92105bb2005-09-07 17:20:26 +0100493 int retval;
David Brownella6472532008-03-03 04:33:30 -0800494 unsigned long flags;
Grygorii Strashkoea5fbe82015-03-23 14:18:29 +0200495 unsigned offset = d->hwirq;
Tony Lindgren92105bb2005-09-07 17:20:26 +0100496
David Brownelle5c56ed2006-12-06 17:13:59 -0800497 if (type & ~IRQ_TYPE_SENSE_MASK)
Tony Lindgren6e60e792006-04-02 17:46:23 +0100498 return -EINVAL;
David Brownelle5c56ed2006-12-06 17:13:59 -0800499
Tarun Kanti DebBarma9ea14d82011-08-30 15:05:44 +0530500 if (!bank->regs->leveldetect0 &&
501 (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
Tony Lindgren92105bb2005-09-07 17:20:26 +0100502 return -EINVAL;
503
Sebastian Andrzej Siewior4dbada22015-07-21 18:26:51 +0200504 raw_spin_lock_irqsave(&bank->lock, flags);
Javier Martinez Canillasa0e827c2014-06-27 22:17:37 +0200505 retval = omap_set_gpio_triggering(bank, offset, type);
Grygorii Strashko977bd8a2015-06-24 17:54:17 +0300506 if (retval) {
Axel Lin627c89b2015-08-05 22:37:41 +0800507 raw_spin_unlock_irqrestore(&bank->lock, flags);
Grygorii Strashko1562e462015-05-22 17:35:49 +0300508 goto error;
Grygorii Strashko977bd8a2015-06-24 17:54:17 +0300509 }
Grygorii Strashko37e14ec2015-03-23 14:18:26 +0200510 omap_gpio_init_irq(bank, offset);
Grygorii Strashkob2b20042015-03-23 14:18:23 +0200511 if (!omap_gpio_is_input(bank, offset)) {
Sebastian Andrzej Siewior4dbada22015-07-21 18:26:51 +0200512 raw_spin_unlock_irqrestore(&bank->lock, flags);
Grygorii Strashko1562e462015-05-22 17:35:49 +0300513 retval = -EINVAL;
514 goto error;
Javier Martinez Canillasfac7fa12013-09-25 02:36:54 +0200515 }
Sebastian Andrzej Siewior4dbada22015-07-21 18:26:51 +0200516 raw_spin_unlock_irqrestore(&bank->lock, flags);
Kevin Hilman672e3022008-01-16 21:56:16 -0800517
518 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
Thomas Gleixner43ec2e42015-06-23 15:52:39 +0200519 irq_set_handler_locked(d, handle_level_irq);
Kevin Hilman672e3022008-01-16 21:56:16 -0800520 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
Thomas Gleixner43ec2e42015-06-23 15:52:39 +0200521 irq_set_handler_locked(d, handle_edge_irq);
Kevin Hilman672e3022008-01-16 21:56:16 -0800522
Grygorii Strashko1562e462015-05-22 17:35:49 +0300523 return 0;
524
525error:
Tony Lindgren92105bb2005-09-07 17:20:26 +0100526 return retval;
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100527}
528
Javier Martinez Canillasa0e827c2014-06-27 22:17:37 +0200529static void omap_clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100530{
Tony Lindgren92105bb2005-09-07 17:20:26 +0100531 void __iomem *reg = bank->base;
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100532
Kevin Hilmaneef4bec2011-04-21 09:17:35 -0700533 reg += bank->regs->irqstatus;
Victor Kamensky661553b2013-11-16 02:01:04 +0200534 writel_relaxed(gpio_mask, reg);
Hiroshi DOYUbee79302006-09-25 12:41:46 +0300535
536 /* Workaround for clearing DSP GPIO interrupts to allow retention */
Kevin Hilmaneef4bec2011-04-21 09:17:35 -0700537 if (bank->regs->irqstatus2) {
538 reg = bank->base + bank->regs->irqstatus2;
Victor Kamensky661553b2013-11-16 02:01:04 +0200539 writel_relaxed(gpio_mask, reg);
Kevin Hilmaneef4bec2011-04-21 09:17:35 -0700540 }
Roger Quadrosbedfd152009-04-23 11:10:50 -0700541
542 /* Flush posted write for the irq status to avoid spurious interrupts */
Victor Kamensky661553b2013-11-16 02:01:04 +0200543 readl_relaxed(reg);
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100544}
545
Grygorii Strashko9943f262015-03-23 14:18:27 +0200546static inline void omap_clear_gpio_irqstatus(struct gpio_bank *bank,
547 unsigned offset)
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100548{
Grygorii Strashko9943f262015-03-23 14:18:27 +0200549 omap_clear_gpio_irqbank(bank, BIT(offset));
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100550}
551
Javier Martinez Canillasa0e827c2014-06-27 22:17:37 +0200552static u32 omap_get_gpio_irqbank_mask(struct gpio_bank *bank)
Imre Deakea6dedd2006-06-26 16:16:00 -0700553{
554 void __iomem *reg = bank->base;
Imre Deak99c47702006-06-26 16:16:07 -0700555 u32 l;
Javier Martinez Canillasb1e9fec2014-04-27 02:00:49 +0200556 u32 mask = (BIT(bank->width)) - 1;
Imre Deakea6dedd2006-06-26 16:16:00 -0700557
Kevin Hilman28f3b5a2011-04-21 09:53:06 -0700558 reg += bank->regs->irqenable;
Victor Kamensky661553b2013-11-16 02:01:04 +0200559 l = readl_relaxed(reg);
Kevin Hilman28f3b5a2011-04-21 09:53:06 -0700560 if (bank->regs->irqenable_inv)
Imre Deak99c47702006-06-26 16:16:07 -0700561 l = ~l;
562 l &= mask;
563 return l;
Imre Deakea6dedd2006-06-26 16:16:00 -0700564}
565
Javier Martinez Canillasa0e827c2014-06-27 22:17:37 +0200566static void omap_enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100567{
Tony Lindgren92105bb2005-09-07 17:20:26 +0100568 void __iomem *reg = bank->base;
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100569 u32 l;
570
Kevin Hilman28f3b5a2011-04-21 09:53:06 -0700571 if (bank->regs->set_irqenable) {
572 reg += bank->regs->set_irqenable;
573 l = gpio_mask;
Tarun Kanti DebBarma2a900eb2012-03-06 12:08:16 +0530574 bank->context.irqenable1 |= gpio_mask;
Kevin Hilman28f3b5a2011-04-21 09:53:06 -0700575 } else {
576 reg += bank->regs->irqenable;
Victor Kamensky661553b2013-11-16 02:01:04 +0200577 l = readl_relaxed(reg);
Kevin Hilman28f3b5a2011-04-21 09:53:06 -0700578 if (bank->regs->irqenable_inv)
579 l &= ~gpio_mask;
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100580 else
581 l |= gpio_mask;
Tarun Kanti DebBarma2a900eb2012-03-06 12:08:16 +0530582 bank->context.irqenable1 = l;
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100583 }
Kevin Hilman28f3b5a2011-04-21 09:53:06 -0700584
Victor Kamensky661553b2013-11-16 02:01:04 +0200585 writel_relaxed(l, reg);
Kevin Hilman28f3b5a2011-04-21 09:53:06 -0700586}
587
Javier Martinez Canillasa0e827c2014-06-27 22:17:37 +0200588static void omap_disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
Kevin Hilman28f3b5a2011-04-21 09:53:06 -0700589{
590 void __iomem *reg = bank->base;
591 u32 l;
592
593 if (bank->regs->clr_irqenable) {
594 reg += bank->regs->clr_irqenable;
595 l = gpio_mask;
Tarun Kanti DebBarma2a900eb2012-03-06 12:08:16 +0530596 bank->context.irqenable1 &= ~gpio_mask;
Kevin Hilman28f3b5a2011-04-21 09:53:06 -0700597 } else {
598 reg += bank->regs->irqenable;
Victor Kamensky661553b2013-11-16 02:01:04 +0200599 l = readl_relaxed(reg);
Kevin Hilman28f3b5a2011-04-21 09:53:06 -0700600 if (bank->regs->irqenable_inv)
601 l |= gpio_mask;
602 else
603 l &= ~gpio_mask;
Tarun Kanti DebBarma2a900eb2012-03-06 12:08:16 +0530604 bank->context.irqenable1 = l;
Kevin Hilman28f3b5a2011-04-21 09:53:06 -0700605 }
606
Victor Kamensky661553b2013-11-16 02:01:04 +0200607 writel_relaxed(l, reg);
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100608}
609
Grygorii Strashko9943f262015-03-23 14:18:27 +0200610static inline void omap_set_gpio_irqenable(struct gpio_bank *bank,
611 unsigned offset, int enable)
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100612{
Tarun Kanti DebBarma8276536c2011-11-25 15:27:37 +0530613 if (enable)
Grygorii Strashko9943f262015-03-23 14:18:27 +0200614 omap_enable_gpio_irqbank(bank, BIT(offset));
Tarun Kanti DebBarma8276536c2011-11-25 15:27:37 +0530615 else
Grygorii Strashko9943f262015-03-23 14:18:27 +0200616 omap_disable_gpio_irqbank(bank, BIT(offset));
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100617}
618
Tony Lindgren92105bb2005-09-07 17:20:26 +0100619/* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
Javier Martinez Canillasa0e827c2014-06-27 22:17:37 +0200620static int omap_gpio_wake_enable(struct irq_data *d, unsigned int enable)
Tony Lindgren92105bb2005-09-07 17:20:26 +0100621{
Javier Martinez Canillasa0e827c2014-06-27 22:17:37 +0200622 struct gpio_bank *bank = omap_irq_data_get_bank(d);
Tony Lindgren92105bb2005-09-07 17:20:26 +0100623
Grygorii Strashko0c0451e2016-04-12 13:52:31 +0300624 return irq_set_irq_wake(bank->irq, enable);
Tony Lindgren92105bb2005-09-07 17:20:26 +0100625}
626
Jarkko Nikula3ff164e2008-12-10 17:35:27 -0800627static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100628{
Linus Walleijd99f7ae2015-12-07 11:16:00 +0100629 struct gpio_bank *bank = gpiochip_get_data(chip);
David Brownella6472532008-03-03 04:33:30 -0800630 unsigned long flags;
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100631
Tarun Kanti DebBarma55b93c32011-09-29 07:23:22 +0530632 /*
633 * If this is the first gpio_request for the bank,
634 * enable the bank module.
635 */
Javier Martinez Canillasfa365e42013-09-25 02:36:52 +0200636 if (!BANK_USED(bank))
Grygorii Strashko7b1e5dc2016-03-04 17:25:35 +0200637 pm_runtime_get_sync(chip->parent);
Tony Lindgren92105bb2005-09-07 17:20:26 +0100638
Sebastian Andrzej Siewior4dbada22015-07-21 18:26:51 +0200639 raw_spin_lock_irqsave(&bank->lock, flags);
Grygorii Strashkoc3518172015-05-22 17:35:51 +0300640 omap_enable_gpio_module(bank, offset);
Javier Martinez Canillasb1e9fec2014-04-27 02:00:49 +0200641 bank->mod_usage |= BIT(offset);
Sebastian Andrzej Siewior4dbada22015-07-21 18:26:51 +0200642 raw_spin_unlock_irqrestore(&bank->lock, flags);
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100643
644 return 0;
645}
646
Jarkko Nikula3ff164e2008-12-10 17:35:27 -0800647static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100648{
Linus Walleijd99f7ae2015-12-07 11:16:00 +0100649 struct gpio_bank *bank = gpiochip_get_data(chip);
David Brownella6472532008-03-03 04:33:30 -0800650 unsigned long flags;
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100651
Sebastian Andrzej Siewior4dbada22015-07-21 18:26:51 +0200652 raw_spin_lock_irqsave(&bank->lock, flags);
Javier Martinez Canillasb1e9fec2014-04-27 02:00:49 +0200653 bank->mod_usage &= ~(BIT(offset));
Grygorii Strashko5f982c72015-05-22 17:35:48 +0300654 if (!LINE_USED(bank->irq_usage, offset)) {
655 omap_set_gpio_direction(bank, offset, 1);
656 omap_clear_gpio_debounce(bank, offset);
657 }
Javier Martinez Canillasa0e827c2014-06-27 22:17:37 +0200658 omap_disable_gpio_module(bank, offset);
Sebastian Andrzej Siewior4dbada22015-07-21 18:26:51 +0200659 raw_spin_unlock_irqrestore(&bank->lock, flags);
Tarun Kanti DebBarma55b93c32011-09-29 07:23:22 +0530660
661 /*
662 * If this is the last gpio to be freed in the bank,
663 * disable the bank module.
664 */
Javier Martinez Canillasfa365e42013-09-25 02:36:52 +0200665 if (!BANK_USED(bank))
Grygorii Strashko7b1e5dc2016-03-04 17:25:35 +0200666 pm_runtime_put(chip->parent);
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100667}
668
669/*
670 * We need to unmask the GPIO bank interrupt as soon as possible to
671 * avoid missing GPIO interrupts for other lines in the bank.
672 * Then we need to mask-read-clear-unmask the triggered GPIO lines
673 * in the bank to avoid missing nested interrupts for a GPIO line.
674 * If we wait to unmask individual GPIO lines in the bank after the
675 * line's interrupt handler has been run, we may miss some nested
676 * interrupts.
677 */
Grygorii Strashko450fa542015-09-25 12:28:03 -0700678static irqreturn_t omap_gpio_irq_handler(int irq, void *gpiobank)
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100679{
Tony Lindgren92105bb2005-09-07 17:20:26 +0100680 void __iomem *isr_reg = NULL;
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100681 u32 isr;
Jon Hunter3513cde2013-04-04 15:16:14 -0500682 unsigned int bit;
Grygorii Strashko450fa542015-09-25 12:28:03 -0700683 struct gpio_bank *bank = gpiobank;
684 unsigned long wa_lock_flags;
Grygorii Strashko235f1eb2015-08-18 14:10:55 +0300685 unsigned long lock_flags;
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100686
Kevin Hilmaneef4bec2011-04-21 09:17:35 -0700687 isr_reg = bank->base + bank->regs->irqstatus;
Evgeny Kuznetsovb1cc4c52010-12-07 16:25:40 -0800688 if (WARN_ON(!isr_reg))
689 goto exit;
690
Grygorii Strashko7b1e5dc2016-03-04 17:25:35 +0200691 pm_runtime_get_sync(bank->chip.parent);
Grygorii Strashko450fa542015-09-25 12:28:03 -0700692
Laurent Navete83507b2013-03-20 13:15:57 +0100693 while (1) {
Tony Lindgren6e60e792006-04-02 17:46:23 +0100694 u32 isr_saved, level_mask = 0;
Imre Deakea6dedd2006-06-26 16:16:00 -0700695 u32 enabled;
Tony Lindgren6e60e792006-04-02 17:46:23 +0100696
Grygorii Strashko235f1eb2015-08-18 14:10:55 +0300697 raw_spin_lock_irqsave(&bank->lock, lock_flags);
698
Javier Martinez Canillasa0e827c2014-06-27 22:17:37 +0200699 enabled = omap_get_gpio_irqbank_mask(bank);
Victor Kamensky661553b2013-11-16 02:01:04 +0200700 isr_saved = isr = readl_relaxed(isr_reg) & enabled;
Tony Lindgren6e60e792006-04-02 17:46:23 +0100701
Tarun Kanti DebBarma9ea14d82011-08-30 15:05:44 +0530702 if (bank->level_mask)
Kevin Hilmanb144ff62008-01-16 21:56:15 -0800703 level_mask = bank->level_mask & enabled;
Tony Lindgren6e60e792006-04-02 17:46:23 +0100704
705 /* clear edge sensitive interrupts before handler(s) are
706 called so that we don't miss any interrupt occurred while
707 executing them */
Javier Martinez Canillasa0e827c2014-06-27 22:17:37 +0200708 omap_disable_gpio_irqbank(bank, isr_saved & ~level_mask);
709 omap_clear_gpio_irqbank(bank, isr_saved & ~level_mask);
710 omap_enable_gpio_irqbank(bank, isr_saved & ~level_mask);
Tony Lindgren6e60e792006-04-02 17:46:23 +0100711
Grygorii Strashko235f1eb2015-08-18 14:10:55 +0300712 raw_spin_unlock_irqrestore(&bank->lock, lock_flags);
713
Tony Lindgren92105bb2005-09-07 17:20:26 +0100714 if (!isr)
715 break;
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100716
Jon Hunter3513cde2013-04-04 15:16:14 -0500717 while (isr) {
718 bit = __ffs(isr);
Javier Martinez Canillasb1e9fec2014-04-27 02:00:49 +0200719 isr &= ~(BIT(bit));
Benoit Cousson25db7112012-02-23 21:50:10 +0100720
Grygorii Strashko235f1eb2015-08-18 14:10:55 +0300721 raw_spin_lock_irqsave(&bank->lock, lock_flags);
Cory Maccarrone4318f362010-01-08 10:29:04 -0800722 /*
723 * Some chips can't respond to both rising and falling
724 * at the same time. If this irq was requested with
725 * both flags, we need to flip the ICR data for the IRQ
726 * to respond to the IRQ for the opposite direction.
727 * This will be indicated in the bank toggle_mask.
728 */
Javier Martinez Canillasb1e9fec2014-04-27 02:00:49 +0200729 if (bank->toggle_mask & (BIT(bit)))
Javier Martinez Canillasa0e827c2014-06-27 22:17:37 +0200730 omap_toggle_gpio_edge_triggering(bank, bit);
Cory Maccarrone4318f362010-01-08 10:29:04 -0800731
Grygorii Strashko235f1eb2015-08-18 14:10:55 +0300732 raw_spin_unlock_irqrestore(&bank->lock, lock_flags);
733
Grygorii Strashko450fa542015-09-25 12:28:03 -0700734 raw_spin_lock_irqsave(&bank->wa_lock, wa_lock_flags);
735
Javier Martinez Canillasfb655f52014-04-06 16:58:16 +0200736 generic_handle_irq(irq_find_mapping(bank->chip.irqdomain,
737 bit));
Grygorii Strashko450fa542015-09-25 12:28:03 -0700738
739 raw_spin_unlock_irqrestore(&bank->wa_lock,
740 wa_lock_flags);
Tony Lindgren92105bb2005-09-07 17:20:26 +0100741 }
Tony Lindgren1a8bfa12005-11-10 14:26:50 +0000742 }
Evgeny Kuznetsovb1cc4c52010-12-07 16:25:40 -0800743exit:
Grygorii Strashko7b1e5dc2016-03-04 17:25:35 +0200744 pm_runtime_put(bank->chip.parent);
Grygorii Strashko450fa542015-09-25 12:28:03 -0700745 return IRQ_HANDLED;
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100746}
747
Tony Lindgren3d009c82015-01-16 14:50:50 -0800748static unsigned int omap_gpio_irq_startup(struct irq_data *d)
749{
750 struct gpio_bank *bank = omap_irq_data_get_bank(d);
Tony Lindgren3d009c82015-01-16 14:50:50 -0800751 unsigned long flags;
Grygorii Strashko37e14ec2015-03-23 14:18:26 +0200752 unsigned offset = d->hwirq;
Tony Lindgren3d009c82015-01-16 14:50:50 -0800753
Sebastian Andrzej Siewior4dbada22015-07-21 18:26:51 +0200754 raw_spin_lock_irqsave(&bank->lock, flags);
Grygorii Strashko121dcb72015-05-22 17:35:52 +0300755
756 if (!LINE_USED(bank->mod_usage, offset))
757 omap_set_gpio_direction(bank, offset, 1);
758 else if (!omap_gpio_is_input(bank, offset))
759 goto err;
760 omap_enable_gpio_module(bank, offset);
761 bank->irq_usage |= BIT(offset);
762
Sebastian Andrzej Siewior4dbada22015-07-21 18:26:51 +0200763 raw_spin_unlock_irqrestore(&bank->lock, flags);
Tony Lindgren3d009c82015-01-16 14:50:50 -0800764 omap_gpio_unmask_irq(d);
765
766 return 0;
Grygorii Strashko121dcb72015-05-22 17:35:52 +0300767err:
Sebastian Andrzej Siewior4dbada22015-07-21 18:26:51 +0200768 raw_spin_unlock_irqrestore(&bank->lock, flags);
Grygorii Strashko121dcb72015-05-22 17:35:52 +0300769 return -EINVAL;
Tony Lindgren3d009c82015-01-16 14:50:50 -0800770}
771
Javier Martinez Canillasa0e827c2014-06-27 22:17:37 +0200772static void omap_gpio_irq_shutdown(struct irq_data *d)
Tony Lindgren4196dd62006-09-25 12:41:38 +0300773{
Javier Martinez Canillasa0e827c2014-06-27 22:17:37 +0200774 struct gpio_bank *bank = omap_irq_data_get_bank(d);
Colin Cross85ec7b92011-06-06 13:38:18 -0700775 unsigned long flags;
Grygorii Strashko9943f262015-03-23 14:18:27 +0200776 unsigned offset = d->hwirq;
Tony Lindgren4196dd62006-09-25 12:41:38 +0300777
Sebastian Andrzej Siewior4dbada22015-07-21 18:26:51 +0200778 raw_spin_lock_irqsave(&bank->lock, flags);
Javier Martinez Canillasb1e9fec2014-04-27 02:00:49 +0200779 bank->irq_usage &= ~(BIT(offset));
Grygorii Strashko6e96c1b2015-05-22 17:35:50 +0300780 omap_set_gpio_irqenable(bank, offset, 0);
781 omap_clear_gpio_irqstatus(bank, offset);
782 omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
783 if (!LINE_USED(bank->mod_usage, offset))
784 omap_clear_gpio_debounce(bank, offset);
Javier Martinez Canillasa0e827c2014-06-27 22:17:37 +0200785 omap_disable_gpio_module(bank, offset);
Sebastian Andrzej Siewior4dbada22015-07-21 18:26:51 +0200786 raw_spin_unlock_irqrestore(&bank->lock, flags);
Grygorii Strashkoaca82d12015-09-25 12:28:02 -0700787}
788
789static void omap_gpio_irq_bus_lock(struct irq_data *data)
790{
791 struct gpio_bank *bank = omap_irq_data_get_bank(data);
792
793 if (!BANK_USED(bank))
Grygorii Strashko7b1e5dc2016-03-04 17:25:35 +0200794 pm_runtime_get_sync(bank->chip.parent);
Grygorii Strashkoaca82d12015-09-25 12:28:02 -0700795}
796
797static void gpio_irq_bus_sync_unlock(struct irq_data *data)
798{
799 struct gpio_bank *bank = omap_irq_data_get_bank(data);
Javier Martinez Canillasfac7fa12013-09-25 02:36:54 +0200800
801 /*
802 * If this is the last IRQ to be freed in the bank,
803 * disable the bank module.
804 */
805 if (!BANK_USED(bank))
Grygorii Strashko7b1e5dc2016-03-04 17:25:35 +0200806 pm_runtime_put(bank->chip.parent);
Tony Lindgren4196dd62006-09-25 12:41:38 +0300807}
808
Javier Martinez Canillasa0e827c2014-06-27 22:17:37 +0200809static void omap_gpio_ack_irq(struct irq_data *d)
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100810{
Javier Martinez Canillasa0e827c2014-06-27 22:17:37 +0200811 struct gpio_bank *bank = omap_irq_data_get_bank(d);
Grygorii Strashko9943f262015-03-23 14:18:27 +0200812 unsigned offset = d->hwirq;
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100813
Grygorii Strashko9943f262015-03-23 14:18:27 +0200814 omap_clear_gpio_irqstatus(bank, offset);
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100815}
816
Javier Martinez Canillasa0e827c2014-06-27 22:17:37 +0200817static void omap_gpio_mask_irq(struct irq_data *d)
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100818{
Javier Martinez Canillasa0e827c2014-06-27 22:17:37 +0200819 struct gpio_bank *bank = omap_irq_data_get_bank(d);
Grygorii Strashko9943f262015-03-23 14:18:27 +0200820 unsigned offset = d->hwirq;
Colin Cross85ec7b92011-06-06 13:38:18 -0700821 unsigned long flags;
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100822
Sebastian Andrzej Siewior4dbada22015-07-21 18:26:51 +0200823 raw_spin_lock_irqsave(&bank->lock, flags);
Grygorii Strashko9943f262015-03-23 14:18:27 +0200824 omap_set_gpio_irqenable(bank, offset, 0);
825 omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
Sebastian Andrzej Siewior4dbada22015-07-21 18:26:51 +0200826 raw_spin_unlock_irqrestore(&bank->lock, flags);
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100827}
828
Javier Martinez Canillasa0e827c2014-06-27 22:17:37 +0200829static void omap_gpio_unmask_irq(struct irq_data *d)
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100830{
Javier Martinez Canillasa0e827c2014-06-27 22:17:37 +0200831 struct gpio_bank *bank = omap_irq_data_get_bank(d);
Grygorii Strashko9943f262015-03-23 14:18:27 +0200832 unsigned offset = d->hwirq;
Thomas Gleixner8c04a172011-03-24 12:40:15 +0100833 u32 trigger = irqd_get_trigger_type(d);
Colin Cross85ec7b92011-06-06 13:38:18 -0700834 unsigned long flags;
Kevin Hilman55b60192009-06-04 15:57:10 -0700835
Sebastian Andrzej Siewior4dbada22015-07-21 18:26:51 +0200836 raw_spin_lock_irqsave(&bank->lock, flags);
Kevin Hilman55b60192009-06-04 15:57:10 -0700837 if (trigger)
Grygorii Strashko9943f262015-03-23 14:18:27 +0200838 omap_set_gpio_triggering(bank, offset, trigger);
Kevin Hilmanb144ff62008-01-16 21:56:15 -0800839
840 /* For level-triggered GPIOs, the clearing must be done after
841 * the HW source is cleared, thus after the handler has run */
Grygorii Strashko9943f262015-03-23 14:18:27 +0200842 if (bank->level_mask & BIT(offset)) {
843 omap_set_gpio_irqenable(bank, offset, 0);
844 omap_clear_gpio_irqstatus(bank, offset);
Kevin Hilmanb144ff62008-01-16 21:56:15 -0800845 }
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100846
Grygorii Strashko9943f262015-03-23 14:18:27 +0200847 omap_set_gpio_irqenable(bank, offset, 1);
Sebastian Andrzej Siewior4dbada22015-07-21 18:26:51 +0200848 raw_spin_unlock_irqrestore(&bank->lock, flags);
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100849}
850
David Brownelle5c56ed2006-12-06 17:13:59 -0800851/*---------------------------------------------------------------------*/
852
Magnus Damm79ee0312009-07-08 13:22:04 +0200853static int omap_mpuio_suspend_noirq(struct device *dev)
David Brownell11a78b72006-12-06 17:14:11 -0800854{
Magnus Damm79ee0312009-07-08 13:22:04 +0200855 struct platform_device *pdev = to_platform_device(dev);
David Brownell11a78b72006-12-06 17:14:11 -0800856 struct gpio_bank *bank = platform_get_drvdata(pdev);
Tony Lindgren5de62b82010-12-07 16:26:58 -0800857 void __iomem *mask_reg = bank->base +
858 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
David Brownella6472532008-03-03 04:33:30 -0800859 unsigned long flags;
David Brownell11a78b72006-12-06 17:14:11 -0800860
Sebastian Andrzej Siewior4dbada22015-07-21 18:26:51 +0200861 raw_spin_lock_irqsave(&bank->lock, flags);
Victor Kamensky661553b2013-11-16 02:01:04 +0200862 writel_relaxed(0xffff & ~bank->context.wake_en, mask_reg);
Sebastian Andrzej Siewior4dbada22015-07-21 18:26:51 +0200863 raw_spin_unlock_irqrestore(&bank->lock, flags);
David Brownell11a78b72006-12-06 17:14:11 -0800864
865 return 0;
866}
867
Magnus Damm79ee0312009-07-08 13:22:04 +0200868static int omap_mpuio_resume_noirq(struct device *dev)
David Brownell11a78b72006-12-06 17:14:11 -0800869{
Magnus Damm79ee0312009-07-08 13:22:04 +0200870 struct platform_device *pdev = to_platform_device(dev);
David Brownell11a78b72006-12-06 17:14:11 -0800871 struct gpio_bank *bank = platform_get_drvdata(pdev);
Tony Lindgren5de62b82010-12-07 16:26:58 -0800872 void __iomem *mask_reg = bank->base +
873 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
David Brownella6472532008-03-03 04:33:30 -0800874 unsigned long flags;
David Brownell11a78b72006-12-06 17:14:11 -0800875
Sebastian Andrzej Siewior4dbada22015-07-21 18:26:51 +0200876 raw_spin_lock_irqsave(&bank->lock, flags);
Victor Kamensky661553b2013-11-16 02:01:04 +0200877 writel_relaxed(bank->context.wake_en, mask_reg);
Sebastian Andrzej Siewior4dbada22015-07-21 18:26:51 +0200878 raw_spin_unlock_irqrestore(&bank->lock, flags);
David Brownell11a78b72006-12-06 17:14:11 -0800879
880 return 0;
881}
882
Alexey Dobriyan47145212009-12-14 18:00:08 -0800883static const struct dev_pm_ops omap_mpuio_dev_pm_ops = {
Magnus Damm79ee0312009-07-08 13:22:04 +0200884 .suspend_noirq = omap_mpuio_suspend_noirq,
885 .resume_noirq = omap_mpuio_resume_noirq,
886};
887
Rafael J. Wysocki3c437ff2011-04-22 22:02:46 +0200888/* use platform_driver for this. */
David Brownell11a78b72006-12-06 17:14:11 -0800889static struct platform_driver omap_mpuio_driver = {
David Brownell11a78b72006-12-06 17:14:11 -0800890 .driver = {
891 .name = "mpuio",
Magnus Damm79ee0312009-07-08 13:22:04 +0200892 .pm = &omap_mpuio_dev_pm_ops,
David Brownell11a78b72006-12-06 17:14:11 -0800893 },
894};
895
896static struct platform_device omap_mpuio_device = {
897 .name = "mpuio",
898 .id = -1,
899 .dev = {
900 .driver = &omap_mpuio_driver.driver,
901 }
902 /* could list the /proc/iomem resources */
903};
904
Javier Martinez Canillasa0e827c2014-06-27 22:17:37 +0200905static inline void omap_mpuio_init(struct gpio_bank *bank)
David Brownell11a78b72006-12-06 17:14:11 -0800906{
Varadarajan, Charulatha77640aa2010-12-07 16:26:57 -0800907 platform_set_drvdata(&omap_mpuio_device, bank);
David Brownellfcf126d2007-04-02 12:46:47 -0700908
David Brownell11a78b72006-12-06 17:14:11 -0800909 if (platform_driver_register(&omap_mpuio_driver) == 0)
910 (void) platform_device_register(&omap_mpuio_device);
911}
912
David Brownelle5c56ed2006-12-06 17:13:59 -0800913/*---------------------------------------------------------------------*/
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100914
Javier Martinez Canillasa0e827c2014-06-27 22:17:37 +0200915static int omap_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
Yegor Yefremov93700842014-04-24 08:57:39 +0200916{
917 struct gpio_bank *bank;
918 unsigned long flags;
919 void __iomem *reg;
920 int dir;
921
Linus Walleijd99f7ae2015-12-07 11:16:00 +0100922 bank = gpiochip_get_data(chip);
Yegor Yefremov93700842014-04-24 08:57:39 +0200923 reg = bank->base + bank->regs->direction;
Sebastian Andrzej Siewior4dbada22015-07-21 18:26:51 +0200924 raw_spin_lock_irqsave(&bank->lock, flags);
Yegor Yefremov93700842014-04-24 08:57:39 +0200925 dir = !!(readl_relaxed(reg) & BIT(offset));
Sebastian Andrzej Siewior4dbada22015-07-21 18:26:51 +0200926 raw_spin_unlock_irqrestore(&bank->lock, flags);
Yegor Yefremov93700842014-04-24 08:57:39 +0200927 return dir;
928}
929
Javier Martinez Canillasa0e827c2014-06-27 22:17:37 +0200930static int omap_gpio_input(struct gpio_chip *chip, unsigned offset)
David Brownell52e31342008-03-03 12:43:23 -0800931{
932 struct gpio_bank *bank;
933 unsigned long flags;
934
Linus Walleijd99f7ae2015-12-07 11:16:00 +0100935 bank = gpiochip_get_data(chip);
Sebastian Andrzej Siewior4dbada22015-07-21 18:26:51 +0200936 raw_spin_lock_irqsave(&bank->lock, flags);
Javier Martinez Canillasa0e827c2014-06-27 22:17:37 +0200937 omap_set_gpio_direction(bank, offset, 1);
Sebastian Andrzej Siewior4dbada22015-07-21 18:26:51 +0200938 raw_spin_unlock_irqrestore(&bank->lock, flags);
David Brownell52e31342008-03-03 12:43:23 -0800939 return 0;
940}
941
Javier Martinez Canillasa0e827c2014-06-27 22:17:37 +0200942static int omap_gpio_get(struct gpio_chip *chip, unsigned offset)
David Brownell52e31342008-03-03 12:43:23 -0800943{
Roger Quadrosb37c45b2009-08-05 16:53:24 +0300944 struct gpio_bank *bank;
Roger Quadrosb37c45b2009-08-05 16:53:24 +0300945
Linus Walleijd99f7ae2015-12-07 11:16:00 +0100946 bank = gpiochip_get_data(chip);
Roger Quadrosb37c45b2009-08-05 16:53:24 +0300947
Grygorii Strashkob2b20042015-03-23 14:18:23 +0200948 if (omap_gpio_is_input(bank, offset))
Javier Martinez Canillasa0e827c2014-06-27 22:17:37 +0200949 return omap_get_gpio_datain(bank, offset);
Roger Quadrosb37c45b2009-08-05 16:53:24 +0300950 else
Javier Martinez Canillasa0e827c2014-06-27 22:17:37 +0200951 return omap_get_gpio_dataout(bank, offset);
David Brownell52e31342008-03-03 12:43:23 -0800952}
953
Javier Martinez Canillasa0e827c2014-06-27 22:17:37 +0200954static int omap_gpio_output(struct gpio_chip *chip, unsigned offset, int value)
David Brownell52e31342008-03-03 12:43:23 -0800955{
956 struct gpio_bank *bank;
957 unsigned long flags;
958
Linus Walleijd99f7ae2015-12-07 11:16:00 +0100959 bank = gpiochip_get_data(chip);
Sebastian Andrzej Siewior4dbada22015-07-21 18:26:51 +0200960 raw_spin_lock_irqsave(&bank->lock, flags);
Kevin Hilmanfa87931a2011-04-20 16:31:23 -0700961 bank->set_dataout(bank, offset, value);
Javier Martinez Canillasa0e827c2014-06-27 22:17:37 +0200962 omap_set_gpio_direction(bank, offset, 0);
Sebastian Andrzej Siewior4dbada22015-07-21 18:26:51 +0200963 raw_spin_unlock_irqrestore(&bank->lock, flags);
Javier Martinez Canillas2f56e0a2013-10-16 02:47:30 +0200964 return 0;
David Brownell52e31342008-03-03 12:43:23 -0800965}
966
Javier Martinez Canillasa0e827c2014-06-27 22:17:37 +0200967static int omap_gpio_debounce(struct gpio_chip *chip, unsigned offset,
968 unsigned debounce)
Felipe Balbi168ef3d2010-05-26 14:42:23 -0700969{
970 struct gpio_bank *bank;
971 unsigned long flags;
David Rivshin198ab402017-04-24 18:56:50 -0400972 int ret;
Felipe Balbi168ef3d2010-05-26 14:42:23 -0700973
Linus Walleijd99f7ae2015-12-07 11:16:00 +0100974 bank = gpiochip_get_data(chip);
Varadarajan, Charulatha77640aa2010-12-07 16:26:57 -0800975
Sebastian Andrzej Siewior4dbada22015-07-21 18:26:51 +0200976 raw_spin_lock_irqsave(&bank->lock, flags);
David Rivshin198ab402017-04-24 18:56:50 -0400977 ret = omap2_set_gpio_debounce(bank, offset, debounce);
Sebastian Andrzej Siewior4dbada22015-07-21 18:26:51 +0200978 raw_spin_unlock_irqrestore(&bank->lock, flags);
Felipe Balbi168ef3d2010-05-26 14:42:23 -0700979
David Rivshin198ab402017-04-24 18:56:50 -0400980 if (ret)
981 dev_info(chip->parent,
982 "Could not set line %u debounce to %u microseconds (%d)",
983 offset, debounce, ret);
984
985 return ret;
Felipe Balbi168ef3d2010-05-26 14:42:23 -0700986}
987
Javier Martinez Canillasa0e827c2014-06-27 22:17:37 +0200988static void omap_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
David Brownell52e31342008-03-03 12:43:23 -0800989{
990 struct gpio_bank *bank;
991 unsigned long flags;
992
Linus Walleijd99f7ae2015-12-07 11:16:00 +0100993 bank = gpiochip_get_data(chip);
Sebastian Andrzej Siewior4dbada22015-07-21 18:26:51 +0200994 raw_spin_lock_irqsave(&bank->lock, flags);
Kevin Hilmanfa87931a2011-04-20 16:31:23 -0700995 bank->set_dataout(bank, offset, value);
Sebastian Andrzej Siewior4dbada22015-07-21 18:26:51 +0200996 raw_spin_unlock_irqrestore(&bank->lock, flags);
David Brownell52e31342008-03-03 12:43:23 -0800997}
998
999/*---------------------------------------------------------------------*/
1000
Tony Lindgren9a748052010-12-07 16:26:56 -08001001static void __init omap_gpio_show_rev(struct gpio_bank *bank)
Tony Lindgren9f7065d2009-10-19 15:25:20 -07001002{
Kevin Hilmane5ff4442011-04-22 14:37:16 -07001003 static bool called;
Tony Lindgren9f7065d2009-10-19 15:25:20 -07001004 u32 rev;
1005
Kevin Hilmane5ff4442011-04-22 14:37:16 -07001006 if (called || bank->regs->revision == USHRT_MAX)
Tony Lindgren9f7065d2009-10-19 15:25:20 -07001007 return;
1008
Victor Kamensky661553b2013-11-16 02:01:04 +02001009 rev = readw_relaxed(bank->base + bank->regs->revision);
Kevin Hilmane5ff4442011-04-22 14:37:16 -07001010 pr_info("OMAP GPIO hardware version %d.%d\n",
Tony Lindgren9f7065d2009-10-19 15:25:20 -07001011 (rev >> 4) & 0x0f, rev & 0x0f);
Kevin Hilmane5ff4442011-04-22 14:37:16 -07001012
1013 called = true;
Tony Lindgren9f7065d2009-10-19 15:25:20 -07001014}
1015
Charulatha V03e128c2011-05-05 19:58:01 +05301016static void omap_gpio_mod_init(struct gpio_bank *bank)
Varadarajan, Charulatha2fae7fb2010-12-07 16:26:55 -08001017{
Tarun Kanti DebBarmaab985f02011-09-13 15:12:05 +05301018 void __iomem *base = bank->base;
1019 u32 l = 0xffffffff;
Varadarajan, Charulatha2fae7fb2010-12-07 16:26:55 -08001020
Tarun Kanti DebBarmaab985f02011-09-13 15:12:05 +05301021 if (bank->width == 16)
1022 l = 0xffff;
Varadarajan, Charulatha2fae7fb2010-12-07 16:26:55 -08001023
Charulatha Vd0d665a2011-08-31 00:02:21 +05301024 if (bank->is_mpuio) {
Victor Kamensky661553b2013-11-16 02:01:04 +02001025 writel_relaxed(l, bank->base + bank->regs->irqenable);
Tarun Kanti DebBarmaab985f02011-09-13 15:12:05 +05301026 return;
Varadarajan, Charulatha2fae7fb2010-12-07 16:26:55 -08001027 }
Tarun Kanti DebBarmaab985f02011-09-13 15:12:05 +05301028
Javier Martinez Canillasa0e827c2014-06-27 22:17:37 +02001029 omap_gpio_rmw(base, bank->regs->irqenable, l,
1030 bank->regs->irqenable_inv);
1031 omap_gpio_rmw(base, bank->regs->irqstatus, l,
1032 !bank->regs->irqenable_inv);
Tarun Kanti DebBarmaab985f02011-09-13 15:12:05 +05301033 if (bank->regs->debounce_en)
Victor Kamensky661553b2013-11-16 02:01:04 +02001034 writel_relaxed(0, base + bank->regs->debounce_en);
Tarun Kanti DebBarmaab985f02011-09-13 15:12:05 +05301035
Tarun Kanti DebBarma2dc983c2011-11-24 02:44:29 +05301036 /* Save OE default value (0xffffffff) in the context */
Victor Kamensky661553b2013-11-16 02:01:04 +02001037 bank->context.oe = readl_relaxed(bank->base + bank->regs->direction);
Tarun Kanti DebBarmaab985f02011-09-13 15:12:05 +05301038 /* Initialize interface clk ungated, module enabled */
1039 if (bank->regs->ctrl)
Victor Kamensky661553b2013-11-16 02:01:04 +02001040 writel_relaxed(0, base + bank->regs->ctrl);
Varadarajan, Charulatha2fae7fb2010-12-07 16:26:55 -08001041}
1042
Nishanth Menon46824e22014-09-05 14:52:55 -05001043static int omap_gpio_chip_init(struct gpio_bank *bank, struct irq_chip *irqc)
Varadarajan, Charulatha2fae7fb2010-12-07 16:26:55 -08001044{
Varadarajan, Charulatha2fae7fb2010-12-07 16:26:55 -08001045 static int gpio;
Javier Martinez Canillasfb655f52014-04-06 16:58:16 +02001046 int irq_base = 0;
Javier Martinez Canillas6ef7f382014-04-06 16:58:14 +02001047 int ret;
Varadarajan, Charulatha2fae7fb2010-12-07 16:26:55 -08001048
Varadarajan, Charulatha2fae7fb2010-12-07 16:26:55 -08001049 /*
1050 * REVISIT eventually switch from OMAP-specific gpio structs
1051 * over to the generic ones
1052 */
1053 bank->chip.request = omap_gpio_request;
1054 bank->chip.free = omap_gpio_free;
Javier Martinez Canillasa0e827c2014-06-27 22:17:37 +02001055 bank->chip.get_direction = omap_gpio_get_direction;
1056 bank->chip.direction_input = omap_gpio_input;
1057 bank->chip.get = omap_gpio_get;
1058 bank->chip.direction_output = omap_gpio_output;
1059 bank->chip.set_debounce = omap_gpio_debounce;
1060 bank->chip.set = omap_gpio_set;
Charulatha Vd0d665a2011-08-31 00:02:21 +05301061 if (bank->is_mpuio) {
Varadarajan, Charulatha2fae7fb2010-12-07 16:26:55 -08001062 bank->chip.label = "mpuio";
Tarun Kanti DebBarma6ed87c52011-09-13 14:41:44 +05301063 if (bank->regs->wkup_en)
Linus Walleij58383c72015-11-04 09:56:26 +01001064 bank->chip.parent = &omap_mpuio_device.dev;
Varadarajan, Charulatha2fae7fb2010-12-07 16:26:55 -08001065 bank->chip.base = OMAP_MPUIO(0);
1066 } else {
1067 bank->chip.label = "gpio";
1068 bank->chip.base = gpio;
Varadarajan, Charulatha2fae7fb2010-12-07 16:26:55 -08001069 }
Kevin Hilmand5f46242011-04-21 09:23:00 -07001070 bank->chip.ngpio = bank->width;
Varadarajan, Charulatha2fae7fb2010-12-07 16:26:55 -08001071
Linus Walleijd99f7ae2015-12-07 11:16:00 +01001072 ret = gpiochip_add_data(&bank->chip, bank);
Javier Martinez Canillas6ef7f382014-04-06 16:58:14 +02001073 if (ret) {
Grygorii Strashko7b1e5dc2016-03-04 17:25:35 +02001074 dev_err(bank->chip.parent,
1075 "Could not register gpio chip %d\n", ret);
Javier Martinez Canillas6ef7f382014-04-06 16:58:14 +02001076 return ret;
1077 }
Varadarajan, Charulatha2fae7fb2010-12-07 16:26:55 -08001078
Tony Lindgren46d4f7c2015-09-03 10:31:27 -07001079 if (!bank->is_mpuio)
1080 gpio += bank->width;
1081
Javier Martinez Canillasfb655f52014-04-06 16:58:16 +02001082#ifdef CONFIG_ARCH_OMAP1
1083 /*
1084 * REVISIT: Once we have OMAP1 supporting SPARSE_IRQ, we can drop
1085 * irq_alloc_descs() since a base IRQ offset will no longer be needed.
1086 */
1087 irq_base = irq_alloc_descs(-1, 0, bank->width, 0);
1088 if (irq_base < 0) {
Grygorii Strashko7b1e5dc2016-03-04 17:25:35 +02001089 dev_err(bank->chip.parent, "Couldn't allocate IRQ numbers\n");
Javier Martinez Canillasfb655f52014-04-06 16:58:16 +02001090 return -ENODEV;
1091 }
1092#endif
1093
Tony Lindgrend2d05c62015-04-23 16:54:17 -07001094 /* MPUIO is a bit different, reading IRQ status clears it */
1095 if (bank->is_mpuio) {
1096 irqc->irq_ack = dummy_irq_chip.irq_ack;
Tony Lindgrend2d05c62015-04-23 16:54:17 -07001097 if (!bank->regs->wkup_en)
1098 irqc->irq_set_wake = NULL;
1099 }
1100
Nishanth Menon46824e22014-09-05 14:52:55 -05001101 ret = gpiochip_irqchip_add(&bank->chip, irqc,
Grygorii Strashko450fa542015-09-25 12:28:03 -07001102 irq_base, handle_bad_irq,
Javier Martinez Canillasfb655f52014-04-06 16:58:16 +02001103 IRQ_TYPE_NONE);
1104
1105 if (ret) {
Grygorii Strashko7b1e5dc2016-03-04 17:25:35 +02001106 dev_err(bank->chip.parent,
1107 "Couldn't add irqchip to gpiochip %d\n", ret);
Linus Walleijda26d5d2014-09-16 15:11:41 -07001108 gpiochip_remove(&bank->chip);
Javier Martinez Canillasfb655f52014-04-06 16:58:16 +02001109 return -ENODEV;
1110 }
1111
Grygorii Strashko450fa542015-09-25 12:28:03 -07001112 gpiochip_set_chained_irqchip(&bank->chip, irqc, bank->irq, NULL);
Javier Martinez Canillasfb655f52014-04-06 16:58:16 +02001113
Grygorii Strashko7b1e5dc2016-03-04 17:25:35 +02001114 ret = devm_request_irq(bank->chip.parent, bank->irq,
1115 omap_gpio_irq_handler,
1116 0, dev_name(bank->chip.parent), bank);
Grygorii Strashko450fa542015-09-25 12:28:03 -07001117 if (ret)
1118 gpiochip_remove(&bank->chip);
1119
1120 return ret;
Varadarajan, Charulatha2fae7fb2010-12-07 16:26:55 -08001121}
1122
Benoit Cousson384ebe12011-08-16 11:53:02 +02001123static const struct of_device_id omap_gpio_match[];
1124
Bill Pemberton38363092012-11-19 13:22:34 -05001125static int omap_gpio_probe(struct platform_device *pdev)
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +01001126{
Benoit Cousson862ff642012-02-01 15:58:56 +01001127 struct device *dev = &pdev->dev;
Benoit Cousson384ebe12011-08-16 11:53:02 +02001128 struct device_node *node = dev->of_node;
1129 const struct of_device_id *match;
Uwe Kleine-Königf6817a22012-05-21 21:57:39 +02001130 const struct omap_gpio_platform_data *pdata;
Varadarajan, Charulatha77640aa2010-12-07 16:26:57 -08001131 struct resource *res;
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +01001132 struct gpio_bank *bank;
Nishanth Menon46824e22014-09-05 14:52:55 -05001133 struct irq_chip *irqc;
Javier Martinez Canillas6ef7f382014-04-06 16:58:14 +02001134 int ret;
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +01001135
Benoit Cousson384ebe12011-08-16 11:53:02 +02001136 match = of_match_device(of_match_ptr(omap_gpio_match), dev);
1137
Jingoo Hane56aee12013-07-30 17:08:05 +09001138 pdata = match ? match->data : dev_get_platdata(dev);
Benoit Cousson384ebe12011-08-16 11:53:02 +02001139 if (!pdata)
Benoit Cousson96751fc2012-02-01 16:01:39 +01001140 return -EINVAL;
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +01001141
Tobias Klauser086d5852012-10-05 11:37:38 +02001142 bank = devm_kzalloc(dev, sizeof(struct gpio_bank), GFP_KERNEL);
Charulatha V03e128c2011-05-05 19:58:01 +05301143 if (!bank) {
Benoit Cousson862ff642012-02-01 15:58:56 +01001144 dev_err(dev, "Memory alloc failed\n");
Benoit Cousson96751fc2012-02-01 16:01:39 +01001145 return -ENOMEM;
Charulatha V03e128c2011-05-05 19:58:01 +05301146 }
Varadarajan, Charulatha77640aa2010-12-07 16:26:57 -08001147
Nishanth Menon46824e22014-09-05 14:52:55 -05001148 irqc = devm_kzalloc(dev, sizeof(*irqc), GFP_KERNEL);
1149 if (!irqc)
1150 return -ENOMEM;
1151
Tony Lindgren3d009c82015-01-16 14:50:50 -08001152 irqc->irq_startup = omap_gpio_irq_startup,
Nishanth Menon46824e22014-09-05 14:52:55 -05001153 irqc->irq_shutdown = omap_gpio_irq_shutdown,
1154 irqc->irq_ack = omap_gpio_ack_irq,
1155 irqc->irq_mask = omap_gpio_mask_irq,
1156 irqc->irq_unmask = omap_gpio_unmask_irq,
1157 irqc->irq_set_type = omap_gpio_irq_type,
1158 irqc->irq_set_wake = omap_gpio_wake_enable,
Grygorii Strashkoaca82d12015-09-25 12:28:02 -07001159 irqc->irq_bus_lock = omap_gpio_irq_bus_lock,
1160 irqc->irq_bus_sync_unlock = gpio_irq_bus_sync_unlock,
Nishanth Menon46824e22014-09-05 14:52:55 -05001161 irqc->name = dev_name(&pdev->dev);
Grygorii Strashko0c0451e2016-04-12 13:52:31 +03001162 irqc->flags = IRQCHIP_MASK_ON_SUSPEND;
Nishanth Menon46824e22014-09-05 14:52:55 -05001163
Grygorii Strashko89d18e32015-08-18 14:10:53 +03001164 bank->irq = platform_get_irq(pdev, 0);
1165 if (bank->irq <= 0) {
1166 if (!bank->irq)
1167 bank->irq = -ENXIO;
1168 if (bank->irq != -EPROBE_DEFER)
1169 dev_err(dev,
1170 "can't get irq resource ret=%d\n", bank->irq);
1171 return bank->irq;
Varadarajan, Charulatha77640aa2010-12-07 16:26:57 -08001172 }
1173
Linus Walleij58383c72015-11-04 09:56:26 +01001174 bank->chip.parent = dev;
Grygorii Strashkoc23837c2015-06-25 18:13:33 +03001175 bank->chip.owner = THIS_MODULE;
Varadarajan, Charulatha77640aa2010-12-07 16:26:57 -08001176 bank->dbck_flag = pdata->dbck_flag;
Tony Lindgren5de62b82010-12-07 16:26:58 -08001177 bank->stride = pdata->bank_stride;
Kevin Hilmand5f46242011-04-21 09:23:00 -07001178 bank->width = pdata->bank_width;
Charulatha Vd0d665a2011-08-31 00:02:21 +05301179 bank->is_mpuio = pdata->is_mpuio;
Charulatha V803a2432011-05-05 17:04:12 +05301180 bank->non_wakeup_gpios = pdata->non_wakeup_gpios;
Kevin Hilmanfa87931a2011-04-20 16:31:23 -07001181 bank->regs = pdata->regs;
Benoit Cousson384ebe12011-08-16 11:53:02 +02001182#ifdef CONFIG_OF_GPIO
1183 bank->chip.of_node = of_node_get(node);
1184#endif
Jon Huntera2797be2013-04-04 15:16:15 -05001185 if (node) {
1186 if (!of_property_read_bool(node, "ti,gpio-always-on"))
1187 bank->loses_context = true;
1188 } else {
1189 bank->loses_context = pdata->loses_context;
Jon Hunter352a2d52013-04-15 13:06:54 -05001190
1191 if (bank->loses_context)
1192 bank->get_context_loss_count =
1193 pdata->get_context_loss_count;
Benoit Cousson384ebe12011-08-16 11:53:02 +02001194 }
1195
Kevin Hilmanfa87931a2011-04-20 16:31:23 -07001196 if (bank->regs->set_dataout && bank->regs->clr_dataout)
Javier Martinez Canillasa0e827c2014-06-27 22:17:37 +02001197 bank->set_dataout = omap_set_gpio_dataout_reg;
Kevin Hilmanfa87931a2011-04-20 16:31:23 -07001198 else
Javier Martinez Canillasa0e827c2014-06-27 22:17:37 +02001199 bank->set_dataout = omap_set_gpio_dataout_mask;
Varadarajan, Charulatha77640aa2010-12-07 16:26:57 -08001200
Sebastian Andrzej Siewior4dbada22015-07-21 18:26:51 +02001201 raw_spin_lock_init(&bank->lock);
Grygorii Strashko450fa542015-09-25 12:28:03 -07001202 raw_spin_lock_init(&bank->wa_lock);
Varadarajan, Charulatha77640aa2010-12-07 16:26:57 -08001203
1204 /* Static mapping, never released */
1205 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
Jingoo Han717f70e2014-02-12 11:51:38 +09001206 bank->base = devm_ioremap_resource(dev, res);
1207 if (IS_ERR(bank->base)) {
Jingoo Han717f70e2014-02-12 11:51:38 +09001208 return PTR_ERR(bank->base);
Varadarajan, Charulatha77640aa2010-12-07 16:26:57 -08001209 }
1210
Grygorii Strashko5d9452e2015-08-18 14:10:56 +03001211 if (bank->dbck_flag) {
Grygorii Strashko7b1e5dc2016-03-04 17:25:35 +02001212 bank->dbck = devm_clk_get(dev, "dbclk");
Grygorii Strashko5d9452e2015-08-18 14:10:56 +03001213 if (IS_ERR(bank->dbck)) {
Grygorii Strashko7b1e5dc2016-03-04 17:25:35 +02001214 dev_err(dev,
Grygorii Strashko5d9452e2015-08-18 14:10:56 +03001215 "Could not get gpio dbck. Disable debounce\n");
1216 bank->dbck_flag = false;
1217 } else {
1218 clk_prepare(bank->dbck);
1219 }
1220 }
1221
Tarun Kanti DebBarma065cd792011-11-24 01:48:52 +05301222 platform_set_drvdata(pdev, bank);
1223
Grygorii Strashko7b1e5dc2016-03-04 17:25:35 +02001224 pm_runtime_enable(dev);
1225 pm_runtime_irq_safe(dev);
1226 pm_runtime_get_sync(dev);
Varadarajan, Charulatha77640aa2010-12-07 16:26:57 -08001227
Charulatha Vd0d665a2011-08-31 00:02:21 +05301228 if (bank->is_mpuio)
Javier Martinez Canillasa0e827c2014-06-27 22:17:37 +02001229 omap_mpuio_init(bank);
Tarun Kanti DebBarmaab985f02011-09-13 15:12:05 +05301230
Charulatha V03e128c2011-05-05 19:58:01 +05301231 omap_gpio_mod_init(bank);
Javier Martinez Canillas6ef7f382014-04-06 16:58:14 +02001232
Nishanth Menon46824e22014-09-05 14:52:55 -05001233 ret = omap_gpio_chip_init(bank, irqc);
Tony Lindgren5e606ab2015-08-28 11:44:49 -07001234 if (ret) {
Grygorii Strashko7b1e5dc2016-03-04 17:25:35 +02001235 pm_runtime_put_sync(dev);
1236 pm_runtime_disable(dev);
Javier Martinez Canillas6ef7f382014-04-06 16:58:14 +02001237 return ret;
Tony Lindgren5e606ab2015-08-28 11:44:49 -07001238 }
Javier Martinez Canillas6ef7f382014-04-06 16:58:14 +02001239
Tony Lindgren9a748052010-12-07 16:26:56 -08001240 omap_gpio_show_rev(bank);
Tony Lindgren9f7065d2009-10-19 15:25:20 -07001241
Grygorii Strashko7b1e5dc2016-03-04 17:25:35 +02001242 pm_runtime_put(dev);
Tarun Kanti DebBarma55b93c32011-09-29 07:23:22 +05301243
Charulatha V03e128c2011-05-05 19:58:01 +05301244 list_add_tail(&bank->node, &omap_gpio_list);
Varadarajan, Charulatha77640aa2010-12-07 16:26:57 -08001245
Jon Hunter879fe322013-04-04 15:16:12 -05001246 return 0;
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +01001247}
1248
Tony Lindgrencac089f2015-04-23 16:56:22 -07001249static int omap_gpio_remove(struct platform_device *pdev)
1250{
1251 struct gpio_bank *bank = platform_get_drvdata(pdev);
1252
1253 list_del(&bank->node);
1254 gpiochip_remove(&bank->chip);
Grygorii Strashko7b1e5dc2016-03-04 17:25:35 +02001255 pm_runtime_disable(&pdev->dev);
Grygorii Strashko5d9452e2015-08-18 14:10:56 +03001256 if (bank->dbck_flag)
1257 clk_unprepare(bank->dbck);
Tony Lindgrencac089f2015-04-23 16:56:22 -07001258
1259 return 0;
1260}
1261
Tarun Kanti DebBarma55b93c32011-09-29 07:23:22 +05301262#ifdef CONFIG_ARCH_OMAP2PLUS
1263
Rafael J. Wysockiecb23122014-12-04 01:03:40 +01001264#if defined(CONFIG_PM)
Tarun Kanti DebBarma60a34372011-09-29 04:47:25 +05301265static void omap_gpio_restore_context(struct gpio_bank *bank);
Juha Yrjola3ac4fa92006-12-06 17:13:52 -08001266
Tarun Kanti DebBarma2dc983c2011-11-24 02:44:29 +05301267static int omap_gpio_runtime_suspend(struct device *dev)
1268{
1269 struct platform_device *pdev = to_platform_device(dev);
1270 struct gpio_bank *bank = platform_get_drvdata(pdev);
1271 u32 l1 = 0, l2 = 0;
1272 unsigned long flags;
Kevin Hilman68942ed2012-03-05 15:10:04 -08001273 u32 wake_low, wake_hi;
Tarun Kanti DebBarma2dc983c2011-11-24 02:44:29 +05301274
Sebastian Andrzej Siewior4dbada22015-07-21 18:26:51 +02001275 raw_spin_lock_irqsave(&bank->lock, flags);
Kevin Hilman68942ed2012-03-05 15:10:04 -08001276
1277 /*
1278 * Only edges can generate a wakeup event to the PRCM.
1279 *
1280 * Therefore, ensure any wake-up capable GPIOs have
1281 * edge-detection enabled before going idle to ensure a wakeup
1282 * to the PRCM is generated on a GPIO transition. (c.f. 34xx
1283 * NDA TRM 25.5.3.1)
1284 *
1285 * The normal values will be restored upon ->runtime_resume()
1286 * by writing back the values saved in bank->context.
1287 */
1288 wake_low = bank->context.leveldetect0 & bank->context.wake_en;
1289 if (wake_low)
Victor Kamensky661553b2013-11-16 02:01:04 +02001290 writel_relaxed(wake_low | bank->context.fallingdetect,
Kevin Hilman68942ed2012-03-05 15:10:04 -08001291 bank->base + bank->regs->fallingdetect);
1292 wake_hi = bank->context.leveldetect1 & bank->context.wake_en;
1293 if (wake_hi)
Victor Kamensky661553b2013-11-16 02:01:04 +02001294 writel_relaxed(wake_hi | bank->context.risingdetect,
Kevin Hilman68942ed2012-03-05 15:10:04 -08001295 bank->base + bank->regs->risingdetect);
1296
Kevin Hilmanb3c64bc2012-05-17 16:42:16 -07001297 if (!bank->enabled_non_wakeup_gpios)
1298 goto update_gpio_context_count;
1299
Tarun Kanti DebBarma2dc983c2011-11-24 02:44:29 +05301300 if (bank->power_mode != OFF_MODE) {
1301 bank->power_mode = 0;
Tarun Kanti DebBarma41d87cb2011-11-15 12:52:38 +05301302 goto update_gpio_context_count;
Tarun Kanti DebBarma2dc983c2011-11-24 02:44:29 +05301303 }
1304 /*
1305 * If going to OFF, remove triggering for all
1306 * non-wakeup GPIOs. Otherwise spurious IRQs will be
1307 * generated. See OMAP2420 Errata item 1.101.
1308 */
Victor Kamensky661553b2013-11-16 02:01:04 +02001309 bank->saved_datain = readl_relaxed(bank->base +
Tarun Kanti DebBarma2dc983c2011-11-24 02:44:29 +05301310 bank->regs->datain);
Tarun Kanti DebBarmac6f31c92012-04-27 19:43:32 +05301311 l1 = bank->context.fallingdetect;
1312 l2 = bank->context.risingdetect;
Tarun Kanti DebBarma2dc983c2011-11-24 02:44:29 +05301313
Tarun Kanti DebBarma2dc983c2011-11-24 02:44:29 +05301314 l1 &= ~bank->enabled_non_wakeup_gpios;
1315 l2 &= ~bank->enabled_non_wakeup_gpios;
1316
Victor Kamensky661553b2013-11-16 02:01:04 +02001317 writel_relaxed(l1, bank->base + bank->regs->fallingdetect);
1318 writel_relaxed(l2, bank->base + bank->regs->risingdetect);
Tarun Kanti DebBarma2dc983c2011-11-24 02:44:29 +05301319
1320 bank->workaround_enabled = true;
1321
Tarun Kanti DebBarma41d87cb2011-11-15 12:52:38 +05301322update_gpio_context_count:
Tarun Kanti DebBarma2dc983c2011-11-24 02:44:29 +05301323 if (bank->get_context_loss_count)
1324 bank->context_loss_count =
Grygorii Strashko7b1e5dc2016-03-04 17:25:35 +02001325 bank->get_context_loss_count(dev);
Tarun Kanti DebBarma2dc983c2011-11-24 02:44:29 +05301326
Javier Martinez Canillasa0e827c2014-06-27 22:17:37 +02001327 omap_gpio_dbck_disable(bank);
Sebastian Andrzej Siewior4dbada22015-07-21 18:26:51 +02001328 raw_spin_unlock_irqrestore(&bank->lock, flags);
Tarun Kanti DebBarma2dc983c2011-11-24 02:44:29 +05301329
1330 return 0;
1331}
1332
Jon Hunter352a2d52013-04-15 13:06:54 -05001333static void omap_gpio_init_context(struct gpio_bank *p);
1334
Tarun Kanti DebBarma2dc983c2011-11-24 02:44:29 +05301335static int omap_gpio_runtime_resume(struct device *dev)
1336{
1337 struct platform_device *pdev = to_platform_device(dev);
1338 struct gpio_bank *bank = platform_get_drvdata(pdev);
Tarun Kanti DebBarma2dc983c2011-11-24 02:44:29 +05301339 u32 l = 0, gen, gen0, gen1;
1340 unsigned long flags;
Jon Huntera2797be2013-04-04 15:16:15 -05001341 int c;
Tarun Kanti DebBarma2dc983c2011-11-24 02:44:29 +05301342
Sebastian Andrzej Siewior4dbada22015-07-21 18:26:51 +02001343 raw_spin_lock_irqsave(&bank->lock, flags);
Jon Hunter352a2d52013-04-15 13:06:54 -05001344
1345 /*
1346 * On the first resume during the probe, the context has not
1347 * been initialised and so initialise it now. Also initialise
1348 * the context loss count.
1349 */
1350 if (bank->loses_context && !bank->context_valid) {
1351 omap_gpio_init_context(bank);
1352
1353 if (bank->get_context_loss_count)
1354 bank->context_loss_count =
Grygorii Strashko7b1e5dc2016-03-04 17:25:35 +02001355 bank->get_context_loss_count(dev);
Jon Hunter352a2d52013-04-15 13:06:54 -05001356 }
1357
Javier Martinez Canillasa0e827c2014-06-27 22:17:37 +02001358 omap_gpio_dbck_enable(bank);
Kevin Hilman68942ed2012-03-05 15:10:04 -08001359
1360 /*
1361 * In ->runtime_suspend(), level-triggered, wakeup-enabled
1362 * GPIOs were set to edge trigger also in order to be able to
1363 * generate a PRCM wakeup. Here we restore the
1364 * pre-runtime_suspend() values for edge triggering.
1365 */
Victor Kamensky661553b2013-11-16 02:01:04 +02001366 writel_relaxed(bank->context.fallingdetect,
Kevin Hilman68942ed2012-03-05 15:10:04 -08001367 bank->base + bank->regs->fallingdetect);
Victor Kamensky661553b2013-11-16 02:01:04 +02001368 writel_relaxed(bank->context.risingdetect,
Kevin Hilman68942ed2012-03-05 15:10:04 -08001369 bank->base + bank->regs->risingdetect);
1370
Jon Huntera2797be2013-04-04 15:16:15 -05001371 if (bank->loses_context) {
1372 if (!bank->get_context_loss_count) {
Tarun Kanti DebBarma2dc983c2011-11-24 02:44:29 +05301373 omap_gpio_restore_context(bank);
1374 } else {
Grygorii Strashko7b1e5dc2016-03-04 17:25:35 +02001375 c = bank->get_context_loss_count(dev);
Jon Huntera2797be2013-04-04 15:16:15 -05001376 if (c != bank->context_loss_count) {
1377 omap_gpio_restore_context(bank);
1378 } else {
Sebastian Andrzej Siewior4dbada22015-07-21 18:26:51 +02001379 raw_spin_unlock_irqrestore(&bank->lock, flags);
Jon Huntera2797be2013-04-04 15:16:15 -05001380 return 0;
1381 }
Tarun Kanti DebBarma2dc983c2011-11-24 02:44:29 +05301382 }
1383 }
1384
Tarun Kanti DebBarma1b1287032012-04-27 19:43:38 +05301385 if (!bank->workaround_enabled) {
Sebastian Andrzej Siewior4dbada22015-07-21 18:26:51 +02001386 raw_spin_unlock_irqrestore(&bank->lock, flags);
Tarun Kanti DebBarma1b1287032012-04-27 19:43:38 +05301387 return 0;
1388 }
1389
Victor Kamensky661553b2013-11-16 02:01:04 +02001390 l = readl_relaxed(bank->base + bank->regs->datain);
Tarun Kanti DebBarma2dc983c2011-11-24 02:44:29 +05301391
1392 /*
1393 * Check if any of the non-wakeup interrupt GPIOs have changed
1394 * state. If so, generate an IRQ by software. This is
1395 * horribly racy, but it's the best we can do to work around
1396 * this silicon bug.
1397 */
1398 l ^= bank->saved_datain;
1399 l &= bank->enabled_non_wakeup_gpios;
1400
1401 /*
1402 * No need to generate IRQs for the rising edge for gpio IRQs
1403 * configured with falling edge only; and vice versa.
1404 */
Tarun Kanti DebBarmac6f31c92012-04-27 19:43:32 +05301405 gen0 = l & bank->context.fallingdetect;
Tarun Kanti DebBarma2dc983c2011-11-24 02:44:29 +05301406 gen0 &= bank->saved_datain;
1407
Tarun Kanti DebBarmac6f31c92012-04-27 19:43:32 +05301408 gen1 = l & bank->context.risingdetect;
Tarun Kanti DebBarma2dc983c2011-11-24 02:44:29 +05301409 gen1 &= ~(bank->saved_datain);
1410
1411 /* FIXME: Consider GPIO IRQs with level detections properly! */
Tarun Kanti DebBarmac6f31c92012-04-27 19:43:32 +05301412 gen = l & (~(bank->context.fallingdetect) &
1413 ~(bank->context.risingdetect));
Tarun Kanti DebBarma2dc983c2011-11-24 02:44:29 +05301414 /* Consider all GPIO IRQs needed to be updated */
1415 gen |= gen0 | gen1;
1416
1417 if (gen) {
1418 u32 old0, old1;
1419
Victor Kamensky661553b2013-11-16 02:01:04 +02001420 old0 = readl_relaxed(bank->base + bank->regs->leveldetect0);
1421 old1 = readl_relaxed(bank->base + bank->regs->leveldetect1);
Tarun Kanti DebBarma2dc983c2011-11-24 02:44:29 +05301422
Tarun Kanti DebBarma4e962e82012-04-27 19:43:37 +05301423 if (!bank->regs->irqstatus_raw0) {
Victor Kamensky661553b2013-11-16 02:01:04 +02001424 writel_relaxed(old0 | gen, bank->base +
Tarun Kanti DebBarma2dc983c2011-11-24 02:44:29 +05301425 bank->regs->leveldetect0);
Victor Kamensky661553b2013-11-16 02:01:04 +02001426 writel_relaxed(old1 | gen, bank->base +
Tarun Kanti DebBarma2dc983c2011-11-24 02:44:29 +05301427 bank->regs->leveldetect1);
1428 }
1429
Tarun Kanti DebBarma4e962e82012-04-27 19:43:37 +05301430 if (bank->regs->irqstatus_raw0) {
Victor Kamensky661553b2013-11-16 02:01:04 +02001431 writel_relaxed(old0 | l, bank->base +
Tarun Kanti DebBarma2dc983c2011-11-24 02:44:29 +05301432 bank->regs->leveldetect0);
Victor Kamensky661553b2013-11-16 02:01:04 +02001433 writel_relaxed(old1 | l, bank->base +
Tarun Kanti DebBarma2dc983c2011-11-24 02:44:29 +05301434 bank->regs->leveldetect1);
1435 }
Victor Kamensky661553b2013-11-16 02:01:04 +02001436 writel_relaxed(old0, bank->base + bank->regs->leveldetect0);
1437 writel_relaxed(old1, bank->base + bank->regs->leveldetect1);
Tarun Kanti DebBarma2dc983c2011-11-24 02:44:29 +05301438 }
1439
1440 bank->workaround_enabled = false;
Sebastian Andrzej Siewior4dbada22015-07-21 18:26:51 +02001441 raw_spin_unlock_irqrestore(&bank->lock, flags);
Tarun Kanti DebBarma2dc983c2011-11-24 02:44:29 +05301442
1443 return 0;
1444}
Rafael J. Wysockiecb23122014-12-04 01:03:40 +01001445#endif /* CONFIG_PM */
Tarun Kanti DebBarma2dc983c2011-11-24 02:44:29 +05301446
Tony Lindgrencac089f2015-04-23 16:56:22 -07001447#if IS_BUILTIN(CONFIG_GPIO_OMAP)
Tarun Kanti DebBarma2dc983c2011-11-24 02:44:29 +05301448void omap2_gpio_prepare_for_idle(int pwr_mode)
Juha Yrjola3ac4fa92006-12-06 17:13:52 -08001449{
Charulatha V03e128c2011-05-05 19:58:01 +05301450 struct gpio_bank *bank;
Juha Yrjola3ac4fa92006-12-06 17:13:52 -08001451
Charulatha V03e128c2011-05-05 19:58:01 +05301452 list_for_each_entry(bank, &omap_gpio_list, node) {
Javier Martinez Canillasfa365e42013-09-25 02:36:52 +02001453 if (!BANK_USED(bank) || !bank->loses_context)
Charulatha V03e128c2011-05-05 19:58:01 +05301454 continue;
1455
Tarun Kanti DebBarma2dc983c2011-11-24 02:44:29 +05301456 bank->power_mode = pwr_mode;
1457
Grygorii Strashko7b1e5dc2016-03-04 17:25:35 +02001458 pm_runtime_put_sync_suspend(bank->chip.parent);
Juha Yrjola3ac4fa92006-12-06 17:13:52 -08001459 }
Juha Yrjola3ac4fa92006-12-06 17:13:52 -08001460}
1461
Kevin Hilman43ffcd92009-01-27 11:09:24 -08001462void omap2_gpio_resume_after_idle(void)
Juha Yrjola3ac4fa92006-12-06 17:13:52 -08001463{
Charulatha V03e128c2011-05-05 19:58:01 +05301464 struct gpio_bank *bank;
Juha Yrjola3ac4fa92006-12-06 17:13:52 -08001465
Charulatha V03e128c2011-05-05 19:58:01 +05301466 list_for_each_entry(bank, &omap_gpio_list, node) {
Javier Martinez Canillasfa365e42013-09-25 02:36:52 +02001467 if (!BANK_USED(bank) || !bank->loses_context)
Charulatha V03e128c2011-05-05 19:58:01 +05301468 continue;
1469
Grygorii Strashko7b1e5dc2016-03-04 17:25:35 +02001470 pm_runtime_get_sync(bank->chip.parent);
Juha Yrjola3ac4fa92006-12-06 17:13:52 -08001471 }
Juha Yrjola3ac4fa92006-12-06 17:13:52 -08001472}
Tony Lindgrencac089f2015-04-23 16:56:22 -07001473#endif
Juha Yrjola3ac4fa92006-12-06 17:13:52 -08001474
Rafael J. Wysockiecb23122014-12-04 01:03:40 +01001475#if defined(CONFIG_PM)
Jon Hunter352a2d52013-04-15 13:06:54 -05001476static void omap_gpio_init_context(struct gpio_bank *p)
1477{
1478 struct omap_gpio_reg_offs *regs = p->regs;
1479 void __iomem *base = p->base;
1480
Victor Kamensky661553b2013-11-16 02:01:04 +02001481 p->context.ctrl = readl_relaxed(base + regs->ctrl);
1482 p->context.oe = readl_relaxed(base + regs->direction);
1483 p->context.wake_en = readl_relaxed(base + regs->wkup_en);
1484 p->context.leveldetect0 = readl_relaxed(base + regs->leveldetect0);
1485 p->context.leveldetect1 = readl_relaxed(base + regs->leveldetect1);
1486 p->context.risingdetect = readl_relaxed(base + regs->risingdetect);
1487 p->context.fallingdetect = readl_relaxed(base + regs->fallingdetect);
1488 p->context.irqenable1 = readl_relaxed(base + regs->irqenable);
1489 p->context.irqenable2 = readl_relaxed(base + regs->irqenable2);
Jon Hunter352a2d52013-04-15 13:06:54 -05001490
1491 if (regs->set_dataout && p->regs->clr_dataout)
Victor Kamensky661553b2013-11-16 02:01:04 +02001492 p->context.dataout = readl_relaxed(base + regs->set_dataout);
Jon Hunter352a2d52013-04-15 13:06:54 -05001493 else
Victor Kamensky661553b2013-11-16 02:01:04 +02001494 p->context.dataout = readl_relaxed(base + regs->dataout);
Jon Hunter352a2d52013-04-15 13:06:54 -05001495
1496 p->context_valid = true;
1497}
1498
Tarun Kanti DebBarma60a34372011-09-29 04:47:25 +05301499static void omap_gpio_restore_context(struct gpio_bank *bank)
Rajendra Nayak40c670f2008-09-26 17:47:48 +05301500{
Victor Kamensky661553b2013-11-16 02:01:04 +02001501 writel_relaxed(bank->context.wake_en,
Tarun Kanti DebBarmaae10f232011-08-30 15:24:27 +05301502 bank->base + bank->regs->wkup_en);
Victor Kamensky661553b2013-11-16 02:01:04 +02001503 writel_relaxed(bank->context.ctrl, bank->base + bank->regs->ctrl);
1504 writel_relaxed(bank->context.leveldetect0,
Tarun Kanti DebBarmaae10f232011-08-30 15:24:27 +05301505 bank->base + bank->regs->leveldetect0);
Victor Kamensky661553b2013-11-16 02:01:04 +02001506 writel_relaxed(bank->context.leveldetect1,
Tarun Kanti DebBarmaae10f232011-08-30 15:24:27 +05301507 bank->base + bank->regs->leveldetect1);
Victor Kamensky661553b2013-11-16 02:01:04 +02001508 writel_relaxed(bank->context.risingdetect,
Tarun Kanti DebBarmaae10f232011-08-30 15:24:27 +05301509 bank->base + bank->regs->risingdetect);
Victor Kamensky661553b2013-11-16 02:01:04 +02001510 writel_relaxed(bank->context.fallingdetect,
Tarun Kanti DebBarmaae10f232011-08-30 15:24:27 +05301511 bank->base + bank->regs->fallingdetect);
Nishanth Menonf86bcc32011-09-09 19:14:08 +05301512 if (bank->regs->set_dataout && bank->regs->clr_dataout)
Victor Kamensky661553b2013-11-16 02:01:04 +02001513 writel_relaxed(bank->context.dataout,
Nishanth Menonf86bcc32011-09-09 19:14:08 +05301514 bank->base + bank->regs->set_dataout);
1515 else
Victor Kamensky661553b2013-11-16 02:01:04 +02001516 writel_relaxed(bank->context.dataout,
Nishanth Menonf86bcc32011-09-09 19:14:08 +05301517 bank->base + bank->regs->dataout);
Victor Kamensky661553b2013-11-16 02:01:04 +02001518 writel_relaxed(bank->context.oe, bank->base + bank->regs->direction);
Nishanth Menon6d13eaa2011-08-29 18:54:50 +05301519
Nishanth Menonae547352011-09-09 19:08:58 +05301520 if (bank->dbck_enable_mask) {
Victor Kamensky661553b2013-11-16 02:01:04 +02001521 writel_relaxed(bank->context.debounce, bank->base +
Nishanth Menonae547352011-09-09 19:08:58 +05301522 bank->regs->debounce);
Victor Kamensky661553b2013-11-16 02:01:04 +02001523 writel_relaxed(bank->context.debounce_en,
Nishanth Menonae547352011-09-09 19:08:58 +05301524 bank->base + bank->regs->debounce_en);
1525 }
Nishanth Menonba805be2011-08-29 18:41:08 +05301526
Victor Kamensky661553b2013-11-16 02:01:04 +02001527 writel_relaxed(bank->context.irqenable1,
Nishanth Menonba805be2011-08-29 18:41:08 +05301528 bank->base + bank->regs->irqenable);
Victor Kamensky661553b2013-11-16 02:01:04 +02001529 writel_relaxed(bank->context.irqenable2,
Nishanth Menonba805be2011-08-29 18:41:08 +05301530 bank->base + bank->regs->irqenable2);
Rajendra Nayak40c670f2008-09-26 17:47:48 +05301531}
Rafael J. Wysockiecb23122014-12-04 01:03:40 +01001532#endif /* CONFIG_PM */
Tarun Kanti DebBarma55b93c32011-09-29 07:23:22 +05301533#else
Tarun Kanti DebBarma2dc983c2011-11-24 02:44:29 +05301534#define omap_gpio_runtime_suspend NULL
1535#define omap_gpio_runtime_resume NULL
Arnd Bergmannea4a21a2013-05-31 17:59:46 +02001536static inline void omap_gpio_init_context(struct gpio_bank *p) {}
Rajendra Nayak40c670f2008-09-26 17:47:48 +05301537#endif
1538
Tarun Kanti DebBarma55b93c32011-09-29 07:23:22 +05301539static const struct dev_pm_ops gpio_pm_ops = {
Tarun Kanti DebBarma2dc983c2011-11-24 02:44:29 +05301540 SET_RUNTIME_PM_OPS(omap_gpio_runtime_suspend, omap_gpio_runtime_resume,
1541 NULL)
Tarun Kanti DebBarma55b93c32011-09-29 07:23:22 +05301542};
1543
Benoit Cousson384ebe12011-08-16 11:53:02 +02001544#if defined(CONFIG_OF)
1545static struct omap_gpio_reg_offs omap2_gpio_regs = {
1546 .revision = OMAP24XX_GPIO_REVISION,
1547 .direction = OMAP24XX_GPIO_OE,
1548 .datain = OMAP24XX_GPIO_DATAIN,
1549 .dataout = OMAP24XX_GPIO_DATAOUT,
1550 .set_dataout = OMAP24XX_GPIO_SETDATAOUT,
1551 .clr_dataout = OMAP24XX_GPIO_CLEARDATAOUT,
1552 .irqstatus = OMAP24XX_GPIO_IRQSTATUS1,
1553 .irqstatus2 = OMAP24XX_GPIO_IRQSTATUS2,
1554 .irqenable = OMAP24XX_GPIO_IRQENABLE1,
1555 .irqenable2 = OMAP24XX_GPIO_IRQENABLE2,
1556 .set_irqenable = OMAP24XX_GPIO_SETIRQENABLE1,
1557 .clr_irqenable = OMAP24XX_GPIO_CLEARIRQENABLE1,
1558 .debounce = OMAP24XX_GPIO_DEBOUNCE_VAL,
1559 .debounce_en = OMAP24XX_GPIO_DEBOUNCE_EN,
1560 .ctrl = OMAP24XX_GPIO_CTRL,
1561 .wkup_en = OMAP24XX_GPIO_WAKE_EN,
1562 .leveldetect0 = OMAP24XX_GPIO_LEVELDETECT0,
1563 .leveldetect1 = OMAP24XX_GPIO_LEVELDETECT1,
1564 .risingdetect = OMAP24XX_GPIO_RISINGDETECT,
1565 .fallingdetect = OMAP24XX_GPIO_FALLINGDETECT,
1566};
1567
1568static struct omap_gpio_reg_offs omap4_gpio_regs = {
1569 .revision = OMAP4_GPIO_REVISION,
1570 .direction = OMAP4_GPIO_OE,
1571 .datain = OMAP4_GPIO_DATAIN,
1572 .dataout = OMAP4_GPIO_DATAOUT,
1573 .set_dataout = OMAP4_GPIO_SETDATAOUT,
1574 .clr_dataout = OMAP4_GPIO_CLEARDATAOUT,
1575 .irqstatus = OMAP4_GPIO_IRQSTATUS0,
1576 .irqstatus2 = OMAP4_GPIO_IRQSTATUS1,
1577 .irqenable = OMAP4_GPIO_IRQSTATUSSET0,
1578 .irqenable2 = OMAP4_GPIO_IRQSTATUSSET1,
1579 .set_irqenable = OMAP4_GPIO_IRQSTATUSSET0,
1580 .clr_irqenable = OMAP4_GPIO_IRQSTATUSCLR0,
1581 .debounce = OMAP4_GPIO_DEBOUNCINGTIME,
1582 .debounce_en = OMAP4_GPIO_DEBOUNCENABLE,
1583 .ctrl = OMAP4_GPIO_CTRL,
1584 .wkup_en = OMAP4_GPIO_IRQWAKEN0,
1585 .leveldetect0 = OMAP4_GPIO_LEVELDETECT0,
1586 .leveldetect1 = OMAP4_GPIO_LEVELDETECT1,
1587 .risingdetect = OMAP4_GPIO_RISINGDETECT,
1588 .fallingdetect = OMAP4_GPIO_FALLINGDETECT,
1589};
1590
Chen Gange9a65bb2013-02-06 18:44:32 +08001591static const struct omap_gpio_platform_data omap2_pdata = {
Benoit Cousson384ebe12011-08-16 11:53:02 +02001592 .regs = &omap2_gpio_regs,
1593 .bank_width = 32,
1594 .dbck_flag = false,
1595};
1596
Chen Gange9a65bb2013-02-06 18:44:32 +08001597static const struct omap_gpio_platform_data omap3_pdata = {
Benoit Cousson384ebe12011-08-16 11:53:02 +02001598 .regs = &omap2_gpio_regs,
1599 .bank_width = 32,
1600 .dbck_flag = true,
1601};
1602
Chen Gange9a65bb2013-02-06 18:44:32 +08001603static const struct omap_gpio_platform_data omap4_pdata = {
Benoit Cousson384ebe12011-08-16 11:53:02 +02001604 .regs = &omap4_gpio_regs,
1605 .bank_width = 32,
1606 .dbck_flag = true,
1607};
1608
1609static const struct of_device_id omap_gpio_match[] = {
1610 {
1611 .compatible = "ti,omap4-gpio",
1612 .data = &omap4_pdata,
1613 },
1614 {
1615 .compatible = "ti,omap3-gpio",
1616 .data = &omap3_pdata,
1617 },
1618 {
1619 .compatible = "ti,omap2-gpio",
1620 .data = &omap2_pdata,
1621 },
1622 { },
1623};
1624MODULE_DEVICE_TABLE(of, omap_gpio_match);
1625#endif
1626
Varadarajan, Charulatha77640aa2010-12-07 16:26:57 -08001627static struct platform_driver omap_gpio_driver = {
1628 .probe = omap_gpio_probe,
Tony Lindgrencac089f2015-04-23 16:56:22 -07001629 .remove = omap_gpio_remove,
Varadarajan, Charulatha77640aa2010-12-07 16:26:57 -08001630 .driver = {
1631 .name = "omap_gpio",
Tarun Kanti DebBarma55b93c32011-09-29 07:23:22 +05301632 .pm = &gpio_pm_ops,
Benoit Cousson384ebe12011-08-16 11:53:02 +02001633 .of_match_table = of_match_ptr(omap_gpio_match),
Varadarajan, Charulatha77640aa2010-12-07 16:26:57 -08001634 },
1635};
1636
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +01001637/*
Varadarajan, Charulatha77640aa2010-12-07 16:26:57 -08001638 * gpio driver register needs to be done before
1639 * machine_init functions access gpio APIs.
1640 * Hence omap_gpio_drv_reg() is a postcore_initcall.
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +01001641 */
Varadarajan, Charulatha77640aa2010-12-07 16:26:57 -08001642static int __init omap_gpio_drv_reg(void)
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +01001643{
Varadarajan, Charulatha77640aa2010-12-07 16:26:57 -08001644 return platform_driver_register(&omap_gpio_driver);
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +01001645}
Varadarajan, Charulatha77640aa2010-12-07 16:26:57 -08001646postcore_initcall(omap_gpio_drv_reg);
Tony Lindgrencac089f2015-04-23 16:56:22 -07001647
1648static void __exit omap_gpio_exit(void)
1649{
1650 platform_driver_unregister(&omap_gpio_driver);
1651}
1652module_exit(omap_gpio_exit);
1653
1654MODULE_DESCRIPTION("omap gpio driver");
1655MODULE_ALIAS("platform:gpio-omap");
1656MODULE_LICENSE("GPL v2");