blob: 661b0e34e0672eedba9e7896c742944aeda18477 [file] [log] [blame]
Erik Gilling3c92db92010-03-15 19:40:06 -07001/*
2 * arch/arm/mach-tegra/gpio.c
3 *
4 * Copyright (c) 2010 Google, Inc
5 *
6 * Author:
7 * Erik Gilling <konkers@google.com>
8 *
9 * This software is licensed under the terms of the GNU General Public
10 * License version 2, as published by the Free Software Foundation, and
11 * may be copied, distributed, and modified under those terms.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 */
19
Thierry Reding641d0342013-01-21 11:09:01 +010020#include <linux/err.h>
Erik Gilling3c92db92010-03-15 19:40:06 -070021#include <linux/init.h>
22#include <linux/irq.h>
Colin Cross2e47b8b2010-04-07 12:59:42 -070023#include <linux/interrupt.h>
Erik Gilling3c92db92010-03-15 19:40:06 -070024#include <linux/io.h>
25#include <linux/gpio.h>
Stephen Warren5c1e2c92012-03-16 17:35:08 -060026#include <linux/of_device.h>
Stephen Warren88d89512011-10-11 16:16:14 -060027#include <linux/platform_device.h>
28#include <linux/module.h>
Stephen Warren6f74dc92012-01-04 08:39:37 +000029#include <linux/irqdomain.h>
Catalin Marinasde88cbb2013-01-18 15:31:37 +000030#include <linux/irqchip/chained_irq.h>
Stephen Warren3e215d02012-02-18 01:04:55 -070031#include <linux/pinctrl/consumer.h>
Laxman Dewangan8939ddc2012-11-07 20:31:32 +053032#include <linux/pm.h>
Erik Gilling3c92db92010-03-15 19:40:06 -070033
Erik Gilling3c92db92010-03-15 19:40:06 -070034#define GPIO_BANK(x) ((x) >> 5)
35#define GPIO_PORT(x) (((x) >> 3) & 0x3)
36#define GPIO_BIT(x) ((x) & 0x7)
37
Laxman Dewanganb546be02016-04-25 16:08:33 +053038#define GPIO_REG(tgi, x) (GPIO_BANK(x) * tgi->soc->bank_stride + \
Stephen Warren5c1e2c92012-03-16 17:35:08 -060039 GPIO_PORT(x) * 4)
Erik Gilling3c92db92010-03-15 19:40:06 -070040
Laxman Dewanganb546be02016-04-25 16:08:33 +053041#define GPIO_CNF(t, x) (GPIO_REG(t, x) + 0x00)
42#define GPIO_OE(t, x) (GPIO_REG(t, x) + 0x10)
43#define GPIO_OUT(t, x) (GPIO_REG(t, x) + 0X20)
44#define GPIO_IN(t, x) (GPIO_REG(t, x) + 0x30)
45#define GPIO_INT_STA(t, x) (GPIO_REG(t, x) + 0x40)
46#define GPIO_INT_ENB(t, x) (GPIO_REG(t, x) + 0x50)
47#define GPIO_INT_LVL(t, x) (GPIO_REG(t, x) + 0x60)
48#define GPIO_INT_CLR(t, x) (GPIO_REG(t, x) + 0x70)
Laxman Dewangan3737de42016-04-25 16:08:34 +053049#define GPIO_DBC_CNT(t, x) (GPIO_REG(t, x) + 0xF0)
50
Erik Gilling3c92db92010-03-15 19:40:06 -070051
Laxman Dewanganb546be02016-04-25 16:08:33 +053052#define GPIO_MSK_CNF(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x00)
53#define GPIO_MSK_OE(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x10)
54#define GPIO_MSK_OUT(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0X20)
Laxman Dewangan3737de42016-04-25 16:08:34 +053055#define GPIO_MSK_DBC_EN(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x30)
Laxman Dewanganb546be02016-04-25 16:08:33 +053056#define GPIO_MSK_INT_STA(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x40)
57#define GPIO_MSK_INT_ENB(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x50)
58#define GPIO_MSK_INT_LVL(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x60)
Erik Gilling3c92db92010-03-15 19:40:06 -070059
60#define GPIO_INT_LVL_MASK 0x010101
61#define GPIO_INT_LVL_EDGE_RISING 0x000101
62#define GPIO_INT_LVL_EDGE_FALLING 0x000100
63#define GPIO_INT_LVL_EDGE_BOTH 0x010100
64#define GPIO_INT_LVL_LEVEL_HIGH 0x000001
65#define GPIO_INT_LVL_LEVEL_LOW 0x000000
66
Laxman Dewanganb546be02016-04-25 16:08:33 +053067struct tegra_gpio_info;
68
Erik Gilling3c92db92010-03-15 19:40:06 -070069struct tegra_gpio_bank {
70 int bank;
71 int irq;
72 spinlock_t lvl_lock[4];
Laxman Dewangan3737de42016-04-25 16:08:34 +053073 spinlock_t dbc_lock[4]; /* Lock for updating debounce count register */
Laxman Dewangan8939ddc2012-11-07 20:31:32 +053074#ifdef CONFIG_PM_SLEEP
Colin Cross2e47b8b2010-04-07 12:59:42 -070075 u32 cnf[4];
76 u32 out[4];
77 u32 oe[4];
78 u32 int_enb[4];
79 u32 int_lvl[4];
Joseph Lo203f31c2013-04-03 19:31:44 +080080 u32 wake_enb[4];
Laxman Dewangan3737de42016-04-25 16:08:34 +053081 u32 dbc_enb[4];
Colin Cross2e47b8b2010-04-07 12:59:42 -070082#endif
Laxman Dewangan3737de42016-04-25 16:08:34 +053083 u32 dbc_cnt[4];
Laxman Dewanganb546be02016-04-25 16:08:33 +053084 struct tegra_gpio_info *tgi;
Erik Gilling3c92db92010-03-15 19:40:06 -070085};
86
Laxman Dewangan171b92c2016-04-25 16:08:31 +053087struct tegra_gpio_soc_config {
Laxman Dewangan3737de42016-04-25 16:08:34 +053088 bool debounce_supported;
Laxman Dewangan171b92c2016-04-25 16:08:31 +053089 u32 bank_stride;
90 u32 upper_offset;
91};
92
Laxman Dewanganb546be02016-04-25 16:08:33 +053093struct tegra_gpio_info {
94 struct device *dev;
95 void __iomem *regs;
96 struct irq_domain *irq_domain;
97 struct tegra_gpio_bank *bank_info;
98 const struct tegra_gpio_soc_config *soc;
99 struct gpio_chip gc;
100 struct irq_chip ic;
Laxman Dewanganb546be02016-04-25 16:08:33 +0530101 u32 bank_count;
102};
Stephen Warren88d89512011-10-11 16:16:14 -0600103
Laxman Dewanganb546be02016-04-25 16:08:33 +0530104static inline void tegra_gpio_writel(struct tegra_gpio_info *tgi,
105 u32 val, u32 reg)
Stephen Warren88d89512011-10-11 16:16:14 -0600106{
Laxman Dewanganb546be02016-04-25 16:08:33 +0530107 __raw_writel(val, tgi->regs + reg);
Stephen Warren88d89512011-10-11 16:16:14 -0600108}
109
Laxman Dewanganb546be02016-04-25 16:08:33 +0530110static inline u32 tegra_gpio_readl(struct tegra_gpio_info *tgi, u32 reg)
Stephen Warren88d89512011-10-11 16:16:14 -0600111{
Laxman Dewanganb546be02016-04-25 16:08:33 +0530112 return __raw_readl(tgi->regs + reg);
Stephen Warren88d89512011-10-11 16:16:14 -0600113}
Erik Gilling3c92db92010-03-15 19:40:06 -0700114
115static int tegra_gpio_compose(int bank, int port, int bit)
116{
117 return (bank << 5) | ((port & 0x3) << 3) | (bit & 0x7);
118}
119
Laxman Dewanganb546be02016-04-25 16:08:33 +0530120static void tegra_gpio_mask_write(struct tegra_gpio_info *tgi, u32 reg,
121 int gpio, int value)
Erik Gilling3c92db92010-03-15 19:40:06 -0700122{
123 u32 val;
124
125 val = 0x100 << GPIO_BIT(gpio);
126 if (value)
127 val |= 1 << GPIO_BIT(gpio);
Laxman Dewanganb546be02016-04-25 16:08:33 +0530128 tegra_gpio_writel(tgi, val, reg);
Erik Gilling3c92db92010-03-15 19:40:06 -0700129}
130
Laxman Dewanganb546be02016-04-25 16:08:33 +0530131static void tegra_gpio_enable(struct tegra_gpio_info *tgi, int gpio)
Erik Gilling3c92db92010-03-15 19:40:06 -0700132{
Laxman Dewanganb546be02016-04-25 16:08:33 +0530133 tegra_gpio_mask_write(tgi, GPIO_MSK_CNF(tgi, gpio), gpio, 1);
Erik Gilling3c92db92010-03-15 19:40:06 -0700134}
135
Laxman Dewanganb546be02016-04-25 16:08:33 +0530136static void tegra_gpio_disable(struct tegra_gpio_info *tgi, int gpio)
Erik Gilling3c92db92010-03-15 19:40:06 -0700137{
Laxman Dewanganb546be02016-04-25 16:08:33 +0530138 tegra_gpio_mask_write(tgi, GPIO_MSK_CNF(tgi, gpio), gpio, 0);
Erik Gilling3c92db92010-03-15 19:40:06 -0700139}
140
Axel Lin924a0982012-11-08 10:45:24 +0800141static int tegra_gpio_request(struct gpio_chip *chip, unsigned offset)
Stephen Warren3e215d02012-02-18 01:04:55 -0700142{
143 return pinctrl_request_gpio(offset);
144}
145
Axel Lin924a0982012-11-08 10:45:24 +0800146static void tegra_gpio_free(struct gpio_chip *chip, unsigned offset)
Stephen Warren3e215d02012-02-18 01:04:55 -0700147{
Laxman Dewanganb546be02016-04-25 16:08:33 +0530148 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
149
Stephen Warren3e215d02012-02-18 01:04:55 -0700150 pinctrl_free_gpio(offset);
Laxman Dewanganb546be02016-04-25 16:08:33 +0530151 tegra_gpio_disable(tgi, offset);
Stephen Warren3e215d02012-02-18 01:04:55 -0700152}
153
Erik Gilling3c92db92010-03-15 19:40:06 -0700154static void tegra_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
155{
Laxman Dewanganb546be02016-04-25 16:08:33 +0530156 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
157
158 tegra_gpio_mask_write(tgi, GPIO_MSK_OUT(tgi, offset), offset, value);
Erik Gilling3c92db92010-03-15 19:40:06 -0700159}
160
161static int tegra_gpio_get(struct gpio_chip *chip, unsigned offset)
162{
Laxman Dewanganb546be02016-04-25 16:08:33 +0530163 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
164 int bval = BIT(GPIO_BIT(offset));
Laxman Dewangan195812e2012-11-09 11:34:20 +0530165
Laxman Dewanganb546be02016-04-25 16:08:33 +0530166 /* If gpio is in output mode then read from the out value */
167 if (tegra_gpio_readl(tgi, GPIO_OE(tgi, offset)) & bval)
168 return !!(tegra_gpio_readl(tgi, GPIO_OUT(tgi, offset)) & bval);
169
170 return !!(tegra_gpio_readl(tgi, GPIO_IN(tgi, offset)) & bval);
Erik Gilling3c92db92010-03-15 19:40:06 -0700171}
172
173static int tegra_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
174{
Laxman Dewanganb546be02016-04-25 16:08:33 +0530175 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
176
177 tegra_gpio_mask_write(tgi, GPIO_MSK_OE(tgi, offset), offset, 0);
178 tegra_gpio_enable(tgi, offset);
Erik Gilling3c92db92010-03-15 19:40:06 -0700179 return 0;
180}
181
182static int tegra_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
183 int value)
184{
Laxman Dewanganb546be02016-04-25 16:08:33 +0530185 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
186
Erik Gilling3c92db92010-03-15 19:40:06 -0700187 tegra_gpio_set(chip, offset, value);
Laxman Dewanganb546be02016-04-25 16:08:33 +0530188 tegra_gpio_mask_write(tgi, GPIO_MSK_OE(tgi, offset), offset, 1);
189 tegra_gpio_enable(tgi, offset);
Erik Gilling3c92db92010-03-15 19:40:06 -0700190 return 0;
191}
192
Laxman Dewanganf002d072016-04-29 21:55:23 +0530193static int tegra_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
194{
195 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
196 u32 pin_mask = BIT(GPIO_BIT(offset));
197 u32 cnf, oe;
198
199 cnf = tegra_gpio_readl(tgi, GPIO_CNF(tgi, offset));
200 if (!(cnf & pin_mask))
201 return -EINVAL;
202
203 oe = tegra_gpio_readl(tgi, GPIO_OE(tgi, offset));
204
205 return (oe & pin_mask) ? GPIOF_DIR_OUT : GPIOF_DIR_IN;
206}
207
Laxman Dewangan3737de42016-04-25 16:08:34 +0530208static int tegra_gpio_set_debounce(struct gpio_chip *chip, unsigned int offset,
209 unsigned int debounce)
210{
211 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
212 struct tegra_gpio_bank *bank = &tgi->bank_info[GPIO_BANK(offset)];
213 unsigned int debounce_ms = DIV_ROUND_UP(debounce, 1000);
214 unsigned long flags;
215 int port;
216
217 if (!debounce_ms) {
218 tegra_gpio_mask_write(tgi, GPIO_MSK_DBC_EN(tgi, offset),
219 offset, 0);
220 return 0;
221 }
222
223 debounce_ms = min(debounce_ms, 255U);
224 port = GPIO_PORT(offset);
225
226 /* There is only one debounce count register per port and hence
227 * set the maximum of current and requested debounce time.
228 */
229 spin_lock_irqsave(&bank->dbc_lock[port], flags);
230 if (bank->dbc_cnt[port] < debounce_ms) {
231 tegra_gpio_writel(tgi, debounce_ms, GPIO_DBC_CNT(tgi, offset));
232 bank->dbc_cnt[port] = debounce_ms;
233 }
234 spin_unlock_irqrestore(&bank->dbc_lock[port], flags);
235
236 tegra_gpio_mask_write(tgi, GPIO_MSK_DBC_EN(tgi, offset), offset, 1);
237
238 return 0;
239}
240
Stephen Warren438a99c2011-08-23 00:39:56 +0100241static int tegra_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
242{
Laxman Dewanganb546be02016-04-25 16:08:33 +0530243 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
Erik Gilling3c92db92010-03-15 19:40:06 -0700244
Laxman Dewanganb546be02016-04-25 16:08:33 +0530245 return irq_find_mapping(tgi->irq_domain, offset);
246}
Erik Gilling3c92db92010-03-15 19:40:06 -0700247
Lennert Buytenhek37337a82010-11-29 11:14:46 +0100248static void tegra_gpio_irq_ack(struct irq_data *d)
Erik Gilling3c92db92010-03-15 19:40:06 -0700249{
Laxman Dewanganb546be02016-04-25 16:08:33 +0530250 struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
251 struct tegra_gpio_info *tgi = bank->tgi;
Stephen Warren6f74dc92012-01-04 08:39:37 +0000252 int gpio = d->hwirq;
Erik Gilling3c92db92010-03-15 19:40:06 -0700253
Laxman Dewanganb546be02016-04-25 16:08:33 +0530254 tegra_gpio_writel(tgi, 1 << GPIO_BIT(gpio), GPIO_INT_CLR(tgi, gpio));
Erik Gilling3c92db92010-03-15 19:40:06 -0700255}
256
Lennert Buytenhek37337a82010-11-29 11:14:46 +0100257static void tegra_gpio_irq_mask(struct irq_data *d)
Erik Gilling3c92db92010-03-15 19:40:06 -0700258{
Laxman Dewanganb546be02016-04-25 16:08:33 +0530259 struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
260 struct tegra_gpio_info *tgi = bank->tgi;
Stephen Warren6f74dc92012-01-04 08:39:37 +0000261 int gpio = d->hwirq;
Erik Gilling3c92db92010-03-15 19:40:06 -0700262
Laxman Dewanganb546be02016-04-25 16:08:33 +0530263 tegra_gpio_mask_write(tgi, GPIO_MSK_INT_ENB(tgi, gpio), gpio, 0);
Erik Gilling3c92db92010-03-15 19:40:06 -0700264}
265
Lennert Buytenhek37337a82010-11-29 11:14:46 +0100266static void tegra_gpio_irq_unmask(struct irq_data *d)
Erik Gilling3c92db92010-03-15 19:40:06 -0700267{
Laxman Dewanganb546be02016-04-25 16:08:33 +0530268 struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
269 struct tegra_gpio_info *tgi = bank->tgi;
Stephen Warren6f74dc92012-01-04 08:39:37 +0000270 int gpio = d->hwirq;
Erik Gilling3c92db92010-03-15 19:40:06 -0700271
Laxman Dewanganb546be02016-04-25 16:08:33 +0530272 tegra_gpio_mask_write(tgi, GPIO_MSK_INT_ENB(tgi, gpio), gpio, 1);
Erik Gilling3c92db92010-03-15 19:40:06 -0700273}
274
Lennert Buytenhek37337a82010-11-29 11:14:46 +0100275static int tegra_gpio_irq_set_type(struct irq_data *d, unsigned int type)
Erik Gilling3c92db92010-03-15 19:40:06 -0700276{
Stephen Warren6f74dc92012-01-04 08:39:37 +0000277 int gpio = d->hwirq;
Lennert Buytenhek37337a82010-11-29 11:14:46 +0100278 struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
Laxman Dewanganb546be02016-04-25 16:08:33 +0530279 struct tegra_gpio_info *tgi = bank->tgi;
Erik Gilling3c92db92010-03-15 19:40:06 -0700280 int port = GPIO_PORT(gpio);
281 int lvl_type;
282 int val;
283 unsigned long flags;
Stephen Warrendf231f22013-10-16 13:25:33 -0600284 int ret;
Erik Gilling3c92db92010-03-15 19:40:06 -0700285
286 switch (type & IRQ_TYPE_SENSE_MASK) {
287 case IRQ_TYPE_EDGE_RISING:
288 lvl_type = GPIO_INT_LVL_EDGE_RISING;
289 break;
290
291 case IRQ_TYPE_EDGE_FALLING:
292 lvl_type = GPIO_INT_LVL_EDGE_FALLING;
293 break;
294
295 case IRQ_TYPE_EDGE_BOTH:
296 lvl_type = GPIO_INT_LVL_EDGE_BOTH;
297 break;
298
299 case IRQ_TYPE_LEVEL_HIGH:
300 lvl_type = GPIO_INT_LVL_LEVEL_HIGH;
301 break;
302
303 case IRQ_TYPE_LEVEL_LOW:
304 lvl_type = GPIO_INT_LVL_LEVEL_LOW;
305 break;
306
307 default:
308 return -EINVAL;
309 }
310
Laxman Dewanganb546be02016-04-25 16:08:33 +0530311 ret = gpiochip_lock_as_irq(&tgi->gc, gpio);
Stephen Warrendf231f22013-10-16 13:25:33 -0600312 if (ret) {
Laxman Dewanganb546be02016-04-25 16:08:33 +0530313 dev_err(tgi->dev,
314 "unable to lock Tegra GPIO %d as IRQ\n", gpio);
Stephen Warrendf231f22013-10-16 13:25:33 -0600315 return ret;
316 }
317
Erik Gilling3c92db92010-03-15 19:40:06 -0700318 spin_lock_irqsave(&bank->lvl_lock[port], flags);
319
Laxman Dewanganb546be02016-04-25 16:08:33 +0530320 val = tegra_gpio_readl(tgi, GPIO_INT_LVL(tgi, gpio));
Erik Gilling3c92db92010-03-15 19:40:06 -0700321 val &= ~(GPIO_INT_LVL_MASK << GPIO_BIT(gpio));
322 val |= lvl_type << GPIO_BIT(gpio);
Laxman Dewanganb546be02016-04-25 16:08:33 +0530323 tegra_gpio_writel(tgi, val, GPIO_INT_LVL(tgi, gpio));
Erik Gilling3c92db92010-03-15 19:40:06 -0700324
325 spin_unlock_irqrestore(&bank->lvl_lock[port], flags);
326
Laxman Dewanganb546be02016-04-25 16:08:33 +0530327 tegra_gpio_mask_write(tgi, GPIO_MSK_OE(tgi, gpio), gpio, 0);
328 tegra_gpio_enable(tgi, gpio);
Stephen Warrend9411362012-03-19 10:31:58 -0600329
Erik Gilling3c92db92010-03-15 19:40:06 -0700330 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
Thomas Gleixnerf170d712015-06-23 15:52:40 +0200331 irq_set_handler_locked(d, handle_level_irq);
Erik Gilling3c92db92010-03-15 19:40:06 -0700332 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
Thomas Gleixnerf170d712015-06-23 15:52:40 +0200333 irq_set_handler_locked(d, handle_edge_irq);
Erik Gilling3c92db92010-03-15 19:40:06 -0700334
335 return 0;
336}
337
Stephen Warrendf231f22013-10-16 13:25:33 -0600338static void tegra_gpio_irq_shutdown(struct irq_data *d)
339{
Laxman Dewanganb546be02016-04-25 16:08:33 +0530340 struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
341 struct tegra_gpio_info *tgi = bank->tgi;
Stephen Warrendf231f22013-10-16 13:25:33 -0600342 int gpio = d->hwirq;
343
Laxman Dewanganb546be02016-04-25 16:08:33 +0530344 gpiochip_unlock_as_irq(&tgi->gc, gpio);
Stephen Warrendf231f22013-10-16 13:25:33 -0600345}
346
Thomas Gleixnerbd0b9ac2015-09-14 10:42:37 +0200347static void tegra_gpio_irq_handler(struct irq_desc *desc)
Erik Gilling3c92db92010-03-15 19:40:06 -0700348{
Erik Gilling3c92db92010-03-15 19:40:06 -0700349 int port;
350 int pin;
351 int unmasked = 0;
Laxman Dewanganb546be02016-04-25 16:08:33 +0530352 int gpio;
353 u32 lvl;
354 unsigned long sta;
Will Deacon98022942011-02-21 13:58:10 +0000355 struct irq_chip *chip = irq_desc_get_chip(desc);
Jiang Liu476f8b42015-06-04 12:13:15 +0800356 struct tegra_gpio_bank *bank = irq_desc_get_handler_data(desc);
Laxman Dewanganb546be02016-04-25 16:08:33 +0530357 struct tegra_gpio_info *tgi = bank->tgi;
Erik Gilling3c92db92010-03-15 19:40:06 -0700358
Will Deacon98022942011-02-21 13:58:10 +0000359 chained_irq_enter(chip, desc);
Erik Gilling3c92db92010-03-15 19:40:06 -0700360
Erik Gilling3c92db92010-03-15 19:40:06 -0700361 for (port = 0; port < 4; port++) {
Laxman Dewanganb546be02016-04-25 16:08:33 +0530362 gpio = tegra_gpio_compose(bank->bank, port, 0);
363 sta = tegra_gpio_readl(tgi, GPIO_INT_STA(tgi, gpio)) &
364 tegra_gpio_readl(tgi, GPIO_INT_ENB(tgi, gpio));
365 lvl = tegra_gpio_readl(tgi, GPIO_INT_LVL(tgi, gpio));
Erik Gilling3c92db92010-03-15 19:40:06 -0700366
367 for_each_set_bit(pin, &sta, 8) {
Laxman Dewanganb546be02016-04-25 16:08:33 +0530368 tegra_gpio_writel(tgi, 1 << pin,
369 GPIO_INT_CLR(tgi, gpio));
Erik Gilling3c92db92010-03-15 19:40:06 -0700370
371 /* if gpio is edge triggered, clear condition
Colin Cronin20a8a962015-05-18 11:41:43 -0700372 * before executing the handler so that we don't
Erik Gilling3c92db92010-03-15 19:40:06 -0700373 * miss edges
374 */
375 if (lvl & (0x100 << pin)) {
376 unmasked = 1;
Will Deacon98022942011-02-21 13:58:10 +0000377 chained_irq_exit(chip, desc);
Erik Gilling3c92db92010-03-15 19:40:06 -0700378 }
379
380 generic_handle_irq(gpio_to_irq(gpio + pin));
381 }
382 }
383
384 if (!unmasked)
Will Deacon98022942011-02-21 13:58:10 +0000385 chained_irq_exit(chip, desc);
Erik Gilling3c92db92010-03-15 19:40:06 -0700386
387}
388
Laxman Dewangan8939ddc2012-11-07 20:31:32 +0530389#ifdef CONFIG_PM_SLEEP
390static int tegra_gpio_resume(struct device *dev)
Colin Cross2e47b8b2010-04-07 12:59:42 -0700391{
Laxman Dewanganb546be02016-04-25 16:08:33 +0530392 struct platform_device *pdev = to_platform_device(dev);
393 struct tegra_gpio_info *tgi = platform_get_drvdata(pdev);
Colin Cross2e47b8b2010-04-07 12:59:42 -0700394 unsigned long flags;
Colin Crossc8309ef2011-03-30 00:24:43 -0700395 int b;
396 int p;
Colin Cross2e47b8b2010-04-07 12:59:42 -0700397
398 local_irq_save(flags);
399
Laxman Dewanganb546be02016-04-25 16:08:33 +0530400 for (b = 0; b < tgi->bank_count; b++) {
401 struct tegra_gpio_bank *bank = &tgi->bank_info[b];
Colin Cross2e47b8b2010-04-07 12:59:42 -0700402
403 for (p = 0; p < ARRAY_SIZE(bank->oe); p++) {
404 unsigned int gpio = (b<<5) | (p<<3);
Laxman Dewanganb546be02016-04-25 16:08:33 +0530405 tegra_gpio_writel(tgi, bank->cnf[p],
406 GPIO_CNF(tgi, gpio));
Laxman Dewangan3737de42016-04-25 16:08:34 +0530407
408 if (tgi->soc->debounce_supported) {
409 tegra_gpio_writel(tgi, bank->dbc_cnt[p],
410 GPIO_DBC_CNT(tgi, gpio));
411 tegra_gpio_writel(tgi, bank->dbc_enb[p],
412 GPIO_MSK_DBC_EN(tgi, gpio));
413 }
414
Laxman Dewanganb546be02016-04-25 16:08:33 +0530415 tegra_gpio_writel(tgi, bank->out[p],
416 GPIO_OUT(tgi, gpio));
417 tegra_gpio_writel(tgi, bank->oe[p],
418 GPIO_OE(tgi, gpio));
419 tegra_gpio_writel(tgi, bank->int_lvl[p],
420 GPIO_INT_LVL(tgi, gpio));
421 tegra_gpio_writel(tgi, bank->int_enb[p],
422 GPIO_INT_ENB(tgi, gpio));
Colin Cross2e47b8b2010-04-07 12:59:42 -0700423 }
424 }
425
426 local_irq_restore(flags);
Laxman Dewangan8939ddc2012-11-07 20:31:32 +0530427 return 0;
Colin Cross2e47b8b2010-04-07 12:59:42 -0700428}
429
Laxman Dewangan8939ddc2012-11-07 20:31:32 +0530430static int tegra_gpio_suspend(struct device *dev)
Colin Cross2e47b8b2010-04-07 12:59:42 -0700431{
Laxman Dewanganb546be02016-04-25 16:08:33 +0530432 struct platform_device *pdev = to_platform_device(dev);
433 struct tegra_gpio_info *tgi = platform_get_drvdata(pdev);
Colin Cross2e47b8b2010-04-07 12:59:42 -0700434 unsigned long flags;
Colin Crossc8309ef2011-03-30 00:24:43 -0700435 int b;
436 int p;
Colin Cross2e47b8b2010-04-07 12:59:42 -0700437
Colin Cross2e47b8b2010-04-07 12:59:42 -0700438 local_irq_save(flags);
Laxman Dewanganb546be02016-04-25 16:08:33 +0530439 for (b = 0; b < tgi->bank_count; b++) {
440 struct tegra_gpio_bank *bank = &tgi->bank_info[b];
Colin Cross2e47b8b2010-04-07 12:59:42 -0700441
442 for (p = 0; p < ARRAY_SIZE(bank->oe); p++) {
443 unsigned int gpio = (b<<5) | (p<<3);
Laxman Dewanganb546be02016-04-25 16:08:33 +0530444 bank->cnf[p] = tegra_gpio_readl(tgi,
445 GPIO_CNF(tgi, gpio));
446 bank->out[p] = tegra_gpio_readl(tgi,
447 GPIO_OUT(tgi, gpio));
448 bank->oe[p] = tegra_gpio_readl(tgi,
449 GPIO_OE(tgi, gpio));
Laxman Dewangan3737de42016-04-25 16:08:34 +0530450 if (tgi->soc->debounce_supported) {
451 bank->dbc_enb[p] = tegra_gpio_readl(tgi,
452 GPIO_MSK_DBC_EN(tgi, gpio));
453 bank->dbc_enb[p] = (bank->dbc_enb[p] << 8) |
454 bank->dbc_enb[p];
455 }
456
Laxman Dewanganb546be02016-04-25 16:08:33 +0530457 bank->int_enb[p] = tegra_gpio_readl(tgi,
458 GPIO_INT_ENB(tgi, gpio));
459 bank->int_lvl[p] = tegra_gpio_readl(tgi,
460 GPIO_INT_LVL(tgi, gpio));
Joseph Lo203f31c2013-04-03 19:31:44 +0800461
462 /* Enable gpio irq for wake up source */
Laxman Dewanganb546be02016-04-25 16:08:33 +0530463 tegra_gpio_writel(tgi, bank->wake_enb[p],
464 GPIO_INT_ENB(tgi, gpio));
Colin Cross2e47b8b2010-04-07 12:59:42 -0700465 }
466 }
467 local_irq_restore(flags);
Laxman Dewangan8939ddc2012-11-07 20:31:32 +0530468 return 0;
Colin Cross2e47b8b2010-04-07 12:59:42 -0700469}
470
Joseph Lo203f31c2013-04-03 19:31:44 +0800471static int tegra_gpio_irq_set_wake(struct irq_data *d, unsigned int enable)
Colin Cross2e47b8b2010-04-07 12:59:42 -0700472{
Lennert Buytenhek37337a82010-11-29 11:14:46 +0100473 struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
Joseph Lo203f31c2013-04-03 19:31:44 +0800474 int gpio = d->hwirq;
475 u32 port, bit, mask;
476
477 port = GPIO_PORT(gpio);
478 bit = GPIO_BIT(gpio);
479 mask = BIT(bit);
480
481 if (enable)
482 bank->wake_enb[port] |= mask;
483 else
484 bank->wake_enb[port] &= ~mask;
485
Thomas Gleixner6845664a2011-03-24 13:25:22 +0100486 return irq_set_irq_wake(bank->irq, enable);
Colin Cross2e47b8b2010-04-07 12:59:42 -0700487}
488#endif
Erik Gilling3c92db92010-03-15 19:40:06 -0700489
Suzuki K. Pouloseb59d5fb2015-11-16 16:07:10 +0000490#ifdef CONFIG_DEBUG_FS
491
492#include <linux/debugfs.h>
493#include <linux/seq_file.h>
494
495static int dbg_gpio_show(struct seq_file *s, void *unused)
496{
Laxman Dewanganb546be02016-04-25 16:08:33 +0530497 struct tegra_gpio_info *tgi = s->private;
Suzuki K. Pouloseb59d5fb2015-11-16 16:07:10 +0000498 int i;
499 int j;
500
Laxman Dewanganb546be02016-04-25 16:08:33 +0530501 for (i = 0; i < tgi->bank_count; i++) {
Suzuki K. Pouloseb59d5fb2015-11-16 16:07:10 +0000502 for (j = 0; j < 4; j++) {
503 int gpio = tegra_gpio_compose(i, j, 0);
504 seq_printf(s,
505 "%d:%d %02x %02x %02x %02x %02x %02x %06x\n",
506 i, j,
Laxman Dewanganb546be02016-04-25 16:08:33 +0530507 tegra_gpio_readl(tgi, GPIO_CNF(tgi, gpio)),
508 tegra_gpio_readl(tgi, GPIO_OE(tgi, gpio)),
509 tegra_gpio_readl(tgi, GPIO_OUT(tgi, gpio)),
510 tegra_gpio_readl(tgi, GPIO_IN(tgi, gpio)),
511 tegra_gpio_readl(tgi, GPIO_INT_STA(tgi, gpio)),
512 tegra_gpio_readl(tgi, GPIO_INT_ENB(tgi, gpio)),
513 tegra_gpio_readl(tgi, GPIO_INT_LVL(tgi, gpio)));
Suzuki K. Pouloseb59d5fb2015-11-16 16:07:10 +0000514 }
515 }
516 return 0;
517}
518
519static int dbg_gpio_open(struct inode *inode, struct file *file)
520{
Laxman Dewanganb546be02016-04-25 16:08:33 +0530521 return single_open(file, dbg_gpio_show, inode->i_private);
Suzuki K. Pouloseb59d5fb2015-11-16 16:07:10 +0000522}
523
524static const struct file_operations debug_fops = {
525 .open = dbg_gpio_open,
526 .read = seq_read,
527 .llseek = seq_lseek,
528 .release = single_release,
529};
530
Laxman Dewanganb546be02016-04-25 16:08:33 +0530531static void tegra_gpio_debuginit(struct tegra_gpio_info *tgi)
Suzuki K. Pouloseb59d5fb2015-11-16 16:07:10 +0000532{
533 (void) debugfs_create_file("tegra_gpio", S_IRUGO,
Laxman Dewanganb546be02016-04-25 16:08:33 +0530534 NULL, tgi, &debug_fops);
Suzuki K. Pouloseb59d5fb2015-11-16 16:07:10 +0000535}
536
537#else
538
Laxman Dewanganb546be02016-04-25 16:08:33 +0530539static inline void tegra_gpio_debuginit(struct tegra_gpio_info *tgi)
Suzuki K. Pouloseb59d5fb2015-11-16 16:07:10 +0000540{
541}
542
543#endif
544
Laxman Dewangan8939ddc2012-11-07 20:31:32 +0530545static const struct dev_pm_ops tegra_gpio_pm_ops = {
546 SET_SYSTEM_SLEEP_PM_OPS(tegra_gpio_suspend, tegra_gpio_resume)
547};
548
Thierry Reding9ee8ff42016-06-06 18:56:27 +0200549/*
550 * This lock class tells lockdep that GPIO irqs are in a different category
551 * than their parents, so it won't report false recursion.
552 */
553static struct lock_class_key gpio_lock_class;
554
Bill Pemberton38363092012-11-19 13:22:34 -0500555static int tegra_gpio_probe(struct platform_device *pdev)
Erik Gilling3c92db92010-03-15 19:40:06 -0700556{
Laxman Dewangan171b92c2016-04-25 16:08:31 +0530557 const struct tegra_gpio_soc_config *config;
Laxman Dewanganb546be02016-04-25 16:08:33 +0530558 struct tegra_gpio_info *tgi;
Stephen Warren88d89512011-10-11 16:16:14 -0600559 struct resource *res;
Erik Gilling3c92db92010-03-15 19:40:06 -0700560 struct tegra_gpio_bank *bank;
Stephen Warrenf57f98a2013-12-06 13:36:11 -0700561 int ret;
Stephen Warren47008002011-08-23 00:39:55 +0100562 int gpio;
Erik Gilling3c92db92010-03-15 19:40:06 -0700563 int i;
564 int j;
565
Laxman Dewangan171b92c2016-04-25 16:08:31 +0530566 config = of_device_get_match_data(&pdev->dev);
567 if (!config) {
Stephen Warren165b6c22013-02-15 14:54:48 -0700568 dev_err(&pdev->dev, "Error: No device match found\n");
569 return -ENODEV;
570 }
Stephen Warren5c1e2c92012-03-16 17:35:08 -0600571
Laxman Dewanganb546be02016-04-25 16:08:33 +0530572 tgi = devm_kzalloc(&pdev->dev, sizeof(*tgi), GFP_KERNEL);
573 if (!tgi)
574 return -ENODEV;
575
576 tgi->soc = config;
577 tgi->dev = &pdev->dev;
Stephen Warren5c1e2c92012-03-16 17:35:08 -0600578
Stephen Warren33918112012-01-19 08:16:35 +0000579 for (;;) {
Laxman Dewanganb546be02016-04-25 16:08:33 +0530580 res = platform_get_resource(pdev, IORESOURCE_IRQ,
581 tgi->bank_count);
Stephen Warren33918112012-01-19 08:16:35 +0000582 if (!res)
583 break;
Laxman Dewanganb546be02016-04-25 16:08:33 +0530584 tgi->bank_count++;
Stephen Warren33918112012-01-19 08:16:35 +0000585 }
Laxman Dewanganb546be02016-04-25 16:08:33 +0530586 if (!tgi->bank_count) {
Stephen Warren33918112012-01-19 08:16:35 +0000587 dev_err(&pdev->dev, "Missing IRQ resource\n");
588 return -ENODEV;
589 }
590
Laxman Dewanganb546be02016-04-25 16:08:33 +0530591 tgi->gc.label = "tegra-gpio";
592 tgi->gc.request = tegra_gpio_request;
593 tgi->gc.free = tegra_gpio_free;
594 tgi->gc.direction_input = tegra_gpio_direction_input;
595 tgi->gc.get = tegra_gpio_get;
596 tgi->gc.direction_output = tegra_gpio_direction_output;
597 tgi->gc.set = tegra_gpio_set;
Laxman Dewanganf002d072016-04-29 21:55:23 +0530598 tgi->gc.get_direction = tegra_gpio_get_direction;
Laxman Dewanganb546be02016-04-25 16:08:33 +0530599 tgi->gc.to_irq = tegra_gpio_to_irq;
600 tgi->gc.base = 0;
601 tgi->gc.ngpio = tgi->bank_count * 32;
602 tgi->gc.parent = &pdev->dev;
603 tgi->gc.of_node = pdev->dev.of_node;
Stephen Warren33918112012-01-19 08:16:35 +0000604
Laxman Dewanganb546be02016-04-25 16:08:33 +0530605 tgi->ic.name = "GPIO";
606 tgi->ic.irq_ack = tegra_gpio_irq_ack;
607 tgi->ic.irq_mask = tegra_gpio_irq_mask;
608 tgi->ic.irq_unmask = tegra_gpio_irq_unmask;
609 tgi->ic.irq_set_type = tegra_gpio_irq_set_type;
610 tgi->ic.irq_shutdown = tegra_gpio_irq_shutdown;
611#ifdef CONFIG_PM_SLEEP
612 tgi->ic.irq_set_wake = tegra_gpio_irq_set_wake;
613#endif
614
615 platform_set_drvdata(pdev, tgi);
616
Laxman Dewangan3737de42016-04-25 16:08:34 +0530617 if (config->debounce_supported)
618 tgi->gc.set_debounce = tegra_gpio_set_debounce;
619
Laxman Dewanganb546be02016-04-25 16:08:33 +0530620 tgi->bank_info = devm_kzalloc(&pdev->dev, tgi->bank_count *
621 sizeof(*tgi->bank_info), GFP_KERNEL);
622 if (!tgi->bank_info)
Stephen Warren33918112012-01-19 08:16:35 +0000623 return -ENODEV;
Stephen Warren33918112012-01-19 08:16:35 +0000624
Laxman Dewanganb546be02016-04-25 16:08:33 +0530625 tgi->irq_domain = irq_domain_add_linear(pdev->dev.of_node,
626 tgi->gc.ngpio,
627 &irq_domain_simple_ops, NULL);
628 if (!tgi->irq_domain)
Linus Walleijd0235672012-10-16 21:00:09 +0200629 return -ENODEV;
Stephen Warren6f74dc92012-01-04 08:39:37 +0000630
Laxman Dewanganb546be02016-04-25 16:08:33 +0530631 for (i = 0; i < tgi->bank_count; i++) {
Stephen Warren88d89512011-10-11 16:16:14 -0600632 res = platform_get_resource(pdev, IORESOURCE_IRQ, i);
633 if (!res) {
634 dev_err(&pdev->dev, "Missing IRQ resource\n");
635 return -ENODEV;
636 }
637
Laxman Dewanganb546be02016-04-25 16:08:33 +0530638 bank = &tgi->bank_info[i];
Stephen Warren88d89512011-10-11 16:16:14 -0600639 bank->bank = i;
640 bank->irq = res->start;
Laxman Dewanganb546be02016-04-25 16:08:33 +0530641 bank->tgi = tgi;
Stephen Warren88d89512011-10-11 16:16:14 -0600642 }
643
644 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
Laxman Dewanganb546be02016-04-25 16:08:33 +0530645 tgi->regs = devm_ioremap_resource(&pdev->dev, res);
646 if (IS_ERR(tgi->regs))
647 return PTR_ERR(tgi->regs);
Stephen Warren88d89512011-10-11 16:16:14 -0600648
Laxman Dewanganb546be02016-04-25 16:08:33 +0530649 for (i = 0; i < tgi->bank_count; i++) {
Erik Gilling3c92db92010-03-15 19:40:06 -0700650 for (j = 0; j < 4; j++) {
651 int gpio = tegra_gpio_compose(i, j, 0);
Laxman Dewanganb546be02016-04-25 16:08:33 +0530652 tegra_gpio_writel(tgi, 0x00, GPIO_INT_ENB(tgi, gpio));
Erik Gilling3c92db92010-03-15 19:40:06 -0700653 }
654 }
655
Laxman Dewanganb546be02016-04-25 16:08:33 +0530656 ret = devm_gpiochip_add_data(&pdev->dev, &tgi->gc, tgi);
Stephen Warrenf57f98a2013-12-06 13:36:11 -0700657 if (ret < 0) {
Laxman Dewanganb546be02016-04-25 16:08:33 +0530658 irq_domain_remove(tgi->irq_domain);
Stephen Warrenf57f98a2013-12-06 13:36:11 -0700659 return ret;
660 }
Erik Gilling3c92db92010-03-15 19:40:06 -0700661
Laxman Dewanganb546be02016-04-25 16:08:33 +0530662 for (gpio = 0; gpio < tgi->gc.ngpio; gpio++) {
663 int irq = irq_create_mapping(tgi->irq_domain, gpio);
Stephen Warren47008002011-08-23 00:39:55 +0100664 /* No validity check; all Tegra GPIOs are valid IRQs */
Erik Gilling3c92db92010-03-15 19:40:06 -0700665
Laxman Dewanganb546be02016-04-25 16:08:33 +0530666 bank = &tgi->bank_info[GPIO_BANK(gpio)];
Stephen Warren47008002011-08-23 00:39:55 +0100667
Thierry Reding9ee8ff42016-06-06 18:56:27 +0200668 irq_set_lockdep_class(irq, &gpio_lock_class);
Stephen Warren47008002011-08-23 00:39:55 +0100669 irq_set_chip_data(irq, bank);
Laxman Dewanganb546be02016-04-25 16:08:33 +0530670 irq_set_chip_and_handler(irq, &tgi->ic, handle_simple_irq);
Erik Gilling3c92db92010-03-15 19:40:06 -0700671 }
672
Laxman Dewanganb546be02016-04-25 16:08:33 +0530673 for (i = 0; i < tgi->bank_count; i++) {
674 bank = &tgi->bank_info[i];
Erik Gilling3c92db92010-03-15 19:40:06 -0700675
Russell Kinge88d2512015-06-16 23:06:50 +0100676 irq_set_chained_handler_and_data(bank->irq,
677 tegra_gpio_irq_handler, bank);
Erik Gilling3c92db92010-03-15 19:40:06 -0700678
Laxman Dewangan3737de42016-04-25 16:08:34 +0530679 for (j = 0; j < 4; j++) {
Erik Gilling3c92db92010-03-15 19:40:06 -0700680 spin_lock_init(&bank->lvl_lock[j]);
Laxman Dewangan3737de42016-04-25 16:08:34 +0530681 spin_lock_init(&bank->dbc_lock[j]);
682 }
Erik Gilling3c92db92010-03-15 19:40:06 -0700683 }
684
Laxman Dewanganb546be02016-04-25 16:08:33 +0530685 tegra_gpio_debuginit(tgi);
Suzuki K. Pouloseb59d5fb2015-11-16 16:07:10 +0000686
Erik Gilling3c92db92010-03-15 19:40:06 -0700687 return 0;
688}
689
Laxman Dewangan804f5682016-04-25 16:08:32 +0530690static const struct tegra_gpio_soc_config tegra20_gpio_config = {
Laxman Dewangan171b92c2016-04-25 16:08:31 +0530691 .bank_stride = 0x80,
692 .upper_offset = 0x800,
693};
694
Laxman Dewangan804f5682016-04-25 16:08:32 +0530695static const struct tegra_gpio_soc_config tegra30_gpio_config = {
Laxman Dewangan171b92c2016-04-25 16:08:31 +0530696 .bank_stride = 0x100,
697 .upper_offset = 0x80,
698};
699
Laxman Dewangan3737de42016-04-25 16:08:34 +0530700static const struct tegra_gpio_soc_config tegra210_gpio_config = {
701 .debounce_supported = true,
702 .bank_stride = 0x100,
703 .upper_offset = 0x80,
704};
705
Laxman Dewangan171b92c2016-04-25 16:08:31 +0530706static const struct of_device_id tegra_gpio_of_match[] = {
Laxman Dewangan3737de42016-04-25 16:08:34 +0530707 { .compatible = "nvidia,tegra210-gpio", .data = &tegra210_gpio_config },
Laxman Dewangan171b92c2016-04-25 16:08:31 +0530708 { .compatible = "nvidia,tegra30-gpio", .data = &tegra30_gpio_config },
709 { .compatible = "nvidia,tegra20-gpio", .data = &tegra20_gpio_config },
710 { },
711};
712
Stephen Warren88d89512011-10-11 16:16:14 -0600713static struct platform_driver tegra_gpio_driver = {
714 .driver = {
715 .name = "tegra-gpio",
Laxman Dewangan8939ddc2012-11-07 20:31:32 +0530716 .pm = &tegra_gpio_pm_ops,
Stephen Warren88d89512011-10-11 16:16:14 -0600717 .of_match_table = tegra_gpio_of_match,
718 },
719 .probe = tegra_gpio_probe,
720};
721
722static int __init tegra_gpio_init(void)
723{
724 return platform_driver_register(&tegra_gpio_driver);
725}
Erik Gilling3c92db92010-03-15 19:40:06 -0700726postcore_initcall(tegra_gpio_init);