blob: 233d088ac59fd69e389c8b759fab75bb5af231eb [file] [log] [blame]
Markus Mayer757651e2013-09-10 11:07:01 -07001/*
2 * Copyright (C) 2012-2013 Broadcom Corporation
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation version 2.
7 *
8 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
9 * kind, whether express or implied; without even the implied warranty
10 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#include <linux/bitops.h>
15#include <linux/err.h>
16#include <linux/io.h>
17#include <linux/gpio.h>
18#include <linux/of_device.h>
19#include <linux/of_irq.h>
20#include <linux/module.h>
21#include <linux/irqdomain.h>
22#include <linux/irqchip/chained_irq.h>
23
24#define BCM_GPIO_PASSWD 0x00a5a501
25#define GPIO_PER_BANK 32
26#define GPIO_MAX_BANK_NUM 8
27
28#define GPIO_BANK(gpio) ((gpio) >> 5)
29#define GPIO_BIT(gpio) ((gpio) & (GPIO_PER_BANK - 1))
30
31#define GPIO_OUT_STATUS(bank) (0x00000000 + ((bank) << 2))
32#define GPIO_IN_STATUS(bank) (0x00000020 + ((bank) << 2))
33#define GPIO_OUT_SET(bank) (0x00000040 + ((bank) << 2))
34#define GPIO_OUT_CLEAR(bank) (0x00000060 + ((bank) << 2))
35#define GPIO_INT_STATUS(bank) (0x00000080 + ((bank) << 2))
36#define GPIO_INT_MASK(bank) (0x000000a0 + ((bank) << 2))
37#define GPIO_INT_MSKCLR(bank) (0x000000c0 + ((bank) << 2))
38#define GPIO_CONTROL(bank) (0x00000100 + ((bank) << 2))
39#define GPIO_PWD_STATUS(bank) (0x00000500 + ((bank) << 2))
40
41#define GPIO_GPPWR_OFFSET 0x00000520
42
43#define GPIO_GPCTR0_DBR_SHIFT 5
44#define GPIO_GPCTR0_DBR_MASK 0x000001e0
45
46#define GPIO_GPCTR0_ITR_SHIFT 3
47#define GPIO_GPCTR0_ITR_MASK 0x00000018
48#define GPIO_GPCTR0_ITR_CMD_RISING_EDGE 0x00000001
49#define GPIO_GPCTR0_ITR_CMD_FALLING_EDGE 0x00000002
50#define GPIO_GPCTR0_ITR_CMD_BOTH_EDGE 0x00000003
51
52#define GPIO_GPCTR0_IOTR_MASK 0x00000001
53#define GPIO_GPCTR0_IOTR_CMD_0UTPUT 0x00000000
54#define GPIO_GPCTR0_IOTR_CMD_INPUT 0x00000001
55
56#define GPIO_GPCTR0_DB_ENABLE_MASK 0x00000100
57
58#define LOCK_CODE 0xffffffff
59#define UNLOCK_CODE 0x00000000
60
61struct bcm_kona_gpio {
62 void __iomem *reg_base;
63 int num_bank;
64 spinlock_t lock;
65 struct gpio_chip gpio_chip;
66 struct irq_domain *irq_domain;
67 struct bcm_kona_gpio_bank *banks;
68 struct platform_device *pdev;
69};
70
71struct bcm_kona_gpio_bank {
72 int id;
73 int irq;
74 /* Used in the interrupt handler */
75 struct bcm_kona_gpio *kona_gpio;
76};
77
78static inline struct bcm_kona_gpio *to_kona_gpio(struct gpio_chip *chip)
79{
80 return container_of(chip, struct bcm_kona_gpio, gpio_chip);
81}
82
83static void bcm_kona_gpio_set_lockcode_bank(void __iomem *reg_base,
84 int bank_id, int lockcode)
85{
86 writel(BCM_GPIO_PASSWD, reg_base + GPIO_GPPWR_OFFSET);
87 writel(lockcode, reg_base + GPIO_PWD_STATUS(bank_id));
88}
89
90static inline void bcm_kona_gpio_lock_bank(void __iomem *reg_base, int bank_id)
91{
92 bcm_kona_gpio_set_lockcode_bank(reg_base, bank_id, LOCK_CODE);
93}
94
95static inline void bcm_kona_gpio_unlock_bank(void __iomem *reg_base,
96 int bank_id)
97{
98 bcm_kona_gpio_set_lockcode_bank(reg_base, bank_id, UNLOCK_CODE);
99}
100
101static void bcm_kona_gpio_set(struct gpio_chip *chip, unsigned gpio, int value)
102{
103 struct bcm_kona_gpio *kona_gpio;
104 void __iomem *reg_base;
105 int bank_id = GPIO_BANK(gpio);
106 int bit = GPIO_BIT(gpio);
107 u32 val, reg_offset;
108 unsigned long flags;
109
110 kona_gpio = to_kona_gpio(chip);
111 reg_base = kona_gpio->reg_base;
112 spin_lock_irqsave(&kona_gpio->lock, flags);
113 bcm_kona_gpio_unlock_bank(reg_base, bank_id);
114
115 /* determine the GPIO pin direction */
116 val = readl(reg_base + GPIO_CONTROL(gpio));
117 val &= GPIO_GPCTR0_IOTR_MASK;
118
119 /* this function only applies to output pin */
120 if (GPIO_GPCTR0_IOTR_CMD_INPUT == val)
121 goto out;
122
123 reg_offset = value ? GPIO_OUT_SET(bank_id) : GPIO_OUT_CLEAR(bank_id);
124
125 val = readl(reg_base + reg_offset);
126 val |= BIT(bit);
127 writel(val, reg_base + reg_offset);
128
129out:
130 bcm_kona_gpio_lock_bank(reg_base, bank_id);
131 spin_unlock_irqrestore(&kona_gpio->lock, flags);
132}
133
134static int bcm_kona_gpio_get(struct gpio_chip *chip, unsigned gpio)
135{
136 struct bcm_kona_gpio *kona_gpio;
137 void __iomem *reg_base;
138 int bank_id = GPIO_BANK(gpio);
139 int bit = GPIO_BIT(gpio);
140 u32 val, reg_offset;
141 unsigned long flags;
142
143 kona_gpio = to_kona_gpio(chip);
144 reg_base = kona_gpio->reg_base;
145 spin_lock_irqsave(&kona_gpio->lock, flags);
146 bcm_kona_gpio_unlock_bank(reg_base, bank_id);
147
148 /* determine the GPIO pin direction */
149 val = readl(reg_base + GPIO_CONTROL(gpio));
150 val &= GPIO_GPCTR0_IOTR_MASK;
151
152 /* read the GPIO bank status */
153 reg_offset = (GPIO_GPCTR0_IOTR_CMD_INPUT == val) ?
154 GPIO_IN_STATUS(bank_id) : GPIO_OUT_STATUS(bank_id);
155 val = readl(reg_base + reg_offset);
156
157 bcm_kona_gpio_lock_bank(reg_base, bank_id);
158 spin_unlock_irqrestore(&kona_gpio->lock, flags);
159
160 /* return the specified bit status */
Markus Mayere2f0b002013-11-21 15:12:46 -0800161 return !!(val & BIT(bit));
Markus Mayer757651e2013-09-10 11:07:01 -0700162}
163
164static int bcm_kona_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
165{
166 struct bcm_kona_gpio *kona_gpio;
167 void __iomem *reg_base;
168 u32 val;
169 unsigned long flags;
170 int bank_id = GPIO_BANK(gpio);
171
172 kona_gpio = to_kona_gpio(chip);
173 reg_base = kona_gpio->reg_base;
174 spin_lock_irqsave(&kona_gpio->lock, flags);
175 bcm_kona_gpio_unlock_bank(reg_base, bank_id);
176
177 val = readl(reg_base + GPIO_CONTROL(gpio));
178 val &= ~GPIO_GPCTR0_IOTR_MASK;
179 val |= GPIO_GPCTR0_IOTR_CMD_INPUT;
180 writel(val, reg_base + GPIO_CONTROL(gpio));
181
182 bcm_kona_gpio_lock_bank(reg_base, bank_id);
183 spin_unlock_irqrestore(&kona_gpio->lock, flags);
184
185 return 0;
186}
187
188static int bcm_kona_gpio_direction_output(struct gpio_chip *chip,
189 unsigned gpio, int value)
190{
191 struct bcm_kona_gpio *kona_gpio;
192 void __iomem *reg_base;
193 int bank_id = GPIO_BANK(gpio);
194 int bit = GPIO_BIT(gpio);
195 u32 val, reg_offset;
196 unsigned long flags;
197
198 kona_gpio = to_kona_gpio(chip);
199 reg_base = kona_gpio->reg_base;
200 spin_lock_irqsave(&kona_gpio->lock, flags);
201 bcm_kona_gpio_unlock_bank(reg_base, bank_id);
202
203 val = readl(reg_base + GPIO_CONTROL(gpio));
204 val &= ~GPIO_GPCTR0_IOTR_MASK;
205 val |= GPIO_GPCTR0_IOTR_CMD_0UTPUT;
206 writel(val, reg_base + GPIO_CONTROL(gpio));
207 reg_offset = value ? GPIO_OUT_SET(bank_id) : GPIO_OUT_CLEAR(bank_id);
208
209 val = readl(reg_base + reg_offset);
210 val |= BIT(bit);
211 writel(val, reg_base + reg_offset);
212
213 bcm_kona_gpio_lock_bank(reg_base, bank_id);
214 spin_unlock_irqrestore(&kona_gpio->lock, flags);
215
216 return 0;
217}
218
219static int bcm_kona_gpio_to_irq(struct gpio_chip *chip, unsigned gpio)
220{
221 struct bcm_kona_gpio *kona_gpio;
222
223 kona_gpio = to_kona_gpio(chip);
224 if (gpio >= kona_gpio->gpio_chip.ngpio)
225 return -ENXIO;
226 return irq_create_mapping(kona_gpio->irq_domain, gpio);
227}
228
229static int bcm_kona_gpio_set_debounce(struct gpio_chip *chip, unsigned gpio,
230 unsigned debounce)
231{
232 struct bcm_kona_gpio *kona_gpio;
233 void __iomem *reg_base;
234 u32 val, res;
235 unsigned long flags;
236 int bank_id = GPIO_BANK(gpio);
237
238 kona_gpio = to_kona_gpio(chip);
239 reg_base = kona_gpio->reg_base;
240 /* debounce must be 1-128ms (or 0) */
241 if ((debounce > 0 && debounce < 1000) || debounce > 128000) {
242 dev_err(chip->dev, "Debounce value %u not in range\n",
243 debounce);
244 return -EINVAL;
245 }
246
247 /* calculate debounce bit value */
248 if (debounce != 0) {
249 /* Convert to ms */
250 debounce /= 1000;
251 /* find the MSB */
252 res = fls(debounce) - 1;
253 /* Check if MSB-1 is set (round up or down) */
254 if (res > 0 && (debounce & BIT(res - 1)))
255 res++;
256 }
257
258 /* spin lock for read-modify-write of the GPIO register */
259 spin_lock_irqsave(&kona_gpio->lock, flags);
260 bcm_kona_gpio_unlock_bank(reg_base, bank_id);
261
262 val = readl(reg_base + GPIO_CONTROL(gpio));
263 val &= ~GPIO_GPCTR0_DBR_MASK;
264
265 if (debounce == 0) {
266 /* disable debounce */
267 val &= ~GPIO_GPCTR0_DB_ENABLE_MASK;
268 } else {
269 val |= GPIO_GPCTR0_DB_ENABLE_MASK |
270 (res << GPIO_GPCTR0_DBR_SHIFT);
271 }
272
273 writel(val, reg_base + GPIO_CONTROL(gpio));
274
275 bcm_kona_gpio_lock_bank(reg_base, bank_id);
276 spin_unlock_irqrestore(&kona_gpio->lock, flags);
277
278 return 0;
279}
280
281static struct gpio_chip template_chip = {
282 .label = "bcm-kona-gpio",
Wei Yongjunafb36902013-10-29 11:49:20 +0800283 .owner = THIS_MODULE,
Markus Mayer757651e2013-09-10 11:07:01 -0700284 .direction_input = bcm_kona_gpio_direction_input,
285 .get = bcm_kona_gpio_get,
286 .direction_output = bcm_kona_gpio_direction_output,
287 .set = bcm_kona_gpio_set,
288 .set_debounce = bcm_kona_gpio_set_debounce,
289 .to_irq = bcm_kona_gpio_to_irq,
290 .base = 0,
291};
292
293static void bcm_kona_gpio_irq_ack(struct irq_data *d)
294{
295 struct bcm_kona_gpio *kona_gpio;
296 void __iomem *reg_base;
297 int gpio = d->hwirq;
298 int bank_id = GPIO_BANK(gpio);
299 int bit = GPIO_BIT(gpio);
300 u32 val;
301 unsigned long flags;
302
303 kona_gpio = irq_data_get_irq_chip_data(d);
304 reg_base = kona_gpio->reg_base;
305 spin_lock_irqsave(&kona_gpio->lock, flags);
306 bcm_kona_gpio_unlock_bank(reg_base, bank_id);
307
308 val = readl(reg_base + GPIO_INT_STATUS(bank_id));
309 val |= BIT(bit);
310 writel(val, reg_base + GPIO_INT_STATUS(bank_id));
311
312 bcm_kona_gpio_lock_bank(reg_base, bank_id);
313 spin_unlock_irqrestore(&kona_gpio->lock, flags);
314}
315
316static void bcm_kona_gpio_irq_mask(struct irq_data *d)
317{
318 struct bcm_kona_gpio *kona_gpio;
319 void __iomem *reg_base;
320 int gpio = d->hwirq;
321 int bank_id = GPIO_BANK(gpio);
322 int bit = GPIO_BIT(gpio);
323 u32 val;
324 unsigned long flags;
325
326 kona_gpio = irq_data_get_irq_chip_data(d);
327 reg_base = kona_gpio->reg_base;
328 spin_lock_irqsave(&kona_gpio->lock, flags);
329 bcm_kona_gpio_unlock_bank(reg_base, bank_id);
330
331 val = readl(reg_base + GPIO_INT_MASK(bank_id));
332 val |= BIT(bit);
333 writel(val, reg_base + GPIO_INT_MASK(bank_id));
334
335 bcm_kona_gpio_lock_bank(reg_base, bank_id);
336 spin_unlock_irqrestore(&kona_gpio->lock, flags);
337}
338
339static void bcm_kona_gpio_irq_unmask(struct irq_data *d)
340{
341 struct bcm_kona_gpio *kona_gpio;
342 void __iomem *reg_base;
343 int gpio = d->hwirq;
344 int bank_id = GPIO_BANK(gpio);
345 int bit = GPIO_BIT(gpio);
346 u32 val;
347 unsigned long flags;
348
349 kona_gpio = irq_data_get_irq_chip_data(d);
350 reg_base = kona_gpio->reg_base;
351 spin_lock_irqsave(&kona_gpio->lock, flags);
352 bcm_kona_gpio_unlock_bank(reg_base, bank_id);
353
354 val = readl(reg_base + GPIO_INT_MSKCLR(bank_id));
355 val |= BIT(bit);
356 writel(val, reg_base + GPIO_INT_MSKCLR(bank_id));
357
358 bcm_kona_gpio_lock_bank(reg_base, bank_id);
359 spin_unlock_irqrestore(&kona_gpio->lock, flags);
360}
361
362static int bcm_kona_gpio_irq_set_type(struct irq_data *d, unsigned int type)
363{
364 struct bcm_kona_gpio *kona_gpio;
365 void __iomem *reg_base;
366 int gpio = d->hwirq;
367 u32 lvl_type;
368 u32 val;
369 unsigned long flags;
370 int bank_id = GPIO_BANK(gpio);
371
372 kona_gpio = irq_data_get_irq_chip_data(d);
373 reg_base = kona_gpio->reg_base;
374 switch (type & IRQ_TYPE_SENSE_MASK) {
375 case IRQ_TYPE_EDGE_RISING:
376 lvl_type = GPIO_GPCTR0_ITR_CMD_RISING_EDGE;
377 break;
378
379 case IRQ_TYPE_EDGE_FALLING:
380 lvl_type = GPIO_GPCTR0_ITR_CMD_FALLING_EDGE;
381 break;
382
383 case IRQ_TYPE_EDGE_BOTH:
384 lvl_type = GPIO_GPCTR0_ITR_CMD_BOTH_EDGE;
385 break;
386
387 case IRQ_TYPE_LEVEL_HIGH:
388 case IRQ_TYPE_LEVEL_LOW:
389 /* BCM GPIO doesn't support level triggering */
390 default:
391 dev_err(kona_gpio->gpio_chip.dev,
392 "Invalid BCM GPIO irq type 0x%x\n", type);
393 return -EINVAL;
394 }
395
396 spin_lock_irqsave(&kona_gpio->lock, flags);
397 bcm_kona_gpio_unlock_bank(reg_base, bank_id);
398
399 val = readl(reg_base + GPIO_CONTROL(gpio));
400 val &= ~GPIO_GPCTR0_ITR_MASK;
401 val |= lvl_type << GPIO_GPCTR0_ITR_SHIFT;
402 writel(val, reg_base + GPIO_CONTROL(gpio));
403
404 bcm_kona_gpio_lock_bank(reg_base, bank_id);
405 spin_unlock_irqrestore(&kona_gpio->lock, flags);
406
407 return 0;
408}
409
410static void bcm_kona_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
411{
412 void __iomem *reg_base;
413 int bit, bank_id;
414 unsigned long sta;
415 struct bcm_kona_gpio_bank *bank = irq_get_handler_data(irq);
416 struct irq_chip *chip = irq_desc_get_chip(desc);
417
418 chained_irq_enter(chip, desc);
419
420 /*
421 * For bank interrupts, we can't use chip_data to store the kona_gpio
422 * pointer, since GIC needs it for its own purposes. Therefore, we get
423 * our pointer from the bank structure.
424 */
425 reg_base = bank->kona_gpio->reg_base;
426 bank_id = bank->id;
427 bcm_kona_gpio_unlock_bank(reg_base, bank_id);
428
429 while ((sta = readl(reg_base + GPIO_INT_STATUS(bank_id)) &
430 (~(readl(reg_base + GPIO_INT_MASK(bank_id)))))) {
431 for_each_set_bit(bit, &sta, 32) {
Linus Walleijd933cc62013-10-11 19:14:50 +0200432 int hwirq = GPIO_PER_BANK * bank_id + bit;
433 int child_irq =
434 irq_find_mapping(bank->kona_gpio->irq_domain,
435 hwirq);
Markus Mayer757651e2013-09-10 11:07:01 -0700436 /*
437 * Clear interrupt before handler is called so we don't
438 * miss any interrupt occurred during executing them.
439 */
440 writel(readl(reg_base + GPIO_INT_STATUS(bank_id)) |
441 BIT(bit), reg_base + GPIO_INT_STATUS(bank_id));
442 /* Invoke interrupt handler */
Linus Walleijd933cc62013-10-11 19:14:50 +0200443 generic_handle_irq(child_irq);
Markus Mayer757651e2013-09-10 11:07:01 -0700444 }
445 }
446
447 bcm_kona_gpio_lock_bank(reg_base, bank_id);
448
449 chained_irq_exit(chip, desc);
450}
451
Linus Walleijdb6b3ad2013-11-19 14:14:50 +0100452static unsigned int bcm_kona_gpio_irq_startup(struct irq_data *d)
453{
454 struct bcm_kona_gpio *kona_gpio = irq_data_get_irq_chip_data(d);
455
456 if (gpio_lock_as_irq(&kona_gpio->gpio_chip, d->hwirq))
457 dev_err(kona_gpio->gpio_chip.dev,
458 "unable to lock HW IRQ %lu for IRQ\n",
459 d->hwirq);
460 bcm_kona_gpio_irq_unmask(d);
461 return 0;
462}
463
464static void bcm_kona_gpio_irq_shutdown(struct irq_data *d)
465{
466 struct bcm_kona_gpio *kona_gpio = irq_data_get_irq_chip_data(d);
467
468 bcm_kona_gpio_irq_mask(d);
469 gpio_unlock_as_irq(&kona_gpio->gpio_chip, d->hwirq);
470}
471
Markus Mayer757651e2013-09-10 11:07:01 -0700472static struct irq_chip bcm_gpio_irq_chip = {
473 .name = "bcm-kona-gpio",
474 .irq_ack = bcm_kona_gpio_irq_ack,
475 .irq_mask = bcm_kona_gpio_irq_mask,
476 .irq_unmask = bcm_kona_gpio_irq_unmask,
477 .irq_set_type = bcm_kona_gpio_irq_set_type,
Linus Walleijdb6b3ad2013-11-19 14:14:50 +0100478 .irq_startup = bcm_kona_gpio_irq_startup,
479 .irq_shutdown = bcm_kona_gpio_irq_shutdown,
Markus Mayer757651e2013-09-10 11:07:01 -0700480};
481
482static struct __initconst of_device_id bcm_kona_gpio_of_match[] = {
483 { .compatible = "brcm,kona-gpio" },
484 {}
485};
486
487MODULE_DEVICE_TABLE(of, bcm_kona_gpio_of_match);
488
489/*
490 * This lock class tells lockdep that GPIO irqs are in a different
491 * category than their parents, so it won't report false recursion.
492 */
493static struct lock_class_key gpio_lock_class;
494
Linus Walleij1dc94272013-09-20 23:14:18 +0200495static int bcm_kona_gpio_irq_map(struct irq_domain *d, unsigned int irq,
Markus Mayer757651e2013-09-10 11:07:01 -0700496 irq_hw_number_t hwirq)
497{
498 int ret;
499
Linus Walleij1dc94272013-09-20 23:14:18 +0200500 ret = irq_set_chip_data(irq, d->host_data);
Markus Mayer757651e2013-09-10 11:07:01 -0700501 if (ret < 0)
502 return ret;
Linus Walleij1dc94272013-09-20 23:14:18 +0200503 irq_set_lockdep_class(irq, &gpio_lock_class);
504 irq_set_chip_and_handler(irq, &bcm_gpio_irq_chip, handle_simple_irq);
Linus Walleij1dc94272013-09-20 23:14:18 +0200505#ifdef CONFIG_ARM
506 set_irq_flags(irq, IRQF_VALID);
507#else
508 irq_set_noprobe(irq);
509#endif
Markus Mayer757651e2013-09-10 11:07:01 -0700510
511 return 0;
512}
513
Linus Walleijd933cc62013-10-11 19:14:50 +0200514static void bcm_kona_gpio_irq_unmap(struct irq_domain *d, unsigned int irq)
Markus Mayer757651e2013-09-10 11:07:01 -0700515{
Linus Walleijd933cc62013-10-11 19:14:50 +0200516 irq_set_chip_and_handler(irq, NULL, NULL);
517 irq_set_chip_data(irq, NULL);
Markus Mayer757651e2013-09-10 11:07:01 -0700518}
519
520static struct irq_domain_ops bcm_kona_irq_ops = {
521 .map = bcm_kona_gpio_irq_map,
522 .unmap = bcm_kona_gpio_irq_unmap,
523 .xlate = irq_domain_xlate_twocell,
524};
525
526static void bcm_kona_gpio_reset(struct bcm_kona_gpio *kona_gpio)
527{
528 void __iomem *reg_base;
529 int i;
530
531 reg_base = kona_gpio->reg_base;
532 /* disable interrupts and clear status */
533 for (i = 0; i < kona_gpio->num_bank; i++) {
534 bcm_kona_gpio_unlock_bank(reg_base, i);
535 writel(0xffffffff, reg_base + GPIO_INT_MASK(i));
536 writel(0xffffffff, reg_base + GPIO_INT_STATUS(i));
537 bcm_kona_gpio_lock_bank(reg_base, i);
538 }
539}
540
541static int bcm_kona_gpio_probe(struct platform_device *pdev)
542{
543 struct device *dev = &pdev->dev;
544 const struct of_device_id *match;
545 struct resource *res;
546 struct bcm_kona_gpio_bank *bank;
547 struct bcm_kona_gpio *kona_gpio;
548 struct gpio_chip *chip;
549 int ret;
550 int i;
551
552 match = of_match_device(bcm_kona_gpio_of_match, dev);
553 if (!match) {
554 dev_err(dev, "Failed to find gpio controller\n");
555 return -ENODEV;
556 }
557
558 kona_gpio = devm_kzalloc(dev, sizeof(*kona_gpio), GFP_KERNEL);
559 if (!kona_gpio)
560 return -ENOMEM;
561
562 kona_gpio->gpio_chip = template_chip;
563 chip = &kona_gpio->gpio_chip;
564 kona_gpio->num_bank = of_irq_count(dev->of_node);
565 if (kona_gpio->num_bank == 0) {
566 dev_err(dev, "Couldn't determine # GPIO banks\n");
567 return -ENOENT;
568 }
569 if (kona_gpio->num_bank > GPIO_MAX_BANK_NUM) {
570 dev_err(dev, "Too many GPIO banks configured (max=%d)\n",
571 GPIO_MAX_BANK_NUM);
572 return -ENXIO;
573 }
574 kona_gpio->banks = devm_kzalloc(dev,
575 kona_gpio->num_bank *
576 sizeof(*kona_gpio->banks), GFP_KERNEL);
577 if (!kona_gpio->banks)
578 return -ENOMEM;
579
580 kona_gpio->pdev = pdev;
581 platform_set_drvdata(pdev, kona_gpio);
582 chip->of_node = dev->of_node;
583 chip->ngpio = kona_gpio->num_bank * GPIO_PER_BANK;
584
585 kona_gpio->irq_domain = irq_domain_add_linear(dev->of_node,
586 chip->ngpio,
587 &bcm_kona_irq_ops,
588 kona_gpio);
589 if (!kona_gpio->irq_domain) {
590 dev_err(dev, "Couldn't allocate IRQ domain\n");
591 return -ENXIO;
592 }
593
594 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
595 kona_gpio->reg_base = devm_ioremap_resource(dev, res);
596 if (IS_ERR(kona_gpio->reg_base)) {
597 ret = -ENXIO;
598 goto err_irq_domain;
599 }
600
601 for (i = 0; i < kona_gpio->num_bank; i++) {
602 bank = &kona_gpio->banks[i];
603 bank->id = i;
604 bank->irq = platform_get_irq(pdev, i);
605 bank->kona_gpio = kona_gpio;
606 if (bank->irq < 0) {
607 dev_err(dev, "Couldn't get IRQ for bank %d", i);
608 ret = -ENOENT;
609 goto err_irq_domain;
610 }
611 }
612
Markus Mayer23b4faa2013-10-18 11:50:03 -0700613 dev_info(&pdev->dev, "Setting up Kona GPIO\n");
Markus Mayer757651e2013-09-10 11:07:01 -0700614
615 bcm_kona_gpio_reset(kona_gpio);
616
617 ret = gpiochip_add(chip);
618 if (ret < 0) {
619 dev_err(dev, "Couldn't add GPIO chip -- %d\n", ret);
620 goto err_irq_domain;
621 }
622 for (i = 0; i < chip->ngpio; i++) {
623 int irq = bcm_kona_gpio_to_irq(chip, i);
624 irq_set_lockdep_class(irq, &gpio_lock_class);
625 irq_set_chip_and_handler(irq, &bcm_gpio_irq_chip,
626 handle_simple_irq);
Linus Walleij1dc94272013-09-20 23:14:18 +0200627#ifdef CONFIG_ARM
Markus Mayer757651e2013-09-10 11:07:01 -0700628 set_irq_flags(irq, IRQF_VALID);
Linus Walleij1dc94272013-09-20 23:14:18 +0200629#else
630 irq_set_noprobe(irq);
631#endif
Markus Mayer757651e2013-09-10 11:07:01 -0700632 }
633 for (i = 0; i < kona_gpio->num_bank; i++) {
634 bank = &kona_gpio->banks[i];
635 irq_set_chained_handler(bank->irq, bcm_kona_gpio_irq_handler);
636 irq_set_handler_data(bank->irq, bank);
637 }
638
639 spin_lock_init(&kona_gpio->lock);
640
641 return 0;
642
643err_irq_domain:
644 irq_domain_remove(kona_gpio->irq_domain);
645
646 return ret;
647}
648
649static struct platform_driver bcm_kona_gpio_driver = {
650 .driver = {
651 .name = "bcm-kona-gpio",
652 .owner = THIS_MODULE,
653 .of_match_table = bcm_kona_gpio_of_match,
654 },
655 .probe = bcm_kona_gpio_probe,
656};
657
658module_platform_driver(bcm_kona_gpio_driver);
659
660MODULE_AUTHOR("Broadcom");
661MODULE_DESCRIPTION("Broadcom Kona GPIO Driver");
662MODULE_LICENSE("GPL v2");