Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2007-2008 Advanced Micro Devices, Inc. |
| 3 | * Author: Joerg Roedel <joerg.roedel@amd.com> |
| 4 | * Leo Duran <leo.duran@amd.com> |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify it |
| 7 | * under the terms of the GNU General Public License version 2 as published |
| 8 | * by the Free Software Foundation. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 18 | */ |
| 19 | |
| 20 | #ifndef __AMD_IOMMU_TYPES_H__ |
| 21 | #define __AMD_IOMMU_TYPES_H__ |
| 22 | |
| 23 | #include <linux/types.h> |
| 24 | #include <linux/list.h> |
| 25 | #include <linux/spinlock.h> |
| 26 | |
| 27 | /* |
| 28 | * some size calculation constants |
| 29 | */ |
| 30 | #define DEV_TABLE_ENTRY_SIZE 256 |
| 31 | #define ALIAS_TABLE_ENTRY_SIZE 2 |
| 32 | #define RLOOKUP_TABLE_ENTRY_SIZE (sizeof(void *)) |
| 33 | |
| 34 | /* helper macros */ |
| 35 | #define LOW_U32(x) ((x) & ((1ULL << 32)-1)) |
| 36 | #define HIGH_U32(x) (LOW_U32((x) >> 32)) |
| 37 | |
| 38 | /* Length of the MMIO region for the AMD IOMMU */ |
| 39 | #define MMIO_REGION_LENGTH 0x4000 |
| 40 | |
| 41 | /* Capability offsets used by the driver */ |
| 42 | #define MMIO_CAP_HDR_OFFSET 0x00 |
| 43 | #define MMIO_RANGE_OFFSET 0x0c |
| 44 | |
| 45 | /* Masks, shifts and macros to parse the device range capability */ |
| 46 | #define MMIO_RANGE_LD_MASK 0xff000000 |
| 47 | #define MMIO_RANGE_FD_MASK 0x00ff0000 |
| 48 | #define MMIO_RANGE_BUS_MASK 0x0000ff00 |
| 49 | #define MMIO_RANGE_LD_SHIFT 24 |
| 50 | #define MMIO_RANGE_FD_SHIFT 16 |
| 51 | #define MMIO_RANGE_BUS_SHIFT 8 |
| 52 | #define MMIO_GET_LD(x) (((x) & MMIO_RANGE_LD_MASK) >> MMIO_RANGE_LD_SHIFT) |
| 53 | #define MMIO_GET_FD(x) (((x) & MMIO_RANGE_FD_MASK) >> MMIO_RANGE_FD_SHIFT) |
| 54 | #define MMIO_GET_BUS(x) (((x) & MMIO_RANGE_BUS_MASK) >> MMIO_RANGE_BUS_SHIFT) |
| 55 | |
| 56 | /* Flag masks for the AMD IOMMU exclusion range */ |
| 57 | #define MMIO_EXCL_ENABLE_MASK 0x01ULL |
| 58 | #define MMIO_EXCL_ALLOW_MASK 0x02ULL |
| 59 | |
| 60 | /* Used offsets into the MMIO space */ |
| 61 | #define MMIO_DEV_TABLE_OFFSET 0x0000 |
| 62 | #define MMIO_CMD_BUF_OFFSET 0x0008 |
| 63 | #define MMIO_EVT_BUF_OFFSET 0x0010 |
| 64 | #define MMIO_CONTROL_OFFSET 0x0018 |
| 65 | #define MMIO_EXCL_BASE_OFFSET 0x0020 |
| 66 | #define MMIO_EXCL_LIMIT_OFFSET 0x0028 |
| 67 | #define MMIO_CMD_HEAD_OFFSET 0x2000 |
| 68 | #define MMIO_CMD_TAIL_OFFSET 0x2008 |
| 69 | #define MMIO_EVT_HEAD_OFFSET 0x2010 |
| 70 | #define MMIO_EVT_TAIL_OFFSET 0x2018 |
| 71 | #define MMIO_STATUS_OFFSET 0x2020 |
| 72 | |
| 73 | /* feature control bits */ |
| 74 | #define CONTROL_IOMMU_EN 0x00ULL |
| 75 | #define CONTROL_HT_TUN_EN 0x01ULL |
| 76 | #define CONTROL_EVT_LOG_EN 0x02ULL |
| 77 | #define CONTROL_EVT_INT_EN 0x03ULL |
| 78 | #define CONTROL_COMWAIT_EN 0x04ULL |
| 79 | #define CONTROL_PASSPW_EN 0x08ULL |
| 80 | #define CONTROL_RESPASSPW_EN 0x09ULL |
| 81 | #define CONTROL_COHERENT_EN 0x0aULL |
| 82 | #define CONTROL_ISOC_EN 0x0bULL |
| 83 | #define CONTROL_CMDBUF_EN 0x0cULL |
| 84 | #define CONTROL_PPFLOG_EN 0x0dULL |
| 85 | #define CONTROL_PPFINT_EN 0x0eULL |
| 86 | |
| 87 | /* command specific defines */ |
| 88 | #define CMD_COMPL_WAIT 0x01 |
| 89 | #define CMD_INV_DEV_ENTRY 0x02 |
| 90 | #define CMD_INV_IOMMU_PAGES 0x03 |
| 91 | |
| 92 | #define CMD_COMPL_WAIT_STORE_MASK 0x01 |
| 93 | #define CMD_INV_IOMMU_PAGES_SIZE_MASK 0x01 |
| 94 | #define CMD_INV_IOMMU_PAGES_PDE_MASK 0x02 |
| 95 | |
Joerg Roedel | 999ba41 | 2008-07-03 19:35:08 +0200 | [diff] [blame] | 96 | #define CMD_INV_IOMMU_ALL_PAGES_ADDRESS 0x7fffffffffffffffULL |
| 97 | |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 98 | /* macros and definitions for device table entries */ |
| 99 | #define DEV_ENTRY_VALID 0x00 |
| 100 | #define DEV_ENTRY_TRANSLATION 0x01 |
| 101 | #define DEV_ENTRY_IR 0x3d |
| 102 | #define DEV_ENTRY_IW 0x3e |
| 103 | #define DEV_ENTRY_EX 0x67 |
| 104 | #define DEV_ENTRY_SYSMGT1 0x68 |
| 105 | #define DEV_ENTRY_SYSMGT2 0x69 |
| 106 | #define DEV_ENTRY_INIT_PASS 0xb8 |
| 107 | #define DEV_ENTRY_EINT_PASS 0xb9 |
| 108 | #define DEV_ENTRY_NMI_PASS 0xba |
| 109 | #define DEV_ENTRY_LINT0_PASS 0xbe |
| 110 | #define DEV_ENTRY_LINT1_PASS 0xbf |
| 111 | |
| 112 | /* constants to configure the command buffer */ |
| 113 | #define CMD_BUFFER_SIZE 8192 |
| 114 | #define CMD_BUFFER_ENTRIES 512 |
| 115 | #define MMIO_CMD_SIZE_SHIFT 56 |
| 116 | #define MMIO_CMD_SIZE_512 (0x9ULL << MMIO_CMD_SIZE_SHIFT) |
| 117 | |
| 118 | #define PAGE_MODE_1_LEVEL 0x01 |
| 119 | #define PAGE_MODE_2_LEVEL 0x02 |
| 120 | #define PAGE_MODE_3_LEVEL 0x03 |
| 121 | |
| 122 | #define IOMMU_PDE_NL_0 0x000ULL |
| 123 | #define IOMMU_PDE_NL_1 0x200ULL |
| 124 | #define IOMMU_PDE_NL_2 0x400ULL |
| 125 | #define IOMMU_PDE_NL_3 0x600ULL |
| 126 | |
| 127 | #define IOMMU_PTE_L2_INDEX(address) (((address) >> 30) & 0x1ffULL) |
| 128 | #define IOMMU_PTE_L1_INDEX(address) (((address) >> 21) & 0x1ffULL) |
| 129 | #define IOMMU_PTE_L0_INDEX(address) (((address) >> 12) & 0x1ffULL) |
| 130 | |
| 131 | #define IOMMU_MAP_SIZE_L1 (1ULL << 21) |
| 132 | #define IOMMU_MAP_SIZE_L2 (1ULL << 30) |
| 133 | #define IOMMU_MAP_SIZE_L3 (1ULL << 39) |
| 134 | |
| 135 | #define IOMMU_PTE_P (1ULL << 0) |
| 136 | #define IOMMU_PTE_U (1ULL << 59) |
| 137 | #define IOMMU_PTE_FC (1ULL << 60) |
| 138 | #define IOMMU_PTE_IR (1ULL << 61) |
| 139 | #define IOMMU_PTE_IW (1ULL << 62) |
| 140 | |
| 141 | #define IOMMU_L1_PDE(address) \ |
| 142 | ((address) | IOMMU_PDE_NL_1 | IOMMU_PTE_P | IOMMU_PTE_IR | IOMMU_PTE_IW) |
| 143 | #define IOMMU_L2_PDE(address) \ |
| 144 | ((address) | IOMMU_PDE_NL_2 | IOMMU_PTE_P | IOMMU_PTE_IR | IOMMU_PTE_IW) |
| 145 | |
| 146 | #define IOMMU_PAGE_MASK (((1ULL << 52) - 1) & ~0xfffULL) |
| 147 | #define IOMMU_PTE_PRESENT(pte) ((pte) & IOMMU_PTE_P) |
| 148 | #define IOMMU_PTE_PAGE(pte) (phys_to_virt((pte) & IOMMU_PAGE_MASK)) |
| 149 | #define IOMMU_PTE_MODE(pte) (((pte) >> 9) & 0x07) |
| 150 | |
| 151 | #define IOMMU_PROT_MASK 0x03 |
| 152 | #define IOMMU_PROT_IR 0x01 |
| 153 | #define IOMMU_PROT_IW 0x02 |
| 154 | |
| 155 | /* IOMMU capabilities */ |
| 156 | #define IOMMU_CAP_IOTLB 24 |
| 157 | #define IOMMU_CAP_NPCACHE 26 |
| 158 | |
| 159 | #define MAX_DOMAIN_ID 65536 |
| 160 | |
| 161 | struct protection_domain { |
| 162 | spinlock_t lock; |
| 163 | u16 id; |
| 164 | int mode; |
| 165 | u64 *pt_root; |
| 166 | void *priv; |
| 167 | }; |
| 168 | |
| 169 | struct dma_ops_domain { |
| 170 | struct list_head list; |
| 171 | struct protection_domain domain; |
| 172 | unsigned long aperture_size; |
| 173 | unsigned long next_bit; |
| 174 | unsigned long *bitmap; |
| 175 | u64 **pte_pages; |
| 176 | }; |
| 177 | |
| 178 | struct amd_iommu { |
| 179 | struct list_head list; |
| 180 | spinlock_t lock; |
| 181 | |
| 182 | u16 devid; |
| 183 | u16 cap_ptr; |
| 184 | |
| 185 | u64 mmio_phys; |
| 186 | u8 *mmio_base; |
| 187 | u32 cap; |
| 188 | u16 first_device; |
| 189 | u16 last_device; |
| 190 | u64 exclusion_start; |
| 191 | u64 exclusion_length; |
| 192 | |
| 193 | u8 *cmd_buf; |
| 194 | u32 cmd_buf_size; |
| 195 | |
| 196 | int need_sync; |
| 197 | |
| 198 | struct dma_ops_domain *default_dom; |
| 199 | }; |
| 200 | |
| 201 | extern struct list_head amd_iommu_list; |
| 202 | |
| 203 | struct dev_table_entry { |
| 204 | u32 data[8]; |
| 205 | }; |
| 206 | |
| 207 | struct unity_map_entry { |
| 208 | struct list_head list; |
| 209 | u16 devid_start; |
| 210 | u16 devid_end; |
| 211 | u64 address_start; |
| 212 | u64 address_end; |
| 213 | int prot; |
| 214 | }; |
| 215 | |
| 216 | extern struct list_head amd_iommu_unity_map; |
| 217 | |
| 218 | /* data structures for device handling */ |
| 219 | extern struct dev_table_entry *amd_iommu_dev_table; |
| 220 | extern u16 *amd_iommu_alias_table; |
| 221 | extern struct amd_iommu **amd_iommu_rlookup_table; |
| 222 | |
| 223 | extern unsigned amd_iommu_aperture_order; |
| 224 | |
| 225 | extern u16 amd_iommu_last_bdf; |
| 226 | |
| 227 | /* data structures for protection domain handling */ |
| 228 | extern struct protection_domain **amd_iommu_pd_table; |
| 229 | extern unsigned long *amd_iommu_pd_alloc_bitmap; |
| 230 | |
| 231 | extern int amd_iommu_isolate; |
| 232 | |
| 233 | static inline void print_devid(u16 devid, int nl) |
| 234 | { |
| 235 | int bus = devid >> 8; |
| 236 | int dev = devid >> 3 & 0x1f; |
| 237 | int fn = devid & 0x07; |
| 238 | |
| 239 | printk("%02x:%02x.%x", bus, dev, fn); |
| 240 | if (nl) |
| 241 | printk("\n"); |
| 242 | } |
| 243 | |
| 244 | #endif |