| Jacob Pan | af2730f | 2010-02-12 10:31:47 -0800 | [diff] [blame] | 1 | /* |
| 2 | * mrst.h: Intel Moorestown platform specific setup code |
| 3 | * |
| 4 | * (C) Copyright 2009 Intel Corporation |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License |
| 8 | * as published by the Free Software Foundation; version 2 |
| 9 | * of the License. |
| 10 | */ |
| 11 | #ifndef _ASM_X86_MRST_H |
| 12 | #define _ASM_X86_MRST_H |
| 13 | extern int pci_mrst_init(void); |
| Jacob Pan | a0c173b | 2010-05-19 12:01:24 -0700 | [diff] [blame^] | 14 | extern int mrst_identify_cpu(void); |
| Feng Tang | cf08945 | 2010-02-12 03:37:38 -0800 | [diff] [blame] | 15 | int __init sfi_parse_mrtc(struct sfi_table_header *table); |
| Jacob Pan | af2730f | 2010-02-12 10:31:47 -0800 | [diff] [blame] | 16 | |
| Jacob Pan | a0c173b | 2010-05-19 12:01:24 -0700 | [diff] [blame^] | 17 | /* |
| 18 | * Medfield is the follow-up of Moorestown, it combines two chip solution into |
| 19 | * one. Other than that it also added always-on and constant tsc and lapic |
| 20 | * timers. Medfield is the platform name, and the chip name is called Penwell |
| 21 | * we treat Medfield/Penwell as a variant of Moorestown. Penwell can be |
| 22 | * identified via MSRs. |
| 23 | */ |
| 24 | enum mrst_cpu_type { |
| 25 | MRST_CPU_CHIP_LINCROFT = 1, |
| 26 | MRST_CPU_CHIP_PENWELL, |
| 27 | }; |
| 28 | |
| 29 | enum mrst_timer_options { |
| 30 | MRST_TIMER_DEFAULT, |
| 31 | MRST_TIMER_APBT_ONLY, |
| 32 | MRST_TIMER_LAPIC_APBT, |
| 33 | }; |
| 34 | |
| Jacob Pan | 16ab539 | 2010-02-12 03:08:30 -0800 | [diff] [blame] | 35 | #define SFI_MTMR_MAX_NUM 8 |
| Feng Tang | cf08945 | 2010-02-12 03:37:38 -0800 | [diff] [blame] | 36 | #define SFI_MRTC_MAX 8 |
| Jacob Pan | 16ab539 | 2010-02-12 03:08:30 -0800 | [diff] [blame] | 37 | |
| Jacob Pan | af2730f | 2010-02-12 10:31:47 -0800 | [diff] [blame] | 38 | #endif /* _ASM_X86_MRST_H */ |