blob: 3adebfa22e3d785b6bf7ffb2149e77652039c3c3 [file] [log] [blame]
Marek Vasut646781d2012-08-03 17:26:11 +02001/*
2 * Freescale MXS SPI master driver
3 *
4 * Copyright 2012 DENX Software Engineering, GmbH.
5 * Copyright 2012 Freescale Semiconductor, Inc.
6 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
7 *
8 * Rework and transition to new API by:
9 * Marek Vasut <marex@denx.de>
10 *
11 * Based on previous attempt by:
12 * Fabio Estevam <fabio.estevam@freescale.com>
13 *
14 * Based on code from U-Boot bootloader by:
15 * Marek Vasut <marex@denx.de>
16 *
17 * Based on spi-stmp.c, which is:
18 * Author: Dmitry Pervushin <dimka@embeddedalley.com>
19 *
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2 of the License, or
23 * (at your option) any later version.
24 *
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
29 */
30
31#include <linux/kernel.h>
32#include <linux/init.h>
33#include <linux/ioport.h>
34#include <linux/of.h>
35#include <linux/of_device.h>
36#include <linux/of_gpio.h>
37#include <linux/platform_device.h>
38#include <linux/delay.h>
39#include <linux/interrupt.h>
40#include <linux/dma-mapping.h>
41#include <linux/dmaengine.h>
42#include <linux/highmem.h>
43#include <linux/clk.h>
44#include <linux/err.h>
45#include <linux/completion.h>
46#include <linux/gpio.h>
47#include <linux/regulator/consumer.h>
48#include <linux/module.h>
Marek Vasut646781d2012-08-03 17:26:11 +020049#include <linux/stmp_device.h>
50#include <linux/spi/spi.h>
51#include <linux/spi/mxs-spi.h>
52
53#define DRIVER_NAME "mxs-spi"
54
Marek Vasut010b4812012-09-04 04:40:15 +020055/* Use 10S timeout for very long transfers, it should suffice. */
56#define SSP_TIMEOUT 10000
Marek Vasut646781d2012-08-03 17:26:11 +020057
Marek Vasut474afc02012-08-03 17:26:13 +020058#define SG_MAXLEN 0xff00
59
Trent Piepho28cad122013-10-01 13:14:50 -070060/*
61 * Flags for txrx functions. More efficient that using an argument register for
62 * each one.
63 */
64#define TXRX_WRITE (1<<0) /* This is a write */
65#define TXRX_DEASSERT_CS (1<<1) /* De-assert CS at end of txrx */
66
Marek Vasut646781d2012-08-03 17:26:11 +020067struct mxs_spi {
68 struct mxs_ssp ssp;
Marek Vasut474afc02012-08-03 17:26:13 +020069 struct completion c;
Trent Piephoa5609432013-10-01 13:15:47 -070070 unsigned int sck; /* Rate requested (vs actual) */
Marek Vasut646781d2012-08-03 17:26:11 +020071};
72
73static int mxs_spi_setup_transfer(struct spi_device *dev,
Trent Piephoaa9e0c62013-10-01 13:15:40 -070074 const struct spi_transfer *t)
Marek Vasut646781d2012-08-03 17:26:11 +020075{
76 struct mxs_spi *spi = spi_master_get_devdata(dev->master);
77 struct mxs_ssp *ssp = &spi->ssp;
Trent Piephoaa9e0c62013-10-01 13:15:40 -070078 const unsigned int hz = min(dev->max_speed_hz, t->speed_hz);
Marek Vasut646781d2012-08-03 17:26:11 +020079
Marek Vasut646781d2012-08-03 17:26:11 +020080 if (hz == 0) {
Trent Piephoaa9e0c62013-10-01 13:15:40 -070081 dev_err(&dev->dev, "SPI clock rate of zero not allowed\n");
Marek Vasut646781d2012-08-03 17:26:11 +020082 return -EINVAL;
83 }
84
Trent Piephoa5609432013-10-01 13:15:47 -070085 if (hz != spi->sck) {
86 mxs_ssp_set_clk_rate(ssp, hz);
87 /*
88 * Save requested rate, hz, rather than the actual rate,
89 * ssp->clk_rate. Otherwise we would set the rate every trasfer
90 * when the actual rate is not quite the same as requested rate.
91 */
92 spi->sck = hz;
93 /*
94 * Perhaps we should return an error if the actual clock is
95 * nowhere close to what was requested?
96 */
97 }
Marek Vasut646781d2012-08-03 17:26:11 +020098
Trent Piepho58f46e42013-10-01 13:14:25 -070099 writel(BM_SSP_CTRL0_LOCK_CS,
100 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
Marek Vasut646781d2012-08-03 17:26:11 +0200101
102 writel(BF_SSP_CTRL1_SSP_MODE(BV_SSP_CTRL1_SSP_MODE__SPI) |
Trent Piephoaa9e0c62013-10-01 13:15:40 -0700103 BF_SSP_CTRL1_WORD_LENGTH(BV_SSP_CTRL1_WORD_LENGTH__EIGHT_BITS) |
104 ((dev->mode & SPI_CPOL) ? BM_SSP_CTRL1_POLARITY : 0) |
105 ((dev->mode & SPI_CPHA) ? BM_SSP_CTRL1_PHASE : 0),
106 ssp->base + HW_SSP_CTRL1(ssp));
Marek Vasut646781d2012-08-03 17:26:11 +0200107
108 writel(0x0, ssp->base + HW_SSP_CMD0);
109 writel(0x0, ssp->base + HW_SSP_CMD1);
110
111 return 0;
112}
113
114static int mxs_spi_setup(struct spi_device *dev)
115{
Marek Vasut646781d2012-08-03 17:26:11 +0200116 if (!dev->bits_per_word)
117 dev->bits_per_word = 8;
118
Trent Piepho9c97e342013-10-01 13:15:25 -0700119 return 0;
Marek Vasut646781d2012-08-03 17:26:11 +0200120}
121
Trent Piepho42e182f2013-10-01 13:15:54 -0700122static u32 mxs_spi_cs_to_reg(unsigned cs)
Marek Vasut646781d2012-08-03 17:26:11 +0200123{
Trent Piepho42e182f2013-10-01 13:15:54 -0700124 u32 select = 0;
Marek Vasut646781d2012-08-03 17:26:11 +0200125
126 /*
127 * i.MX28 Datasheet: 17.10.1: HW_SSP_CTRL0
128 *
129 * The bits BM_SSP_CTRL0_WAIT_FOR_CMD and BM_SSP_CTRL0_WAIT_FOR_IRQ
130 * in HW_SSP_CTRL0 register do have multiple usage, please refer to
131 * the datasheet for further details. In SPI mode, they are used to
132 * toggle the chip-select lines (nCS pins).
133 */
134 if (cs & 1)
135 select |= BM_SSP_CTRL0_WAIT_FOR_CMD;
136 if (cs & 2)
137 select |= BM_SSP_CTRL0_WAIT_FOR_IRQ;
138
139 return select;
140}
141
Marek Vasut646781d2012-08-03 17:26:11 +0200142static int mxs_ssp_wait(struct mxs_spi *spi, int offset, int mask, bool set)
143{
Marek Vasutf13639d2012-09-04 04:40:18 +0200144 const unsigned long timeout = jiffies + msecs_to_jiffies(SSP_TIMEOUT);
Marek Vasut646781d2012-08-03 17:26:11 +0200145 struct mxs_ssp *ssp = &spi->ssp;
Trent Piepho42e182f2013-10-01 13:15:54 -0700146 u32 reg;
Marek Vasut646781d2012-08-03 17:26:11 +0200147
Marek Vasutf13639d2012-09-04 04:40:18 +0200148 do {
Marek Vasut646781d2012-08-03 17:26:11 +0200149 reg = readl_relaxed(ssp->base + offset);
150
Marek Vasutf13639d2012-09-04 04:40:18 +0200151 if (!set)
152 reg = ~reg;
Marek Vasut646781d2012-08-03 17:26:11 +0200153
Marek Vasutf13639d2012-09-04 04:40:18 +0200154 reg &= mask;
Marek Vasut646781d2012-08-03 17:26:11 +0200155
Marek Vasutf13639d2012-09-04 04:40:18 +0200156 if (reg == mask)
157 return 0;
158 } while (time_before(jiffies, timeout));
Marek Vasut646781d2012-08-03 17:26:11 +0200159
Marek Vasutf13639d2012-09-04 04:40:18 +0200160 return -ETIMEDOUT;
Marek Vasut646781d2012-08-03 17:26:11 +0200161}
162
Marek Vasut474afc02012-08-03 17:26:13 +0200163static void mxs_ssp_dma_irq_callback(void *param)
164{
165 struct mxs_spi *spi = param;
166 complete(&spi->c);
167}
168
169static irqreturn_t mxs_ssp_irq_handler(int irq, void *dev_id)
170{
171 struct mxs_ssp *ssp = dev_id;
172 dev_err(ssp->dev, "%s[%i] CTRL1=%08x STATUS=%08x\n",
173 __func__, __LINE__,
174 readl(ssp->base + HW_SSP_CTRL1(ssp)),
175 readl(ssp->base + HW_SSP_STATUS(ssp)));
176 return IRQ_HANDLED;
177}
178
Trent Piepho0b782f72013-10-01 13:15:04 -0700179static int mxs_spi_txrx_dma(struct mxs_spi *spi,
Marek Vasut474afc02012-08-03 17:26:13 +0200180 unsigned char *buf, int len,
Trent Piepho28cad122013-10-01 13:14:50 -0700181 unsigned int flags)
Marek Vasut474afc02012-08-03 17:26:13 +0200182{
183 struct mxs_ssp *ssp = &spi->ssp;
Marek Vasut010b4812012-09-04 04:40:15 +0200184 struct dma_async_tx_descriptor *desc = NULL;
185 const bool vmalloced_buf = is_vmalloc_addr(buf);
186 const int desc_len = vmalloced_buf ? PAGE_SIZE : SG_MAXLEN;
187 const int sgs = DIV_ROUND_UP(len, desc_len);
Marek Vasut474afc02012-08-03 17:26:13 +0200188 int sg_count;
Marek Vasut010b4812012-09-04 04:40:15 +0200189 int min, ret;
Trent Piepho42e182f2013-10-01 13:15:54 -0700190 u32 ctrl0;
Marek Vasut010b4812012-09-04 04:40:15 +0200191 struct page *vm_page;
192 void *sg_buf;
193 struct {
Trent Piepho42e182f2013-10-01 13:15:54 -0700194 u32 pio[4];
Marek Vasut010b4812012-09-04 04:40:15 +0200195 struct scatterlist sg;
196 } *dma_xfer;
Marek Vasut474afc02012-08-03 17:26:13 +0200197
Marek Vasut010b4812012-09-04 04:40:15 +0200198 if (!len)
Marek Vasut474afc02012-08-03 17:26:13 +0200199 return -EINVAL;
Marek Vasut010b4812012-09-04 04:40:15 +0200200
201 dma_xfer = kzalloc(sizeof(*dma_xfer) * sgs, GFP_KERNEL);
202 if (!dma_xfer)
203 return -ENOMEM;
Marek Vasut474afc02012-08-03 17:26:13 +0200204
Wolfram Sang16735d02013-11-14 14:32:02 -0800205 reinit_completion(&spi->c);
Marek Vasut474afc02012-08-03 17:26:13 +0200206
Trent Piepho0b782f72013-10-01 13:15:04 -0700207 /* Chip select was already programmed into CTRL0 */
Marek Vasut010b4812012-09-04 04:40:15 +0200208 ctrl0 = readl(ssp->base + HW_SSP_CTRL0);
Trent Piephodf232862013-10-01 13:14:57 -0700209 ctrl0 &= ~(BM_SSP_CTRL0_XFER_COUNT | BM_SSP_CTRL0_IGNORE_CRC |
210 BM_SSP_CTRL0_READ);
Trent Piepho0b782f72013-10-01 13:15:04 -0700211 ctrl0 |= BM_SSP_CTRL0_DATA_XFER;
Marek Vasut010b4812012-09-04 04:40:15 +0200212
Trent Piepho28cad122013-10-01 13:14:50 -0700213 if (!(flags & TXRX_WRITE))
Marek Vasut010b4812012-09-04 04:40:15 +0200214 ctrl0 |= BM_SSP_CTRL0_READ;
Marek Vasut474afc02012-08-03 17:26:13 +0200215
216 /* Queue the DMA data transfer. */
Marek Vasut010b4812012-09-04 04:40:15 +0200217 for (sg_count = 0; sg_count < sgs; sg_count++) {
Trent Piepho28cad122013-10-01 13:14:50 -0700218 /* Prepare the transfer descriptor. */
Marek Vasut010b4812012-09-04 04:40:15 +0200219 min = min(len, desc_len);
Marek Vasut474afc02012-08-03 17:26:13 +0200220
Trent Piepho28cad122013-10-01 13:14:50 -0700221 /*
222 * De-assert CS on last segment if flag is set (i.e., no more
223 * transfers will follow)
224 */
225 if ((sg_count + 1 == sgs) && (flags & TXRX_DEASSERT_CS))
Marek Vasut010b4812012-09-04 04:40:15 +0200226 ctrl0 |= BM_SSP_CTRL0_IGNORE_CRC;
Marek Vasut474afc02012-08-03 17:26:13 +0200227
Juha Lummeba486a22012-12-26 14:48:51 +0900228 if (ssp->devid == IMX23_SSP) {
229 ctrl0 &= ~BM_SSP_CTRL0_XFER_COUNT;
Marek Vasut010b4812012-09-04 04:40:15 +0200230 ctrl0 |= min;
Juha Lummeba486a22012-12-26 14:48:51 +0900231 }
Marek Vasut010b4812012-09-04 04:40:15 +0200232
233 dma_xfer[sg_count].pio[0] = ctrl0;
234 dma_xfer[sg_count].pio[3] = min;
235
236 if (vmalloced_buf) {
237 vm_page = vmalloc_to_page(buf);
238 if (!vm_page) {
239 ret = -ENOMEM;
240 goto err_vmalloc;
241 }
242 sg_buf = page_address(vm_page) +
243 ((size_t)buf & ~PAGE_MASK);
244 } else {
245 sg_buf = buf;
246 }
247
248 sg_init_one(&dma_xfer[sg_count].sg, sg_buf, min);
249 ret = dma_map_sg(ssp->dev, &dma_xfer[sg_count].sg, 1,
Trent Piepho28cad122013-10-01 13:14:50 -0700250 (flags & TXRX_WRITE) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
Marek Vasut010b4812012-09-04 04:40:15 +0200251
252 len -= min;
253 buf += min;
254
255 /* Queue the PIO register write transfer. */
256 desc = dmaengine_prep_slave_sg(ssp->dmach,
257 (struct scatterlist *)dma_xfer[sg_count].pio,
258 (ssp->devid == IMX23_SSP) ? 1 : 4,
259 DMA_TRANS_NONE,
260 sg_count ? DMA_PREP_INTERRUPT : 0);
261 if (!desc) {
262 dev_err(ssp->dev,
263 "Failed to get PIO reg. write descriptor.\n");
264 ret = -EINVAL;
265 goto err_mapped;
266 }
267
268 desc = dmaengine_prep_slave_sg(ssp->dmach,
269 &dma_xfer[sg_count].sg, 1,
Trent Piepho28cad122013-10-01 13:14:50 -0700270 (flags & TXRX_WRITE) ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
Marek Vasut010b4812012-09-04 04:40:15 +0200271 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
272
273 if (!desc) {
274 dev_err(ssp->dev,
275 "Failed to get DMA data write descriptor.\n");
276 ret = -EINVAL;
277 goto err_mapped;
278 }
Marek Vasut474afc02012-08-03 17:26:13 +0200279 }
280
281 /*
282 * The last descriptor must have this callback,
283 * to finish the DMA transaction.
284 */
285 desc->callback = mxs_ssp_dma_irq_callback;
286 desc->callback_param = spi;
287
288 /* Start the transfer. */
289 dmaengine_submit(desc);
290 dma_async_issue_pending(ssp->dmach);
291
292 ret = wait_for_completion_timeout(&spi->c,
293 msecs_to_jiffies(SSP_TIMEOUT));
Marek Vasut474afc02012-08-03 17:26:13 +0200294 if (!ret) {
295 dev_err(ssp->dev, "DMA transfer timeout\n");
296 ret = -ETIMEDOUT;
Marek Vasut44968462012-10-14 04:32:56 +0200297 dmaengine_terminate_all(ssp->dmach);
Marek Vasut010b4812012-09-04 04:40:15 +0200298 goto err_vmalloc;
Marek Vasut474afc02012-08-03 17:26:13 +0200299 }
300
301 ret = 0;
302
Marek Vasut010b4812012-09-04 04:40:15 +0200303err_vmalloc:
304 while (--sg_count >= 0) {
305err_mapped:
306 dma_unmap_sg(ssp->dev, &dma_xfer[sg_count].sg, 1,
Trent Piepho28cad122013-10-01 13:14:50 -0700307 (flags & TXRX_WRITE) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
Marek Vasut474afc02012-08-03 17:26:13 +0200308 }
309
Marek Vasut010b4812012-09-04 04:40:15 +0200310 kfree(dma_xfer);
311
Marek Vasut474afc02012-08-03 17:26:13 +0200312 return ret;
313}
314
Trent Piepho0b782f72013-10-01 13:15:04 -0700315static int mxs_spi_txrx_pio(struct mxs_spi *spi,
Marek Vasut646781d2012-08-03 17:26:11 +0200316 unsigned char *buf, int len,
Trent Piepho28cad122013-10-01 13:14:50 -0700317 unsigned int flags)
Marek Vasut646781d2012-08-03 17:26:11 +0200318{
319 struct mxs_ssp *ssp = &spi->ssp;
320
Trent Piepho75e73fa2013-10-01 13:14:39 -0700321 writel(BM_SSP_CTRL0_IGNORE_CRC,
322 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
Marek Vasut646781d2012-08-03 17:26:11 +0200323
324 while (len--) {
Trent Piepho28cad122013-10-01 13:14:50 -0700325 if (len == 0 && (flags & TXRX_DEASSERT_CS))
Trent Piephof5bc7382013-10-01 13:14:32 -0700326 writel(BM_SSP_CTRL0_IGNORE_CRC,
327 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
Marek Vasut646781d2012-08-03 17:26:11 +0200328
329 if (ssp->devid == IMX23_SSP) {
330 writel(BM_SSP_CTRL0_XFER_COUNT,
331 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
332 writel(1,
333 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
334 } else {
335 writel(1, ssp->base + HW_SSP_XFER_SIZE);
336 }
337
Trent Piepho28cad122013-10-01 13:14:50 -0700338 if (flags & TXRX_WRITE)
Marek Vasut646781d2012-08-03 17:26:11 +0200339 writel(BM_SSP_CTRL0_READ,
340 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
341 else
342 writel(BM_SSP_CTRL0_READ,
343 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
344
345 writel(BM_SSP_CTRL0_RUN,
346 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
347
348 if (mxs_ssp_wait(spi, HW_SSP_CTRL0, BM_SSP_CTRL0_RUN, 1))
349 return -ETIMEDOUT;
350
Trent Piepho28cad122013-10-01 13:14:50 -0700351 if (flags & TXRX_WRITE)
Marek Vasut646781d2012-08-03 17:26:11 +0200352 writel(*buf, ssp->base + HW_SSP_DATA(ssp));
353
354 writel(BM_SSP_CTRL0_DATA_XFER,
355 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
356
Trent Piepho28cad122013-10-01 13:14:50 -0700357 if (!(flags & TXRX_WRITE)) {
Marek Vasut646781d2012-08-03 17:26:11 +0200358 if (mxs_ssp_wait(spi, HW_SSP_STATUS(ssp),
359 BM_SSP_STATUS_FIFO_EMPTY, 0))
360 return -ETIMEDOUT;
361
362 *buf = (readl(ssp->base + HW_SSP_DATA(ssp)) & 0xff);
363 }
364
365 if (mxs_ssp_wait(spi, HW_SSP_CTRL0, BM_SSP_CTRL0_RUN, 0))
366 return -ETIMEDOUT;
367
368 buf++;
369 }
370
371 if (len <= 0)
372 return 0;
373
374 return -ETIMEDOUT;
375}
376
377static int mxs_spi_transfer_one(struct spi_master *master,
378 struct spi_message *m)
379{
380 struct mxs_spi *spi = spi_master_get_devdata(master);
381 struct mxs_ssp *ssp = &spi->ssp;
Marek Vasut646781d2012-08-03 17:26:11 +0200382 struct spi_transfer *t, *tmp_t;
Trent Piepho28cad122013-10-01 13:14:50 -0700383 unsigned int flag;
Marek Vasut646781d2012-08-03 17:26:11 +0200384 int status = 0;
Marek Vasut646781d2012-08-03 17:26:11 +0200385
Trent Piepho0b782f72013-10-01 13:15:04 -0700386 /* Program CS register bits here, it will be used for all transfers. */
387 writel(BM_SSP_CTRL0_WAIT_FOR_CMD | BM_SSP_CTRL0_WAIT_FOR_IRQ,
388 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
389 writel(mxs_spi_cs_to_reg(m->spi->chip_select),
390 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
Marek Vasut646781d2012-08-03 17:26:11 +0200391
392 list_for_each_entry_safe(t, tmp_t, &m->transfers, transfer_list) {
393
394 status = mxs_spi_setup_transfer(m->spi, t);
395 if (status)
396 break;
397
Trent Piepho28cad122013-10-01 13:14:50 -0700398 /* De-assert on last transfer, inverted by cs_change flag */
399 flag = (&t->transfer_list == m->transfers.prev) ^ t->cs_change ?
400 TXRX_DEASSERT_CS : 0;
Marek Vasut646781d2012-08-03 17:26:11 +0200401
Marek Vasut474afc02012-08-03 17:26:13 +0200402 /*
403 * Small blocks can be transfered via PIO.
404 * Measured by empiric means:
405 *
406 * dd if=/dev/mtdblock0 of=/dev/null bs=1024k count=1
407 *
408 * DMA only: 2.164808 seconds, 473.0KB/s
409 * Combined: 1.676276 seconds, 610.9KB/s
410 */
Marek Vasut727c10e2012-09-04 04:40:17 +0200411 if (t->len < 32) {
Marek Vasut474afc02012-08-03 17:26:13 +0200412 writel(BM_SSP_CTRL1_DMA_ENABLE,
413 ssp->base + HW_SSP_CTRL1(ssp) +
414 STMP_OFFSET_REG_CLR);
415
416 if (t->tx_buf)
Trent Piepho0b782f72013-10-01 13:15:04 -0700417 status = mxs_spi_txrx_pio(spi,
Marek Vasut474afc02012-08-03 17:26:13 +0200418 (void *)t->tx_buf,
Trent Piepho28cad122013-10-01 13:14:50 -0700419 t->len, flag | TXRX_WRITE);
Marek Vasut474afc02012-08-03 17:26:13 +0200420 if (t->rx_buf)
Trent Piepho0b782f72013-10-01 13:15:04 -0700421 status = mxs_spi_txrx_pio(spi,
Marek Vasut474afc02012-08-03 17:26:13 +0200422 t->rx_buf, t->len,
Trent Piepho28cad122013-10-01 13:14:50 -0700423 flag);
Marek Vasut474afc02012-08-03 17:26:13 +0200424 } else {
425 writel(BM_SSP_CTRL1_DMA_ENABLE,
426 ssp->base + HW_SSP_CTRL1(ssp) +
427 STMP_OFFSET_REG_SET);
428
429 if (t->tx_buf)
Trent Piepho0b782f72013-10-01 13:15:04 -0700430 status = mxs_spi_txrx_dma(spi,
Marek Vasut474afc02012-08-03 17:26:13 +0200431 (void *)t->tx_buf, t->len,
Trent Piepho28cad122013-10-01 13:14:50 -0700432 flag | TXRX_WRITE);
Marek Vasut474afc02012-08-03 17:26:13 +0200433 if (t->rx_buf)
Trent Piepho0b782f72013-10-01 13:15:04 -0700434 status = mxs_spi_txrx_dma(spi,
Marek Vasut474afc02012-08-03 17:26:13 +0200435 t->rx_buf, t->len,
Trent Piepho28cad122013-10-01 13:14:50 -0700436 flag);
Marek Vasut474afc02012-08-03 17:26:13 +0200437 }
Marek Vasut646781d2012-08-03 17:26:11 +0200438
Marek Vasutc895db02012-08-24 04:34:18 +0200439 if (status) {
440 stmp_reset_block(ssp->base);
Marek Vasut646781d2012-08-03 17:26:11 +0200441 break;
Marek Vasutc895db02012-08-24 04:34:18 +0200442 }
Marek Vasut646781d2012-08-03 17:26:11 +0200443
Marek Vasut204e7062012-09-04 04:40:16 +0200444 m->actual_length += t->len;
Marek Vasut646781d2012-08-03 17:26:11 +0200445 }
446
Marek Vasutd856f1eb2012-10-14 04:32:55 +0200447 m->status = status;
Marek Vasut646781d2012-08-03 17:26:11 +0200448 spi_finalize_current_message(master);
449
450 return status;
451}
452
453static const struct of_device_id mxs_spi_dt_ids[] = {
454 { .compatible = "fsl,imx23-spi", .data = (void *) IMX23_SSP, },
455 { .compatible = "fsl,imx28-spi", .data = (void *) IMX28_SSP, },
456 { /* sentinel */ }
457};
458MODULE_DEVICE_TABLE(of, mxs_spi_dt_ids);
459
Grant Likelyfd4a3192012-12-07 16:57:14 +0000460static int mxs_spi_probe(struct platform_device *pdev)
Marek Vasut646781d2012-08-03 17:26:11 +0200461{
462 const struct of_device_id *of_id =
463 of_match_device(mxs_spi_dt_ids, &pdev->dev);
464 struct device_node *np = pdev->dev.of_node;
465 struct spi_master *master;
466 struct mxs_spi *spi;
467 struct mxs_ssp *ssp;
Shawn Guo26aafa72013-02-26 11:07:32 +0800468 struct resource *iores;
Marek Vasut646781d2012-08-03 17:26:11 +0200469 struct clk *clk;
470 void __iomem *base;
Shawn Guo26aafa72013-02-26 11:07:32 +0800471 int devid, clk_freq;
472 int ret = 0, irq_err;
Marek Vasut646781d2012-08-03 17:26:11 +0200473
Marek Vasute64d07a2012-08-22 22:38:35 +0200474 /*
475 * Default clock speed for the SPI core. 160MHz seems to
476 * work reasonably well with most SPI flashes, so use this
477 * as a default. Override with "clock-frequency" DT prop.
478 */
479 const int clk_freq_default = 160000000;
480
Marek Vasut646781d2012-08-03 17:26:11 +0200481 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
Marek Vasut474afc02012-08-03 17:26:13 +0200482 irq_err = platform_get_irq(pdev, 0);
Fabio Estevam796305a2013-07-21 22:29:54 -0300483 if (irq_err < 0)
Marek Vasut646781d2012-08-03 17:26:11 +0200484 return -EINVAL;
485
Thierry Redingb0ee5602013-01-21 11:09:18 +0100486 base = devm_ioremap_resource(&pdev->dev, iores);
487 if (IS_ERR(base))
488 return PTR_ERR(base);
Marek Vasut646781d2012-08-03 17:26:11 +0200489
Marek Vasut646781d2012-08-03 17:26:11 +0200490 clk = devm_clk_get(&pdev->dev, NULL);
491 if (IS_ERR(clk))
492 return PTR_ERR(clk);
493
Shawn Guo26aafa72013-02-26 11:07:32 +0800494 devid = (enum mxs_ssp_id) of_id->data;
495 ret = of_property_read_u32(np, "clock-frequency",
496 &clk_freq);
497 if (ret)
Marek Vasute64d07a2012-08-22 22:38:35 +0200498 clk_freq = clk_freq_default;
Marek Vasut646781d2012-08-03 17:26:11 +0200499
500 master = spi_alloc_master(&pdev->dev, sizeof(*spi));
501 if (!master)
502 return -ENOMEM;
503
504 master->transfer_one_message = mxs_spi_transfer_one;
505 master->setup = mxs_spi_setup;
Stephen Warren24778be2013-05-21 20:36:35 -0600506 master->bits_per_word_mask = SPI_BPW_MASK(8);
Marek Vasut646781d2012-08-03 17:26:11 +0200507 master->mode_bits = SPI_CPOL | SPI_CPHA;
508 master->num_chipselect = 3;
509 master->dev.of_node = np;
510 master->flags = SPI_MASTER_HALF_DUPLEX;
511
512 spi = spi_master_get_devdata(master);
513 ssp = &spi->ssp;
514 ssp->dev = &pdev->dev;
515 ssp->clk = clk;
516 ssp->base = base;
517 ssp->devid = devid;
518
Marek Vasut41682e02012-08-24 04:56:27 +0200519 init_completion(&spi->c);
520
Marek Vasut474afc02012-08-03 17:26:13 +0200521 ret = devm_request_irq(&pdev->dev, irq_err, mxs_ssp_irq_handler, 0,
522 DRIVER_NAME, ssp);
523 if (ret)
524 goto out_master_free;
525
Shawn Guo26aafa72013-02-26 11:07:32 +0800526 ssp->dmach = dma_request_slave_channel(&pdev->dev, "rx-tx");
Marek Vasut474afc02012-08-03 17:26:13 +0200527 if (!ssp->dmach) {
528 dev_err(ssp->dev, "Failed to request DMA\n");
Wei Yongjun58ad60b2013-04-03 21:06:40 +0800529 ret = -ENODEV;
Marek Vasut474afc02012-08-03 17:26:13 +0200530 goto out_master_free;
531 }
532
Fabio Estevam9c4a39a2013-07-10 00:16:28 -0300533 ret = clk_prepare_enable(ssp->clk);
534 if (ret)
535 goto out_dma_release;
536
Marek Vasute64d07a2012-08-22 22:38:35 +0200537 clk_set_rate(ssp->clk, clk_freq);
Marek Vasut646781d2012-08-03 17:26:11 +0200538
Fabio Estevam8498bce2013-07-10 00:16:29 -0300539 ret = stmp_reset_block(ssp->base);
540 if (ret)
541 goto out_disable_clk;
Marek Vasut646781d2012-08-03 17:26:11 +0200542
543 platform_set_drvdata(pdev, master);
544
Jingoo Han33e195a2013-09-24 13:32:56 +0900545 ret = devm_spi_register_master(&pdev->dev, master);
Marek Vasut646781d2012-08-03 17:26:11 +0200546 if (ret) {
547 dev_err(&pdev->dev, "Cannot register SPI master, %d\n", ret);
Fabio Estevam9c4a39a2013-07-10 00:16:28 -0300548 goto out_disable_clk;
Marek Vasut646781d2012-08-03 17:26:11 +0200549 }
550
551 return 0;
552
Fabio Estevam9c4a39a2013-07-10 00:16:28 -0300553out_disable_clk:
Marek Vasut646781d2012-08-03 17:26:11 +0200554 clk_disable_unprepare(ssp->clk);
Fabio Estevam9c4a39a2013-07-10 00:16:28 -0300555out_dma_release:
Fabio Estevame11933f2013-07-10 00:16:27 -0300556 dma_release_channel(ssp->dmach);
Marek Vasut474afc02012-08-03 17:26:13 +0200557out_master_free:
Marek Vasut646781d2012-08-03 17:26:11 +0200558 spi_master_put(master);
559 return ret;
560}
561
Grant Likelyfd4a3192012-12-07 16:57:14 +0000562static int mxs_spi_remove(struct platform_device *pdev)
Marek Vasut646781d2012-08-03 17:26:11 +0200563{
564 struct spi_master *master;
565 struct mxs_spi *spi;
566 struct mxs_ssp *ssp;
567
Wei Yongjune322ce92013-11-15 15:50:31 +0800568 master = platform_get_drvdata(pdev);
Marek Vasut646781d2012-08-03 17:26:11 +0200569 spi = spi_master_get_devdata(master);
570 ssp = &spi->ssp;
571
Marek Vasut646781d2012-08-03 17:26:11 +0200572 clk_disable_unprepare(ssp->clk);
Fabio Estevame11933f2013-07-10 00:16:27 -0300573 dma_release_channel(ssp->dmach);
Marek Vasut646781d2012-08-03 17:26:11 +0200574
575 return 0;
576}
577
578static struct platform_driver mxs_spi_driver = {
579 .probe = mxs_spi_probe,
Grant Likelyfd4a3192012-12-07 16:57:14 +0000580 .remove = mxs_spi_remove,
Marek Vasut646781d2012-08-03 17:26:11 +0200581 .driver = {
582 .name = DRIVER_NAME,
583 .owner = THIS_MODULE,
584 .of_match_table = mxs_spi_dt_ids,
585 },
586};
587
588module_platform_driver(mxs_spi_driver);
589
590MODULE_AUTHOR("Marek Vasut <marex@denx.de>");
591MODULE_DESCRIPTION("MXS SPI master driver");
592MODULE_LICENSE("GPL");
593MODULE_ALIAS("platform:mxs-spi");