Daniel Drake | 66bb42f | 2007-11-19 16:20:12 +0000 | [diff] [blame] | 1 | /* ZD1211 USB-WLAN driver for Linux |
| 2 | * |
| 3 | * Copyright (C) 2005-2007 Ulrich Kunitz <kune@deine-taler.de> |
| 4 | * Copyright (C) 2006-2007 Daniel Drake <dsd@gentoo.org> |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; either version 2 of the License, or |
| 9 | * (at your option) any later version. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 19 | */ |
| 20 | |
| 21 | /* This file implements all the hardware specific functions for the ZD1211 |
| 22 | * and ZD1211B chips. Support for the ZD1211B was possible after Timothy |
| 23 | * Legge sent me a ZD1211B device. Thank you Tim. -- Uli |
| 24 | */ |
| 25 | |
| 26 | #include <linux/kernel.h> |
| 27 | #include <linux/errno.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 28 | #include <linux/slab.h> |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 29 | |
| 30 | #include "zd_def.h" |
| 31 | #include "zd_chip.h" |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 32 | #include "zd_mac.h" |
| 33 | #include "zd_rf.h" |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 34 | |
| 35 | void zd_chip_init(struct zd_chip *chip, |
Daniel Drake | 459c51a | 2007-11-19 15:00:29 +0000 | [diff] [blame] | 36 | struct ieee80211_hw *hw, |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 37 | struct usb_interface *intf) |
| 38 | { |
| 39 | memset(chip, 0, sizeof(*chip)); |
| 40 | mutex_init(&chip->mutex); |
Daniel Drake | 459c51a | 2007-11-19 15:00:29 +0000 | [diff] [blame] | 41 | zd_usb_init(&chip->usb, hw, intf); |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 42 | zd_rf_init(&chip->rf); |
| 43 | } |
| 44 | |
| 45 | void zd_chip_clear(struct zd_chip *chip) |
| 46 | { |
Ulrich Kunitz | c48cf12 | 2006-08-12 18:00:17 +0100 | [diff] [blame] | 47 | ZD_ASSERT(!mutex_is_locked(&chip->mutex)); |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 48 | zd_usb_clear(&chip->usb); |
| 49 | zd_rf_clear(&chip->rf); |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 50 | mutex_destroy(&chip->mutex); |
Ulrich Kunitz | c48cf12 | 2006-08-12 18:00:17 +0100 | [diff] [blame] | 51 | ZD_MEMCLEAR(chip, sizeof(*chip)); |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 52 | } |
| 53 | |
Daniel Drake | 74553ae | 2007-07-01 18:22:32 +0100 | [diff] [blame] | 54 | static int scnprint_mac_oui(struct zd_chip *chip, char *buffer, size_t size) |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 55 | { |
Daniel Drake | 459c51a | 2007-11-19 15:00:29 +0000 | [diff] [blame] | 56 | u8 *addr = zd_mac_get_perm_addr(zd_chip_to_mac(chip)); |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 57 | return scnprintf(buffer, size, "%02x-%02x-%02x", |
| 58 | addr[0], addr[1], addr[2]); |
| 59 | } |
| 60 | |
| 61 | /* Prints an identifier line, which will support debugging. */ |
| 62 | static int scnprint_id(struct zd_chip *chip, char *buffer, size_t size) |
| 63 | { |
| 64 | int i = 0; |
| 65 | |
| 66 | i = scnprintf(buffer, size, "zd1211%s chip ", |
Daniel Drake | 74553ae | 2007-07-01 18:22:32 +0100 | [diff] [blame] | 67 | zd_chip_is_zd1211b(chip) ? "b" : ""); |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 68 | i += zd_usb_scnprint_id(&chip->usb, buffer+i, size-i); |
| 69 | i += scnprintf(buffer+i, size-i, " "); |
Daniel Drake | 74553ae | 2007-07-01 18:22:32 +0100 | [diff] [blame] | 70 | i += scnprint_mac_oui(chip, buffer+i, size-i); |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 71 | i += scnprintf(buffer+i, size-i, " "); |
| 72 | i += zd_rf_scnprint_id(&chip->rf, buffer+i, size-i); |
Daniel Drake | f2a81a1 | 2007-03-11 19:54:28 +0000 | [diff] [blame] | 73 | i += scnprintf(buffer+i, size-i, " pa%1x %c%c%c%c%c", chip->pa_type, |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 74 | chip->patch_cck_gain ? 'g' : '-', |
| 75 | chip->patch_cr157 ? '7' : '-', |
Daniel Drake | 20fe217 | 2006-08-12 17:59:42 +0100 | [diff] [blame] | 76 | chip->patch_6m_band_edge ? '6' : '-', |
Daniel Drake | f2a81a1 | 2007-03-11 19:54:28 +0000 | [diff] [blame] | 77 | chip->new_phy_layout ? 'N' : '-', |
| 78 | chip->al2230s_bit ? 'S' : '-'); |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 79 | return i; |
| 80 | } |
| 81 | |
| 82 | static void print_id(struct zd_chip *chip) |
| 83 | { |
| 84 | char buffer[80]; |
| 85 | |
| 86 | scnprint_id(chip, buffer, sizeof(buffer)); |
| 87 | buffer[sizeof(buffer)-1] = 0; |
| 88 | dev_info(zd_chip_dev(chip), "%s\n", buffer); |
| 89 | } |
| 90 | |
Daniel Drake | 0ce34bc | 2006-12-12 01:26:11 +0000 | [diff] [blame] | 91 | static zd_addr_t inc_addr(zd_addr_t addr) |
| 92 | { |
| 93 | u16 a = (u16)addr; |
| 94 | /* Control registers use byte addressing, but everything else uses word |
| 95 | * addressing. */ |
| 96 | if ((a & 0xf000) == CR_START) |
| 97 | a += 2; |
| 98 | else |
| 99 | a += 1; |
| 100 | return (zd_addr_t)a; |
| 101 | } |
| 102 | |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 103 | /* Read a variable number of 32-bit values. Parameter count is not allowed to |
| 104 | * exceed USB_MAX_IOREAD32_COUNT. |
| 105 | */ |
| 106 | int zd_ioread32v_locked(struct zd_chip *chip, u32 *values, const zd_addr_t *addr, |
| 107 | unsigned int count) |
| 108 | { |
| 109 | int r; |
| 110 | int i; |
Jussi Kivilinna | 9bca0c3 | 2011-01-31 20:49:14 +0200 | [diff] [blame] | 111 | zd_addr_t a16[USB_MAX_IOREAD32_COUNT * 2]; |
| 112 | u16 v16[USB_MAX_IOREAD32_COUNT * 2]; |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 113 | unsigned int count16; |
| 114 | |
| 115 | if (count > USB_MAX_IOREAD32_COUNT) |
| 116 | return -EINVAL; |
| 117 | |
Jussi Kivilinna | 9bca0c3 | 2011-01-31 20:49:14 +0200 | [diff] [blame] | 118 | /* Use stack for values and addresses. */ |
| 119 | count16 = 2 * count; |
| 120 | BUG_ON(count16 * sizeof(zd_addr_t) > sizeof(a16)); |
| 121 | BUG_ON(count16 * sizeof(u16) > sizeof(v16)); |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 122 | |
| 123 | for (i = 0; i < count; i++) { |
| 124 | int j = 2*i; |
| 125 | /* We read the high word always first. */ |
Daniel Drake | 0ce34bc | 2006-12-12 01:26:11 +0000 | [diff] [blame] | 126 | a16[j] = inc_addr(addr[i]); |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 127 | a16[j+1] = addr[i]; |
| 128 | } |
| 129 | |
| 130 | r = zd_ioread16v_locked(chip, v16, a16, count16); |
| 131 | if (r) { |
| 132 | dev_dbg_f(zd_chip_dev(chip), |
| 133 | "error: zd_ioread16v_locked. Error number %d\n", r); |
Jussi Kivilinna | 9bca0c3 | 2011-01-31 20:49:14 +0200 | [diff] [blame] | 134 | return r; |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 135 | } |
| 136 | |
| 137 | for (i = 0; i < count; i++) { |
| 138 | int j = 2*i; |
| 139 | values[i] = (v16[j] << 16) | v16[j+1]; |
| 140 | } |
| 141 | |
Jussi Kivilinna | 9bca0c3 | 2011-01-31 20:49:14 +0200 | [diff] [blame] | 142 | return 0; |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 143 | } |
| 144 | |
| 145 | int _zd_iowrite32v_locked(struct zd_chip *chip, const struct zd_ioreq32 *ioreqs, |
| 146 | unsigned int count) |
| 147 | { |
| 148 | int i, j, r; |
Jussi Kivilinna | 9bca0c3 | 2011-01-31 20:49:14 +0200 | [diff] [blame] | 149 | struct zd_ioreq16 ioreqs16[USB_MAX_IOWRITE32_COUNT * 2]; |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 150 | unsigned int count16; |
| 151 | |
Jussi Kivilinna | 9bca0c3 | 2011-01-31 20:49:14 +0200 | [diff] [blame] | 152 | /* Use stack for values and addresses. */ |
| 153 | |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 154 | ZD_ASSERT(mutex_is_locked(&chip->mutex)); |
| 155 | |
| 156 | if (count == 0) |
| 157 | return 0; |
| 158 | if (count > USB_MAX_IOWRITE32_COUNT) |
| 159 | return -EINVAL; |
| 160 | |
Jussi Kivilinna | 9bca0c3 | 2011-01-31 20:49:14 +0200 | [diff] [blame] | 161 | count16 = 2 * count; |
| 162 | BUG_ON(count16 * sizeof(struct zd_ioreq16) > sizeof(ioreqs16)); |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 163 | |
| 164 | for (i = 0; i < count; i++) { |
| 165 | j = 2*i; |
| 166 | /* We write the high word always first. */ |
| 167 | ioreqs16[j].value = ioreqs[i].value >> 16; |
Daniel Drake | 0ce34bc | 2006-12-12 01:26:11 +0000 | [diff] [blame] | 168 | ioreqs16[j].addr = inc_addr(ioreqs[i].addr); |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 169 | ioreqs16[j+1].value = ioreqs[i].value; |
| 170 | ioreqs16[j+1].addr = ioreqs[i].addr; |
| 171 | } |
| 172 | |
| 173 | r = zd_usb_iowrite16v(&chip->usb, ioreqs16, count16); |
| 174 | #ifdef DEBUG |
| 175 | if (r) { |
| 176 | dev_dbg_f(zd_chip_dev(chip), |
| 177 | "error %d in zd_usb_write16v\n", r); |
| 178 | } |
| 179 | #endif /* DEBUG */ |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 180 | return r; |
| 181 | } |
| 182 | |
| 183 | int zd_iowrite16a_locked(struct zd_chip *chip, |
| 184 | const struct zd_ioreq16 *ioreqs, unsigned int count) |
| 185 | { |
| 186 | int r; |
| 187 | unsigned int i, j, t, max; |
| 188 | |
| 189 | ZD_ASSERT(mutex_is_locked(&chip->mutex)); |
| 190 | for (i = 0; i < count; i += j + t) { |
| 191 | t = 0; |
| 192 | max = count-i; |
| 193 | if (max > USB_MAX_IOWRITE16_COUNT) |
| 194 | max = USB_MAX_IOWRITE16_COUNT; |
| 195 | for (j = 0; j < max; j++) { |
| 196 | if (!ioreqs[i+j].addr) { |
| 197 | t = 1; |
| 198 | break; |
| 199 | } |
| 200 | } |
| 201 | |
| 202 | r = zd_usb_iowrite16v(&chip->usb, &ioreqs[i], j); |
| 203 | if (r) { |
| 204 | dev_dbg_f(zd_chip_dev(chip), |
| 205 | "error zd_usb_iowrite16v. Error number %d\n", |
| 206 | r); |
| 207 | return r; |
| 208 | } |
| 209 | } |
| 210 | |
| 211 | return 0; |
| 212 | } |
| 213 | |
| 214 | /* Writes a variable number of 32 bit registers. The functions will split |
| 215 | * that in several USB requests. A split can be forced by inserting an IO |
| 216 | * request with an zero address field. |
| 217 | */ |
| 218 | int zd_iowrite32a_locked(struct zd_chip *chip, |
| 219 | const struct zd_ioreq32 *ioreqs, unsigned int count) |
| 220 | { |
| 221 | int r; |
| 222 | unsigned int i, j, t, max; |
| 223 | |
| 224 | for (i = 0; i < count; i += j + t) { |
| 225 | t = 0; |
| 226 | max = count-i; |
| 227 | if (max > USB_MAX_IOWRITE32_COUNT) |
| 228 | max = USB_MAX_IOWRITE32_COUNT; |
| 229 | for (j = 0; j < max; j++) { |
| 230 | if (!ioreqs[i+j].addr) { |
| 231 | t = 1; |
| 232 | break; |
| 233 | } |
| 234 | } |
| 235 | |
| 236 | r = _zd_iowrite32v_locked(chip, &ioreqs[i], j); |
| 237 | if (r) { |
| 238 | dev_dbg_f(zd_chip_dev(chip), |
| 239 | "error _zd_iowrite32v_locked." |
| 240 | " Error number %d\n", r); |
| 241 | return r; |
| 242 | } |
| 243 | } |
| 244 | |
| 245 | return 0; |
| 246 | } |
| 247 | |
| 248 | int zd_ioread16(struct zd_chip *chip, zd_addr_t addr, u16 *value) |
| 249 | { |
| 250 | int r; |
| 251 | |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 252 | mutex_lock(&chip->mutex); |
| 253 | r = zd_ioread16_locked(chip, value, addr); |
| 254 | mutex_unlock(&chip->mutex); |
| 255 | return r; |
| 256 | } |
| 257 | |
| 258 | int zd_ioread32(struct zd_chip *chip, zd_addr_t addr, u32 *value) |
| 259 | { |
| 260 | int r; |
| 261 | |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 262 | mutex_lock(&chip->mutex); |
| 263 | r = zd_ioread32_locked(chip, value, addr); |
| 264 | mutex_unlock(&chip->mutex); |
| 265 | return r; |
| 266 | } |
| 267 | |
| 268 | int zd_iowrite16(struct zd_chip *chip, zd_addr_t addr, u16 value) |
| 269 | { |
| 270 | int r; |
| 271 | |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 272 | mutex_lock(&chip->mutex); |
| 273 | r = zd_iowrite16_locked(chip, value, addr); |
| 274 | mutex_unlock(&chip->mutex); |
| 275 | return r; |
| 276 | } |
| 277 | |
| 278 | int zd_iowrite32(struct zd_chip *chip, zd_addr_t addr, u32 value) |
| 279 | { |
| 280 | int r; |
| 281 | |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 282 | mutex_lock(&chip->mutex); |
| 283 | r = zd_iowrite32_locked(chip, value, addr); |
| 284 | mutex_unlock(&chip->mutex); |
| 285 | return r; |
| 286 | } |
| 287 | |
| 288 | int zd_ioread32v(struct zd_chip *chip, const zd_addr_t *addresses, |
| 289 | u32 *values, unsigned int count) |
| 290 | { |
| 291 | int r; |
| 292 | |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 293 | mutex_lock(&chip->mutex); |
| 294 | r = zd_ioread32v_locked(chip, values, addresses, count); |
| 295 | mutex_unlock(&chip->mutex); |
| 296 | return r; |
| 297 | } |
| 298 | |
| 299 | int zd_iowrite32a(struct zd_chip *chip, const struct zd_ioreq32 *ioreqs, |
| 300 | unsigned int count) |
| 301 | { |
| 302 | int r; |
| 303 | |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 304 | mutex_lock(&chip->mutex); |
| 305 | r = zd_iowrite32a_locked(chip, ioreqs, count); |
| 306 | mutex_unlock(&chip->mutex); |
| 307 | return r; |
| 308 | } |
| 309 | |
| 310 | static int read_pod(struct zd_chip *chip, u8 *rf_type) |
| 311 | { |
| 312 | int r; |
| 313 | u32 value; |
| 314 | |
| 315 | ZD_ASSERT(mutex_is_locked(&chip->mutex)); |
| 316 | r = zd_ioread32_locked(chip, &value, E2P_POD); |
| 317 | if (r) |
| 318 | goto error; |
| 319 | dev_dbg_f(zd_chip_dev(chip), "E2P_POD %#010x\n", value); |
| 320 | |
| 321 | /* FIXME: AL2230 handling (Bit 7 in POD) */ |
| 322 | *rf_type = value & 0x0f; |
| 323 | chip->pa_type = (value >> 16) & 0x0f; |
| 324 | chip->patch_cck_gain = (value >> 8) & 0x1; |
| 325 | chip->patch_cr157 = (value >> 13) & 0x1; |
| 326 | chip->patch_6m_band_edge = (value >> 21) & 0x1; |
Daniel Drake | 20fe217 | 2006-08-12 17:59:42 +0100 | [diff] [blame] | 327 | chip->new_phy_layout = (value >> 31) & 0x1; |
Daniel Drake | ae6ead4 | 2007-03-11 19:54:11 +0000 | [diff] [blame] | 328 | chip->al2230s_bit = (value >> 7) & 0x1; |
Ulrich Kunitz | 583afd1e | 2006-09-13 02:42:38 +0100 | [diff] [blame] | 329 | chip->link_led = ((value >> 4) & 1) ? LED1 : LED2; |
| 330 | chip->supports_tx_led = 1; |
| 331 | if (value & (1 << 24)) { /* LED scenario */ |
| 332 | if (value & (1 << 29)) |
| 333 | chip->supports_tx_led = 0; |
| 334 | } |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 335 | |
| 336 | dev_dbg_f(zd_chip_dev(chip), |
| 337 | "RF %s %#01x PA type %#01x patch CCK %d patch CR157 %d " |
Ulrich Kunitz | 583afd1e | 2006-09-13 02:42:38 +0100 | [diff] [blame] | 338 | "patch 6M %d new PHY %d link LED%d tx led %d\n", |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 339 | zd_rf_name(*rf_type), *rf_type, |
| 340 | chip->pa_type, chip->patch_cck_gain, |
Ulrich Kunitz | 583afd1e | 2006-09-13 02:42:38 +0100 | [diff] [blame] | 341 | chip->patch_cr157, chip->patch_6m_band_edge, |
| 342 | chip->new_phy_layout, |
| 343 | chip->link_led == LED1 ? 1 : 2, |
| 344 | chip->supports_tx_led); |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 345 | return 0; |
| 346 | error: |
| 347 | *rf_type = 0; |
| 348 | chip->pa_type = 0; |
| 349 | chip->patch_cck_gain = 0; |
| 350 | chip->patch_cr157 = 0; |
| 351 | chip->patch_6m_band_edge = 0; |
Daniel Drake | 20fe217 | 2006-08-12 17:59:42 +0100 | [diff] [blame] | 352 | chip->new_phy_layout = 0; |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 353 | return r; |
| 354 | } |
| 355 | |
Jussi Kivilinna | c2fadcb | 2011-01-31 20:48:06 +0200 | [diff] [blame] | 356 | static int zd_write_mac_addr_common(struct zd_chip *chip, const u8 *mac_addr, |
| 357 | const struct zd_ioreq32 *in_reqs, |
| 358 | const char *type) |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 359 | { |
| 360 | int r; |
Jussi Kivilinna | c2fadcb | 2011-01-31 20:48:06 +0200 | [diff] [blame] | 361 | struct zd_ioreq32 reqs[2] = {in_reqs[0], in_reqs[1]}; |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 362 | |
Daniel Drake | 459c51a | 2007-11-19 15:00:29 +0000 | [diff] [blame] | 363 | if (mac_addr) { |
| 364 | reqs[0].value = (mac_addr[3] << 24) |
| 365 | | (mac_addr[2] << 16) |
| 366 | | (mac_addr[1] << 8) |
| 367 | | mac_addr[0]; |
| 368 | reqs[1].value = (mac_addr[5] << 8) |
| 369 | | mac_addr[4]; |
Jussi Kivilinna | c2fadcb | 2011-01-31 20:48:06 +0200 | [diff] [blame] | 370 | dev_dbg_f(zd_chip_dev(chip), "%s addr %pM\n", type, mac_addr); |
Daniel Drake | 459c51a | 2007-11-19 15:00:29 +0000 | [diff] [blame] | 371 | } else { |
Jussi Kivilinna | c2fadcb | 2011-01-31 20:48:06 +0200 | [diff] [blame] | 372 | dev_dbg_f(zd_chip_dev(chip), "set NULL %s\n", type); |
Daniel Drake | 459c51a | 2007-11-19 15:00:29 +0000 | [diff] [blame] | 373 | } |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 374 | |
| 375 | mutex_lock(&chip->mutex); |
| 376 | r = zd_iowrite32a_locked(chip, reqs, ARRAY_SIZE(reqs)); |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 377 | mutex_unlock(&chip->mutex); |
| 378 | return r; |
| 379 | } |
| 380 | |
Jussi Kivilinna | c2fadcb | 2011-01-31 20:48:06 +0200 | [diff] [blame] | 381 | /* MAC address: if custom mac addresses are to be used CR_MAC_ADDR_P1 and |
| 382 | * CR_MAC_ADDR_P2 must be overwritten |
| 383 | */ |
| 384 | int zd_write_mac_addr(struct zd_chip *chip, const u8 *mac_addr) |
| 385 | { |
| 386 | static const struct zd_ioreq32 reqs[2] = { |
| 387 | [0] = { .addr = CR_MAC_ADDR_P1 }, |
| 388 | [1] = { .addr = CR_MAC_ADDR_P2 }, |
| 389 | }; |
| 390 | |
| 391 | return zd_write_mac_addr_common(chip, mac_addr, reqs, "mac"); |
| 392 | } |
| 393 | |
| 394 | int zd_write_bssid(struct zd_chip *chip, const u8 *bssid) |
| 395 | { |
| 396 | static const struct zd_ioreq32 reqs[2] = { |
| 397 | [0] = { .addr = CR_BSSID_P1 }, |
| 398 | [1] = { .addr = CR_BSSID_P2 }, |
| 399 | }; |
| 400 | |
| 401 | return zd_write_mac_addr_common(chip, bssid, reqs, "bssid"); |
| 402 | } |
| 403 | |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 404 | int zd_read_regdomain(struct zd_chip *chip, u8 *regdomain) |
| 405 | { |
| 406 | int r; |
| 407 | u32 value; |
| 408 | |
| 409 | mutex_lock(&chip->mutex); |
| 410 | r = zd_ioread32_locked(chip, &value, E2P_SUBID); |
| 411 | mutex_unlock(&chip->mutex); |
| 412 | if (r) |
| 413 | return r; |
| 414 | |
| 415 | *regdomain = value >> 16; |
| 416 | dev_dbg_f(zd_chip_dev(chip), "regdomain: %#04x\n", *regdomain); |
| 417 | |
| 418 | return 0; |
| 419 | } |
| 420 | |
| 421 | static int read_values(struct zd_chip *chip, u8 *values, size_t count, |
| 422 | zd_addr_t e2p_addr, u32 guard) |
| 423 | { |
| 424 | int r; |
| 425 | int i; |
| 426 | u32 v; |
| 427 | |
| 428 | ZD_ASSERT(mutex_is_locked(&chip->mutex)); |
| 429 | for (i = 0;;) { |
Daniel Drake | 0ce34bc | 2006-12-12 01:26:11 +0000 | [diff] [blame] | 430 | r = zd_ioread32_locked(chip, &v, |
| 431 | (zd_addr_t)((u16)e2p_addr+i/2)); |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 432 | if (r) |
| 433 | return r; |
| 434 | v -= guard; |
| 435 | if (i+4 < count) { |
| 436 | values[i++] = v; |
| 437 | values[i++] = v >> 8; |
| 438 | values[i++] = v >> 16; |
| 439 | values[i++] = v >> 24; |
| 440 | continue; |
| 441 | } |
| 442 | for (;i < count; i++) |
| 443 | values[i] = v >> (8*(i%3)); |
| 444 | return 0; |
| 445 | } |
| 446 | } |
| 447 | |
| 448 | static int read_pwr_cal_values(struct zd_chip *chip) |
| 449 | { |
| 450 | return read_values(chip, chip->pwr_cal_values, |
| 451 | E2P_CHANNEL_COUNT, E2P_PWR_CAL_VALUE1, |
| 452 | 0); |
| 453 | } |
| 454 | |
| 455 | static int read_pwr_int_values(struct zd_chip *chip) |
| 456 | { |
| 457 | return read_values(chip, chip->pwr_int_values, |
| 458 | E2P_CHANNEL_COUNT, E2P_PWR_INT_VALUE1, |
| 459 | E2P_PWR_INT_GUARD); |
| 460 | } |
| 461 | |
| 462 | static int read_ofdm_cal_values(struct zd_chip *chip) |
| 463 | { |
| 464 | int r; |
| 465 | int i; |
| 466 | static const zd_addr_t addresses[] = { |
| 467 | E2P_36M_CAL_VALUE1, |
| 468 | E2P_48M_CAL_VALUE1, |
| 469 | E2P_54M_CAL_VALUE1, |
| 470 | }; |
| 471 | |
| 472 | for (i = 0; i < 3; i++) { |
| 473 | r = read_values(chip, chip->ofdm_cal_values[i], |
| 474 | E2P_CHANNEL_COUNT, addresses[i], 0); |
| 475 | if (r) |
| 476 | return r; |
| 477 | } |
| 478 | return 0; |
| 479 | } |
| 480 | |
| 481 | static int read_cal_int_tables(struct zd_chip *chip) |
| 482 | { |
| 483 | int r; |
| 484 | |
| 485 | r = read_pwr_cal_values(chip); |
| 486 | if (r) |
| 487 | return r; |
| 488 | r = read_pwr_int_values(chip); |
| 489 | if (r) |
| 490 | return r; |
| 491 | r = read_ofdm_cal_values(chip); |
| 492 | if (r) |
| 493 | return r; |
| 494 | return 0; |
| 495 | } |
| 496 | |
| 497 | /* phy means physical registers */ |
| 498 | int zd_chip_lock_phy_regs(struct zd_chip *chip) |
| 499 | { |
| 500 | int r; |
| 501 | u32 tmp; |
| 502 | |
| 503 | ZD_ASSERT(mutex_is_locked(&chip->mutex)); |
| 504 | r = zd_ioread32_locked(chip, &tmp, CR_REG1); |
| 505 | if (r) { |
| 506 | dev_err(zd_chip_dev(chip), "error ioread32(CR_REG1): %d\n", r); |
| 507 | return r; |
| 508 | } |
| 509 | |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 510 | tmp &= ~UNLOCK_PHY_REGS; |
| 511 | |
| 512 | r = zd_iowrite32_locked(chip, tmp, CR_REG1); |
| 513 | if (r) |
| 514 | dev_err(zd_chip_dev(chip), "error iowrite32(CR_REG1): %d\n", r); |
| 515 | return r; |
| 516 | } |
| 517 | |
| 518 | int zd_chip_unlock_phy_regs(struct zd_chip *chip) |
| 519 | { |
| 520 | int r; |
| 521 | u32 tmp; |
| 522 | |
| 523 | ZD_ASSERT(mutex_is_locked(&chip->mutex)); |
| 524 | r = zd_ioread32_locked(chip, &tmp, CR_REG1); |
| 525 | if (r) { |
| 526 | dev_err(zd_chip_dev(chip), |
| 527 | "error ioread32(CR_REG1): %d\n", r); |
| 528 | return r; |
| 529 | } |
| 530 | |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 531 | tmp |= UNLOCK_PHY_REGS; |
| 532 | |
| 533 | r = zd_iowrite32_locked(chip, tmp, CR_REG1); |
| 534 | if (r) |
| 535 | dev_err(zd_chip_dev(chip), "error iowrite32(CR_REG1): %d\n", r); |
| 536 | return r; |
| 537 | } |
| 538 | |
Daniel Drake | 92b3e2e | 2007-04-03 23:17:37 +0100 | [diff] [blame] | 539 | /* CR157 can be optionally patched by the EEPROM for original ZD1211 */ |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 540 | static int patch_cr157(struct zd_chip *chip) |
| 541 | { |
| 542 | int r; |
Daniel Drake | 92b3e2e | 2007-04-03 23:17:37 +0100 | [diff] [blame] | 543 | u16 value; |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 544 | |
| 545 | if (!chip->patch_cr157) |
| 546 | return 0; |
| 547 | |
Daniel Drake | 92b3e2e | 2007-04-03 23:17:37 +0100 | [diff] [blame] | 548 | r = zd_ioread16_locked(chip, &value, E2P_PHY_REG); |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 549 | if (r) |
| 550 | return r; |
| 551 | |
| 552 | dev_dbg_f(zd_chip_dev(chip), "patching value %x\n", value >> 8); |
| 553 | return zd_iowrite32_locked(chip, value >> 8, CR157); |
| 554 | } |
| 555 | |
| 556 | /* |
| 557 | * 6M band edge can be optionally overwritten for certain RF's |
| 558 | * Vendor driver says: for FCC regulation, enabled per HWFeature 6M band edge |
| 559 | * bit (for AL2230, AL2230S) |
| 560 | */ |
Daniel Drake | 72018b22 | 2007-04-07 16:00:15 +0100 | [diff] [blame] | 561 | static int patch_6m_band_edge(struct zd_chip *chip, u8 channel) |
| 562 | { |
| 563 | ZD_ASSERT(mutex_is_locked(&chip->mutex)); |
| 564 | if (!chip->patch_6m_band_edge) |
| 565 | return 0; |
| 566 | |
| 567 | return zd_rf_patch_6m_band_edge(&chip->rf, channel); |
| 568 | } |
| 569 | |
| 570 | /* Generic implementation of 6M band edge patching, used by most RFs via |
| 571 | * zd_rf_generic_patch_6m() */ |
| 572 | int zd_chip_generic_patch_6m_band(struct zd_chip *chip, int channel) |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 573 | { |
| 574 | struct zd_ioreq16 ioreqs[] = { |
| 575 | { CR128, 0x14 }, { CR129, 0x12 }, { CR130, 0x10 }, |
| 576 | { CR47, 0x1e }, |
| 577 | }; |
| 578 | |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 579 | /* FIXME: Channel 11 is not the edge for all regulatory domains. */ |
| 580 | if (channel == 1 || channel == 11) |
| 581 | ioreqs[0].value = 0x12; |
| 582 | |
| 583 | dev_dbg_f(zd_chip_dev(chip), "patching for channel %d\n", channel); |
| 584 | return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs)); |
| 585 | } |
| 586 | |
| 587 | static int zd1211_hw_reset_phy(struct zd_chip *chip) |
| 588 | { |
| 589 | static const struct zd_ioreq16 ioreqs[] = { |
| 590 | { CR0, 0x0a }, { CR1, 0x06 }, { CR2, 0x26 }, |
| 591 | { CR3, 0x38 }, { CR4, 0x80 }, { CR9, 0xa0 }, |
| 592 | { CR10, 0x81 }, { CR11, 0x00 }, { CR12, 0x7f }, |
| 593 | { CR13, 0x8c }, { CR14, 0x80 }, { CR15, 0x3d }, |
| 594 | { CR16, 0x20 }, { CR17, 0x1e }, { CR18, 0x0a }, |
| 595 | { CR19, 0x48 }, { CR20, 0x0c }, { CR21, 0x0c }, |
| 596 | { CR22, 0x23 }, { CR23, 0x90 }, { CR24, 0x14 }, |
| 597 | { CR25, 0x40 }, { CR26, 0x10 }, { CR27, 0x19 }, |
| 598 | { CR28, 0x7f }, { CR29, 0x80 }, { CR30, 0x4b }, |
| 599 | { CR31, 0x60 }, { CR32, 0x43 }, { CR33, 0x08 }, |
| 600 | { CR34, 0x06 }, { CR35, 0x0a }, { CR36, 0x00 }, |
| 601 | { CR37, 0x00 }, { CR38, 0x38 }, { CR39, 0x0c }, |
| 602 | { CR40, 0x84 }, { CR41, 0x2a }, { CR42, 0x80 }, |
| 603 | { CR43, 0x10 }, { CR44, 0x12 }, { CR46, 0xff }, |
| 604 | { CR47, 0x1E }, { CR48, 0x26 }, { CR49, 0x5b }, |
| 605 | { CR64, 0xd0 }, { CR65, 0x04 }, { CR66, 0x58 }, |
| 606 | { CR67, 0xc9 }, { CR68, 0x88 }, { CR69, 0x41 }, |
| 607 | { CR70, 0x23 }, { CR71, 0x10 }, { CR72, 0xff }, |
| 608 | { CR73, 0x32 }, { CR74, 0x30 }, { CR75, 0x65 }, |
| 609 | { CR76, 0x41 }, { CR77, 0x1b }, { CR78, 0x30 }, |
| 610 | { CR79, 0x68 }, { CR80, 0x64 }, { CR81, 0x64 }, |
| 611 | { CR82, 0x00 }, { CR83, 0x00 }, { CR84, 0x00 }, |
| 612 | { CR85, 0x02 }, { CR86, 0x00 }, { CR87, 0x00 }, |
| 613 | { CR88, 0xff }, { CR89, 0xfc }, { CR90, 0x00 }, |
| 614 | { CR91, 0x00 }, { CR92, 0x00 }, { CR93, 0x08 }, |
| 615 | { CR94, 0x00 }, { CR95, 0x00 }, { CR96, 0xff }, |
| 616 | { CR97, 0xe7 }, { CR98, 0x00 }, { CR99, 0x00 }, |
| 617 | { CR100, 0x00 }, { CR101, 0xae }, { CR102, 0x02 }, |
| 618 | { CR103, 0x00 }, { CR104, 0x03 }, { CR105, 0x65 }, |
| 619 | { CR106, 0x04 }, { CR107, 0x00 }, { CR108, 0x0a }, |
| 620 | { CR109, 0xaa }, { CR110, 0xaa }, { CR111, 0x25 }, |
| 621 | { CR112, 0x25 }, { CR113, 0x00 }, { CR119, 0x1e }, |
| 622 | { CR125, 0x90 }, { CR126, 0x00 }, { CR127, 0x00 }, |
| 623 | { }, |
| 624 | { CR5, 0x00 }, { CR6, 0x00 }, { CR7, 0x00 }, |
| 625 | { CR8, 0x00 }, { CR9, 0x20 }, { CR12, 0xf0 }, |
| 626 | { CR20, 0x0e }, { CR21, 0x0e }, { CR27, 0x10 }, |
| 627 | { CR44, 0x33 }, { CR47, 0x1E }, { CR83, 0x24 }, |
| 628 | { CR84, 0x04 }, { CR85, 0x00 }, { CR86, 0x0C }, |
| 629 | { CR87, 0x12 }, { CR88, 0x0C }, { CR89, 0x00 }, |
| 630 | { CR90, 0x10 }, { CR91, 0x08 }, { CR93, 0x00 }, |
| 631 | { CR94, 0x01 }, { CR95, 0x00 }, { CR96, 0x50 }, |
| 632 | { CR97, 0x37 }, { CR98, 0x35 }, { CR101, 0x13 }, |
| 633 | { CR102, 0x27 }, { CR103, 0x27 }, { CR104, 0x18 }, |
| 634 | { CR105, 0x12 }, { CR109, 0x27 }, { CR110, 0x27 }, |
| 635 | { CR111, 0x27 }, { CR112, 0x27 }, { CR113, 0x27 }, |
| 636 | { CR114, 0x27 }, { CR115, 0x26 }, { CR116, 0x24 }, |
| 637 | { CR117, 0xfc }, { CR118, 0xfa }, { CR120, 0x4f }, |
Daniel Drake | dc536a7 | 2007-04-03 23:17:10 +0100 | [diff] [blame] | 638 | { CR125, 0xaa }, { CR127, 0x03 }, { CR128, 0x14 }, |
| 639 | { CR129, 0x12 }, { CR130, 0x10 }, { CR131, 0x0C }, |
| 640 | { CR136, 0xdf }, { CR137, 0x40 }, { CR138, 0xa0 }, |
| 641 | { CR139, 0xb0 }, { CR140, 0x99 }, { CR141, 0x82 }, |
| 642 | { CR142, 0x54 }, { CR143, 0x1c }, { CR144, 0x6c }, |
| 643 | { CR147, 0x07 }, { CR148, 0x4c }, { CR149, 0x50 }, |
| 644 | { CR150, 0x0e }, { CR151, 0x18 }, { CR160, 0xfe }, |
| 645 | { CR161, 0xee }, { CR162, 0xaa }, { CR163, 0xfa }, |
| 646 | { CR164, 0xfa }, { CR165, 0xea }, { CR166, 0xbe }, |
| 647 | { CR167, 0xbe }, { CR168, 0x6a }, { CR169, 0xba }, |
| 648 | { CR170, 0xba }, { CR171, 0xba }, |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 649 | /* Note: CR204 must lead the CR203 */ |
| 650 | { CR204, 0x7d }, |
| 651 | { }, |
| 652 | { CR203, 0x30 }, |
| 653 | }; |
| 654 | |
| 655 | int r, t; |
| 656 | |
| 657 | dev_dbg_f(zd_chip_dev(chip), "\n"); |
| 658 | |
| 659 | r = zd_chip_lock_phy_regs(chip); |
| 660 | if (r) |
| 661 | goto out; |
| 662 | |
| 663 | r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs)); |
| 664 | if (r) |
| 665 | goto unlock; |
| 666 | |
| 667 | r = patch_cr157(chip); |
| 668 | unlock: |
| 669 | t = zd_chip_unlock_phy_regs(chip); |
| 670 | if (t && !r) |
| 671 | r = t; |
| 672 | out: |
| 673 | return r; |
| 674 | } |
| 675 | |
| 676 | static int zd1211b_hw_reset_phy(struct zd_chip *chip) |
| 677 | { |
| 678 | static const struct zd_ioreq16 ioreqs[] = { |
| 679 | { CR0, 0x14 }, { CR1, 0x06 }, { CR2, 0x26 }, |
| 680 | { CR3, 0x38 }, { CR4, 0x80 }, { CR9, 0xe0 }, |
| 681 | { CR10, 0x81 }, |
| 682 | /* power control { { CR11, 1 << 6 }, */ |
| 683 | { CR11, 0x00 }, |
| 684 | { CR12, 0xf0 }, { CR13, 0x8c }, { CR14, 0x80 }, |
| 685 | { CR15, 0x3d }, { CR16, 0x20 }, { CR17, 0x1e }, |
| 686 | { CR18, 0x0a }, { CR19, 0x48 }, |
| 687 | { CR20, 0x10 }, /* Org:0x0E, ComTrend:RalLink AP */ |
| 688 | { CR21, 0x0e }, { CR22, 0x23 }, { CR23, 0x90 }, |
| 689 | { CR24, 0x14 }, { CR25, 0x40 }, { CR26, 0x10 }, |
| 690 | { CR27, 0x10 }, { CR28, 0x7f }, { CR29, 0x80 }, |
Daniel Drake | fe7215c | 2006-08-12 17:59:12 +0100 | [diff] [blame] | 691 | { CR30, 0x4b }, /* ASIC/FWT, no jointly decoder */ |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 692 | { CR31, 0x60 }, { CR32, 0x43 }, { CR33, 0x08 }, |
| 693 | { CR34, 0x06 }, { CR35, 0x0a }, { CR36, 0x00 }, |
| 694 | { CR37, 0x00 }, { CR38, 0x38 }, { CR39, 0x0c }, |
| 695 | { CR40, 0x84 }, { CR41, 0x2a }, { CR42, 0x80 }, |
| 696 | { CR43, 0x10 }, { CR44, 0x33 }, { CR46, 0xff }, |
| 697 | { CR47, 0x1E }, { CR48, 0x26 }, { CR49, 0x5b }, |
| 698 | { CR64, 0xd0 }, { CR65, 0x04 }, { CR66, 0x58 }, |
| 699 | { CR67, 0xc9 }, { CR68, 0x88 }, { CR69, 0x41 }, |
| 700 | { CR70, 0x23 }, { CR71, 0x10 }, { CR72, 0xff }, |
| 701 | { CR73, 0x32 }, { CR74, 0x30 }, { CR75, 0x65 }, |
| 702 | { CR76, 0x41 }, { CR77, 0x1b }, { CR78, 0x30 }, |
| 703 | { CR79, 0xf0 }, { CR80, 0x64 }, { CR81, 0x64 }, |
| 704 | { CR82, 0x00 }, { CR83, 0x24 }, { CR84, 0x04 }, |
| 705 | { CR85, 0x00 }, { CR86, 0x0c }, { CR87, 0x12 }, |
| 706 | { CR88, 0x0c }, { CR89, 0x00 }, { CR90, 0x58 }, |
| 707 | { CR91, 0x04 }, { CR92, 0x00 }, { CR93, 0x00 }, |
| 708 | { CR94, 0x01 }, |
| 709 | { CR95, 0x20 }, /* ZD1211B */ |
| 710 | { CR96, 0x50 }, { CR97, 0x37 }, { CR98, 0x35 }, |
| 711 | { CR99, 0x00 }, { CR100, 0x01 }, { CR101, 0x13 }, |
| 712 | { CR102, 0x27 }, { CR103, 0x27 }, { CR104, 0x18 }, |
| 713 | { CR105, 0x12 }, { CR106, 0x04 }, { CR107, 0x00 }, |
| 714 | { CR108, 0x0a }, { CR109, 0x27 }, { CR110, 0x27 }, |
| 715 | { CR111, 0x27 }, { CR112, 0x27 }, { CR113, 0x27 }, |
| 716 | { CR114, 0x27 }, { CR115, 0x26 }, { CR116, 0x24 }, |
| 717 | { CR117, 0xfc }, { CR118, 0xfa }, { CR119, 0x1e }, |
| 718 | { CR125, 0x90 }, { CR126, 0x00 }, { CR127, 0x00 }, |
| 719 | { CR128, 0x14 }, { CR129, 0x12 }, { CR130, 0x10 }, |
| 720 | { CR131, 0x0c }, { CR136, 0xdf }, { CR137, 0xa0 }, |
| 721 | { CR138, 0xa8 }, { CR139, 0xb4 }, { CR140, 0x98 }, |
| 722 | { CR141, 0x82 }, { CR142, 0x53 }, { CR143, 0x1c }, |
| 723 | { CR144, 0x6c }, { CR147, 0x07 }, { CR148, 0x40 }, |
| 724 | { CR149, 0x40 }, /* Org:0x50 ComTrend:RalLink AP */ |
| 725 | { CR150, 0x14 }, /* Org:0x0E ComTrend:RalLink AP */ |
| 726 | { CR151, 0x18 }, { CR159, 0x70 }, { CR160, 0xfe }, |
| 727 | { CR161, 0xee }, { CR162, 0xaa }, { CR163, 0xfa }, |
| 728 | { CR164, 0xfa }, { CR165, 0xea }, { CR166, 0xbe }, |
| 729 | { CR167, 0xbe }, { CR168, 0x6a }, { CR169, 0xba }, |
| 730 | { CR170, 0xba }, { CR171, 0xba }, |
| 731 | /* Note: CR204 must lead the CR203 */ |
| 732 | { CR204, 0x7d }, |
| 733 | {}, |
| 734 | { CR203, 0x30 }, |
| 735 | }; |
| 736 | |
| 737 | int r, t; |
| 738 | |
| 739 | dev_dbg_f(zd_chip_dev(chip), "\n"); |
| 740 | |
| 741 | r = zd_chip_lock_phy_regs(chip); |
| 742 | if (r) |
| 743 | goto out; |
| 744 | |
| 745 | r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs)); |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 746 | t = zd_chip_unlock_phy_regs(chip); |
| 747 | if (t && !r) |
| 748 | r = t; |
| 749 | out: |
| 750 | return r; |
| 751 | } |
| 752 | |
| 753 | static int hw_reset_phy(struct zd_chip *chip) |
| 754 | { |
Daniel Drake | 74553ae | 2007-07-01 18:22:32 +0100 | [diff] [blame] | 755 | return zd_chip_is_zd1211b(chip) ? zd1211b_hw_reset_phy(chip) : |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 756 | zd1211_hw_reset_phy(chip); |
| 757 | } |
| 758 | |
| 759 | static int zd1211_hw_init_hmac(struct zd_chip *chip) |
| 760 | { |
| 761 | static const struct zd_ioreq32 ioreqs[] = { |
Benoit PAPILLAULT | 7f4013f | 2009-10-22 12:04:52 +0200 | [diff] [blame] | 762 | { CR_ZD1211_RETRY_MAX, ZD1211_RETRY_COUNT }, |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 763 | { CR_RX_THRESHOLD, 0x000c0640 }, |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 764 | }; |
| 765 | |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 766 | dev_dbg_f(zd_chip_dev(chip), "\n"); |
| 767 | ZD_ASSERT(mutex_is_locked(&chip->mutex)); |
Daniel Drake | 34c449126 | 2006-12-12 01:25:13 +0000 | [diff] [blame] | 768 | return zd_iowrite32a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs)); |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 769 | } |
| 770 | |
| 771 | static int zd1211b_hw_init_hmac(struct zd_chip *chip) |
| 772 | { |
| 773 | static const struct zd_ioreq32 ioreqs[] = { |
Benoit PAPILLAULT | 7f4013f | 2009-10-22 12:04:52 +0200 | [diff] [blame] | 774 | { CR_ZD1211B_RETRY_MAX, ZD1211B_RETRY_COUNT }, |
Javier Cardona | e51c683 | 2008-02-08 18:41:17 -0800 | [diff] [blame] | 775 | { CR_ZD1211B_CWIN_MAX_MIN_AC0, 0x007f003f }, |
| 776 | { CR_ZD1211B_CWIN_MAX_MIN_AC1, 0x007f003f }, |
| 777 | { CR_ZD1211B_CWIN_MAX_MIN_AC2, 0x003f001f }, |
| 778 | { CR_ZD1211B_CWIN_MAX_MIN_AC3, 0x001f000f }, |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 779 | { CR_ZD1211B_AIFS_CTL1, 0x00280028 }, |
| 780 | { CR_ZD1211B_AIFS_CTL2, 0x008C003C }, |
| 781 | { CR_ZD1211B_TXOP, 0x01800824 }, |
Daniel Drake | 34c449126 | 2006-12-12 01:25:13 +0000 | [diff] [blame] | 782 | { CR_RX_THRESHOLD, 0x000c0eff, }, |
| 783 | }; |
| 784 | |
| 785 | dev_dbg_f(zd_chip_dev(chip), "\n"); |
| 786 | ZD_ASSERT(mutex_is_locked(&chip->mutex)); |
| 787 | return zd_iowrite32a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs)); |
| 788 | } |
| 789 | |
| 790 | static int hw_init_hmac(struct zd_chip *chip) |
| 791 | { |
| 792 | int r; |
| 793 | static const struct zd_ioreq32 ioreqs[] = { |
| 794 | { CR_ACK_TIMEOUT_EXT, 0x20 }, |
| 795 | { CR_ADDA_MBIAS_WARMTIME, 0x30000808 }, |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 796 | { CR_SNIFFER_ON, 0 }, |
Ulrich Kunitz | fde627b | 2006-08-01 23:43:35 +0200 | [diff] [blame] | 797 | { CR_RX_FILTER, STA_RX_FILTER }, |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 798 | { CR_GROUP_HASH_P1, 0x00 }, |
| 799 | { CR_GROUP_HASH_P2, 0x80000000 }, |
| 800 | { CR_REG1, 0xa4 }, |
| 801 | { CR_ADDA_PWR_DWN, 0x7f }, |
| 802 | { CR_BCN_PLCP_CFG, 0x00f00401 }, |
| 803 | { CR_PHY_DELAY, 0x00 }, |
| 804 | { CR_ACK_TIMEOUT_EXT, 0x80 }, |
| 805 | { CR_ADDA_PWR_DWN, 0x00 }, |
| 806 | { CR_ACK_TIME_80211, 0x100 }, |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 807 | { CR_RX_PE_DELAY, 0x70 }, |
| 808 | { CR_PS_CTRL, 0x10000000 }, |
| 809 | { CR_RTS_CTS_RATE, 0x02030203 }, |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 810 | { CR_AFTER_PNP, 0x1 }, |
| 811 | { CR_WEP_PROTECT, 0x114 }, |
Daniel Drake | 34c449126 | 2006-12-12 01:25:13 +0000 | [diff] [blame] | 812 | { CR_IFS_VALUE, IFS_VALUE_DEFAULT }, |
Luis Carlos Cobo | 72e77a8 | 2008-03-03 12:32:15 -0800 | [diff] [blame] | 813 | { CR_CAM_MODE, MODE_AP_WDS}, |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 814 | }; |
| 815 | |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 816 | ZD_ASSERT(mutex_is_locked(&chip->mutex)); |
| 817 | r = zd_iowrite32a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs)); |
Daniel Drake | 34c449126 | 2006-12-12 01:25:13 +0000 | [diff] [blame] | 818 | if (r) |
| 819 | return r; |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 820 | |
Daniel Drake | 74553ae | 2007-07-01 18:22:32 +0100 | [diff] [blame] | 821 | return zd_chip_is_zd1211b(chip) ? |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 822 | zd1211b_hw_init_hmac(chip) : zd1211_hw_init_hmac(chip); |
| 823 | } |
| 824 | |
| 825 | struct aw_pt_bi { |
| 826 | u32 atim_wnd_period; |
| 827 | u32 pre_tbtt; |
| 828 | u32 beacon_interval; |
| 829 | }; |
| 830 | |
| 831 | static int get_aw_pt_bi(struct zd_chip *chip, struct aw_pt_bi *s) |
| 832 | { |
| 833 | int r; |
| 834 | static const zd_addr_t aw_pt_bi_addr[] = |
| 835 | { CR_ATIM_WND_PERIOD, CR_PRE_TBTT, CR_BCN_INTERVAL }; |
| 836 | u32 values[3]; |
| 837 | |
| 838 | r = zd_ioread32v_locked(chip, values, (const zd_addr_t *)aw_pt_bi_addr, |
| 839 | ARRAY_SIZE(aw_pt_bi_addr)); |
| 840 | if (r) { |
| 841 | memset(s, 0, sizeof(*s)); |
| 842 | return r; |
| 843 | } |
| 844 | |
| 845 | s->atim_wnd_period = values[0]; |
| 846 | s->pre_tbtt = values[1]; |
| 847 | s->beacon_interval = values[2]; |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 848 | return 0; |
| 849 | } |
| 850 | |
| 851 | static int set_aw_pt_bi(struct zd_chip *chip, struct aw_pt_bi *s) |
| 852 | { |
| 853 | struct zd_ioreq32 reqs[3]; |
Jussi Kivilinna | 88a1159 | 2011-01-31 20:47:36 +0200 | [diff] [blame] | 854 | u16 b_interval = s->beacon_interval & 0xffff; |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 855 | |
Jussi Kivilinna | 88a1159 | 2011-01-31 20:47:36 +0200 | [diff] [blame] | 856 | if (b_interval <= 5) |
| 857 | b_interval = 5; |
| 858 | if (s->pre_tbtt < 4 || s->pre_tbtt >= b_interval) |
| 859 | s->pre_tbtt = b_interval - 1; |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 860 | if (s->atim_wnd_period >= s->pre_tbtt) |
| 861 | s->atim_wnd_period = s->pre_tbtt - 1; |
| 862 | |
| 863 | reqs[0].addr = CR_ATIM_WND_PERIOD; |
| 864 | reqs[0].value = s->atim_wnd_period; |
| 865 | reqs[1].addr = CR_PRE_TBTT; |
| 866 | reqs[1].value = s->pre_tbtt; |
| 867 | reqs[2].addr = CR_BCN_INTERVAL; |
Jussi Kivilinna | 88a1159 | 2011-01-31 20:47:36 +0200 | [diff] [blame] | 868 | reqs[2].value = (s->beacon_interval & ~0xffff) | b_interval; |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 869 | |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 870 | return zd_iowrite32a_locked(chip, reqs, ARRAY_SIZE(reqs)); |
| 871 | } |
| 872 | |
| 873 | |
Jussi Kivilinna | b91a515 | 2011-01-31 20:48:25 +0200 | [diff] [blame] | 874 | static int set_beacon_interval(struct zd_chip *chip, u16 interval, |
| 875 | u8 dtim_period, int type) |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 876 | { |
| 877 | int r; |
| 878 | struct aw_pt_bi s; |
Jussi Kivilinna | b91a515 | 2011-01-31 20:48:25 +0200 | [diff] [blame] | 879 | u32 b_interval, mode_flag; |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 880 | |
| 881 | ZD_ASSERT(mutex_is_locked(&chip->mutex)); |
Jussi Kivilinna | 88a1159 | 2011-01-31 20:47:36 +0200 | [diff] [blame] | 882 | |
Jussi Kivilinna | b91a515 | 2011-01-31 20:48:25 +0200 | [diff] [blame] | 883 | if (interval > 0) { |
| 884 | switch (type) { |
| 885 | case NL80211_IFTYPE_ADHOC: |
| 886 | case NL80211_IFTYPE_MESH_POINT: |
| 887 | mode_flag = BCN_MODE_IBSS; |
| 888 | break; |
| 889 | case NL80211_IFTYPE_AP: |
| 890 | mode_flag = BCN_MODE_AP; |
| 891 | break; |
| 892 | default: |
| 893 | mode_flag = 0; |
| 894 | break; |
| 895 | } |
| 896 | } else { |
| 897 | dtim_period = 0; |
| 898 | mode_flag = 0; |
| 899 | } |
| 900 | |
| 901 | b_interval = mode_flag | (dtim_period << 16) | interval; |
| 902 | |
| 903 | r = zd_iowrite32_locked(chip, b_interval, CR_BCN_INTERVAL); |
Jussi Kivilinna | 88a1159 | 2011-01-31 20:47:36 +0200 | [diff] [blame] | 904 | if (r) |
| 905 | return r; |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 906 | r = get_aw_pt_bi(chip, &s); |
| 907 | if (r) |
| 908 | return r; |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 909 | return set_aw_pt_bi(chip, &s); |
| 910 | } |
| 911 | |
Jussi Kivilinna | b91a515 | 2011-01-31 20:48:25 +0200 | [diff] [blame] | 912 | int zd_set_beacon_interval(struct zd_chip *chip, u16 interval, u8 dtim_period, |
| 913 | int type) |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 914 | { |
| 915 | int r; |
| 916 | |
| 917 | mutex_lock(&chip->mutex); |
Jussi Kivilinna | b91a515 | 2011-01-31 20:48:25 +0200 | [diff] [blame] | 918 | r = set_beacon_interval(chip, interval, dtim_period, type); |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 919 | mutex_unlock(&chip->mutex); |
| 920 | return r; |
| 921 | } |
| 922 | |
| 923 | static int hw_init(struct zd_chip *chip) |
| 924 | { |
| 925 | int r; |
| 926 | |
| 927 | dev_dbg_f(zd_chip_dev(chip), "\n"); |
| 928 | ZD_ASSERT(mutex_is_locked(&chip->mutex)); |
| 929 | r = hw_reset_phy(chip); |
| 930 | if (r) |
| 931 | return r; |
| 932 | |
| 933 | r = hw_init_hmac(chip); |
| 934 | if (r) |
| 935 | return r; |
Daniel Drake | 98227a9 | 2006-08-12 17:59:22 +0100 | [diff] [blame] | 936 | |
Jussi Kivilinna | b91a515 | 2011-01-31 20:48:25 +0200 | [diff] [blame] | 937 | return set_beacon_interval(chip, 100, 0, NL80211_IFTYPE_UNSPECIFIED); |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 938 | } |
| 939 | |
Daniel Drake | 0ce34bc | 2006-12-12 01:26:11 +0000 | [diff] [blame] | 940 | static zd_addr_t fw_reg_addr(struct zd_chip *chip, u16 offset) |
| 941 | { |
| 942 | return (zd_addr_t)((u16)chip->fw_regs_base + offset); |
| 943 | } |
| 944 | |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 945 | #ifdef DEBUG |
| 946 | static int dump_cr(struct zd_chip *chip, const zd_addr_t addr, |
| 947 | const char *addr_string) |
| 948 | { |
| 949 | int r; |
| 950 | u32 value; |
| 951 | |
| 952 | r = zd_ioread32_locked(chip, &value, addr); |
| 953 | if (r) { |
| 954 | dev_dbg_f(zd_chip_dev(chip), |
| 955 | "error reading %s. Error number %d\n", addr_string, r); |
| 956 | return r; |
| 957 | } |
| 958 | |
| 959 | dev_dbg_f(zd_chip_dev(chip), "%s %#010x\n", |
| 960 | addr_string, (unsigned int)value); |
| 961 | return 0; |
| 962 | } |
| 963 | |
| 964 | static int test_init(struct zd_chip *chip) |
| 965 | { |
| 966 | int r; |
| 967 | |
| 968 | r = dump_cr(chip, CR_AFTER_PNP, "CR_AFTER_PNP"); |
| 969 | if (r) |
| 970 | return r; |
| 971 | r = dump_cr(chip, CR_GPI_EN, "CR_GPI_EN"); |
| 972 | if (r) |
| 973 | return r; |
| 974 | return dump_cr(chip, CR_INTERRUPT, "CR_INTERRUPT"); |
| 975 | } |
| 976 | |
| 977 | static void dump_fw_registers(struct zd_chip *chip) |
| 978 | { |
Daniel Drake | 0ce34bc | 2006-12-12 01:26:11 +0000 | [diff] [blame] | 979 | const zd_addr_t addr[4] = { |
| 980 | fw_reg_addr(chip, FW_REG_FIRMWARE_VER), |
| 981 | fw_reg_addr(chip, FW_REG_USB_SPEED), |
| 982 | fw_reg_addr(chip, FW_REG_FIX_TX_RATE), |
| 983 | fw_reg_addr(chip, FW_REG_LED_LINK_STATUS), |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 984 | }; |
| 985 | |
| 986 | int r; |
| 987 | u16 values[4]; |
| 988 | |
| 989 | r = zd_ioread16v_locked(chip, values, (const zd_addr_t*)addr, |
| 990 | ARRAY_SIZE(addr)); |
| 991 | if (r) { |
| 992 | dev_dbg_f(zd_chip_dev(chip), "error %d zd_ioread16v_locked\n", |
| 993 | r); |
| 994 | return; |
| 995 | } |
| 996 | |
| 997 | dev_dbg_f(zd_chip_dev(chip), "FW_FIRMWARE_VER %#06hx\n", values[0]); |
| 998 | dev_dbg_f(zd_chip_dev(chip), "FW_USB_SPEED %#06hx\n", values[1]); |
| 999 | dev_dbg_f(zd_chip_dev(chip), "FW_FIX_TX_RATE %#06hx\n", values[2]); |
| 1000 | dev_dbg_f(zd_chip_dev(chip), "FW_LINK_STATUS %#06hx\n", values[3]); |
| 1001 | } |
| 1002 | #endif /* DEBUG */ |
| 1003 | |
| 1004 | static int print_fw_version(struct zd_chip *chip) |
| 1005 | { |
John W. Linville | 68e887e | 2010-07-29 13:58:48 -0400 | [diff] [blame] | 1006 | struct wiphy *wiphy = zd_chip_to_mac(chip)->hw->wiphy; |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 1007 | int r; |
| 1008 | u16 version; |
| 1009 | |
Daniel Drake | 0ce34bc | 2006-12-12 01:26:11 +0000 | [diff] [blame] | 1010 | r = zd_ioread16_locked(chip, &version, |
| 1011 | fw_reg_addr(chip, FW_REG_FIRMWARE_VER)); |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 1012 | if (r) |
| 1013 | return r; |
| 1014 | |
| 1015 | dev_info(zd_chip_dev(chip),"firmware version %04hx\n", version); |
John W. Linville | 68e887e | 2010-07-29 13:58:48 -0400 | [diff] [blame] | 1016 | |
| 1017 | snprintf(wiphy->fw_version, sizeof(wiphy->fw_version), |
| 1018 | "%04hx", version); |
| 1019 | |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 1020 | return 0; |
| 1021 | } |
| 1022 | |
Johannes Berg | 8318d78 | 2008-01-24 19:38:38 +0100 | [diff] [blame] | 1023 | static int set_mandatory_rates(struct zd_chip *chip, int gmode) |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 1024 | { |
| 1025 | u32 rates; |
| 1026 | ZD_ASSERT(mutex_is_locked(&chip->mutex)); |
| 1027 | /* This sets the mandatory rates, which only depend from the standard |
| 1028 | * that the device is supporting. Until further notice we should try |
| 1029 | * to support 802.11g also for full speed USB. |
| 1030 | */ |
Johannes Berg | 8318d78 | 2008-01-24 19:38:38 +0100 | [diff] [blame] | 1031 | if (!gmode) |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 1032 | rates = CR_RATE_1M|CR_RATE_2M|CR_RATE_5_5M|CR_RATE_11M; |
Johannes Berg | 8318d78 | 2008-01-24 19:38:38 +0100 | [diff] [blame] | 1033 | else |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 1034 | rates = CR_RATE_1M|CR_RATE_2M|CR_RATE_5_5M|CR_RATE_11M| |
| 1035 | CR_RATE_6M|CR_RATE_12M|CR_RATE_24M; |
Johannes Berg | 8318d78 | 2008-01-24 19:38:38 +0100 | [diff] [blame] | 1036 | |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 1037 | return zd_iowrite32_locked(chip, rates, CR_MANDATORY_RATE_TBL); |
| 1038 | } |
| 1039 | |
Daniel Drake | b1382ed | 2006-11-22 00:06:48 +0000 | [diff] [blame] | 1040 | int zd_chip_set_rts_cts_rate_locked(struct zd_chip *chip, |
Daniel Drake | 459c51a | 2007-11-19 15:00:29 +0000 | [diff] [blame] | 1041 | int preamble) |
Daniel Drake | b1382ed | 2006-11-22 00:06:48 +0000 | [diff] [blame] | 1042 | { |
Daniel Drake | b1382ed | 2006-11-22 00:06:48 +0000 | [diff] [blame] | 1043 | u32 value = 0; |
| 1044 | |
Daniel Drake | 459c51a | 2007-11-19 15:00:29 +0000 | [diff] [blame] | 1045 | dev_dbg_f(zd_chip_dev(chip), "preamble=%x\n", preamble); |
Daniel Drake | b1382ed | 2006-11-22 00:06:48 +0000 | [diff] [blame] | 1046 | value |= preamble << RTSCTS_SH_RTS_PMB_TYPE; |
| 1047 | value |= preamble << RTSCTS_SH_CTS_PMB_TYPE; |
| 1048 | |
Daniel Drake | 459c51a | 2007-11-19 15:00:29 +0000 | [diff] [blame] | 1049 | /* We always send 11M RTS/self-CTS messages, like the vendor driver. */ |
| 1050 | value |= ZD_PURE_RATE(ZD_CCK_RATE_11M) << RTSCTS_SH_RTS_RATE; |
| 1051 | value |= ZD_RX_CCK << RTSCTS_SH_RTS_MOD_TYPE; |
Ulrich Kunitz | 64f222c | 2007-08-06 01:24:31 +0100 | [diff] [blame] | 1052 | value |= ZD_PURE_RATE(ZD_CCK_RATE_11M) << RTSCTS_SH_CTS_RATE; |
Daniel Drake | b1382ed | 2006-11-22 00:06:48 +0000 | [diff] [blame] | 1053 | value |= ZD_RX_CCK << RTSCTS_SH_CTS_MOD_TYPE; |
| 1054 | |
| 1055 | return zd_iowrite32_locked(chip, value, CR_RTS_CTS_RATE); |
| 1056 | } |
| 1057 | |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 1058 | int zd_chip_enable_hwint(struct zd_chip *chip) |
| 1059 | { |
| 1060 | int r; |
| 1061 | |
| 1062 | mutex_lock(&chip->mutex); |
| 1063 | r = zd_iowrite32_locked(chip, HWINT_ENABLED, CR_INTERRUPT); |
| 1064 | mutex_unlock(&chip->mutex); |
| 1065 | return r; |
| 1066 | } |
| 1067 | |
| 1068 | static int disable_hwint(struct zd_chip *chip) |
| 1069 | { |
| 1070 | return zd_iowrite32_locked(chip, HWINT_DISABLED, CR_INTERRUPT); |
| 1071 | } |
| 1072 | |
| 1073 | int zd_chip_disable_hwint(struct zd_chip *chip) |
| 1074 | { |
| 1075 | int r; |
| 1076 | |
| 1077 | mutex_lock(&chip->mutex); |
| 1078 | r = disable_hwint(chip); |
| 1079 | mutex_unlock(&chip->mutex); |
| 1080 | return r; |
| 1081 | } |
| 1082 | |
Daniel Drake | 0ce34bc | 2006-12-12 01:26:11 +0000 | [diff] [blame] | 1083 | static int read_fw_regs_offset(struct zd_chip *chip) |
| 1084 | { |
| 1085 | int r; |
| 1086 | |
| 1087 | ZD_ASSERT(mutex_is_locked(&chip->mutex)); |
| 1088 | r = zd_ioread16_locked(chip, (u16*)&chip->fw_regs_base, |
| 1089 | FWRAW_REGS_ADDR); |
| 1090 | if (r) |
| 1091 | return r; |
| 1092 | dev_dbg_f(zd_chip_dev(chip), "fw_regs_base: %#06hx\n", |
| 1093 | (u16)chip->fw_regs_base); |
| 1094 | |
| 1095 | return 0; |
| 1096 | } |
| 1097 | |
Daniel Drake | 74553ae | 2007-07-01 18:22:32 +0100 | [diff] [blame] | 1098 | /* Read mac address using pre-firmware interface */ |
| 1099 | int zd_chip_read_mac_addr_fw(struct zd_chip *chip, u8 *addr) |
| 1100 | { |
| 1101 | dev_dbg_f(zd_chip_dev(chip), "\n"); |
| 1102 | return zd_usb_read_fw(&chip->usb, E2P_MAC_ADDR_P1, addr, |
| 1103 | ETH_ALEN); |
| 1104 | } |
Daniel Drake | 0ce34bc | 2006-12-12 01:26:11 +0000 | [diff] [blame] | 1105 | |
Daniel Drake | 74553ae | 2007-07-01 18:22:32 +0100 | [diff] [blame] | 1106 | int zd_chip_init_hw(struct zd_chip *chip) |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 1107 | { |
| 1108 | int r; |
| 1109 | u8 rf_type; |
| 1110 | |
| 1111 | dev_dbg_f(zd_chip_dev(chip), "\n"); |
| 1112 | |
| 1113 | mutex_lock(&chip->mutex); |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 1114 | |
| 1115 | #ifdef DEBUG |
| 1116 | r = test_init(chip); |
| 1117 | if (r) |
| 1118 | goto out; |
| 1119 | #endif |
| 1120 | r = zd_iowrite32_locked(chip, 1, CR_AFTER_PNP); |
| 1121 | if (r) |
| 1122 | goto out; |
| 1123 | |
Daniel Drake | 0ce34bc | 2006-12-12 01:26:11 +0000 | [diff] [blame] | 1124 | r = read_fw_regs_offset(chip); |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 1125 | if (r) |
| 1126 | goto out; |
| 1127 | |
| 1128 | /* GPI is always disabled, also in the other driver. |
| 1129 | */ |
| 1130 | r = zd_iowrite32_locked(chip, 0, CR_GPI_EN); |
| 1131 | if (r) |
| 1132 | goto out; |
| 1133 | r = zd_iowrite32_locked(chip, CWIN_SIZE, CR_CWMIN_CWMAX); |
| 1134 | if (r) |
| 1135 | goto out; |
| 1136 | /* Currently we support IEEE 802.11g for full and high speed USB. |
| 1137 | * It might be discussed, whether we should suppport pure b mode for |
| 1138 | * full speed USB. |
| 1139 | */ |
Johannes Berg | 8318d78 | 2008-01-24 19:38:38 +0100 | [diff] [blame] | 1140 | r = set_mandatory_rates(chip, 1); |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 1141 | if (r) |
| 1142 | goto out; |
| 1143 | /* Disabling interrupts is certainly a smart thing here. |
| 1144 | */ |
| 1145 | r = disable_hwint(chip); |
| 1146 | if (r) |
| 1147 | goto out; |
| 1148 | r = read_pod(chip, &rf_type); |
| 1149 | if (r) |
| 1150 | goto out; |
| 1151 | r = hw_init(chip); |
| 1152 | if (r) |
| 1153 | goto out; |
| 1154 | r = zd_rf_init_hw(&chip->rf, rf_type); |
| 1155 | if (r) |
| 1156 | goto out; |
| 1157 | |
| 1158 | r = print_fw_version(chip); |
| 1159 | if (r) |
| 1160 | goto out; |
| 1161 | |
| 1162 | #ifdef DEBUG |
| 1163 | dump_fw_registers(chip); |
| 1164 | r = test_init(chip); |
| 1165 | if (r) |
| 1166 | goto out; |
| 1167 | #endif /* DEBUG */ |
| 1168 | |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 1169 | r = read_cal_int_tables(chip); |
| 1170 | if (r) |
| 1171 | goto out; |
| 1172 | |
| 1173 | print_id(chip); |
| 1174 | out: |
| 1175 | mutex_unlock(&chip->mutex); |
| 1176 | return r; |
| 1177 | } |
| 1178 | |
| 1179 | static int update_pwr_int(struct zd_chip *chip, u8 channel) |
| 1180 | { |
| 1181 | u8 value = chip->pwr_int_values[channel - 1]; |
Ulrich Kunitz | cbb5e6b | 2006-09-13 02:41:02 +0100 | [diff] [blame] | 1182 | return zd_iowrite16_locked(chip, value, CR31); |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 1183 | } |
| 1184 | |
| 1185 | static int update_pwr_cal(struct zd_chip *chip, u8 channel) |
| 1186 | { |
| 1187 | u8 value = chip->pwr_cal_values[channel-1]; |
Ulrich Kunitz | cbb5e6b | 2006-09-13 02:41:02 +0100 | [diff] [blame] | 1188 | return zd_iowrite16_locked(chip, value, CR68); |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 1189 | } |
| 1190 | |
| 1191 | static int update_ofdm_cal(struct zd_chip *chip, u8 channel) |
| 1192 | { |
Ulrich Kunitz | cbb5e6b | 2006-09-13 02:41:02 +0100 | [diff] [blame] | 1193 | struct zd_ioreq16 ioreqs[3]; |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 1194 | |
| 1195 | ioreqs[0].addr = CR67; |
| 1196 | ioreqs[0].value = chip->ofdm_cal_values[OFDM_36M_INDEX][channel-1]; |
| 1197 | ioreqs[1].addr = CR66; |
| 1198 | ioreqs[1].value = chip->ofdm_cal_values[OFDM_48M_INDEX][channel-1]; |
| 1199 | ioreqs[2].addr = CR65; |
| 1200 | ioreqs[2].value = chip->ofdm_cal_values[OFDM_54M_INDEX][channel-1]; |
| 1201 | |
Ulrich Kunitz | cbb5e6b | 2006-09-13 02:41:02 +0100 | [diff] [blame] | 1202 | return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs)); |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 1203 | } |
| 1204 | |
| 1205 | static int update_channel_integration_and_calibration(struct zd_chip *chip, |
| 1206 | u8 channel) |
| 1207 | { |
| 1208 | int r; |
| 1209 | |
Daniel Drake | 9c8fc71 | 2007-05-24 01:06:41 +0100 | [diff] [blame] | 1210 | if (!zd_rf_should_update_pwr_int(&chip->rf)) |
| 1211 | return 0; |
| 1212 | |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 1213 | r = update_pwr_int(chip, channel); |
| 1214 | if (r) |
| 1215 | return r; |
Daniel Drake | 74553ae | 2007-07-01 18:22:32 +0100 | [diff] [blame] | 1216 | if (zd_chip_is_zd1211b(chip)) { |
Ulrich Kunitz | cbb5e6b | 2006-09-13 02:41:02 +0100 | [diff] [blame] | 1217 | static const struct zd_ioreq16 ioreqs[] = { |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 1218 | { CR69, 0x28 }, |
| 1219 | {}, |
| 1220 | { CR69, 0x2a }, |
| 1221 | }; |
| 1222 | |
| 1223 | r = update_ofdm_cal(chip, channel); |
| 1224 | if (r) |
| 1225 | return r; |
| 1226 | r = update_pwr_cal(chip, channel); |
| 1227 | if (r) |
| 1228 | return r; |
Ulrich Kunitz | cbb5e6b | 2006-09-13 02:41:02 +0100 | [diff] [blame] | 1229 | r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs)); |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 1230 | if (r) |
| 1231 | return r; |
| 1232 | } |
| 1233 | |
| 1234 | return 0; |
| 1235 | } |
| 1236 | |
| 1237 | /* The CCK baseband gain can be optionally patched by the EEPROM */ |
| 1238 | static int patch_cck_gain(struct zd_chip *chip) |
| 1239 | { |
| 1240 | int r; |
| 1241 | u32 value; |
| 1242 | |
Daniel Drake | aaf83d4 | 2007-05-24 01:07:15 +0100 | [diff] [blame] | 1243 | if (!chip->patch_cck_gain || !zd_rf_should_patch_cck_gain(&chip->rf)) |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 1244 | return 0; |
| 1245 | |
| 1246 | ZD_ASSERT(mutex_is_locked(&chip->mutex)); |
| 1247 | r = zd_ioread32_locked(chip, &value, E2P_PHY_REG); |
| 1248 | if (r) |
| 1249 | return r; |
| 1250 | dev_dbg_f(zd_chip_dev(chip), "patching value %x\n", value & 0xff); |
Ulrich Kunitz | cbb5e6b | 2006-09-13 02:41:02 +0100 | [diff] [blame] | 1251 | return zd_iowrite16_locked(chip, value & 0xff, CR47); |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 1252 | } |
| 1253 | |
| 1254 | int zd_chip_set_channel(struct zd_chip *chip, u8 channel) |
| 1255 | { |
| 1256 | int r, t; |
| 1257 | |
| 1258 | mutex_lock(&chip->mutex); |
| 1259 | r = zd_chip_lock_phy_regs(chip); |
| 1260 | if (r) |
| 1261 | goto out; |
| 1262 | r = zd_rf_set_channel(&chip->rf, channel); |
| 1263 | if (r) |
| 1264 | goto unlock; |
| 1265 | r = update_channel_integration_and_calibration(chip, channel); |
| 1266 | if (r) |
| 1267 | goto unlock; |
| 1268 | r = patch_cck_gain(chip); |
| 1269 | if (r) |
| 1270 | goto unlock; |
| 1271 | r = patch_6m_band_edge(chip, channel); |
| 1272 | if (r) |
| 1273 | goto unlock; |
| 1274 | r = zd_iowrite32_locked(chip, 0, CR_CONFIG_PHILIPS); |
| 1275 | unlock: |
| 1276 | t = zd_chip_unlock_phy_regs(chip); |
| 1277 | if (t && !r) |
| 1278 | r = t; |
| 1279 | out: |
| 1280 | mutex_unlock(&chip->mutex); |
| 1281 | return r; |
| 1282 | } |
| 1283 | |
| 1284 | u8 zd_chip_get_channel(struct zd_chip *chip) |
| 1285 | { |
| 1286 | u8 channel; |
| 1287 | |
| 1288 | mutex_lock(&chip->mutex); |
| 1289 | channel = chip->rf.channel; |
| 1290 | mutex_unlock(&chip->mutex); |
| 1291 | return channel; |
| 1292 | } |
| 1293 | |
Ulrich Kunitz | 583afd1e | 2006-09-13 02:42:38 +0100 | [diff] [blame] | 1294 | int zd_chip_control_leds(struct zd_chip *chip, enum led_status status) |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 1295 | { |
Daniel Drake | 0ce34bc | 2006-12-12 01:26:11 +0000 | [diff] [blame] | 1296 | const zd_addr_t a[] = { |
| 1297 | fw_reg_addr(chip, FW_REG_LED_LINK_STATUS), |
Ulrich Kunitz | 583afd1e | 2006-09-13 02:42:38 +0100 | [diff] [blame] | 1298 | CR_LED, |
| 1299 | }; |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 1300 | |
Ulrich Kunitz | 583afd1e | 2006-09-13 02:42:38 +0100 | [diff] [blame] | 1301 | int r; |
| 1302 | u16 v[ARRAY_SIZE(a)]; |
| 1303 | struct zd_ioreq16 ioreqs[ARRAY_SIZE(a)] = { |
Daniel Drake | 0ce34bc | 2006-12-12 01:26:11 +0000 | [diff] [blame] | 1304 | [0] = { fw_reg_addr(chip, FW_REG_LED_LINK_STATUS) }, |
Ulrich Kunitz | 583afd1e | 2006-09-13 02:42:38 +0100 | [diff] [blame] | 1305 | [1] = { CR_LED }, |
| 1306 | }; |
| 1307 | u16 other_led; |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 1308 | |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 1309 | mutex_lock(&chip->mutex); |
Ulrich Kunitz | 583afd1e | 2006-09-13 02:42:38 +0100 | [diff] [blame] | 1310 | r = zd_ioread16v_locked(chip, v, (const zd_addr_t *)a, ARRAY_SIZE(a)); |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 1311 | if (r) |
Ulrich Kunitz | 583afd1e | 2006-09-13 02:42:38 +0100 | [diff] [blame] | 1312 | goto out; |
| 1313 | |
| 1314 | other_led = chip->link_led == LED1 ? LED2 : LED1; |
| 1315 | |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 1316 | switch (status) { |
Luis R. Rodriguez | 14b46c8 | 2009-08-04 14:04:17 -0700 | [diff] [blame] | 1317 | case ZD_LED_OFF: |
Ulrich Kunitz | 583afd1e | 2006-09-13 02:42:38 +0100 | [diff] [blame] | 1318 | ioreqs[0].value = FW_LINK_OFF; |
| 1319 | ioreqs[1].value = v[1] & ~(LED1|LED2); |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 1320 | break; |
Luis R. Rodriguez | 14b46c8 | 2009-08-04 14:04:17 -0700 | [diff] [blame] | 1321 | case ZD_LED_SCANNING: |
Ulrich Kunitz | 583afd1e | 2006-09-13 02:42:38 +0100 | [diff] [blame] | 1322 | ioreqs[0].value = FW_LINK_OFF; |
| 1323 | ioreqs[1].value = v[1] & ~other_led; |
| 1324 | if (get_seconds() % 3 == 0) { |
| 1325 | ioreqs[1].value &= ~chip->link_led; |
| 1326 | } else { |
| 1327 | ioreqs[1].value |= chip->link_led; |
| 1328 | } |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 1329 | break; |
Luis R. Rodriguez | 14b46c8 | 2009-08-04 14:04:17 -0700 | [diff] [blame] | 1330 | case ZD_LED_ASSOCIATED: |
Ulrich Kunitz | 583afd1e | 2006-09-13 02:42:38 +0100 | [diff] [blame] | 1331 | ioreqs[0].value = FW_LINK_TX; |
| 1332 | ioreqs[1].value = v[1] & ~other_led; |
| 1333 | ioreqs[1].value |= chip->link_led; |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 1334 | break; |
| 1335 | default: |
Ulrich Kunitz | 583afd1e | 2006-09-13 02:42:38 +0100 | [diff] [blame] | 1336 | r = -EINVAL; |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 1337 | goto out; |
| 1338 | } |
Ulrich Kunitz | 583afd1e | 2006-09-13 02:42:38 +0100 | [diff] [blame] | 1339 | |
| 1340 | if (v[0] != ioreqs[0].value || v[1] != ioreqs[1].value) { |
| 1341 | r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs)); |
| 1342 | if (r) |
| 1343 | goto out; |
| 1344 | } |
| 1345 | r = 0; |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 1346 | out: |
| 1347 | mutex_unlock(&chip->mutex); |
| 1348 | return r; |
| 1349 | } |
| 1350 | |
Daniel Drake | 459c51a | 2007-11-19 15:00:29 +0000 | [diff] [blame] | 1351 | int zd_chip_set_basic_rates(struct zd_chip *chip, u16 cr_rates) |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 1352 | { |
Daniel Drake | 459c51a | 2007-11-19 15:00:29 +0000 | [diff] [blame] | 1353 | int r; |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 1354 | |
Daniel Drake | 459c51a | 2007-11-19 15:00:29 +0000 | [diff] [blame] | 1355 | if (cr_rates & ~(CR_RATES_80211B|CR_RATES_80211G)) |
| 1356 | return -EINVAL; |
| 1357 | |
| 1358 | mutex_lock(&chip->mutex); |
| 1359 | r = zd_iowrite32_locked(chip, cr_rates, CR_BASIC_RATE_TBL); |
| 1360 | mutex_unlock(&chip->mutex); |
| 1361 | return r; |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 1362 | } |
| 1363 | |
Ulrich Kunitz | 64f222c | 2007-08-06 01:24:31 +0100 | [diff] [blame] | 1364 | static inline u8 zd_rate_from_ofdm_plcp_header(const void *rx_frame) |
| 1365 | { |
| 1366 | return ZD_OFDM | zd_ofdm_plcp_header_rate(rx_frame); |
| 1367 | } |
| 1368 | |
Daniel Drake | 459c51a | 2007-11-19 15:00:29 +0000 | [diff] [blame] | 1369 | /** |
| 1370 | * zd_rx_rate - report zd-rate |
| 1371 | * @rx_frame - received frame |
| 1372 | * @rx_status - rx_status as given by the device |
| 1373 | * |
| 1374 | * This function converts the rate as encoded in the received packet to the |
| 1375 | * zd-rate, we are using on other places in the driver. |
| 1376 | */ |
| 1377 | u8 zd_rx_rate(const void *rx_frame, const struct rx_status *status) |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 1378 | { |
Daniel Drake | 459c51a | 2007-11-19 15:00:29 +0000 | [diff] [blame] | 1379 | u8 zd_rate; |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 1380 | if (status->frame_status & ZD_RX_OFDM) { |
Daniel Drake | 459c51a | 2007-11-19 15:00:29 +0000 | [diff] [blame] | 1381 | zd_rate = zd_rate_from_ofdm_plcp_header(rx_frame); |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 1382 | } else { |
Ulrich Kunitz | 64f222c | 2007-08-06 01:24:31 +0100 | [diff] [blame] | 1383 | switch (zd_cck_plcp_header_signal(rx_frame)) { |
| 1384 | case ZD_CCK_PLCP_SIGNAL_1M: |
Daniel Drake | 459c51a | 2007-11-19 15:00:29 +0000 | [diff] [blame] | 1385 | zd_rate = ZD_CCK_RATE_1M; |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 1386 | break; |
Ulrich Kunitz | 64f222c | 2007-08-06 01:24:31 +0100 | [diff] [blame] | 1387 | case ZD_CCK_PLCP_SIGNAL_2M: |
Daniel Drake | 459c51a | 2007-11-19 15:00:29 +0000 | [diff] [blame] | 1388 | zd_rate = ZD_CCK_RATE_2M; |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 1389 | break; |
Ulrich Kunitz | 64f222c | 2007-08-06 01:24:31 +0100 | [diff] [blame] | 1390 | case ZD_CCK_PLCP_SIGNAL_5M5: |
Daniel Drake | 459c51a | 2007-11-19 15:00:29 +0000 | [diff] [blame] | 1391 | zd_rate = ZD_CCK_RATE_5_5M; |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 1392 | break; |
Ulrich Kunitz | 64f222c | 2007-08-06 01:24:31 +0100 | [diff] [blame] | 1393 | case ZD_CCK_PLCP_SIGNAL_11M: |
Daniel Drake | 459c51a | 2007-11-19 15:00:29 +0000 | [diff] [blame] | 1394 | zd_rate = ZD_CCK_RATE_11M; |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 1395 | break; |
| 1396 | default: |
Daniel Drake | 459c51a | 2007-11-19 15:00:29 +0000 | [diff] [blame] | 1397 | zd_rate = 0; |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 1398 | } |
| 1399 | } |
| 1400 | |
Daniel Drake | 459c51a | 2007-11-19 15:00:29 +0000 | [diff] [blame] | 1401 | return zd_rate; |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 1402 | } |
| 1403 | |
| 1404 | int zd_chip_switch_radio_on(struct zd_chip *chip) |
| 1405 | { |
| 1406 | int r; |
| 1407 | |
| 1408 | mutex_lock(&chip->mutex); |
| 1409 | r = zd_switch_radio_on(&chip->rf); |
| 1410 | mutex_unlock(&chip->mutex); |
| 1411 | return r; |
| 1412 | } |
| 1413 | |
| 1414 | int zd_chip_switch_radio_off(struct zd_chip *chip) |
| 1415 | { |
| 1416 | int r; |
| 1417 | |
| 1418 | mutex_lock(&chip->mutex); |
| 1419 | r = zd_switch_radio_off(&chip->rf); |
| 1420 | mutex_unlock(&chip->mutex); |
| 1421 | return r; |
| 1422 | } |
| 1423 | |
| 1424 | int zd_chip_enable_int(struct zd_chip *chip) |
| 1425 | { |
| 1426 | int r; |
| 1427 | |
| 1428 | mutex_lock(&chip->mutex); |
| 1429 | r = zd_usb_enable_int(&chip->usb); |
| 1430 | mutex_unlock(&chip->mutex); |
| 1431 | return r; |
| 1432 | } |
| 1433 | |
| 1434 | void zd_chip_disable_int(struct zd_chip *chip) |
| 1435 | { |
| 1436 | mutex_lock(&chip->mutex); |
| 1437 | zd_usb_disable_int(&chip->usb); |
| 1438 | mutex_unlock(&chip->mutex); |
Jussi Kivilinna | d741900 | 2011-01-31 20:47:17 +0200 | [diff] [blame] | 1439 | |
| 1440 | /* cancel pending interrupt work */ |
| 1441 | cancel_work_sync(&zd_chip_to_mac(chip)->process_intr); |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 1442 | } |
| 1443 | |
Daniel Drake | 459c51a | 2007-11-19 15:00:29 +0000 | [diff] [blame] | 1444 | int zd_chip_enable_rxtx(struct zd_chip *chip) |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 1445 | { |
| 1446 | int r; |
| 1447 | |
| 1448 | mutex_lock(&chip->mutex); |
Daniel Drake | 459c51a | 2007-11-19 15:00:29 +0000 | [diff] [blame] | 1449 | zd_usb_enable_tx(&chip->usb); |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 1450 | r = zd_usb_enable_rx(&chip->usb); |
Jussi Kivilinna | a0fd751 | 2011-01-31 20:49:52 +0200 | [diff] [blame^] | 1451 | zd_tx_watchdog_enable(&chip->usb); |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 1452 | mutex_unlock(&chip->mutex); |
| 1453 | return r; |
| 1454 | } |
| 1455 | |
Daniel Drake | 459c51a | 2007-11-19 15:00:29 +0000 | [diff] [blame] | 1456 | void zd_chip_disable_rxtx(struct zd_chip *chip) |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 1457 | { |
| 1458 | mutex_lock(&chip->mutex); |
Jussi Kivilinna | a0fd751 | 2011-01-31 20:49:52 +0200 | [diff] [blame^] | 1459 | zd_tx_watchdog_disable(&chip->usb); |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 1460 | zd_usb_disable_rx(&chip->usb); |
Daniel Drake | 459c51a | 2007-11-19 15:00:29 +0000 | [diff] [blame] | 1461 | zd_usb_disable_tx(&chip->usb); |
Daniel Drake | e85d091 | 2006-06-02 17:11:32 +0100 | [diff] [blame] | 1462 | mutex_unlock(&chip->mutex); |
| 1463 | } |
| 1464 | |
| 1465 | int zd_rfwritev_locked(struct zd_chip *chip, |
| 1466 | const u32* values, unsigned int count, u8 bits) |
| 1467 | { |
| 1468 | int r; |
| 1469 | unsigned int i; |
| 1470 | |
| 1471 | for (i = 0; i < count; i++) { |
| 1472 | r = zd_rfwrite_locked(chip, values[i], bits); |
| 1473 | if (r) |
| 1474 | return r; |
| 1475 | } |
| 1476 | |
| 1477 | return 0; |
| 1478 | } |
Daniel Drake | 20fe217 | 2006-08-12 17:59:42 +0100 | [diff] [blame] | 1479 | |
| 1480 | /* |
| 1481 | * We can optionally program the RF directly through CR regs, if supported by |
| 1482 | * the hardware. This is much faster than the older method. |
| 1483 | */ |
Daniel Drake | ec62bd9 | 2006-08-12 17:59:46 +0100 | [diff] [blame] | 1484 | int zd_rfwrite_cr_locked(struct zd_chip *chip, u32 value) |
Daniel Drake | 20fe217 | 2006-08-12 17:59:42 +0100 | [diff] [blame] | 1485 | { |
Joe Perches | 7253965 | 2010-11-20 18:39:03 -0800 | [diff] [blame] | 1486 | const struct zd_ioreq16 ioreqs[] = { |
Daniel Drake | 20fe217 | 2006-08-12 17:59:42 +0100 | [diff] [blame] | 1487 | { CR244, (value >> 16) & 0xff }, |
| 1488 | { CR243, (value >> 8) & 0xff }, |
| 1489 | { CR242, value & 0xff }, |
| 1490 | }; |
| 1491 | ZD_ASSERT(mutex_is_locked(&chip->mutex)); |
| 1492 | return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs)); |
| 1493 | } |
| 1494 | |
| 1495 | int zd_rfwritev_cr_locked(struct zd_chip *chip, |
| 1496 | const u32 *values, unsigned int count) |
| 1497 | { |
| 1498 | int r; |
| 1499 | unsigned int i; |
| 1500 | |
| 1501 | for (i = 0; i < count; i++) { |
| 1502 | r = zd_rfwrite_cr_locked(chip, values[i]); |
| 1503 | if (r) |
| 1504 | return r; |
| 1505 | } |
| 1506 | |
| 1507 | return 0; |
| 1508 | } |
Ulrich Kunitz | 9cdac96 | 2006-12-01 00:58:07 +0000 | [diff] [blame] | 1509 | |
| 1510 | int zd_chip_set_multicast_hash(struct zd_chip *chip, |
| 1511 | struct zd_mc_hash *hash) |
| 1512 | { |
Joe Perches | 7253965 | 2010-11-20 18:39:03 -0800 | [diff] [blame] | 1513 | const struct zd_ioreq32 ioreqs[] = { |
Ulrich Kunitz | 9cdac96 | 2006-12-01 00:58:07 +0000 | [diff] [blame] | 1514 | { CR_GROUP_HASH_P1, hash->low }, |
| 1515 | { CR_GROUP_HASH_P2, hash->high }, |
| 1516 | }; |
| 1517 | |
Ulrich Kunitz | 9cdac96 | 2006-12-01 00:58:07 +0000 | [diff] [blame] | 1518 | return zd_iowrite32a(chip, ioreqs, ARRAY_SIZE(ioreqs)); |
| 1519 | } |
Alina Friedrichsen | 5fe7319 | 2009-02-25 00:49:18 +0100 | [diff] [blame] | 1520 | |
| 1521 | u64 zd_chip_get_tsf(struct zd_chip *chip) |
| 1522 | { |
| 1523 | int r; |
| 1524 | static const zd_addr_t aw_pt_bi_addr[] = |
| 1525 | { CR_TSF_LOW_PART, CR_TSF_HIGH_PART }; |
| 1526 | u32 values[2]; |
| 1527 | u64 tsf; |
| 1528 | |
| 1529 | mutex_lock(&chip->mutex); |
| 1530 | r = zd_ioread32v_locked(chip, values, (const zd_addr_t *)aw_pt_bi_addr, |
| 1531 | ARRAY_SIZE(aw_pt_bi_addr)); |
| 1532 | mutex_unlock(&chip->mutex); |
| 1533 | if (r) |
| 1534 | return 0; |
| 1535 | |
| 1536 | tsf = values[1]; |
| 1537 | tsf = (tsf << 32) | values[0]; |
| 1538 | |
| 1539 | return tsf; |
| 1540 | } |