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Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -08001# Put here option for CPU selection and depending optimization
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -08002choice
3 prompt "Processor family"
Sam Ravnborg1032c0b2007-11-06 21:35:08 +01004 default M686 if X86_32
5 default GENERIC_CPU if X86_64
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -08006
7config M386
8 bool "386"
Sam Ravnborg1032c0b2007-11-06 21:35:08 +01009 depends on X86_32 && !UML
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -080010 ---help---
11 This is the processor type of your CPU. This information is used for
12 optimizing purposes. In order to compile a kernel that can run on
13 all x86 CPU types (albeit not optimally fast), you can specify
14 "386" here.
15
16 The kernel will not necessarily run on earlier architectures than
17 the one you have chosen, e.g. a Pentium optimized kernel will run on
18 a PPro, but not necessarily on a i486.
19
20 Here are the settings recommended for greatest speed:
21 - "386" for the AMD/Cyrix/Intel 386DX/DXL/SL/SLC/SX, Cyrix/TI
Dmitri Vorobievf7f17a62008-04-21 00:47:55 +040022 486DLC/DLC2, and UMC 486SX-S. Only "386" kernels will run on a 386
23 class machine.
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -080024 - "486" for the AMD/Cyrix/IBM/Intel 486DX/DX2/DX4 or
25 SL/SLC/SLC2/SLC3/SX/SX2 and UMC U5D or U5S.
26 - "586" for generic Pentium CPUs lacking the TSC
27 (time stamp counter) register.
28 - "Pentium-Classic" for the Intel Pentium.
29 - "Pentium-MMX" for the Intel Pentium MMX.
30 - "Pentium-Pro" for the Intel Pentium Pro.
31 - "Pentium-II" for the Intel Pentium II or pre-Coppermine Celeron.
32 - "Pentium-III" for the Intel Pentium III or Coppermine Celeron.
33 - "Pentium-4" for the Intel Pentium 4 or P4-based Celeron.
34 - "K6" for the AMD K6, K6-II and K6-III (aka K6-3D).
35 - "Athlon" for the AMD K7 family (Athlon/Duron/Thunderbird).
36 - "Crusoe" for the Transmeta Crusoe series.
37 - "Efficeon" for the Transmeta Efficeon series.
38 - "Winchip-C6" for original IDT Winchip.
Krzysztof Helt69d45dd2008-09-28 21:28:15 +020039 - "Winchip-2" for IDT Winchips with 3dNow! capabilities.
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -080040 - "GeodeGX1" for Geode GX1 (Cyrix MediaGX).
Jordan Crousef90b8112006-01-06 00:12:14 -080041 - "Geode GX/LX" For AMD Geode GX and LX processors.
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -080042 - "CyrixIII/VIA C3" for VIA Cyrix III or VIA C3.
Egry Gabor48a12042006-06-26 18:47:15 +020043 - "VIA C3-2" for VIA C3-2 "Nehemiah" (model 9 and above).
Simon Arlott0949be32007-05-02 19:27:05 +020044 - "VIA C7" for VIA C7.
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -080045
46 If you don't know what to do, choose "386".
47
48config M486
49 bool "486"
Sam Ravnborg1032c0b2007-11-06 21:35:08 +010050 depends on X86_32
Ingo Molnar8f9ca472009-02-05 16:21:53 +010051 ---help---
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -080052 Select this for a 486 series processor, either Intel or one of the
53 compatible processors from AMD, Cyrix, IBM, or Intel. Includes DX,
54 DX2, and DX4 variants; also SL/SLC/SLC2/SLC3/SX/SX2 and UMC U5D or
55 U5S.
56
57config M586
58 bool "586/K5/5x86/6x86/6x86MX"
Sam Ravnborg1032c0b2007-11-06 21:35:08 +010059 depends on X86_32
Ingo Molnar8f9ca472009-02-05 16:21:53 +010060 ---help---
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -080061 Select this for an 586 or 686 series processor such as the AMD K5,
62 the Cyrix 5x86, 6x86 and 6x86MX. This choice does not
63 assume the RDTSC (Read Time Stamp Counter) instruction.
64
65config M586TSC
66 bool "Pentium-Classic"
Sam Ravnborg1032c0b2007-11-06 21:35:08 +010067 depends on X86_32
Ingo Molnar8f9ca472009-02-05 16:21:53 +010068 ---help---
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -080069 Select this for a Pentium Classic processor with the RDTSC (Read
70 Time Stamp Counter) instruction for benchmarking.
71
72config M586MMX
73 bool "Pentium-MMX"
Sam Ravnborg1032c0b2007-11-06 21:35:08 +010074 depends on X86_32
Ingo Molnar8f9ca472009-02-05 16:21:53 +010075 ---help---
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -080076 Select this for a Pentium with the MMX graphics/multimedia
77 extended instructions.
78
79config M686
80 bool "Pentium-Pro"
Sam Ravnborg1032c0b2007-11-06 21:35:08 +010081 depends on X86_32
Ingo Molnar8f9ca472009-02-05 16:21:53 +010082 ---help---
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -080083 Select this for Intel Pentium Pro chips. This enables the use of
84 Pentium Pro extended instructions, and disables the init-time guard
85 against the f00f bug found in earlier Pentiums.
86
87config MPENTIUMII
88 bool "Pentium-II/Celeron(pre-Coppermine)"
Sam Ravnborg1032c0b2007-11-06 21:35:08 +010089 depends on X86_32
Ingo Molnar8f9ca472009-02-05 16:21:53 +010090 ---help---
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -080091 Select this for Intel chips based on the Pentium-II and
92 pre-Coppermine Celeron core. This option enables an unaligned
93 copy optimization, compiles the kernel with optimization flags
94 tailored for the chip, and applies any applicable Pentium Pro
95 optimizations.
96
97config MPENTIUMIII
98 bool "Pentium-III/Celeron(Coppermine)/Pentium-III Xeon"
Sam Ravnborg1032c0b2007-11-06 21:35:08 +010099 depends on X86_32
Ingo Molnar8f9ca472009-02-05 16:21:53 +0100100 ---help---
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800101 Select this for Intel chips based on the Pentium-III and
102 Celeron-Coppermine core. This option enables use of some
103 extended prefetch instructions in addition to the Pentium II
104 extensions.
105
106config MPENTIUMM
107 bool "Pentium M"
Sam Ravnborg1032c0b2007-11-06 21:35:08 +0100108 depends on X86_32
Ingo Molnar8f9ca472009-02-05 16:21:53 +0100109 ---help---
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800110 Select this for Intel Pentium M (not Pentium-4 M)
111 notebook chips.
112
113config MPENTIUM4
Andi Kleenc55d92d2006-12-07 02:14:09 +0100114 bool "Pentium-4/Celeron(P4-based)/Pentium-4 M/older Xeon"
Sam Ravnborg1032c0b2007-11-06 21:35:08 +0100115 depends on X86_32
Ingo Molnar8f9ca472009-02-05 16:21:53 +0100116 ---help---
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800117 Select this for Intel Pentium 4 chips. This includes the
Oliver Pinter75e38082007-10-17 18:04:36 +0200118 Pentium 4, Pentium D, P4-based Celeron and Xeon, and
119 Pentium-4 M (not Pentium M) chips. This option enables compile
120 flags optimized for the chip, uses the correct cache line size, and
121 applies any applicable optimizations.
122
123 CPUIDs: F[0-6][1-A] (in /proc/cpuinfo show = cpu family : 15 )
124
125 Select this for:
126 Pentiums (Pentium 4, Pentium D, Celeron, Celeron D) corename:
127 -Willamette
128 -Northwood
129 -Mobile Pentium 4
130 -Mobile Pentium 4 M
131 -Extreme Edition (Gallatin)
132 -Prescott
133 -Prescott 2M
134 -Cedar Mill
135 -Presler
136 -Smithfiled
137 Xeons (Intel Xeon, Xeon MP, Xeon LV, Xeon MV) corename:
138 -Foster
139 -Prestonia
140 -Gallatin
141 -Nocona
142 -Irwindale
143 -Cranford
144 -Potomac
145 -Paxville
146 -Dempsey
147
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800148
149config MK6
150 bool "K6/K6-II/K6-III"
Sam Ravnborg1032c0b2007-11-06 21:35:08 +0100151 depends on X86_32
Ingo Molnar8f9ca472009-02-05 16:21:53 +0100152 ---help---
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800153 Select this for an AMD K6-family processor. Enables use of
154 some extended instructions, and passes appropriate optimization
155 flags to GCC.
156
157config MK7
158 bool "Athlon/Duron/K7"
Sam Ravnborg1032c0b2007-11-06 21:35:08 +0100159 depends on X86_32
Ingo Molnar8f9ca472009-02-05 16:21:53 +0100160 ---help---
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800161 Select this for an AMD Athlon K7-family processor. Enables use of
162 some extended instructions, and passes appropriate optimization
163 flags to GCC.
164
165config MK8
166 bool "Opteron/Athlon64/Hammer/K8"
Ingo Molnar8f9ca472009-02-05 16:21:53 +0100167 ---help---
Borislav Petkov36723bf2009-02-04 21:44:04 +0100168 Select this for an AMD Opteron or Athlon64 Hammer-family processor.
169 Enables use of some extended instructions, and passes appropriate
170 optimization flags to GCC.
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800171
172config MCRUSOE
173 bool "Crusoe"
Sam Ravnborg1032c0b2007-11-06 21:35:08 +0100174 depends on X86_32
Ingo Molnar8f9ca472009-02-05 16:21:53 +0100175 ---help---
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800176 Select this for a Transmeta Crusoe processor. Treats the processor
177 like a 586 with TSC, and sets some GCC optimization flags (like a
178 Pentium Pro with no alignment requirements).
179
180config MEFFICEON
181 bool "Efficeon"
Sam Ravnborg1032c0b2007-11-06 21:35:08 +0100182 depends on X86_32
Ingo Molnar8f9ca472009-02-05 16:21:53 +0100183 ---help---
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800184 Select this for a Transmeta Efficeon processor.
185
186config MWINCHIPC6
187 bool "Winchip-C6"
Sam Ravnborg1032c0b2007-11-06 21:35:08 +0100188 depends on X86_32
Ingo Molnar8f9ca472009-02-05 16:21:53 +0100189 ---help---
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800190 Select this for an IDT Winchip C6 chip. Linux and GCC
191 treat this chip as a 586TSC with some extended instructions
192 and alignment requirements.
193
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800194config MWINCHIP3D
Krzysztof Helt69d45dd2008-09-28 21:28:15 +0200195 bool "Winchip-2/Winchip-2A/Winchip-3"
Sam Ravnborg1032c0b2007-11-06 21:35:08 +0100196 depends on X86_32
Ingo Molnar8f9ca472009-02-05 16:21:53 +0100197 ---help---
Krzysztof Helt69d45dd2008-09-28 21:28:15 +0200198 Select this for an IDT Winchip-2, 2A or 3. Linux and GCC
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800199 treat this chip as a 586TSC with some extended instructions
David Sterba3dde6ad2007-05-09 07:12:20 +0200200 and alignment requirements. Also enable out of order memory
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800201 stores for this CPU, which can increase performance of some
202 operations.
203
Ian Campbellce9c99a2011-04-08 07:42:29 +0100204config MELAN
205 bool "AMD Elan"
206 depends on X86_32
207 ---help---
208 Select this for an AMD Elan processor.
209
210 Do not use this option for K6/Athlon/Opteron processors!
211
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800212config MGEODEGX1
213 bool "GeodeGX1"
Sam Ravnborg1032c0b2007-11-06 21:35:08 +0100214 depends on X86_32
Ingo Molnar8f9ca472009-02-05 16:21:53 +0100215 ---help---
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800216 Select this for a Geode GX1 (Cyrix MediaGX) chip.
217
Jordan Crousef90b8112006-01-06 00:12:14 -0800218config MGEODE_LX
Harvey Harrison96daa8c2008-01-30 13:31:03 +0100219 bool "Geode GX/LX"
Sam Ravnborg1032c0b2007-11-06 21:35:08 +0100220 depends on X86_32
Ingo Molnar8f9ca472009-02-05 16:21:53 +0100221 ---help---
Harvey Harrison96daa8c2008-01-30 13:31:03 +0100222 Select this for AMD Geode GX and LX processors.
Jordan Crousef90b8112006-01-06 00:12:14 -0800223
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800224config MCYRIXIII
225 bool "CyrixIII/VIA-C3"
Sam Ravnborg1032c0b2007-11-06 21:35:08 +0100226 depends on X86_32
Ingo Molnar8f9ca472009-02-05 16:21:53 +0100227 ---help---
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800228 Select this for a Cyrix III or C3 chip. Presently Linux and GCC
229 treat this chip as a generic 586. Whilst the CPU is 686 class,
230 it lacks the cmov extension which gcc assumes is present when
231 generating 686 code.
232 Note that Nehemiah (Model 9) and above will not boot with this
233 kernel due to them lacking the 3DNow! instructions used in earlier
234 incarnations of the CPU.
235
236config MVIAC3_2
237 bool "VIA C3-2 (Nehemiah)"
Sam Ravnborg1032c0b2007-11-06 21:35:08 +0100238 depends on X86_32
Ingo Molnar8f9ca472009-02-05 16:21:53 +0100239 ---help---
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800240 Select this for a VIA C3 "Nehemiah". Selecting this enables usage
241 of SSE and tells gcc to treat the CPU as a 686.
242 Note, this kernel will not boot on older (pre model 9) C3s.
243
Simon Arlott0949be32007-05-02 19:27:05 +0200244config MVIAC7
245 bool "VIA C7"
Sam Ravnborg1032c0b2007-11-06 21:35:08 +0100246 depends on X86_32
Ingo Molnar8f9ca472009-02-05 16:21:53 +0100247 ---help---
Simon Arlott0949be32007-05-02 19:27:05 +0200248 Select this for a VIA C7. Selecting this uses the correct cache
249 shift and tells gcc to treat the CPU as a 686.
250
Sam Ravnborg1032c0b2007-11-06 21:35:08 +0100251config MPSC
252 bool "Intel P4 / older Netburst based Xeon"
253 depends on X86_64
Ingo Molnar8f9ca472009-02-05 16:21:53 +0100254 ---help---
Sam Ravnborg1032c0b2007-11-06 21:35:08 +0100255 Optimize for Intel Pentium 4, Pentium D and older Nocona/Dempsey
256 Xeon CPUs with Intel 64bit which is compatible with x86-64.
257 Note that the latest Xeons (Xeon 51xx and 53xx) are not based on the
Harvey Harrison96daa8c2008-01-30 13:31:03 +0100258 Netburst core and shouldn't use this option. You can distinguish them
Sam Ravnborg1032c0b2007-11-06 21:35:08 +0100259 using the cpu family field
260 in /proc/cpuinfo. Family 15 is an older Xeon, Family 6 a newer one.
261
262config MCORE2
263 bool "Core 2/newer Xeon"
Ingo Molnar8f9ca472009-02-05 16:21:53 +0100264 ---help---
Borislav Petkov36723bf2009-02-04 21:44:04 +0100265
266 Select this for Intel Core 2 and newer Core 2 Xeons (Xeon 51xx and
267 53xx) CPUs. You can distinguish newer from older Xeons by the CPU
268 family in /proc/cpuinfo. Newer ones have 6 and older ones 15
269 (not a typo)
Sam Ravnborg1032c0b2007-11-06 21:35:08 +0100270
Tobias Doerffel366d19e2009-08-21 23:06:23 +0200271config MATOM
272 bool "Intel Atom"
273 ---help---
274
275 Select this for the Intel Atom platform. Intel Atom CPUs have an
276 in-order pipelining architecture and thus can benefit from
277 accordingly optimized code. Use a recent GCC with specific Atom
278 support in order to fully benefit from selecting this option.
279
Sam Ravnborg1032c0b2007-11-06 21:35:08 +0100280config GENERIC_CPU
281 bool "Generic-x86-64"
282 depends on X86_64
Ingo Molnar8f9ca472009-02-05 16:21:53 +0100283 ---help---
Sam Ravnborg1032c0b2007-11-06 21:35:08 +0100284 Generic x86-64 CPU.
285 Run equally well on all x86-64 CPUs.
286
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800287endchoice
288
289config X86_GENERIC
Sam Ravnborg1032c0b2007-11-06 21:35:08 +0100290 bool "Generic x86 support"
291 depends on X86_32
Ingo Molnar8f9ca472009-02-05 16:21:53 +0100292 ---help---
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800293 Instead of just including optimizations for the selected
294 x86 variant (e.g. PII, Crusoe or Athlon), include some more
295 generic optimizations as well. This will make the kernel
296 perform better on x86 CPUs other than that selected.
297
298 This is really intended for distributors who need more
299 generic optimizations.
300
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800301#
302# Define implied options from the CPU selection here
Jan Beulich350f8f52009-11-13 11:54:40 +0000303config X86_INTERNODE_CACHE_SHIFT
Sam Ravnborg1032c0b2007-11-06 21:35:08 +0100304 int
Jan Beulich350f8f52009-11-13 11:54:40 +0000305 default "12" if X86_VSMP
306 default "7" if NUMA
307 default X86_L1_CACHE_SHIFT
Sam Ravnborg1032c0b2007-11-06 21:35:08 +0100308
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800309config X86_CMPXCHG
Sam Ravnborg1032c0b2007-11-06 21:35:08 +0100310 def_bool X86_64 || (X86_32 && !M386)
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800311
Christoph Lameter7296e082010-12-14 10:28:44 -0600312config CMPXCHG_LOCAL
313 def_bool X86_64 || (X86_32 && !M386)
314
Christoph Lameter3824abd2011-06-01 12:25:47 -0500315config CMPXCHG_DOUBLE
316 def_bool y
317
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800318config X86_L1_CACHE_SHIFT
319 int
Ingo Molnar0a2a18b72009-01-12 23:37:16 +0100320 default "7" if MPENTIUM4 || MPSC
Jan Beulich350f8f52009-11-13 11:54:40 +0000321 default "6" if MK7 || MK8 || MPENTIUMM || MCORE2 || MATOM || MVIAC7 || X86_GENERIC || GENERIC_CPU
Ian Campbellce9c99a2011-04-08 07:42:29 +0100322 default "4" if MELAN || M486 || M386 || MGEODEGX1
Krzysztof Helt69d45dd2008-09-28 21:28:15 +0200323 default "5" if MWINCHIP3D || MWINCHIPC6 || MCRUSOE || MEFFICEON || MCYRIXIII || MK6 || MPENTIUMIII || MPENTIUMII || M686 || M586MMX || M586TSC || M586 || MVIAC3_2 || MGEODE_LX
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800324
Andi Kleenc7f81c92007-05-02 19:27:20 +0200325config X86_XADD
Harvey Harrison96daa8c2008-01-30 13:31:03 +0100326 def_bool y
Linus Torvaldsbafaecd2010-01-12 18:16:42 -0800327 depends on X86_64 || !M386
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800328
329config X86_PPRO_FENCE
Nick Pigginfb0328e2008-01-30 13:32:31 +0100330 bool "PentiumPro memory ordering errata workaround"
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800331 depends on M686 || M586MMX || M586TSC || M586 || M486 || M386 || MGEODEGX1
Ingo Molnar8f9ca472009-02-05 16:21:53 +0100332 ---help---
Borislav Petkov36723bf2009-02-04 21:44:04 +0100333 Old PentiumPro multiprocessor systems had errata that could cause
334 memory operations to violate the x86 ordering standard in rare cases.
335 Enabling this option will attempt to work around some (but not all)
Lucas De Marchi0d2eb442011-03-17 16:24:16 -0300336 occurrences of this problem, at the cost of much heavier spinlock and
Borislav Petkov36723bf2009-02-04 21:44:04 +0100337 memory barrier operations.
Nick Pigginfb0328e2008-01-30 13:32:31 +0100338
Borislav Petkov36723bf2009-02-04 21:44:04 +0100339 If unsure, say n here. Even distro kernels should think twice before
340 enabling this: there are few systems, and an unlikely bug.
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800341
342config X86_F00F_BUG
Harvey Harrison96daa8c2008-01-30 13:31:03 +0100343 def_bool y
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800344 depends on M586MMX || M586TSC || M586 || M486 || M386
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800345
Brian Gerst40d2e762010-03-21 09:00:43 -0400346config X86_INVD_BUG
347 def_bool y
348 depends on M486 || M386
349
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800350config X86_WP_WORKS_OK
Harvey Harrison96daa8c2008-01-30 13:31:03 +0100351 def_bool y
Glauber Costa293e6a22008-06-25 11:40:42 -0300352 depends on !M386
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800353
354config X86_INVLPG
Harvey Harrison96daa8c2008-01-30 13:31:03 +0100355 def_bool y
Sam Ravnborg1032c0b2007-11-06 21:35:08 +0100356 depends on X86_32 && !M386
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800357
358config X86_BSWAP
Harvey Harrison96daa8c2008-01-30 13:31:03 +0100359 def_bool y
Sam Ravnborg1032c0b2007-11-06 21:35:08 +0100360 depends on X86_32 && !M386
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800361
362config X86_POPAD_OK
Harvey Harrison96daa8c2008-01-30 13:31:03 +0100363 def_bool y
Sam Ravnborg1032c0b2007-11-06 21:35:08 +0100364 depends on X86_32 && !M386
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800365
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800366config X86_ALIGNMENT_16
Harvey Harrison96daa8c2008-01-30 13:31:03 +0100367 def_bool y
Ian Campbellce9c99a2011-04-08 07:42:29 +0100368 depends on MWINCHIP3D || MWINCHIPC6 || MCYRIXIII || MELAN || MK6 || M586MMX || M586TSC || M586 || M486 || MVIAC3_2 || MGEODEGX1
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800369
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800370config X86_INTEL_USERCOPY
Harvey Harrison96daa8c2008-01-30 13:31:03 +0100371 def_bool y
Andi Kleenc55d92d2006-12-07 02:14:09 +0100372 depends on MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M586MMX || X86_GENERIC || MK8 || MK7 || MEFFICEON || MCORE2
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800373
374config X86_USE_PPRO_CHECKSUM
Harvey Harrison96daa8c2008-01-30 13:31:03 +0100375 def_bool y
Jon Nettleton1eda75c2011-03-16 15:32:47 +0000376 depends on MWINCHIP3D || MWINCHIPC6 || MCYRIXIII || MK7 || MK6 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MK8 || MVIAC3_2 || MVIAC7 || MEFFICEON || MGEODE_LX || MCORE2 || MATOM
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800377
378config X86_USE_3DNOW
Harvey Harrison96daa8c2008-01-30 13:31:03 +0100379 def_bool y
Paolo 'Blaisorblade' Giarrusso1b4ad242006-10-11 01:21:35 -0700380 depends on (MCYRIXIII || MK7 || MGEODE_LX) && !UML
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800381
382config X86_OOSTORE
Harvey Harrison96daa8c2008-01-30 13:31:03 +0100383 def_bool y
Krzysztof Helt69d45dd2008-09-28 21:28:15 +0200384 depends on (MWINCHIP3D || MWINCHIPC6) && MTRR
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800385
H. Peter Anvin959b3be2008-02-14 14:56:45 -0800386#
387# P6_NOPs are a relatively minor optimization that require a family >=
388# 6 processor, except that it is broken on certain VIA chips.
389# Furthermore, AMD chips prefer a totally different sequence of NOPs
Linus Torvalds14469a82008-09-05 09:30:14 -0700390# (which work on all CPUs). In addition, it looks like Virtual PC
391# does not understand them.
392#
393# As a result, disallow these if we're not compiling for X86_64 (these
394# NOPs do work on all x86-64 capable chips); the list of processors in
395# the right-hand clause are the cores that benefit from this optimization.
H. Peter Anvin959b3be2008-02-14 14:56:45 -0800396#
H. Peter Anvin7343b3b2008-02-14 14:52:05 -0800397config X86_P6_NOP
398 def_bool y
Linus Torvalds14469a82008-09-05 09:30:14 -0700399 depends on X86_64
400 depends on (MCORE2 || MPENTIUM4 || MPSC)
H. Peter Anvin7343b3b2008-02-14 14:52:05 -0800401
Paolo 'Blaisorblade' Giarrusso96d55b82005-10-30 15:00:07 -0800402config X86_TSC
Harvey Harrison96daa8c2008-01-30 13:31:03 +0100403 def_bool y
Tobias Doerffel366d19e2009-08-21 23:06:23 +0200404 depends on ((MWINCHIP3D || MCRUSOE || MEFFICEON || MCYRIXIII || MK7 || MK6 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || M586MMX || M586TSC || MK8 || MVIAC3_2 || MVIAC7 || MGEODEGX1 || MGEODE_LX || MCORE2 || MATOM) && !X86_NUMAQ) || X86_64
Andi Kleenc7f81c92007-05-02 19:27:20 +0200405
Jan Beulichf8096f92008-04-22 16:27:29 +0100406config X86_CMPXCHG64
407 def_bool y
Rusty Russelldb677ff2010-01-05 12:48:49 +1030408 depends on X86_PAE || X86_64 || MCORE2 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MATOM
Jan Beulichf8096f92008-04-22 16:27:29 +0100409
Andi Kleenc7f81c92007-05-02 19:27:20 +0200410# this should be set for all -march=.. options where the compiler
411# generates cmov.
412config X86_CMOV
Harvey Harrison96daa8c2008-01-30 13:31:03 +0100413 def_bool y
Matteo Croce98059e32009-10-01 17:11:10 +0200414 depends on (MK8 || MK7 || MCORE2 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MVIAC3_2 || MVIAC7 || MCRUSOE || MEFFICEON || X86_64 || MATOM || MGEODE_LX)
Andi Kleenc7f81c92007-05-02 19:27:20 +0200415
H. Peter Anvinde32e042007-07-11 12:18:30 -0700416config X86_MINIMUM_CPU_FAMILY
Andi Kleenc7f81c92007-05-02 19:27:20 +0200417 int
Sam Ravnborg1032c0b2007-11-06 21:35:08 +0100418 default "64" if X86_64
H. Peter Anvin7343b3b2008-02-14 14:52:05 -0800419 default "6" if X86_32 && X86_P6_NOP
Linus Torvalds982d0072009-09-30 17:57:27 -0700420 default "5" if X86_32 && X86_CMPXCHG64
Sam Ravnborg1032c0b2007-11-06 21:35:08 +0100421 default "4" if X86_32 && (X86_XADD || X86_CMPXCHG || X86_BSWAP || X86_WP_WORKS_OK)
H. Peter Anvinde32e042007-07-11 12:18:30 -0700422 default "3"
Andi Kleenc7f81c92007-05-02 19:27:20 +0200423
Roland McGrath0a049bb2008-01-30 13:30:54 +0100424config X86_DEBUGCTLMSR
Harvey Harrison96daa8c2008-01-30 13:31:03 +0100425 def_bool y
Al Viro5641f1f2009-01-05 17:19:02 +0000426 depends on !(MK6 || MWINCHIPC6 || MWINCHIP3D || MCYRIXIII || M586MMX || M586TSC || M586 || M486 || M386) && !UML
Thomas Petazzoni8d02c212008-08-05 11:45:19 +0200427
428menuconfig PROCESSOR_SELECT
David Rientjes6a108a12011-01-20 14:44:16 -0800429 bool "Supported processor vendors" if EXPERT
Ingo Molnar8f9ca472009-02-05 16:21:53 +0100430 ---help---
Thomas Petazzoni8d02c212008-08-05 11:45:19 +0200431 This lets you choose what x86 vendor support code your kernel
432 will include.
433
Yinghai Lu879d7922008-09-09 16:40:37 -0700434config CPU_SUP_INTEL
Thomas Petazzoni8d02c212008-08-05 11:45:19 +0200435 default y
436 bool "Support Intel processors" if PROCESSOR_SELECT
Ingo Molnar8f9ca472009-02-05 16:21:53 +0100437 ---help---
Ingo Molnarb7b3a422008-10-12 15:36:24 +0200438 This enables detection, tunings and quirks for Intel processors
439
440 You need this enabled if you want your kernel to run on an
441 Intel CPU. Disabling this option on other types of CPUs
442 makes the kernel a tiny bit smaller. Disabling it on an Intel
443 CPU might render the kernel unbootable.
444
445 If unsure, say N.
Thomas Petazzoni8d02c212008-08-05 11:45:19 +0200446
447config CPU_SUP_CYRIX_32
448 default y
449 bool "Support Cyrix processors" if PROCESSOR_SELECT
450 depends on !64BIT
Ingo Molnar8f9ca472009-02-05 16:21:53 +0100451 ---help---
Ingo Molnarb7b3a422008-10-12 15:36:24 +0200452 This enables detection, tunings and quirks for Cyrix processors
453
454 You need this enabled if you want your kernel to run on a
455 Cyrix CPU. Disabling this option on other types of CPUs
456 makes the kernel a tiny bit smaller. Disabling it on a Cyrix
457 CPU might render the kernel unbootable.
458
459 If unsure, say N.
Thomas Petazzoni8d02c212008-08-05 11:45:19 +0200460
Yinghai Luff731522008-09-07 17:58:56 -0700461config CPU_SUP_AMD
Thomas Petazzoni8d02c212008-08-05 11:45:19 +0200462 default y
463 bool "Support AMD processors" if PROCESSOR_SELECT
Ingo Molnar8f9ca472009-02-05 16:21:53 +0100464 ---help---
Ingo Molnarb7b3a422008-10-12 15:36:24 +0200465 This enables detection, tunings and quirks for AMD processors
466
467 You need this enabled if you want your kernel to run on an
468 AMD CPU. Disabling this option on other types of CPUs
469 makes the kernel a tiny bit smaller. Disabling it on an AMD
470 CPU might render the kernel unbootable.
471
472 If unsure, say N.
Thomas Petazzoni8d02c212008-08-05 11:45:19 +0200473
Sebastian Andrzej Siewior48f4c482009-03-14 12:24:02 +0100474config CPU_SUP_CENTAUR
Thomas Petazzoni8d02c212008-08-05 11:45:19 +0200475 default y
476 bool "Support Centaur processors" if PROCESSOR_SELECT
Ingo Molnar8f9ca472009-02-05 16:21:53 +0100477 ---help---
Ingo Molnarb7b3a422008-10-12 15:36:24 +0200478 This enables detection, tunings and quirks for Centaur processors
479
480 You need this enabled if you want your kernel to run on a
481 Centaur CPU. Disabling this option on other types of CPUs
482 makes the kernel a tiny bit smaller. Disabling it on a Centaur
483 CPU might render the kernel unbootable.
484
485 If unsure, say N.
Thomas Petazzoni8d02c212008-08-05 11:45:19 +0200486
487config CPU_SUP_TRANSMETA_32
488 default y
489 bool "Support Transmeta processors" if PROCESSOR_SELECT
490 depends on !64BIT
Ingo Molnar8f9ca472009-02-05 16:21:53 +0100491 ---help---
Ingo Molnarb7b3a422008-10-12 15:36:24 +0200492 This enables detection, tunings and quirks for Transmeta processors
493
494 You need this enabled if you want your kernel to run on a
495 Transmeta CPU. Disabling this option on other types of CPUs
496 makes the kernel a tiny bit smaller. Disabling it on a Transmeta
497 CPU might render the kernel unbootable.
498
499 If unsure, say N.
Thomas Petazzoni8d02c212008-08-05 11:45:19 +0200500
501config CPU_SUP_UMC_32
502 default y
503 bool "Support UMC processors" if PROCESSOR_SELECT
504 depends on !64BIT
Ingo Molnar8f9ca472009-02-05 16:21:53 +0100505 ---help---
Ingo Molnarb7b3a422008-10-12 15:36:24 +0200506 This enables detection, tunings and quirks for UMC processors
507
508 You need this enabled if you want your kernel to run on a
509 UMC CPU. Disabling this option on other types of CPUs
510 makes the kernel a tiny bit smaller. Disabling it on a UMC
511 CPU might render the kernel unbootable.
512
513 If unsure, say N.