Laurent Pinchart | f94859c | 2013-10-17 23:54:07 +0200 | [diff] [blame] | 1 | * Renesas CPG Module Stop (MSTP) Clocks |
| 2 | |
| 3 | The CPG can gate SoC device clocks. The gates are organized in groups of up to |
| 4 | 32 gates. |
| 5 | |
| 6 | This device tree binding describes a single 32 gate clocks group per node. |
| 7 | Clocks are referenced by user nodes by the MSTP node phandle and the clock |
| 8 | index in the group, from 0 to 31. |
| 9 | |
| 10 | Required Properties: |
| 11 | |
| 12 | - compatible: Must be one of the following |
Wolfram Sang | b557dea | 2014-05-14 03:10:05 +0200 | [diff] [blame] | 13 | - "renesas,r7s72100-mstp-clocks" for R7S72100 (RZ) MSTP gate clocks |
Ulrich Hecht | b32c44b | 2014-09-02 11:13:04 +0200 | [diff] [blame] | 14 | - "renesas,r8a7740-mstp-clocks" for R8A7740 (R-Mobile A1) MSTP gate clocks |
Simon Horman | 5483bf6 | 2014-04-18 08:05:51 +0900 | [diff] [blame] | 15 | - "renesas,r8a7779-mstp-clocks" for R8A7779 (R-Car H1) MSTP gate clocks |
Laurent Pinchart | f94859c | 2013-10-17 23:54:07 +0200 | [diff] [blame] | 16 | - "renesas,r8a7790-mstp-clocks" for R8A7790 (R-Car H2) MSTP gate clocks |
| 17 | - "renesas,r8a7791-mstp-clocks" for R8A7791 (R-Car M2) MSTP gate clocks |
Ulrich Hecht | 5acb7bb | 2014-08-29 20:15:08 +0200 | [diff] [blame] | 18 | - "renesas,r8a7794-mstp-clocks" for R8A7794 (R-Car E2) MSTP gate clocks |
Ulrich Hecht | b32c44b | 2014-09-02 11:13:04 +0200 | [diff] [blame] | 19 | - "renesas,sh73a0-mstp-clocks" for SH73A0 (SH-MobileAG5) MSTP gate clocks |
Laurent Pinchart | f94859c | 2013-10-17 23:54:07 +0200 | [diff] [blame] | 20 | - "renesas,cpg-mstp-clock" for generic MSTP gate clocks |
| 21 | - reg: Base address and length of the I/O mapped registers used by the MSTP |
| 22 | clocks. The first register is the clock control register and is mandatory. |
| 23 | The second register is the clock status register and is optional when not |
| 24 | implemented in hardware. |
| 25 | - clocks: Reference to the parent clocks, one per output clock. The parents |
| 26 | must appear in the same order as the output clocks. |
| 27 | - #clock-cells: Must be 1 |
| 28 | - clock-output-names: The name of the clocks as free-form strings |
Laurent Pinchart | 6048099 | 2014-02-19 18:13:24 +0100 | [diff] [blame] | 29 | - renesas,clock-indices: Indices of the gate clocks into the group (0 to 31) |
Laurent Pinchart | f94859c | 2013-10-17 23:54:07 +0200 | [diff] [blame] | 30 | |
Laurent Pinchart | 6048099 | 2014-02-19 18:13:24 +0100 | [diff] [blame] | 31 | The clocks, clock-output-names and renesas,clock-indices properties contain one |
Laurent Pinchart | f94859c | 2013-10-17 23:54:07 +0200 | [diff] [blame] | 32 | entry per gate clock. The MSTP groups are sparsely populated. Unimplemented |
| 33 | gate clocks must not be declared. |
| 34 | |
| 35 | |
| 36 | Example |
| 37 | ------- |
| 38 | |
| 39 | #include <dt-bindings/clock/r8a7790-clock.h> |
| 40 | |
| 41 | mstp3_clks: mstp3_clks@e615013c { |
| 42 | compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; |
| 43 | reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; |
| 44 | clocks = <&cp_clk>, <&mmc1_clk>, <&sd3_clk>, <&sd2_clk>, |
| 45 | <&cpg_clocks R8A7790_CLK_SD1>, <&cpg_clocks R8A7790_CLK_SD0>, |
| 46 | <&mmc0_clk>; |
| 47 | #clock-cells = <1>; |
| 48 | clock-output-names = |
| 49 | "tpu0", "mmcif1", "sdhi3", "sdhi2", |
| 50 | "sdhi1", "sdhi0", "mmcif0"; |
Ben Dooks | 8e33f91 | 2014-04-15 17:06:34 +0100 | [diff] [blame] | 51 | clock-indices = < |
Laurent Pinchart | f94859c | 2013-10-17 23:54:07 +0200 | [diff] [blame] | 52 | R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SDHI3 |
| 53 | R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0 |
| 54 | R8A7790_CLK_MMCIF0 |
| 55 | >; |
| 56 | }; |