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gerrit-public.fairphone.software / kernel / msm-4.9 / a15ebd371992dbadb8a30367fd80cb5cd73b8fb1 / . / drivers / net / ethernet / qlogic / qlcnic / qlcnic_hw.h
blob: 937d75f939aa508b6c062c481f6cecc3c0064ff8 [file] [log] [blame]
Sony Chacko7e2cf4f2013-01-01 03:20:17 +0000[diff] [blame]1#ifndef __QLCNIC_HW_H
2#define __QLCNIC_HW_H
3
4/* Common registers in 83xx and 82xx */
5enum qlcnic_regs {
6 QLCNIC_PEG_HALT_STATUS1 = 0,
7 QLCNIC_PEG_HALT_STATUS2,
8 QLCNIC_PEG_ALIVE_COUNTER,
9 QLCNIC_FLASH_LOCK_OWNER,
10 QLCNIC_FW_CAPABILITIES,
11 QLCNIC_CRB_DRV_ACTIVE,
12 QLCNIC_CRB_DEV_STATE,
13 QLCNIC_CRB_DRV_STATE,
14 QLCNIC_CRB_DRV_SCRATCH,
15 QLCNIC_CRB_DEV_PARTITION_INFO,
16 QLCNIC_CRB_DRV_IDC_VER,
17 QLCNIC_FW_VERSION_MAJOR,
18 QLCNIC_FW_VERSION_MINOR,
19 QLCNIC_FW_VERSION_SUB,
20 QLCNIC_CRB_DEV_NPAR_STATE,
21 QLCNIC_FW_IMG_VALID,
22 QLCNIC_CMDPEG_STATE,
23 QLCNIC_RCVPEG_STATE,
24 QLCNIC_ASIC_TEMP,
25 QLCNIC_FW_API,
26 QLCNIC_DRV_OP_MODE,
27 QLCNIC_FLASH_LOCK,
28 QLCNIC_FLASH_UNLOCK,
29};
30
Himanshu Madhania15ebd32013-01-01 03:20:18 +0000[diff] [blame^]31/* Read from an address offset from BAR0, existing registers */
32#define QLC_SHARED_REG_RD32(a, addr) \
33 readl(((a)->ahw->pci_base0) + ((a)->ahw->reg_tbl[addr]))
34
35/* Write to an address offset from BAR0, existing registers */
36#define QLC_SHARED_REG_WR32(a, addr, value) \
37 writel(value, ((a)->ahw->pci_base0) + ((a)->ahw->reg_tbl[addr]))
38
Sony Chacko7e2cf4f2013-01-01 03:20:17 +0000[diff] [blame]39#define QLCNIC_CMD_CONFIGURE_IP_ADDR 0x1
40#define QLCNIC_CMD_CONFIG_INTRPT 0x2
41#define QLCNIC_CMD_CREATE_RX_CTX 0x7
42#define QLCNIC_CMD_DESTROY_RX_CTX 0x8
43#define QLCNIC_CMD_CREATE_TX_CTX 0x9
44#define QLCNIC_CMD_DESTROY_TX_CTX 0xa
45#define QLCNIC_CMD_CONFIGURE_LRO 0xC
46#define QLCNIC_CMD_CONFIGURE_MAC_LEARNING 0xD
47#define QLCNIC_CMD_GET_STATISTICS 0xF
48#define QLCNIC_CMD_INTRPT_TEST 0x11
49#define QLCNIC_CMD_SET_MTU 0x12
50#define QLCNIC_CMD_READ_PHY 0x13
51#define QLCNIC_CMD_WRITE_PHY 0x14
52#define QLCNIC_CMD_READ_HW_REG 0x15
53#define QLCNIC_CMD_GET_FLOW_CTL 0x16
54#define QLCNIC_CMD_SET_FLOW_CTL 0x17
55#define QLCNIC_CMD_READ_MAX_MTU 0x18
56#define QLCNIC_CMD_READ_MAX_LRO 0x19
57#define QLCNIC_CMD_MAC_ADDRESS 0x1f
58#define QLCNIC_CMD_GET_PCI_INFO 0x20
59#define QLCNIC_CMD_GET_NIC_INFO 0x21
60#define QLCNIC_CMD_SET_NIC_INFO 0x22
61#define QLCNIC_CMD_GET_ESWITCH_CAPABILITY 0x24
62#define QLCNIC_CMD_TOGGLE_ESWITCH 0x25
63#define QLCNIC_CMD_GET_ESWITCH_STATUS 0x26
64#define QLCNIC_CMD_SET_PORTMIRRORING 0x27
65#define QLCNIC_CMD_CONFIGURE_ESWITCH 0x28
66#define QLCNIC_CMD_GET_ESWITCH_PORT_CONFIG 0x29
67#define QLCNIC_CMD_GET_ESWITCH_STATS 0x2a
68#define QLCNIC_CMD_CONFIG_PORT 0x2e
69#define QLCNIC_CMD_TEMP_SIZE 0x2f
70#define QLCNIC_CMD_GET_TEMP_HDR 0x30
71#define QLCNIC_CMD_GET_MAC_STATS 0x37
72#define QLCNIC_CMD_SET_DRV_VER 0x38
73#define QLCNIC_CMD_CONFIGURE_RSS 0x41
74#define QLCNIC_CMD_CONFIG_INTR_COAL 0x43
75#define QLCNIC_CMD_CONFIGURE_LED 0x44
76#define QLCNIC_CMD_CONFIG_MAC_VLAN 0x45
77#define QLCNIC_CMD_GET_LINK_EVENT 0x48
78#define QLCNIC_CMD_CONFIGURE_MAC_RX_MODE 0x49
79#define QLCNIC_CMD_CONFIGURE_HW_LRO 0x4A
80#define QLCNIC_CMD_INIT_NIC_FUNC 0x60
81#define QLCNIC_CMD_STOP_NIC_FUNC 0x61
82#define QLCNIC_CMD_IDC_ACK 0x63
83#define QLCNIC_CMD_SET_PORT_CONFIG 0x66
84#define QLCNIC_CMD_GET_PORT_CONFIG 0x67
85#define QLCNIC_CMD_GET_LINK_STATUS 0x68
86#define QLCNIC_CMD_SET_LED_CONFIG 0x69
87#define QLCNIC_CMD_GET_LED_CONFIG 0x6A
88
89#define QLCNIC_INTRPT_INTX 1
90#define QLCNIC_INTRPT_MSIX 3
91#define QLCNIC_INTRPT_ADD 1
92#define QLCNIC_INTRPT_DEL 2
93
94#define QLCNIC_GET_CURRENT_MAC 1
95#define QLCNIC_SET_STATION_MAC 2
96#define QLCNIC_GET_DEFAULT_MAC 3
97#define QLCNIC_GET_FAC_DEF_MAC 4
98#define QLCNIC_SET_FAC_DEF_MAC 5
99
100#define QLCNIC_MBX_LINK_EVENT 0x8001
101#define QLCNIC_MBX_COMP_EVENT 0x8100
102#define QLCNIC_MBX_REQUEST_EVENT 0x8101
103#define QLCNIC_MBX_TIME_EXTEND_EVENT 0x8102
104#define QLCNIC_MBX_SFP_INSERT_EVENT 0x8130
105#define QLCNIC_MBX_SFP_REMOVE_EVENT 0x8131
106
107struct qlcnic_mailbox_metadata {
108 u32 cmd;
109 u32 in_args;
110 u32 out_args;
111};
112
113#define QLCNIC_MBX_RSP_OK 1
114#define QLCNIC_MBX_PORT_RSP_OK 0x1a
115
116struct qlcnic_pci_info;
117struct qlcnic_info;
118struct qlcnic_cmd_args;
119struct ethtool_stats;
120struct pci_device_id;
121struct qlcnic_host_sds_ring;
122struct qlcnic_host_tx_ring;
123struct qlcnic_host_tx_ring;
124struct qlcnic_hardware_context;
125struct qlcnic_adapter;
126
127int qlcnic_82xx_start_firmware(struct qlcnic_adapter *);
128int qlcnic_82xx_hw_read_wx_2M(struct qlcnic_adapter *adapter, ulong);
129int qlcnic_82xx_hw_write_wx_2M(struct qlcnic_adapter *, ulong, u32);
130int qlcnic_82xx_config_hw_lro(struct qlcnic_adapter *adapter, int);
131int qlcnic_82xx_nic_set_promisc(struct qlcnic_adapter *adapter, u32);
132int qlcnic_82xx_napi_add(struct qlcnic_adapter *adapter,
133 struct net_device *netdev);
134void qlcnic_82xx_change_filter(struct qlcnic_adapter *adapter,
135 u64 *uaddr, __le16 vlan_id);
136void qlcnic_82xx_config_intr_coalesce(struct qlcnic_adapter *adapter);
137int qlcnic_82xx_config_rss(struct qlcnic_adapter *adapter, int);
138void qlcnic_82xx_config_ipaddr(struct qlcnic_adapter *adapter,
139 __be32, int);
140int qlcnic_82xx_linkevent_request(struct qlcnic_adapter *adapter, int);
141void qlcnic_82xx_process_rcv_ring_diag(struct qlcnic_host_sds_ring *sds_ring);
142int qlcnic_82xx_clear_lb_mode(struct qlcnic_adapter *adapter, u8);
143int qlcnic_82xx_set_lb_mode(struct qlcnic_adapter *, u8);
144void qlcnic_82xx_write_crb(struct qlcnic_adapter *, char *, loff_t, size_t);
145void qlcnic_82xx_read_crb(struct qlcnic_adapter *, char *, loff_t, size_t);
146void qlcnic_82xx_dev_request_reset(struct qlcnic_adapter *, u32);
147int qlcnic_82xx_setup_intr(struct qlcnic_adapter *, u8);
148irqreturn_t qlcnic_82xx_clear_legacy_intr(struct qlcnic_adapter *);
149int qlcnic_82xx_issue_cmd(struct qlcnic_adapter *adapter,
150 struct qlcnic_cmd_args *);
151int qlcnic_82xx_fw_cmd_create_rx_ctx(struct qlcnic_adapter *);
152int qlcnic_82xx_fw_cmd_create_tx_ctx(struct qlcnic_adapter *,
153 struct qlcnic_host_tx_ring *tx_ring, int);
154int qlcnic_82xx_sre_macaddr_change(struct qlcnic_adapter *, u8 *, __le16, u8);
155int qlcnic_82xx_get_mac_address(struct qlcnic_adapter *, u8*);
156int qlcnic_82xx_get_nic_info(struct qlcnic_adapter *, struct qlcnic_info *, u8);
157int qlcnic_82xx_set_nic_info(struct qlcnic_adapter *, struct qlcnic_info *);
158int qlcnic_82xx_get_pci_info(struct qlcnic_adapter *, struct qlcnic_pci_info*);
159int qlcnic_82xx_alloc_mbx_args(struct qlcnic_cmd_args *,
160 struct qlcnic_adapter *, u32);
161int qlcnic_82xx_hw_write_wx_2M(struct qlcnic_adapter *, ulong, u32);
162int qlcnic_82xx_get_board_info(struct qlcnic_adapter *);
163int qlcnic_82xx_config_led(struct qlcnic_adapter *, u32, u32);
164void qlcnic_82xx_get_func_no(struct qlcnic_adapter *);
165int qlcnic_82xx_api_lock(struct qlcnic_adapter *);
166void qlcnic_82xx_api_unlock(struct qlcnic_adapter *);
167void qlcnic_82xx_napi_enable(struct qlcnic_adapter *);
168void qlcnic_82xx_napi_disable(struct qlcnic_adapter *);
169#endif /* __QLCNIC_HW_H_ */