Andrew Victor | 1a0ed73 | 2006-12-01 09:04:47 +0100 | [diff] [blame] | 1 | /* |
Andrew Victor | ad48ce7 | 2008-04-16 20:43:49 +0100 | [diff] [blame] | 2 | * at91sam926x_time.c - Periodic Interval Timer (PIT) for at91sam926x |
Andrew Victor | 1a0ed73 | 2006-12-01 09:04:47 +0100 | [diff] [blame] | 3 | * |
| 4 | * Copyright (C) 2005-2006 M. Amine SAYA, ATMEL Rousset, France |
| 5 | * Revision 2005 M. Nicolas Diremdjian, ATMEL Rousset, France |
Andrew Victor | ad48ce7 | 2008-04-16 20:43:49 +0100 | [diff] [blame] | 6 | * Converted to ClockSource/ClockEvents by David Brownell. |
Andrew Victor | 1a0ed73 | 2006-12-01 09:04:47 +0100 | [diff] [blame] | 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License version 2 as |
| 10 | * published by the Free Software Foundation. |
| 11 | */ |
Maxime Ripard | 52c3ffb | 2014-07-01 11:33:14 +0200 | [diff] [blame] | 12 | |
Maxime Ripard | cffbfe6 | 2014-07-01 11:33:21 +0200 | [diff] [blame] | 13 | #define pr_fmt(fmt) "AT91: PIT: " fmt |
| 14 | |
Maxime Ripard | 52c3ffb | 2014-07-01 11:33:14 +0200 | [diff] [blame] | 15 | #include <linux/clk.h> |
| 16 | #include <linux/clockchips.h> |
Andrew Victor | 1a0ed73 | 2006-12-01 09:04:47 +0100 | [diff] [blame] | 17 | #include <linux/interrupt.h> |
| 18 | #include <linux/irq.h> |
| 19 | #include <linux/kernel.h> |
Jean-Christophe PLAGNIOL-VILLARD | 23fa648 | 2012-02-27 11:19:34 +0100 | [diff] [blame] | 20 | #include <linux/of.h> |
| 21 | #include <linux/of_address.h> |
| 22 | #include <linux/of_irq.h> |
Maxime Ripard | 64568d1 | 2014-07-01 11:33:23 +0200 | [diff] [blame] | 23 | #include <linux/slab.h> |
Andrew Victor | 1a0ed73 | 2006-12-01 09:04:47 +0100 | [diff] [blame] | 24 | |
Jean-Christophe PLAGNIOL-VILLARD | ffe5cd8 | 2012-10-30 08:09:09 +0800 | [diff] [blame] | 25 | #define AT91_PIT_MR 0x00 /* Mode Register */ |
Maxime Ripard | 52c3ffb | 2014-07-01 11:33:14 +0200 | [diff] [blame] | 26 | #define AT91_PIT_PITIEN BIT(25) /* Timer Interrupt Enable */ |
| 27 | #define AT91_PIT_PITEN BIT(24) /* Timer Enabled */ |
| 28 | #define AT91_PIT_PIV GENMASK(19, 0) /* Periodic Interval Value */ |
Andrew Victor | 1a0ed73 | 2006-12-01 09:04:47 +0100 | [diff] [blame] | 29 | |
Jean-Christophe PLAGNIOL-VILLARD | ffe5cd8 | 2012-10-30 08:09:09 +0800 | [diff] [blame] | 30 | #define AT91_PIT_SR 0x04 /* Status Register */ |
Maxime Ripard | 52c3ffb | 2014-07-01 11:33:14 +0200 | [diff] [blame] | 31 | #define AT91_PIT_PITS BIT(0) /* Timer Status */ |
Jean-Christophe PLAGNIOL-VILLARD | ffe5cd8 | 2012-10-30 08:09:09 +0800 | [diff] [blame] | 32 | |
| 33 | #define AT91_PIT_PIVR 0x08 /* Periodic Interval Value Register */ |
| 34 | #define AT91_PIT_PIIR 0x0c /* Periodic Interval Image Register */ |
Maxime Ripard | 52c3ffb | 2014-07-01 11:33:14 +0200 | [diff] [blame] | 35 | #define AT91_PIT_PICNT GENMASK(31, 20) /* Interval Counter */ |
| 36 | #define AT91_PIT_CPIV GENMASK(19, 0) /* Inverval Value */ |
Andrew Victor | 1a0ed73 | 2006-12-01 09:04:47 +0100 | [diff] [blame] | 37 | |
| 38 | #define PIT_CPIV(x) ((x) & AT91_PIT_CPIV) |
| 39 | #define PIT_PICNT(x) (((x) & AT91_PIT_PICNT) >> 20) |
| 40 | |
Maxime Ripard | 64568d1 | 2014-07-01 11:33:23 +0200 | [diff] [blame] | 41 | struct pit_data { |
| 42 | struct clock_event_device clkevt; |
| 43 | struct clocksource clksrc; |
Andrew Victor | ad48ce7 | 2008-04-16 20:43:49 +0100 | [diff] [blame] | 44 | |
Maxime Ripard | 64568d1 | 2014-07-01 11:33:23 +0200 | [diff] [blame] | 45 | void __iomem *base; |
| 46 | u32 cycle; |
| 47 | u32 cnt; |
| 48 | unsigned int irq; |
| 49 | struct clk *mck; |
| 50 | }; |
| 51 | |
| 52 | static inline struct pit_data *clksrc_to_pit_data(struct clocksource *clksrc) |
Jean-Christophe PLAGNIOL-VILLARD | 4ab0c599 | 2011-09-18 22:29:50 +0800 | [diff] [blame] | 53 | { |
Maxime Ripard | 64568d1 | 2014-07-01 11:33:23 +0200 | [diff] [blame] | 54 | return container_of(clksrc, struct pit_data, clksrc); |
Jean-Christophe PLAGNIOL-VILLARD | 4ab0c599 | 2011-09-18 22:29:50 +0800 | [diff] [blame] | 55 | } |
| 56 | |
Maxime Ripard | 64568d1 | 2014-07-01 11:33:23 +0200 | [diff] [blame] | 57 | static inline struct pit_data *clkevt_to_pit_data(struct clock_event_device *clkevt) |
Jean-Christophe PLAGNIOL-VILLARD | 4ab0c599 | 2011-09-18 22:29:50 +0800 | [diff] [blame] | 58 | { |
Maxime Ripard | 64568d1 | 2014-07-01 11:33:23 +0200 | [diff] [blame] | 59 | return container_of(clkevt, struct pit_data, clkevt); |
| 60 | } |
| 61 | |
| 62 | static inline unsigned int pit_read(void __iomem *base, unsigned int reg_offset) |
| 63 | { |
Ben Dooks | 4806c87 | 2015-03-30 22:17:09 +0200 | [diff] [blame] | 64 | return readl_relaxed(base + reg_offset); |
Maxime Ripard | 64568d1 | 2014-07-01 11:33:23 +0200 | [diff] [blame] | 65 | } |
| 66 | |
| 67 | static inline void pit_write(void __iomem *base, unsigned int reg_offset, unsigned long value) |
| 68 | { |
Ben Dooks | 4806c87 | 2015-03-30 22:17:09 +0200 | [diff] [blame] | 69 | writel_relaxed(value, base + reg_offset); |
Jean-Christophe PLAGNIOL-VILLARD | 4ab0c599 | 2011-09-18 22:29:50 +0800 | [diff] [blame] | 70 | } |
Andrew Victor | ad48ce7 | 2008-04-16 20:43:49 +0100 | [diff] [blame] | 71 | |
Andrew Victor | 1a0ed73 | 2006-12-01 09:04:47 +0100 | [diff] [blame] | 72 | /* |
Andrew Victor | ad48ce7 | 2008-04-16 20:43:49 +0100 | [diff] [blame] | 73 | * Clocksource: just a monotonic counter of MCK/16 cycles. |
| 74 | * We don't care whether or not PIT irqs are enabled. |
Andrew Victor | 1a0ed73 | 2006-12-01 09:04:47 +0100 | [diff] [blame] | 75 | */ |
Magnus Damm | 8e19608 | 2009-04-21 12:24:00 -0700 | [diff] [blame] | 76 | static cycle_t read_pit_clk(struct clocksource *cs) |
Andrew Victor | 1a0ed73 | 2006-12-01 09:04:47 +0100 | [diff] [blame] | 77 | { |
Maxime Ripard | 64568d1 | 2014-07-01 11:33:23 +0200 | [diff] [blame] | 78 | struct pit_data *data = clksrc_to_pit_data(cs); |
Andrew Victor | ad48ce7 | 2008-04-16 20:43:49 +0100 | [diff] [blame] | 79 | unsigned long flags; |
| 80 | u32 elapsed; |
| 81 | u32 t; |
Andrew Victor | 1a0ed73 | 2006-12-01 09:04:47 +0100 | [diff] [blame] | 82 | |
Andrew Victor | ad48ce7 | 2008-04-16 20:43:49 +0100 | [diff] [blame] | 83 | raw_local_irq_save(flags); |
Maxime Ripard | 64568d1 | 2014-07-01 11:33:23 +0200 | [diff] [blame] | 84 | elapsed = data->cnt; |
| 85 | t = pit_read(data->base, AT91_PIT_PIIR); |
Andrew Victor | ad48ce7 | 2008-04-16 20:43:49 +0100 | [diff] [blame] | 86 | raw_local_irq_restore(flags); |
Andrew Victor | 1a0ed73 | 2006-12-01 09:04:47 +0100 | [diff] [blame] | 87 | |
Maxime Ripard | 64568d1 | 2014-07-01 11:33:23 +0200 | [diff] [blame] | 88 | elapsed += PIT_PICNT(t) * data->cycle; |
Andrew Victor | ad48ce7 | 2008-04-16 20:43:49 +0100 | [diff] [blame] | 89 | elapsed += PIT_CPIV(t); |
| 90 | return elapsed; |
Andrew Victor | 1a0ed73 | 2006-12-01 09:04:47 +0100 | [diff] [blame] | 91 | } |
| 92 | |
Viresh Kumar | 85250fb | 2015-06-18 16:24:44 +0530 | [diff] [blame] | 93 | static int pit_clkevt_shutdown(struct clock_event_device *dev) |
Andrew Victor | ad48ce7 | 2008-04-16 20:43:49 +0100 | [diff] [blame] | 94 | { |
Maxime Ripard | 64568d1 | 2014-07-01 11:33:23 +0200 | [diff] [blame] | 95 | struct pit_data *data = clkevt_to_pit_data(dev); |
| 96 | |
Viresh Kumar | 85250fb | 2015-06-18 16:24:44 +0530 | [diff] [blame] | 97 | /* disable irq, leaving the clocksource active */ |
| 98 | pit_write(data->base, AT91_PIT_MR, (data->cycle - 1) | AT91_PIT_PITEN); |
| 99 | return 0; |
| 100 | } |
| 101 | |
| 102 | /* |
| 103 | * Clockevent device: interrupts every 1/HZ (== pit_cycles * MCK/16) |
| 104 | */ |
| 105 | static int pit_clkevt_set_periodic(struct clock_event_device *dev) |
| 106 | { |
| 107 | struct pit_data *data = clkevt_to_pit_data(dev); |
| 108 | |
| 109 | /* update clocksource counter */ |
| 110 | data->cnt += data->cycle * PIT_PICNT(pit_read(data->base, AT91_PIT_PIVR)); |
| 111 | pit_write(data->base, AT91_PIT_MR, |
| 112 | (data->cycle - 1) | AT91_PIT_PITEN | AT91_PIT_PITIEN); |
| 113 | return 0; |
Andrew Victor | ad48ce7 | 2008-04-16 20:43:49 +0100 | [diff] [blame] | 114 | } |
| 115 | |
Stephen Warren | 49356ae | 2012-11-07 16:32:41 -0700 | [diff] [blame] | 116 | static void at91sam926x_pit_suspend(struct clock_event_device *cedev) |
| 117 | { |
Maxime Ripard | 64568d1 | 2014-07-01 11:33:23 +0200 | [diff] [blame] | 118 | struct pit_data *data = clkevt_to_pit_data(cedev); |
| 119 | |
Stephen Warren | 49356ae | 2012-11-07 16:32:41 -0700 | [diff] [blame] | 120 | /* Disable timer */ |
Maxime Ripard | 64568d1 | 2014-07-01 11:33:23 +0200 | [diff] [blame] | 121 | pit_write(data->base, AT91_PIT_MR, 0); |
Stephen Warren | 49356ae | 2012-11-07 16:32:41 -0700 | [diff] [blame] | 122 | } |
| 123 | |
Maxime Ripard | 64568d1 | 2014-07-01 11:33:23 +0200 | [diff] [blame] | 124 | static void at91sam926x_pit_reset(struct pit_data *data) |
Stephen Warren | 49356ae | 2012-11-07 16:32:41 -0700 | [diff] [blame] | 125 | { |
| 126 | /* Disable timer and irqs */ |
Maxime Ripard | 64568d1 | 2014-07-01 11:33:23 +0200 | [diff] [blame] | 127 | pit_write(data->base, AT91_PIT_MR, 0); |
Stephen Warren | 49356ae | 2012-11-07 16:32:41 -0700 | [diff] [blame] | 128 | |
| 129 | /* Clear any pending interrupts, wait for PIT to stop counting */ |
Maxime Ripard | 64568d1 | 2014-07-01 11:33:23 +0200 | [diff] [blame] | 130 | while (PIT_CPIV(pit_read(data->base, AT91_PIT_PIVR)) != 0) |
Stephen Warren | 49356ae | 2012-11-07 16:32:41 -0700 | [diff] [blame] | 131 | cpu_relax(); |
| 132 | |
| 133 | /* Start PIT but don't enable IRQ */ |
Maxime Ripard | 64568d1 | 2014-07-01 11:33:23 +0200 | [diff] [blame] | 134 | pit_write(data->base, AT91_PIT_MR, |
| 135 | (data->cycle - 1) | AT91_PIT_PITEN); |
Stephen Warren | 49356ae | 2012-11-07 16:32:41 -0700 | [diff] [blame] | 136 | } |
| 137 | |
| 138 | static void at91sam926x_pit_resume(struct clock_event_device *cedev) |
| 139 | { |
Maxime Ripard | 64568d1 | 2014-07-01 11:33:23 +0200 | [diff] [blame] | 140 | struct pit_data *data = clkevt_to_pit_data(cedev); |
| 141 | |
| 142 | at91sam926x_pit_reset(data); |
Stephen Warren | 49356ae | 2012-11-07 16:32:41 -0700 | [diff] [blame] | 143 | } |
| 144 | |
Andrew Victor | 1a0ed73 | 2006-12-01 09:04:47 +0100 | [diff] [blame] | 145 | /* |
| 146 | * IRQ handler for the timer. |
| 147 | */ |
Andrew Victor | ad48ce7 | 2008-04-16 20:43:49 +0100 | [diff] [blame] | 148 | static irqreturn_t at91sam926x_pit_interrupt(int irq, void *dev_id) |
Andrew Victor | 1a0ed73 | 2006-12-01 09:04:47 +0100 | [diff] [blame] | 149 | { |
Maxime Ripard | 64568d1 | 2014-07-01 11:33:23 +0200 | [diff] [blame] | 150 | struct pit_data *data = dev_id; |
| 151 | |
Uwe Kleine-König | 501d703 | 2009-09-21 09:30:09 +0200 | [diff] [blame] | 152 | /* |
| 153 | * irqs should be disabled here, but as the irq is shared they are only |
| 154 | * guaranteed to be off if the timer irq is registered first. |
| 155 | */ |
| 156 | WARN_ON_ONCE(!irqs_disabled()); |
Andrew Victor | 1a0ed73 | 2006-12-01 09:04:47 +0100 | [diff] [blame] | 157 | |
Andrew Victor | ad48ce7 | 2008-04-16 20:43:49 +0100 | [diff] [blame] | 158 | /* The PIT interrupt may be disabled, and is shared */ |
Viresh Kumar | 85250fb | 2015-06-18 16:24:44 +0530 | [diff] [blame] | 159 | if (clockevent_state_periodic(&data->clkevt) && |
Maxime Ripard | 64568d1 | 2014-07-01 11:33:23 +0200 | [diff] [blame] | 160 | (pit_read(data->base, AT91_PIT_SR) & AT91_PIT_PITS)) { |
Andrew Victor | ad48ce7 | 2008-04-16 20:43:49 +0100 | [diff] [blame] | 161 | unsigned nr_ticks; |
| 162 | |
| 163 | /* Get number of ticks performed before irq, and ack it */ |
Maxime Ripard | 64568d1 | 2014-07-01 11:33:23 +0200 | [diff] [blame] | 164 | nr_ticks = PIT_PICNT(pit_read(data->base, AT91_PIT_PIVR)); |
Andrew Victor | 1a0ed73 | 2006-12-01 09:04:47 +0100 | [diff] [blame] | 165 | do { |
Maxime Ripard | 64568d1 | 2014-07-01 11:33:23 +0200 | [diff] [blame] | 166 | data->cnt += data->cycle; |
| 167 | data->clkevt.event_handler(&data->clkevt); |
Andrew Victor | 1a0ed73 | 2006-12-01 09:04:47 +0100 | [diff] [blame] | 168 | nr_ticks--; |
| 169 | } while (nr_ticks); |
| 170 | |
Andrew Victor | 1a0ed73 | 2006-12-01 09:04:47 +0100 | [diff] [blame] | 171 | return IRQ_HANDLED; |
Andrew Victor | ad48ce7 | 2008-04-16 20:43:49 +0100 | [diff] [blame] | 172 | } |
| 173 | |
| 174 | return IRQ_NONE; |
Andrew Victor | 1a0ed73 | 2006-12-01 09:04:47 +0100 | [diff] [blame] | 175 | } |
| 176 | |
Andrew Victor | 1a0ed73 | 2006-12-01 09:04:47 +0100 | [diff] [blame] | 177 | /* |
Andrew Victor | ad48ce7 | 2008-04-16 20:43:49 +0100 | [diff] [blame] | 178 | * Set up both clocksource and clockevent support. |
Andrew Victor | 1a0ed73 | 2006-12-01 09:04:47 +0100 | [diff] [blame] | 179 | */ |
Alexandre Belloni | a17686c | 2016-09-09 13:13:48 +0200 | [diff] [blame^] | 180 | static int __init at91sam926x_pit_dt_init(struct device_node *node) |
Andrew Victor | 1a0ed73 | 2006-12-01 09:04:47 +0100 | [diff] [blame] | 181 | { |
Alexandre Belloni | a17686c | 2016-09-09 13:13:48 +0200 | [diff] [blame^] | 182 | unsigned long pit_rate; |
| 183 | unsigned bits; |
| 184 | int ret; |
| 185 | struct pit_data *data; |
| 186 | |
| 187 | data = kzalloc(sizeof(*data), GFP_KERNEL); |
| 188 | if (!data) |
| 189 | return -ENOMEM; |
| 190 | |
| 191 | data->base = of_iomap(node, 0); |
| 192 | if (!data->base) { |
| 193 | pr_err("Could not map PIT address\n"); |
| 194 | return -ENXIO; |
| 195 | } |
| 196 | |
| 197 | data->mck = of_clk_get(node, 0); |
| 198 | if (IS_ERR(data->mck)) { |
| 199 | pr_err("Unable to get mck clk\n"); |
| 200 | return PTR_ERR(data->mck); |
| 201 | } |
| 202 | |
| 203 | ret = clk_prepare_enable(data->mck); |
| 204 | if (ret) { |
| 205 | pr_err("Unable to enable mck\n"); |
| 206 | return ret; |
| 207 | } |
| 208 | |
| 209 | /* Get the interrupts property */ |
| 210 | data->irq = irq_of_parse_and_map(node, 0); |
| 211 | if (!data->irq) { |
| 212 | pr_err("Unable to get IRQ from DT\n"); |
| 213 | return -EINVAL; |
| 214 | } |
Andrew Victor | 1a0ed73 | 2006-12-01 09:04:47 +0100 | [diff] [blame] | 215 | |
Andrew Victor | ad48ce7 | 2008-04-16 20:43:49 +0100 | [diff] [blame] | 216 | /* |
| 217 | * Use our actual MCK to figure out how many MCK/16 ticks per |
| 218 | * 1/HZ period (instead of a compile-time constant LATCH). |
| 219 | */ |
Maxime Ripard | 64568d1 | 2014-07-01 11:33:23 +0200 | [diff] [blame] | 220 | pit_rate = clk_get_rate(data->mck) / 16; |
| 221 | data->cycle = DIV_ROUND_CLOSEST(pit_rate, HZ); |
| 222 | WARN_ON(((data->cycle - 1) & ~AT91_PIT_PIV) != 0); |
Andrew Victor | ad48ce7 | 2008-04-16 20:43:49 +0100 | [diff] [blame] | 223 | |
| 224 | /* Initialize and enable the timer */ |
Maxime Ripard | 64568d1 | 2014-07-01 11:33:23 +0200 | [diff] [blame] | 225 | at91sam926x_pit_reset(data); |
Andrew Victor | ad48ce7 | 2008-04-16 20:43:49 +0100 | [diff] [blame] | 226 | |
| 227 | /* |
| 228 | * Register clocksource. The high order bits of PIV are unused, |
| 229 | * so this isn't a 32-bit counter unless we get clockevent irqs. |
| 230 | */ |
Maxime Ripard | 64568d1 | 2014-07-01 11:33:23 +0200 | [diff] [blame] | 231 | bits = 12 /* PICNT */ + ilog2(data->cycle) /* PIV */; |
| 232 | data->clksrc.mask = CLOCKSOURCE_MASK(bits); |
| 233 | data->clksrc.name = "pit"; |
| 234 | data->clksrc.rating = 175; |
Daniel Lezcano | 005e562 | 2015-08-04 11:59:42 +0200 | [diff] [blame] | 235 | data->clksrc.read = read_pit_clk; |
| 236 | data->clksrc.flags = CLOCK_SOURCE_IS_CONTINUOUS; |
Daniel Lezcano | 504f34c | 2016-06-06 19:10:55 +0200 | [diff] [blame] | 237 | |
| 238 | ret = clocksource_register_hz(&data->clksrc, pit_rate); |
| 239 | if (ret) { |
| 240 | pr_err("Failed to register clocksource"); |
| 241 | return ret; |
| 242 | } |
Andrew Victor | ad48ce7 | 2008-04-16 20:43:49 +0100 | [diff] [blame] | 243 | |
| 244 | /* Set up irq handler */ |
Maxime Ripard | 64568d1 | 2014-07-01 11:33:23 +0200 | [diff] [blame] | 245 | ret = request_irq(data->irq, at91sam926x_pit_interrupt, |
Maxime Ripard | 7f282e0 | 2014-07-01 11:33:22 +0200 | [diff] [blame] | 246 | IRQF_SHARED | IRQF_TIMER | IRQF_IRQPOLL, |
Maxime Ripard | 64568d1 | 2014-07-01 11:33:23 +0200 | [diff] [blame] | 247 | "at91_tick", data); |
Daniel Lezcano | 504f34c | 2016-06-06 19:10:55 +0200 | [diff] [blame] | 248 | if (ret) { |
| 249 | pr_err("Unable to setup IRQ\n"); |
| 250 | return ret; |
| 251 | } |
Andrew Victor | ad48ce7 | 2008-04-16 20:43:49 +0100 | [diff] [blame] | 252 | |
| 253 | /* Set up and register clockevents */ |
Maxime Ripard | 64568d1 | 2014-07-01 11:33:23 +0200 | [diff] [blame] | 254 | data->clkevt.name = "pit"; |
| 255 | data->clkevt.features = CLOCK_EVT_FEAT_PERIODIC; |
| 256 | data->clkevt.shift = 32; |
| 257 | data->clkevt.mult = div_sc(pit_rate, NSEC_PER_SEC, data->clkevt.shift); |
| 258 | data->clkevt.rating = 100; |
| 259 | data->clkevt.cpumask = cpumask_of(0); |
| 260 | |
Viresh Kumar | 85250fb | 2015-06-18 16:24:44 +0530 | [diff] [blame] | 261 | data->clkevt.set_state_shutdown = pit_clkevt_shutdown; |
| 262 | data->clkevt.set_state_periodic = pit_clkevt_set_periodic; |
Maxime Ripard | 64568d1 | 2014-07-01 11:33:23 +0200 | [diff] [blame] | 263 | data->clkevt.resume = at91sam926x_pit_resume; |
| 264 | data->clkevt.suspend = at91sam926x_pit_suspend; |
| 265 | clockevents_register_device(&data->clkevt); |
Daniel Lezcano | 504f34c | 2016-06-06 19:10:55 +0200 | [diff] [blame] | 266 | |
| 267 | return 0; |
Andrew Victor | 1a0ed73 | 2006-12-01 09:04:47 +0100 | [diff] [blame] | 268 | } |
Daniel Lezcano | 177cf6e | 2016-06-07 00:27:44 +0200 | [diff] [blame] | 269 | CLOCKSOURCE_OF_DECLARE(at91sam926x_pit, "atmel,at91sam9260-pit", |
Maxime Ripard | f807a89 | 2014-07-01 11:33:18 +0200 | [diff] [blame] | 270 | at91sam926x_pit_dt_init); |