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Andrew Victor1a0ed732006-12-01 09:04:47 +01001/*
Andrew Victorad48ce72008-04-16 20:43:49 +01002 * at91sam926x_time.c - Periodic Interval Timer (PIT) for at91sam926x
Andrew Victor1a0ed732006-12-01 09:04:47 +01003 *
4 * Copyright (C) 2005-2006 M. Amine SAYA, ATMEL Rousset, France
5 * Revision 2005 M. Nicolas Diremdjian, ATMEL Rousset, France
Andrew Victorad48ce72008-04-16 20:43:49 +01006 * Converted to ClockSource/ClockEvents by David Brownell.
Andrew Victor1a0ed732006-12-01 09:04:47 +01007 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
Maxime Ripard52c3ffb2014-07-01 11:33:14 +020012
Maxime Ripardcffbfe62014-07-01 11:33:21 +020013#define pr_fmt(fmt) "AT91: PIT: " fmt
14
Maxime Ripard52c3ffb2014-07-01 11:33:14 +020015#include <linux/clk.h>
16#include <linux/clockchips.h>
Andrew Victor1a0ed732006-12-01 09:04:47 +010017#include <linux/interrupt.h>
18#include <linux/irq.h>
19#include <linux/kernel.h>
Jean-Christophe PLAGNIOL-VILLARD23fa6482012-02-27 11:19:34 +010020#include <linux/of.h>
21#include <linux/of_address.h>
22#include <linux/of_irq.h>
Maxime Ripard64568d12014-07-01 11:33:23 +020023#include <linux/slab.h>
Andrew Victor1a0ed732006-12-01 09:04:47 +010024
Jean-Christophe PLAGNIOL-VILLARDffe5cd82012-10-30 08:09:09 +080025#define AT91_PIT_MR 0x00 /* Mode Register */
Maxime Ripard52c3ffb2014-07-01 11:33:14 +020026#define AT91_PIT_PITIEN BIT(25) /* Timer Interrupt Enable */
27#define AT91_PIT_PITEN BIT(24) /* Timer Enabled */
28#define AT91_PIT_PIV GENMASK(19, 0) /* Periodic Interval Value */
Andrew Victor1a0ed732006-12-01 09:04:47 +010029
Jean-Christophe PLAGNIOL-VILLARDffe5cd82012-10-30 08:09:09 +080030#define AT91_PIT_SR 0x04 /* Status Register */
Maxime Ripard52c3ffb2014-07-01 11:33:14 +020031#define AT91_PIT_PITS BIT(0) /* Timer Status */
Jean-Christophe PLAGNIOL-VILLARDffe5cd82012-10-30 08:09:09 +080032
33#define AT91_PIT_PIVR 0x08 /* Periodic Interval Value Register */
34#define AT91_PIT_PIIR 0x0c /* Periodic Interval Image Register */
Maxime Ripard52c3ffb2014-07-01 11:33:14 +020035#define AT91_PIT_PICNT GENMASK(31, 20) /* Interval Counter */
36#define AT91_PIT_CPIV GENMASK(19, 0) /* Inverval Value */
Andrew Victor1a0ed732006-12-01 09:04:47 +010037
38#define PIT_CPIV(x) ((x) & AT91_PIT_CPIV)
39#define PIT_PICNT(x) (((x) & AT91_PIT_PICNT) >> 20)
40
Maxime Ripard64568d12014-07-01 11:33:23 +020041struct pit_data {
42 struct clock_event_device clkevt;
43 struct clocksource clksrc;
Andrew Victorad48ce72008-04-16 20:43:49 +010044
Maxime Ripard64568d12014-07-01 11:33:23 +020045 void __iomem *base;
46 u32 cycle;
47 u32 cnt;
48 unsigned int irq;
49 struct clk *mck;
50};
51
52static inline struct pit_data *clksrc_to_pit_data(struct clocksource *clksrc)
Jean-Christophe PLAGNIOL-VILLARD4ab0c5992011-09-18 22:29:50 +080053{
Maxime Ripard64568d12014-07-01 11:33:23 +020054 return container_of(clksrc, struct pit_data, clksrc);
Jean-Christophe PLAGNIOL-VILLARD4ab0c5992011-09-18 22:29:50 +080055}
56
Maxime Ripard64568d12014-07-01 11:33:23 +020057static inline struct pit_data *clkevt_to_pit_data(struct clock_event_device *clkevt)
Jean-Christophe PLAGNIOL-VILLARD4ab0c5992011-09-18 22:29:50 +080058{
Maxime Ripard64568d12014-07-01 11:33:23 +020059 return container_of(clkevt, struct pit_data, clkevt);
60}
61
62static inline unsigned int pit_read(void __iomem *base, unsigned int reg_offset)
63{
Ben Dooks4806c872015-03-30 22:17:09 +020064 return readl_relaxed(base + reg_offset);
Maxime Ripard64568d12014-07-01 11:33:23 +020065}
66
67static inline void pit_write(void __iomem *base, unsigned int reg_offset, unsigned long value)
68{
Ben Dooks4806c872015-03-30 22:17:09 +020069 writel_relaxed(value, base + reg_offset);
Jean-Christophe PLAGNIOL-VILLARD4ab0c5992011-09-18 22:29:50 +080070}
Andrew Victorad48ce72008-04-16 20:43:49 +010071
Andrew Victor1a0ed732006-12-01 09:04:47 +010072/*
Andrew Victorad48ce72008-04-16 20:43:49 +010073 * Clocksource: just a monotonic counter of MCK/16 cycles.
74 * We don't care whether or not PIT irqs are enabled.
Andrew Victor1a0ed732006-12-01 09:04:47 +010075 */
Magnus Damm8e196082009-04-21 12:24:00 -070076static cycle_t read_pit_clk(struct clocksource *cs)
Andrew Victor1a0ed732006-12-01 09:04:47 +010077{
Maxime Ripard64568d12014-07-01 11:33:23 +020078 struct pit_data *data = clksrc_to_pit_data(cs);
Andrew Victorad48ce72008-04-16 20:43:49 +010079 unsigned long flags;
80 u32 elapsed;
81 u32 t;
Andrew Victor1a0ed732006-12-01 09:04:47 +010082
Andrew Victorad48ce72008-04-16 20:43:49 +010083 raw_local_irq_save(flags);
Maxime Ripard64568d12014-07-01 11:33:23 +020084 elapsed = data->cnt;
85 t = pit_read(data->base, AT91_PIT_PIIR);
Andrew Victorad48ce72008-04-16 20:43:49 +010086 raw_local_irq_restore(flags);
Andrew Victor1a0ed732006-12-01 09:04:47 +010087
Maxime Ripard64568d12014-07-01 11:33:23 +020088 elapsed += PIT_PICNT(t) * data->cycle;
Andrew Victorad48ce72008-04-16 20:43:49 +010089 elapsed += PIT_CPIV(t);
90 return elapsed;
Andrew Victor1a0ed732006-12-01 09:04:47 +010091}
92
Viresh Kumar85250fb2015-06-18 16:24:44 +053093static int pit_clkevt_shutdown(struct clock_event_device *dev)
Andrew Victorad48ce72008-04-16 20:43:49 +010094{
Maxime Ripard64568d12014-07-01 11:33:23 +020095 struct pit_data *data = clkevt_to_pit_data(dev);
96
Viresh Kumar85250fb2015-06-18 16:24:44 +053097 /* disable irq, leaving the clocksource active */
98 pit_write(data->base, AT91_PIT_MR, (data->cycle - 1) | AT91_PIT_PITEN);
99 return 0;
100}
101
102/*
103 * Clockevent device: interrupts every 1/HZ (== pit_cycles * MCK/16)
104 */
105static int pit_clkevt_set_periodic(struct clock_event_device *dev)
106{
107 struct pit_data *data = clkevt_to_pit_data(dev);
108
109 /* update clocksource counter */
110 data->cnt += data->cycle * PIT_PICNT(pit_read(data->base, AT91_PIT_PIVR));
111 pit_write(data->base, AT91_PIT_MR,
112 (data->cycle - 1) | AT91_PIT_PITEN | AT91_PIT_PITIEN);
113 return 0;
Andrew Victorad48ce72008-04-16 20:43:49 +0100114}
115
Stephen Warren49356ae2012-11-07 16:32:41 -0700116static void at91sam926x_pit_suspend(struct clock_event_device *cedev)
117{
Maxime Ripard64568d12014-07-01 11:33:23 +0200118 struct pit_data *data = clkevt_to_pit_data(cedev);
119
Stephen Warren49356ae2012-11-07 16:32:41 -0700120 /* Disable timer */
Maxime Ripard64568d12014-07-01 11:33:23 +0200121 pit_write(data->base, AT91_PIT_MR, 0);
Stephen Warren49356ae2012-11-07 16:32:41 -0700122}
123
Maxime Ripard64568d12014-07-01 11:33:23 +0200124static void at91sam926x_pit_reset(struct pit_data *data)
Stephen Warren49356ae2012-11-07 16:32:41 -0700125{
126 /* Disable timer and irqs */
Maxime Ripard64568d12014-07-01 11:33:23 +0200127 pit_write(data->base, AT91_PIT_MR, 0);
Stephen Warren49356ae2012-11-07 16:32:41 -0700128
129 /* Clear any pending interrupts, wait for PIT to stop counting */
Maxime Ripard64568d12014-07-01 11:33:23 +0200130 while (PIT_CPIV(pit_read(data->base, AT91_PIT_PIVR)) != 0)
Stephen Warren49356ae2012-11-07 16:32:41 -0700131 cpu_relax();
132
133 /* Start PIT but don't enable IRQ */
Maxime Ripard64568d12014-07-01 11:33:23 +0200134 pit_write(data->base, AT91_PIT_MR,
135 (data->cycle - 1) | AT91_PIT_PITEN);
Stephen Warren49356ae2012-11-07 16:32:41 -0700136}
137
138static void at91sam926x_pit_resume(struct clock_event_device *cedev)
139{
Maxime Ripard64568d12014-07-01 11:33:23 +0200140 struct pit_data *data = clkevt_to_pit_data(cedev);
141
142 at91sam926x_pit_reset(data);
Stephen Warren49356ae2012-11-07 16:32:41 -0700143}
144
Andrew Victor1a0ed732006-12-01 09:04:47 +0100145/*
146 * IRQ handler for the timer.
147 */
Andrew Victorad48ce72008-04-16 20:43:49 +0100148static irqreturn_t at91sam926x_pit_interrupt(int irq, void *dev_id)
Andrew Victor1a0ed732006-12-01 09:04:47 +0100149{
Maxime Ripard64568d12014-07-01 11:33:23 +0200150 struct pit_data *data = dev_id;
151
Uwe Kleine-König501d7032009-09-21 09:30:09 +0200152 /*
153 * irqs should be disabled here, but as the irq is shared they are only
154 * guaranteed to be off if the timer irq is registered first.
155 */
156 WARN_ON_ONCE(!irqs_disabled());
Andrew Victor1a0ed732006-12-01 09:04:47 +0100157
Andrew Victorad48ce72008-04-16 20:43:49 +0100158 /* The PIT interrupt may be disabled, and is shared */
Viresh Kumar85250fb2015-06-18 16:24:44 +0530159 if (clockevent_state_periodic(&data->clkevt) &&
Maxime Ripard64568d12014-07-01 11:33:23 +0200160 (pit_read(data->base, AT91_PIT_SR) & AT91_PIT_PITS)) {
Andrew Victorad48ce72008-04-16 20:43:49 +0100161 unsigned nr_ticks;
162
163 /* Get number of ticks performed before irq, and ack it */
Maxime Ripard64568d12014-07-01 11:33:23 +0200164 nr_ticks = PIT_PICNT(pit_read(data->base, AT91_PIT_PIVR));
Andrew Victor1a0ed732006-12-01 09:04:47 +0100165 do {
Maxime Ripard64568d12014-07-01 11:33:23 +0200166 data->cnt += data->cycle;
167 data->clkevt.event_handler(&data->clkevt);
Andrew Victor1a0ed732006-12-01 09:04:47 +0100168 nr_ticks--;
169 } while (nr_ticks);
170
Andrew Victor1a0ed732006-12-01 09:04:47 +0100171 return IRQ_HANDLED;
Andrew Victorad48ce72008-04-16 20:43:49 +0100172 }
173
174 return IRQ_NONE;
Andrew Victor1a0ed732006-12-01 09:04:47 +0100175}
176
Andrew Victor1a0ed732006-12-01 09:04:47 +0100177/*
Andrew Victorad48ce72008-04-16 20:43:49 +0100178 * Set up both clocksource and clockevent support.
Andrew Victor1a0ed732006-12-01 09:04:47 +0100179 */
Alexandre Bellonia17686c2016-09-09 13:13:48 +0200180static int __init at91sam926x_pit_dt_init(struct device_node *node)
Andrew Victor1a0ed732006-12-01 09:04:47 +0100181{
Alexandre Bellonia17686c2016-09-09 13:13:48 +0200182 unsigned long pit_rate;
183 unsigned bits;
184 int ret;
185 struct pit_data *data;
186
187 data = kzalloc(sizeof(*data), GFP_KERNEL);
188 if (!data)
189 return -ENOMEM;
190
191 data->base = of_iomap(node, 0);
192 if (!data->base) {
193 pr_err("Could not map PIT address\n");
194 return -ENXIO;
195 }
196
197 data->mck = of_clk_get(node, 0);
198 if (IS_ERR(data->mck)) {
199 pr_err("Unable to get mck clk\n");
200 return PTR_ERR(data->mck);
201 }
202
203 ret = clk_prepare_enable(data->mck);
204 if (ret) {
205 pr_err("Unable to enable mck\n");
206 return ret;
207 }
208
209 /* Get the interrupts property */
210 data->irq = irq_of_parse_and_map(node, 0);
211 if (!data->irq) {
212 pr_err("Unable to get IRQ from DT\n");
213 return -EINVAL;
214 }
Andrew Victor1a0ed732006-12-01 09:04:47 +0100215
Andrew Victorad48ce72008-04-16 20:43:49 +0100216 /*
217 * Use our actual MCK to figure out how many MCK/16 ticks per
218 * 1/HZ period (instead of a compile-time constant LATCH).
219 */
Maxime Ripard64568d12014-07-01 11:33:23 +0200220 pit_rate = clk_get_rate(data->mck) / 16;
221 data->cycle = DIV_ROUND_CLOSEST(pit_rate, HZ);
222 WARN_ON(((data->cycle - 1) & ~AT91_PIT_PIV) != 0);
Andrew Victorad48ce72008-04-16 20:43:49 +0100223
224 /* Initialize and enable the timer */
Maxime Ripard64568d12014-07-01 11:33:23 +0200225 at91sam926x_pit_reset(data);
Andrew Victorad48ce72008-04-16 20:43:49 +0100226
227 /*
228 * Register clocksource. The high order bits of PIV are unused,
229 * so this isn't a 32-bit counter unless we get clockevent irqs.
230 */
Maxime Ripard64568d12014-07-01 11:33:23 +0200231 bits = 12 /* PICNT */ + ilog2(data->cycle) /* PIV */;
232 data->clksrc.mask = CLOCKSOURCE_MASK(bits);
233 data->clksrc.name = "pit";
234 data->clksrc.rating = 175;
Daniel Lezcano005e5622015-08-04 11:59:42 +0200235 data->clksrc.read = read_pit_clk;
236 data->clksrc.flags = CLOCK_SOURCE_IS_CONTINUOUS;
Daniel Lezcano504f34c2016-06-06 19:10:55 +0200237
238 ret = clocksource_register_hz(&data->clksrc, pit_rate);
239 if (ret) {
240 pr_err("Failed to register clocksource");
241 return ret;
242 }
Andrew Victorad48ce72008-04-16 20:43:49 +0100243
244 /* Set up irq handler */
Maxime Ripard64568d12014-07-01 11:33:23 +0200245 ret = request_irq(data->irq, at91sam926x_pit_interrupt,
Maxime Ripard7f282e02014-07-01 11:33:22 +0200246 IRQF_SHARED | IRQF_TIMER | IRQF_IRQPOLL,
Maxime Ripard64568d12014-07-01 11:33:23 +0200247 "at91_tick", data);
Daniel Lezcano504f34c2016-06-06 19:10:55 +0200248 if (ret) {
249 pr_err("Unable to setup IRQ\n");
250 return ret;
251 }
Andrew Victorad48ce72008-04-16 20:43:49 +0100252
253 /* Set up and register clockevents */
Maxime Ripard64568d12014-07-01 11:33:23 +0200254 data->clkevt.name = "pit";
255 data->clkevt.features = CLOCK_EVT_FEAT_PERIODIC;
256 data->clkevt.shift = 32;
257 data->clkevt.mult = div_sc(pit_rate, NSEC_PER_SEC, data->clkevt.shift);
258 data->clkevt.rating = 100;
259 data->clkevt.cpumask = cpumask_of(0);
260
Viresh Kumar85250fb2015-06-18 16:24:44 +0530261 data->clkevt.set_state_shutdown = pit_clkevt_shutdown;
262 data->clkevt.set_state_periodic = pit_clkevt_set_periodic;
Maxime Ripard64568d12014-07-01 11:33:23 +0200263 data->clkevt.resume = at91sam926x_pit_resume;
264 data->clkevt.suspend = at91sam926x_pit_suspend;
265 clockevents_register_device(&data->clkevt);
Daniel Lezcano504f34c2016-06-06 19:10:55 +0200266
267 return 0;
Andrew Victor1a0ed732006-12-01 09:04:47 +0100268}
Daniel Lezcano177cf6e2016-06-07 00:27:44 +0200269CLOCKSOURCE_OF_DECLARE(at91sam926x_pit, "atmel,at91sam9260-pit",
Maxime Ripardf807a892014-07-01 11:33:18 +0200270 at91sam926x_pit_dt_init);