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gerrit-public.fairphone.software / kernel / msm-4.9 / a177f1848c536a8729315fca8d3c2a724c5e8125 / . / arch / arm / boot / dts / imx6qdl-nitrogen6x.dtsi
blob: 489377e354745110174707f42fa85d5ecc11923a [file] [log] [blame]
Troy Kiskya177f182013-12-16 18:13:03 -0700[diff] [blame^]1/*
2 * Copyright 2013 Boundary Devices, Inc.
3 * Copyright 2011 Freescale Semiconductor, Inc.
4 * Copyright 2011 Linaro Ltd.
5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14/ {
15 memory {
16 reg = <0x10000000 0x40000000>;
17 };
18
19 regulators {
20 compatible = "simple-bus";
21 #address-cells = <1>;
22 #size-cells = <0>;
23
24 reg_2p5v: regulator@0 {
25 compatible = "regulator-fixed";
26 reg = <0>;
27 regulator-name = "2P5V";
28 regulator-min-microvolt = <2500000>;
29 regulator-max-microvolt = <2500000>;
30 regulator-always-on;
31 };
32
33 reg_3p3v: regulator@1 {
34 compatible = "regulator-fixed";
35 reg = <1>;
36 regulator-name = "3P3V";
37 regulator-min-microvolt = <3300000>;
38 regulator-max-microvolt = <3300000>;
39 regulator-always-on;
40 };
41
42 reg_usb_otg_vbus: regulator@2 {
43 compatible = "regulator-fixed";
44 reg = <2>;
45 regulator-name = "usb_otg_vbus";
46 regulator-min-microvolt = <5000000>;
47 regulator-max-microvolt = <5000000>;
48 gpio = <&gpio3 22 0>;
49 enable-active-high;
50 };
51 };
52
53 sound {
54 compatible = "fsl,imx6q-nitrogen6x-sgtl5000",
55 "fsl,imx-audio-sgtl5000";
56 model = "imx6q-nitrogen6x-sgtl5000";
57 ssi-controller = <&ssi1>;
58 audio-codec = <&codec>;
59 audio-routing =
60 "MIC_IN", "Mic Jack",
61 "Mic Jack", "Mic Bias",
62 "Headphone Jack", "HP_OUT";
63 mux-int-port = <1>;
64 mux-ext-port = <3>;
65 };
66
67 backlight_lcd {
68 compatible = "pwm-backlight";
69 pwms = <&pwm1 0 5000000>;
70 brightness-levels = <0 4 8 16 32 64 128 255>;
71 default-brightness-level = <7>;
72 power-supply = <&reg_3p3v>;
73 status = "okay";
74 };
75
76 backlight_lvds {
77 compatible = "pwm-backlight";
78 pwms = <&pwm4 0 5000000>;
79 brightness-levels = <0 4 8 16 32 64 128 255>;
80 default-brightness-level = <7>;
81 power-supply = <&reg_3p3v>;
82 status = "okay";
83 };
84};
85
86&audmux {
87 pinctrl-names = "default";
88 pinctrl-0 = <&pinctrl_audmux>;
89 status = "okay";
90};
91
92&ecspi1 {
93 fsl,spi-num-chipselects = <1>;
94 cs-gpios = <&gpio3 19 0>;
95 pinctrl-names = "default";
96 pinctrl-0 = <&pinctrl_ecspi1>;
97 status = "okay";
98
99 flash: m25p80@0 {
100 compatible = "sst,sst25vf016b";
101 spi-max-frequency = <20000000>;
102 reg = <0>;
103 };
104};
105
106&fec {
107 pinctrl-names = "default";
108 pinctrl-0 = <&pinctrl_enet>;
109 phy-mode = "rgmii";
110 phy-reset-gpios = <&gpio1 27 0>;
111 txen-skew-ps = <0>;
112 txc-skew-ps = <3000>;
113 rxdv-skew-ps = <0>;
114 rxc-skew-ps = <3000>;
115 rxd0-skew-ps = <0>;
116 rxd1-skew-ps = <0>;
117 rxd2-skew-ps = <0>;
118 rxd3-skew-ps = <0>;
119 txd0-skew-ps = <0>;
120 txd1-skew-ps = <0>;
121 txd2-skew-ps = <0>;
122 txd3-skew-ps = <0>;
123 status = "okay";
124};
125
126&i2c1 {
127 clock-frequency = <100000>;
128 pinctrl-names = "default";
129 pinctrl-0 = <&pinctrl_i2c1>;
130 status = "okay";
131
132 codec: sgtl5000@0a {
133 compatible = "fsl,sgtl5000";
134 reg = <0x0a>;
135 clocks = <&clks 201>;
136 VDDA-supply = <&reg_2p5v>;
137 VDDIO-supply = <&reg_3p3v>;
138 };
139};
140
141&iomuxc {
142 pinctrl-names = "default";
143 pinctrl-0 = <&pinctrl_hog>;
144
145 imx6q-nitrogen6x {
146 pinctrl_hog: hoggrp {
147 fsl,pins = <
148 /* SGTL5000 sys_mclk */
149 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x030b0
150 >;
151 };
152
153 pinctrl_audmux: audmuxgrp {
154 fsl,pins = <
155 MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
156 MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
157 MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0
158 MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
159 >;
160 };
161
162 pinctrl_ecspi1: ecspi1grp {
163 fsl,pins = <
164 MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
165 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
166 MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
167 MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1 /* CS */
168 >;
169 };
170
171 pinctrl_enet: enetgrp {
172 fsl,pins = <
173 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0
174 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0
175 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x100b0
176 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x100b0
177 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x100b0
178 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x100b0
179 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0
180 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0
181 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0
182 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
183 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
184 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
185 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
186 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
187 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
188 /* Phy reset */
189 MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x000b0
190 >;
191 };
192
193 pinctrl_i2c1: i2c1grp {
194 fsl,pins = <
195 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
196 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
197 >;
198 };
199
200 pinctrl_pwm1: pwm1grp {
201 fsl,pins = <
202 MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1
203 >;
204 };
205
206 pinctrl_pwm3: pwm3grp {
207 fsl,pins = <
208 MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
209 >;
210 };
211
212 pinctrl_pwm4: pwm4grp {
213 fsl,pins = <
214 MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
215 >;
216 };
217
218 pinctrl_uart1: uart1grp {
219 fsl,pins = <
220 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
221 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
222 >;
223 };
224
225 pinctrl_uart2: uart2grp {
226 fsl,pins = <
227 MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
228 MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
229 >;
230 };
231
232 pinctrl_usbotg: usbotggrp {
233 fsl,pins = <
234 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
235 MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0
236 /* power enable, high active */
237 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x000b0
238 >;
239 };
240
241 pinctrl_usdhc3: usdhc3grp {
242 fsl,pins = <
243 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
244 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
245 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
246 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
247 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
248 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
249 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 /* CD */
250 >;
251 };
252
253 pinctrl_usdhc4: usdhc4grp {
254 fsl,pins = <
255 MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
256 MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
257 MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
258 MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
259 MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
260 MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
261 MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x1b0b0 /* CD */
262 >;
263 };
264 };
265};
266
267&ldb {
268 status = "okay";
269
270 lvds-channel@0 {
271 fsl,data-mapping = "spwg";
272 fsl,data-width = <18>;
273 status = "okay";
274
275 display-timings {
276 native-mode = <&timing0>;
277 timing0: hsd100pxn1 {
278 clock-frequency = <65000000>;
279 hactive = <1024>;
280 vactive = <768>;
281 hback-porch = <220>;
282 hfront-porch = <40>;
283 vback-porch = <21>;
284 vfront-porch = <7>;
285 hsync-len = <60>;
286 vsync-len = <10>;
287 };
288 };
289 };
290};
291
292&pcie {
293 status = "okay";
294};
295
296&pwm1 {
297 pinctrl-names = "default";
298 pinctrl-0 = <&pinctrl_pwm1>;
299 status = "okay";
300};
301
302&pwm3 {
303 pinctrl-names = "default";
304 pinctrl-0 = <&pinctrl_pwm3>;
305 status = "okay";
306};
307
308&pwm4 {
309 pinctrl-names = "default";
310 pinctrl-0 = <&pinctrl_pwm4>;
311 status = "okay";
312};
313
314&ssi1 {
315 fsl,mode = "i2s-slave";
316 status = "okay";
317};
318
319&uart1 {
320 pinctrl-names = "default";
321 pinctrl-0 = <&pinctrl_uart1>;
322 status = "okay";
323};
324
325&uart2 {
326 pinctrl-names = "default";
327 pinctrl-0 = <&pinctrl_uart2>;
328 status = "okay";
329};
330
331&usbh1 {
332 status = "okay";
333};
334
335&usbotg {
336 vbus-supply = <&reg_usb_otg_vbus>;
337 pinctrl-names = "default";
338 pinctrl-0 = <&pinctrl_usbotg>;
339 disable-over-current;
340 status = "okay";
341};
342
343&usdhc3 {
344 pinctrl-names = "default";
345 pinctrl-0 = <&pinctrl_usdhc3>;
346 cd-gpios = <&gpio7 0 0>;
347 vmmc-supply = <&reg_3p3v>;
348 status = "okay";
349};
350
351&usdhc4 {
352 pinctrl-names = "default";
353 pinctrl-0 = <&pinctrl_usdhc4>;
354 cd-gpios = <&gpio2 6 0>;
355 vmmc-supply = <&reg_3p3v>;
356 status = "okay";
357};