blob: 1eeb3ed9f0cbd10139e1850f13742bce567e6a5c [file] [log] [blame]
Jie Yang43250dd2009-02-18 17:24:15 -08001/*
2 * Copyright(c) 2008 - 2009 Atheros Corporation. All rights reserved.
3 *
4 * Derived from Intel e1000 driver
5 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the Free
9 * Software Foundation; either version 2 of the License, or (at your option)
10 * any later version.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc., 59
19 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 */
21
22#ifndef _ATL1C_HW_H_
23#define _ATL1C_HW_H_
24
25#include <linux/types.h>
26#include <linux/mii.h>
27
28struct atl1c_adapter;
29struct atl1c_hw;
30
31/* function prototype */
32void atl1c_phy_disable(struct atl1c_hw *hw);
33void atl1c_hw_set_mac_addr(struct atl1c_hw *hw);
34int atl1c_phy_reset(struct atl1c_hw *hw);
35int atl1c_read_mac_addr(struct atl1c_hw *hw);
36int atl1c_get_speed_and_duplex(struct atl1c_hw *hw, u16 *speed, u16 *duplex);
37u32 atl1c_hash_mc_addr(struct atl1c_hw *hw, u8 *mc_addr);
38void atl1c_hash_set(struct atl1c_hw *hw, u32 hash_value);
39int atl1c_read_phy_reg(struct atl1c_hw *hw, u16 reg_addr, u16 *phy_data);
40int atl1c_write_phy_reg(struct atl1c_hw *hw, u32 reg_addr, u16 phy_data);
41bool atl1c_read_eeprom(struct atl1c_hw *hw, u32 offset, u32 *p_value);
42int atl1c_phy_init(struct atl1c_hw *hw);
43int atl1c_check_eeprom_exist(struct atl1c_hw *hw);
44int atl1c_restart_autoneg(struct atl1c_hw *hw);
45
46/* register definition */
47#define REG_DEVICE_CAP 0x5C
48#define DEVICE_CAP_MAX_PAYLOAD_MASK 0x7
49#define DEVICE_CAP_MAX_PAYLOAD_SHIFT 0
50
51#define REG_DEVICE_CTRL 0x60
52#define DEVICE_CTRL_MAX_PAYLOAD_MASK 0x7
53#define DEVICE_CTRL_MAX_PAYLOAD_SHIFT 5
54#define DEVICE_CTRL_MAX_RREQ_SZ_MASK 0x7
55#define DEVICE_CTRL_MAX_RREQ_SZ_SHIFT 12
56
57#define REG_LINK_CTRL 0x68
58#define LINK_CTRL_L0S_EN 0x01
59#define LINK_CTRL_L1_EN 0x02
Luis R. Rodriguez496c1852010-02-16 15:16:45 -080060#define LINK_CTRL_EXT_SYNC 0x80
Jie Yang43250dd2009-02-18 17:24:15 -080061
62#define REG_VPD_CAP 0x6C
63#define VPD_CAP_ID_MASK 0xff
64#define VPD_CAP_ID_SHIFT 0
65#define VPD_CAP_NEXT_PTR_MASK 0xFF
66#define VPD_CAP_NEXT_PTR_SHIFT 8
67#define VPD_CAP_VPD_ADDR_MASK 0x7FFF
68#define VPD_CAP_VPD_ADDR_SHIFT 16
69#define VPD_CAP_VPD_FLAG 0x80000000
70
71#define REG_VPD_DATA 0x70
72
73#define REG_PCIE_UC_SEVERITY 0x10C
74#define PCIE_UC_SERVRITY_TRN 0x00000001
75#define PCIE_UC_SERVRITY_DLP 0x00000010
76#define PCIE_UC_SERVRITY_PSN_TLP 0x00001000
77#define PCIE_UC_SERVRITY_FCP 0x00002000
78#define PCIE_UC_SERVRITY_CPL_TO 0x00004000
79#define PCIE_UC_SERVRITY_CA 0x00008000
80#define PCIE_UC_SERVRITY_UC 0x00010000
81#define PCIE_UC_SERVRITY_ROV 0x00020000
82#define PCIE_UC_SERVRITY_MLFP 0x00040000
83#define PCIE_UC_SERVRITY_ECRC 0x00080000
84#define PCIE_UC_SERVRITY_UR 0x00100000
85
86#define REG_DEV_SERIALNUM_CTRL 0x200
87#define REG_DEV_MAC_SEL_MASK 0x0 /* 0:EUI; 1:MAC */
88#define REG_DEV_MAC_SEL_SHIFT 0
89#define REG_DEV_SERIAL_NUM_EN_MASK 0x1
90#define REG_DEV_SERIAL_NUM_EN_SHIFT 1
91
92#define REG_TWSI_CTRL 0x218
93#define TWSI_CTRL_LD_OFFSET_MASK 0xFF
94#define TWSI_CTRL_LD_OFFSET_SHIFT 0
95#define TWSI_CTRL_LD_SLV_ADDR_MASK 0x7
96#define TWSI_CTRL_LD_SLV_ADDR_SHIFT 8
97#define TWSI_CTRL_SW_LDSTART 0x800
98#define TWSI_CTRL_HW_LDSTART 0x1000
99#define TWSI_CTRL_SMB_SLV_ADDR_MASK 0x7F
100#define TWSI_CTRL_SMB_SLV_ADDR_SHIFT 15
101#define TWSI_CTRL_LD_EXIST 0x400000
102#define TWSI_CTRL_READ_FREQ_SEL_MASK 0x3
103#define TWSI_CTRL_READ_FREQ_SEL_SHIFT 23
104#define TWSI_CTRL_FREQ_SEL_100K 0
105#define TWSI_CTRL_FREQ_SEL_200K 1
106#define TWSI_CTRL_FREQ_SEL_300K 2
107#define TWSI_CTRL_FREQ_SEL_400K 3
108#define TWSI_CTRL_SMB_SLV_ADDR
109#define TWSI_CTRL_WRITE_FREQ_SEL_MASK 0x3
110#define TWSI_CTRL_WRITE_FREQ_SEL_SHIFT 24
111
112
113#define REG_PCIE_DEV_MISC_CTRL 0x21C
114#define PCIE_DEV_MISC_EXT_PIPE 0x2
115#define PCIE_DEV_MISC_RETRY_BUFDIS 0x1
116#define PCIE_DEV_MISC_SPIROM_EXIST 0x4
117#define PCIE_DEV_MISC_SERDES_ENDIAN 0x8
118#define PCIE_DEV_MISC_SERDES_SEL_DIN 0x10
119
120#define REG_PCIE_PHYMISC 0x1000
121#define PCIE_PHYMISC_FORCE_RCV_DET 0x4
122
123#define REG_TWSI_DEBUG 0x1108
124#define TWSI_DEBUG_DEV_EXIST 0x20000000
125
126#define REG_EEPROM_CTRL 0x12C0
127#define EEPROM_CTRL_DATA_HI_MASK 0xFFFF
128#define EEPROM_CTRL_DATA_HI_SHIFT 0
129#define EEPROM_CTRL_ADDR_MASK 0x3FF
130#define EEPROM_CTRL_ADDR_SHIFT 16
131#define EEPROM_CTRL_ACK 0x40000000
132#define EEPROM_CTRL_RW 0x80000000
133
134#define REG_EEPROM_DATA_LO 0x12C4
135
136#define REG_OTP_CTRL 0x12F0
137#define OTP_CTRL_CLK_EN 0x0002
138
139#define REG_PM_CTRL 0x12F8
140#define PM_CTRL_SDES_EN 0x00000001
141#define PM_CTRL_RBER_EN 0x00000002
142#define PM_CTRL_CLK_REQ_EN 0x00000004
143#define PM_CTRL_ASPM_L1_EN 0x00000008
144#define PM_CTRL_SERDES_L1_EN 0x00000010
145#define PM_CTRL_SERDES_PLL_L1_EN 0x00000020
146#define PM_CTRL_SERDES_PD_EX_L1 0x00000040
147#define PM_CTRL_SERDES_BUDS_RX_L1_EN 0x00000080
148#define PM_CTRL_L0S_ENTRY_TIMER_MASK 0xF
149#define PM_CTRL_L0S_ENTRY_TIMER_SHIFT 8
150#define PM_CTRL_ASPM_L0S_EN 0x00001000
151#define PM_CTRL_CLK_SWH_L1 0x00002000
152#define PM_CTRL_CLK_PWM_VER1_1 0x00004000
153#define PM_CTRL_PCIE_RECV 0x00008000
154#define PM_CTRL_L1_ENTRY_TIMER_MASK 0xF
155#define PM_CTRL_L1_ENTRY_TIMER_SHIFT 16
156#define PM_CTRL_PM_REQ_TIMER_MASK 0xF
157#define PM_CTRL_PM_REQ_TIMER_SHIFT 20
158#define PM_CTRL_LCKDET_TIMER_MASK 0x3F
159#define PM_CTRL_LCKDET_TIMER_SHIFT 24
Luis R. Rodriguez496c1852010-02-16 15:16:45 -0800160#define PM_CTRL_EN_BUFS_RX_L0S 0x10000000
161#define PM_CTRL_SA_DLY_EN 0x20000000
Jie Yang43250dd2009-02-18 17:24:15 -0800162#define PM_CTRL_MAC_ASPM_CHK 0x40000000
163#define PM_CTRL_HOTRST 0x80000000
164
165/* Selene Master Control Register */
166#define REG_MASTER_CTRL 0x1400
167#define MASTER_CTRL_SOFT_RST 0x1
168#define MASTER_CTRL_TEST_MODE_MASK 0x3
169#define MASTER_CTRL_TEST_MODE_SHIFT 2
170#define MASTER_CTRL_BERT_START 0x10
171#define MASTER_CTRL_MTIMER_EN 0x100
172#define MASTER_CTRL_MANUAL_INT 0x200
173#define MASTER_CTRL_TX_ITIMER_EN 0x400
174#define MASTER_CTRL_RX_ITIMER_EN 0x800
175#define MASTER_CTRL_CLK_SEL_DIS 0x1000
176#define MASTER_CTRL_CLK_SWH_MODE 0x2000
177#define MASTER_CTRL_INT_RDCLR 0x4000
178#define MASTER_CTRL_REV_NUM_SHIFT 16
179#define MASTER_CTRL_REV_NUM_MASK 0xff
180#define MASTER_CTRL_DEV_ID_SHIFT 24
181#define MASTER_CTRL_DEV_ID_MASK 0x7f
182#define MASTER_CTRL_OTP_SEL 0x80000000
183
184/* Timer Initial Value Register */
185#define REG_MANUAL_TIMER_INIT 0x1404
186
187/* IRQ ModeratorTimer Initial Value Register */
188#define REG_IRQ_MODRT_TIMER_INIT 0x1408
189#define IRQ_MODRT_TIMER_MASK 0xffff
190#define IRQ_MODRT_TX_TIMER_SHIFT 0
191#define IRQ_MODRT_RX_TIMER_SHIFT 16
192
193#define REG_GPHY_CTRL 0x140C
194#define GPHY_CTRL_EXT_RESET 0x1
195#define GPHY_CTRL_RTL_MODE 0x2
196#define GPHY_CTRL_LED_MODE 0x4
197#define GPHY_CTRL_ANEG_NOW 0x8
198#define GPHY_CTRL_REV_ANEG 0x10
199#define GPHY_CTRL_GATE_25M_EN 0x20
200#define GPHY_CTRL_LPW_EXIT 0x40
201#define GPHY_CTRL_PHY_IDDQ 0x80
202#define GPHY_CTRL_PHY_IDDQ_DIS 0x100
203#define GPHY_CTRL_GIGA_DIS 0x200
204#define GPHY_CTRL_HIB_EN 0x400
205#define GPHY_CTRL_HIB_PULSE 0x800
206#define GPHY_CTRL_SEL_ANA_RST 0x1000
207#define GPHY_CTRL_PHY_PLL_ON 0x2000
208#define GPHY_CTRL_PWDOWN_HW 0x4000
209#define GPHY_CTRL_PHY_PLL_BYPASS 0x8000
210
211#define GPHY_CTRL_DEFAULT ( \
212 GPHY_CTRL_SEL_ANA_RST |\
213 GPHY_CTRL_HIB_PULSE |\
214 GPHY_CTRL_HIB_EN)
215
216#define GPHY_CTRL_PW_WOL_DIS ( \
217 GPHY_CTRL_SEL_ANA_RST |\
218 GPHY_CTRL_HIB_PULSE |\
219 GPHY_CTRL_HIB_EN |\
220 GPHY_CTRL_PWDOWN_HW |\
221 GPHY_CTRL_PHY_IDDQ)
222
223/* Block IDLE Status Register */
224#define REG_IDLE_STATUS 0x1410
225#define IDLE_STATUS_MASK 0x00FF
226#define IDLE_STATUS_RXMAC_NO_IDLE 0x1
227#define IDLE_STATUS_TXMAC_NO_IDLE 0x2
228#define IDLE_STATUS_RXQ_NO_IDLE 0x4
229#define IDLE_STATUS_TXQ_NO_IDLE 0x8
230#define IDLE_STATUS_DMAR_NO_IDLE 0x10
231#define IDLE_STATUS_DMAW_NO_IDLE 0x20
232#define IDLE_STATUS_SMB_NO_IDLE 0x40
233#define IDLE_STATUS_CMB_NO_IDLE 0x80
234
235/* MDIO Control Register */
236#define REG_MDIO_CTRL 0x1414
237#define MDIO_DATA_MASK 0xffff /* On MDIO write, the 16-bit
238 * control data to write to PHY
239 * MII management register */
240#define MDIO_DATA_SHIFT 0 /* On MDIO read, the 16-bit
241 * status data that was read
242 * from the PHY MII management register */
243#define MDIO_REG_ADDR_MASK 0x1f /* MDIO register address */
244#define MDIO_REG_ADDR_SHIFT 16
245#define MDIO_RW 0x200000 /* 1: read, 0: write */
246#define MDIO_SUP_PREAMBLE 0x400000 /* Suppress preamble */
247#define MDIO_START 0x800000 /* Write 1 to initiate the MDIO
248 * master. And this bit is self
249 * cleared after one cycle */
250#define MDIO_CLK_SEL_SHIFT 24
251#define MDIO_CLK_25_4 0
252#define MDIO_CLK_25_6 2
253#define MDIO_CLK_25_8 3
254#define MDIO_CLK_25_10 4
255#define MDIO_CLK_25_14 5
256#define MDIO_CLK_25_20 6
257#define MDIO_CLK_25_28 7
258#define MDIO_BUSY 0x8000000
259#define MDIO_AP_EN 0x10000000
260#define MDIO_WAIT_TIMES 10
261
262/* MII PHY Status Register */
263#define REG_PHY_STATUS 0x1418
264#define PHY_GENERAL_STATUS_MASK 0xFFFF
265#define PHY_STATUS_RECV_ENABLE 0x0001
266#define PHY_OE_PWSP_STATUS_MASK 0x07FF
267#define PHY_OE_PWSP_STATUS_SHIFT 16
268#define PHY_STATUS_LPW_STATE 0x80000000
269/* BIST Control and Status Register0 (for the Packet Memory) */
270#define REG_BIST0_CTRL 0x141c
271#define BIST0_NOW 0x1
272#define BIST0_SRAM_FAIL 0x2 /* 1: The SRAM failure is
273 * un-repairable because
274 * it has address decoder
275 * failure or more than 1 cell
276 * stuck-to-x failure */
277#define BIST0_FUSE_FLAG 0x4
278
279/* BIST Control and Status Register1(for the retry buffer of PCI Express) */
280#define REG_BIST1_CTRL 0x1420
281#define BIST1_NOW 0x1
282#define BIST1_SRAM_FAIL 0x2
283#define BIST1_FUSE_FLAG 0x4
284
285/* SerDes Lock Detect Control and Status Register */
286#define REG_SERDES_LOCK 0x1424
287#define SERDES_LOCK_DETECT 0x1 /* SerDes lock detected. This signal
288 * comes from Analog SerDes */
289#define SERDES_LOCK_DETECT_EN 0x2 /* 1: Enable SerDes Lock detect function */
290
291/* MAC Control Register */
292#define REG_MAC_CTRL 0x1480
293#define MAC_CTRL_TX_EN 0x1
294#define MAC_CTRL_RX_EN 0x2
295#define MAC_CTRL_TX_FLOW 0x4
296#define MAC_CTRL_RX_FLOW 0x8
297#define MAC_CTRL_LOOPBACK 0x10
298#define MAC_CTRL_DUPLX 0x20
299#define MAC_CTRL_ADD_CRC 0x40
300#define MAC_CTRL_PAD 0x80
301#define MAC_CTRL_LENCHK 0x100
302#define MAC_CTRL_HUGE_EN 0x200
303#define MAC_CTRL_PRMLEN_SHIFT 10
304#define MAC_CTRL_PRMLEN_MASK 0xf
305#define MAC_CTRL_RMV_VLAN 0x4000
306#define MAC_CTRL_PROMIS_EN 0x8000
307#define MAC_CTRL_TX_PAUSE 0x10000
308#define MAC_CTRL_SCNT 0x20000
309#define MAC_CTRL_SRST_TX 0x40000
310#define MAC_CTRL_TX_SIMURST 0x80000
311#define MAC_CTRL_SPEED_SHIFT 20
312#define MAC_CTRL_SPEED_MASK 0x3
313#define MAC_CTRL_DBG_TX_BKPRESURE 0x400000
314#define MAC_CTRL_TX_HUGE 0x800000
315#define MAC_CTRL_RX_CHKSUM_EN 0x1000000
316#define MAC_CTRL_MC_ALL_EN 0x2000000
317#define MAC_CTRL_BC_EN 0x4000000
318#define MAC_CTRL_DBG 0x8000000
319#define MAC_CTRL_SINGLE_PAUSE_EN 0x10000000
Luis R. Rodriguez496c1852010-02-16 15:16:45 -0800320#define MAC_CTRL_HASH_ALG_CRC32 0x20000000
321#define MAC_CTRL_SPEED_MODE_SW 0x40000000
Jie Yang43250dd2009-02-18 17:24:15 -0800322
323/* MAC IPG/IFG Control Register */
324#define REG_MAC_IPG_IFG 0x1484
325#define MAC_IPG_IFG_IPGT_SHIFT 0 /* Desired back to back
326 * inter-packet gap. The
327 * default is 96-bit time */
328#define MAC_IPG_IFG_IPGT_MASK 0x7f
329#define MAC_IPG_IFG_MIFG_SHIFT 8 /* Minimum number of IFG to
330 * enforce in between RX frames */
331#define MAC_IPG_IFG_MIFG_MASK 0xff /* Frame gap below such IFP is dropped */
332#define MAC_IPG_IFG_IPGR1_SHIFT 16 /* 64bit Carrier-Sense window */
333#define MAC_IPG_IFG_IPGR1_MASK 0x7f
334#define MAC_IPG_IFG_IPGR2_SHIFT 24 /* 96-bit IPG window */
335#define MAC_IPG_IFG_IPGR2_MASK 0x7f
336
337/* MAC STATION ADDRESS */
338#define REG_MAC_STA_ADDR 0x1488
339
340/* Hash table for multicast address */
341#define REG_RX_HASH_TABLE 0x1490
342
343/* MAC Half-Duplex Control Register */
344#define REG_MAC_HALF_DUPLX_CTRL 0x1498
345#define MAC_HALF_DUPLX_CTRL_LCOL_SHIFT 0 /* Collision Window */
346#define MAC_HALF_DUPLX_CTRL_LCOL_MASK 0x3ff
347#define MAC_HALF_DUPLX_CTRL_RETRY_SHIFT 12
348#define MAC_HALF_DUPLX_CTRL_RETRY_MASK 0xf
349#define MAC_HALF_DUPLX_CTRL_EXC_DEF_EN 0x10000
350#define MAC_HALF_DUPLX_CTRL_NO_BACK_C 0x20000
351#define MAC_HALF_DUPLX_CTRL_NO_BACK_P 0x40000 /* No back-off on backpressure,
352 * immediately start the
353 * transmission after back pressure */
354#define MAC_HALF_DUPLX_CTRL_ABEBE 0x80000 /* 1: Alternative Binary Exponential Back-off Enabled */
355#define MAC_HALF_DUPLX_CTRL_ABEBT_SHIFT 20 /* Maximum binary exponential number */
356#define MAC_HALF_DUPLX_CTRL_ABEBT_MASK 0xf
357#define MAC_HALF_DUPLX_CTRL_JAMIPG_SHIFT 24 /* IPG to start JAM for collision based flow control in half-duplex */
358#define MAC_HALF_DUPLX_CTRL_JAMIPG_MASK 0xf /* mode. In unit of 8-bit time */
359
360/* Maximum Frame Length Control Register */
361#define REG_MTU 0x149c
362
363/* Wake-On-Lan control register */
364#define REG_WOL_CTRL 0x14a0
365#define WOL_PATTERN_EN 0x00000001
366#define WOL_PATTERN_PME_EN 0x00000002
367#define WOL_MAGIC_EN 0x00000004
368#define WOL_MAGIC_PME_EN 0x00000008
369#define WOL_LINK_CHG_EN 0x00000010
370#define WOL_LINK_CHG_PME_EN 0x00000020
371#define WOL_PATTERN_ST 0x00000100
372#define WOL_MAGIC_ST 0x00000200
373#define WOL_LINKCHG_ST 0x00000400
374#define WOL_CLK_SWITCH_EN 0x00008000
375#define WOL_PT0_EN 0x00010000
376#define WOL_PT1_EN 0x00020000
377#define WOL_PT2_EN 0x00040000
378#define WOL_PT3_EN 0x00080000
379#define WOL_PT4_EN 0x00100000
380#define WOL_PT5_EN 0x00200000
381#define WOL_PT6_EN 0x00400000
382
383/* WOL Length ( 2 DWORD ) */
384#define REG_WOL_PATTERN_LEN 0x14a4
385#define WOL_PT_LEN_MASK 0x7f
386#define WOL_PT0_LEN_SHIFT 0
387#define WOL_PT1_LEN_SHIFT 8
388#define WOL_PT2_LEN_SHIFT 16
389#define WOL_PT3_LEN_SHIFT 24
390#define WOL_PT4_LEN_SHIFT 0
391#define WOL_PT5_LEN_SHIFT 8
392#define WOL_PT6_LEN_SHIFT 16
393
394/* Internal SRAM Partition Register */
395#define RFDX_HEAD_ADDR_MASK 0x03FF
396#define RFDX_HARD_ADDR_SHIFT 0
397#define RFDX_TAIL_ADDR_MASK 0x03FF
398#define RFDX_TAIL_ADDR_SHIFT 16
399
400#define REG_SRAM_RFD0_INFO 0x1500
401#define REG_SRAM_RFD1_INFO 0x1504
402#define REG_SRAM_RFD2_INFO 0x1508
403#define REG_SRAM_RFD3_INFO 0x150C
404
405#define REG_RFD_NIC_LEN 0x1510 /* In 8-bytes */
406#define RFD_NIC_LEN_MASK 0x03FF
407
408#define REG_SRAM_TRD_ADDR 0x1518
409#define TPD_HEAD_ADDR_MASK 0x03FF
410#define TPD_HEAD_ADDR_SHIFT 0
411#define TPD_TAIL_ADDR_MASK 0x03FF
412#define TPD_TAIL_ADDR_SHIFT 16
413
414#define REG_SRAM_TRD_LEN 0x151C /* In 8-bytes */
415#define TPD_NIC_LEN_MASK 0x03FF
416
417#define REG_SRAM_RXF_ADDR 0x1520
418#define REG_SRAM_RXF_LEN 0x1524
419#define REG_SRAM_TXF_ADDR 0x1528
420#define REG_SRAM_TXF_LEN 0x152C
421#define REG_SRAM_TCPH_ADDR 0x1530
422#define REG_SRAM_PKTH_ADDR 0x1532
423
424/*
425 * Load Ptr Register
426 * Software sets this bit after the initialization of the head and tail */
427#define REG_LOAD_PTR 0x1534
428
429/*
430 * addresses of all descriptors, as well as the following descriptor
431 * control register, which triggers each function block to load the head
432 * pointer to prepare for the operation. This bit is then self-cleared
433 * after one cycle.
434 */
435#define REG_RX_BASE_ADDR_HI 0x1540
436#define REG_TX_BASE_ADDR_HI 0x1544
437#define REG_SMB_BASE_ADDR_HI 0x1548
438#define REG_SMB_BASE_ADDR_LO 0x154C
439#define REG_RFD0_HEAD_ADDR_LO 0x1550
440#define REG_RFD1_HEAD_ADDR_LO 0x1554
441#define REG_RFD2_HEAD_ADDR_LO 0x1558
442#define REG_RFD3_HEAD_ADDR_LO 0x155C
443#define REG_RFD_RING_SIZE 0x1560
444#define RFD_RING_SIZE_MASK 0x0FFF
445#define REG_RX_BUF_SIZE 0x1564
446#define RX_BUF_SIZE_MASK 0xFFFF
447#define REG_RRD0_HEAD_ADDR_LO 0x1568
448#define REG_RRD1_HEAD_ADDR_LO 0x156C
449#define REG_RRD2_HEAD_ADDR_LO 0x1570
450#define REG_RRD3_HEAD_ADDR_LO 0x1574
451#define REG_RRD_RING_SIZE 0x1578
452#define RRD_RING_SIZE_MASK 0x0FFF
453#define REG_HTPD_HEAD_ADDR_LO 0x157C
454#define REG_NTPD_HEAD_ADDR_LO 0x1580
455#define REG_TPD_RING_SIZE 0x1584
456#define TPD_RING_SIZE_MASK 0xFFFF
457#define REG_CMB_BASE_ADDR_LO 0x1588
458
459/* RSS about */
460#define REG_RSS_KEY0 0x14B0
461#define REG_RSS_KEY1 0x14B4
462#define REG_RSS_KEY2 0x14B8
463#define REG_RSS_KEY3 0x14BC
464#define REG_RSS_KEY4 0x14C0
465#define REG_RSS_KEY5 0x14C4
466#define REG_RSS_KEY6 0x14C8
467#define REG_RSS_KEY7 0x14CC
468#define REG_RSS_KEY8 0x14D0
469#define REG_RSS_KEY9 0x14D4
470#define REG_IDT_TABLE0 0x14E0
471#define REG_IDT_TABLE1 0x14E4
472#define REG_IDT_TABLE2 0x14E8
473#define REG_IDT_TABLE3 0x14EC
474#define REG_IDT_TABLE4 0x14F0
475#define REG_IDT_TABLE5 0x14F4
476#define REG_IDT_TABLE6 0x14F8
477#define REG_IDT_TABLE7 0x14FC
478#define REG_IDT_TABLE REG_IDT_TABLE0
479#define REG_RSS_HASH_VALUE 0x15B0
480#define REG_RSS_HASH_FLAG 0x15B4
481#define REG_BASE_CPU_NUMBER 0x15B8
482
483/* TXQ Control Register */
484#define REG_TXQ_CTRL 0x1590
485#define TXQ_NUM_TPD_BURST_MASK 0xF
486#define TXQ_NUM_TPD_BURST_SHIFT 0
487#define TXQ_CTRL_IP_OPTION_EN 0x10
488#define TXQ_CTRL_EN 0x20
489#define TXQ_CTRL_ENH_MODE 0x40
490#define TXQ_CTRL_LS_8023_EN 0x80
491#define TXQ_TXF_BURST_NUM_SHIFT 16
492#define TXQ_TXF_BURST_NUM_MASK 0xFFFF
493
494/* Jumbo packet Threshold for task offload */
495#define REG_TX_TSO_OFFLOAD_THRESH 0x1594 /* In 8-bytes */
496#define TX_TSO_OFFLOAD_THRESH_MASK 0x07FF
497
498#define REG_TXF_WATER_MARK 0x1598 /* In 8-bytes */
499#define TXF_WATER_MARK_MASK 0x0FFF
500#define TXF_LOW_WATER_MARK_SHIFT 0
501#define TXF_HIGH_WATER_MARK_SHIFT 16
502#define TXQ_CTRL_BURST_MODE_EN 0x80000000
503
504#define REG_THRUPUT_MON_CTRL 0x159C
505#define THRUPUT_MON_RATE_MASK 0x3
506#define THRUPUT_MON_RATE_SHIFT 0
507#define THRUPUT_MON_EN 0x80
508
509/* RXQ Control Register */
510#define REG_RXQ_CTRL 0x15A0
511#define ASPM_THRUPUT_LIMIT_MASK 0x3
512#define ASPM_THRUPUT_LIMIT_SHIFT 0
513#define ASPM_THRUPUT_LIMIT_NO 0x00
514#define ASPM_THRUPUT_LIMIT_1M 0x01
515#define ASPM_THRUPUT_LIMIT_10M 0x02
516#define ASPM_THRUPUT_LIMIT_100M 0x04
517#define RXQ1_CTRL_EN 0x10
518#define RXQ2_CTRL_EN 0x20
519#define RXQ3_CTRL_EN 0x40
520#define IPV6_CHKSUM_CTRL_EN 0x80
521#define RSS_HASH_BITS_MASK 0x00FF
522#define RSS_HASH_BITS_SHIFT 8
523#define RSS_HASH_IPV4 0x10000
524#define RSS_HASH_IPV4_TCP 0x20000
525#define RSS_HASH_IPV6 0x40000
526#define RSS_HASH_IPV6_TCP 0x80000
527#define RXQ_RFD_BURST_NUM_MASK 0x003F
528#define RXQ_RFD_BURST_NUM_SHIFT 20
529#define RSS_MODE_MASK 0x0003
530#define RSS_MODE_SHIFT 26
531#define RSS_NIP_QUEUE_SEL_MASK 0x1
532#define RSS_NIP_QUEUE_SEL_SHIFT 28
533#define RRS_HASH_CTRL_EN 0x20000000
534#define RX_CUT_THRU_EN 0x40000000
535#define RXQ_CTRL_EN 0x80000000
536
537#define REG_RFD_FREE_THRESH 0x15A4
538#define RFD_FREE_THRESH_MASK 0x003F
539#define RFD_FREE_HI_THRESH_SHIFT 0
540#define RFD_FREE_LO_THRESH_SHIFT 6
541
542/* RXF flow control register */
543#define REG_RXQ_RXF_PAUSE_THRESH 0x15A8
544#define RXQ_RXF_PAUSE_TH_HI_SHIFT 0
545#define RXQ_RXF_PAUSE_TH_HI_MASK 0x0FFF
546#define RXQ_RXF_PAUSE_TH_LO_SHIFT 16
547#define RXQ_RXF_PAUSE_TH_LO_MASK 0x0FFF
548
549#define REG_RXD_DMA_CTRL 0x15AC
550#define RXD_DMA_THRESH_MASK 0x0FFF /* In 8-bytes */
551#define RXD_DMA_THRESH_SHIFT 0
552#define RXD_DMA_DOWN_TIMER_MASK 0xFFFF
553#define RXD_DMA_DOWN_TIMER_SHIFT 16
554
555/* DMA Engine Control Register */
556#define REG_DMA_CTRL 0x15C0
557#define DMA_CTRL_DMAR_IN_ORDER 0x1
558#define DMA_CTRL_DMAR_ENH_ORDER 0x2
559#define DMA_CTRL_DMAR_OUT_ORDER 0x4
560#define DMA_CTRL_RCB_VALUE 0x8
561#define DMA_CTRL_DMAR_BURST_LEN_MASK 0x0007
562#define DMA_CTRL_DMAR_BURST_LEN_SHIFT 4
563#define DMA_CTRL_DMAW_BURST_LEN_MASK 0x0007
564#define DMA_CTRL_DMAW_BURST_LEN_SHIFT 7
565#define DMA_CTRL_DMAR_REQ_PRI 0x400
566#define DMA_CTRL_DMAR_DLY_CNT_MASK 0x001F
567#define DMA_CTRL_DMAR_DLY_CNT_SHIFT 11
568#define DMA_CTRL_DMAW_DLY_CNT_MASK 0x000F
569#define DMA_CTRL_DMAW_DLY_CNT_SHIFT 16
570#define DMA_CTRL_CMB_EN 0x100000
571#define DMA_CTRL_SMB_EN 0x200000
572#define DMA_CTRL_CMB_NOW 0x400000
573#define MAC_CTRL_SMB_DIS 0x1000000
574#define DMA_CTRL_SMB_NOW 0x80000000
575
576/* CMB/SMB Control Register */
577#define REG_SMB_STAT_TIMER 0x15C4 /* 2us resolution */
578#define SMB_STAT_TIMER_MASK 0xFFFFFF
579#define REG_CMB_TPD_THRESH 0x15C8
580#define CMB_TPD_THRESH_MASK 0xFFFF
581#define REG_CMB_TX_TIMER 0x15CC /* 2us resolution */
582#define CMB_TX_TIMER_MASK 0xFFFF
583
584/* Mail box */
585#define MB_RFDX_PROD_IDX_MASK 0xFFFF
586#define REG_MB_RFD0_PROD_IDX 0x15E0
587#define REG_MB_RFD1_PROD_IDX 0x15E4
588#define REG_MB_RFD2_PROD_IDX 0x15E8
589#define REG_MB_RFD3_PROD_IDX 0x15EC
590
591#define MB_PRIO_PROD_IDX_MASK 0xFFFF
592#define REG_MB_PRIO_PROD_IDX 0x15F0
593#define MB_HTPD_PROD_IDX_SHIFT 0
594#define MB_NTPD_PROD_IDX_SHIFT 16
595
596#define MB_PRIO_CONS_IDX_MASK 0xFFFF
597#define REG_MB_PRIO_CONS_IDX 0x15F4
598#define MB_HTPD_CONS_IDX_SHIFT 0
599#define MB_NTPD_CONS_IDX_SHIFT 16
600
601#define REG_MB_RFD01_CONS_IDX 0x15F8
602#define MB_RFD0_CONS_IDX_MASK 0x0000FFFF
603#define MB_RFD1_CONS_IDX_MASK 0xFFFF0000
604#define REG_MB_RFD23_CONS_IDX 0x15FC
605#define MB_RFD2_CONS_IDX_MASK 0x0000FFFF
606#define MB_RFD3_CONS_IDX_MASK 0xFFFF0000
607
608/* Interrupt Status Register */
609#define REG_ISR 0x1600
610#define ISR_SMB 0x00000001
611#define ISR_TIMER 0x00000002
612/*
613 * Software manual interrupt, for debug. Set when SW_MAN_INT_EN is set
614 * in Table 51 Selene Master Control Register (Offset 0x1400).
615 */
616#define ISR_MANUAL 0x00000004
617#define ISR_HW_RXF_OV 0x00000008 /* RXF overflow interrupt */
618#define ISR_RFD0_UR 0x00000010 /* RFD0 under run */
619#define ISR_RFD1_UR 0x00000020
620#define ISR_RFD2_UR 0x00000040
621#define ISR_RFD3_UR 0x00000080
622#define ISR_TXF_UR 0x00000100
623#define ISR_DMAR_TO_RST 0x00000200
624#define ISR_DMAW_TO_RST 0x00000400
625#define ISR_TX_CREDIT 0x00000800
626#define ISR_GPHY 0x00001000
627/* GPHY low power state interrupt */
628#define ISR_GPHY_LPW 0x00002000
629#define ISR_TXQ_TO_RST 0x00004000
630#define ISR_TX_PKT 0x00008000
631#define ISR_RX_PKT_0 0x00010000
632#define ISR_RX_PKT_1 0x00020000
633#define ISR_RX_PKT_2 0x00040000
634#define ISR_RX_PKT_3 0x00080000
635#define ISR_MAC_RX 0x00100000
636#define ISR_MAC_TX 0x00200000
637#define ISR_UR_DETECTED 0x00400000
638#define ISR_FERR_DETECTED 0x00800000
639#define ISR_NFERR_DETECTED 0x01000000
640#define ISR_CERR_DETECTED 0x02000000
641#define ISR_PHY_LINKDOWN 0x04000000
642#define ISR_DIS_INT 0x80000000
643
644/* Interrupt Mask Register */
645#define REG_IMR 0x1604
646
647#define IMR_NORMAL_MASK (\
648 ISR_MANUAL |\
649 ISR_HW_RXF_OV |\
650 ISR_RFD0_UR |\
651 ISR_TXF_UR |\
652 ISR_DMAR_TO_RST |\
653 ISR_TXQ_TO_RST |\
654 ISR_DMAW_TO_RST |\
655 ISR_GPHY |\
656 ISR_TX_PKT |\
657 ISR_RX_PKT_0 |\
658 ISR_GPHY_LPW |\
659 ISR_PHY_LINKDOWN)
660
661#define ISR_RX_PKT (\
662 ISR_RX_PKT_0 |\
663 ISR_RX_PKT_1 |\
664 ISR_RX_PKT_2 |\
665 ISR_RX_PKT_3)
666
667#define ISR_OVER (\
668 ISR_RFD0_UR |\
669 ISR_RFD1_UR |\
670 ISR_RFD2_UR |\
671 ISR_RFD3_UR |\
672 ISR_HW_RXF_OV |\
673 ISR_TXF_UR)
674
675#define ISR_ERROR (\
676 ISR_DMAR_TO_RST |\
677 ISR_TXQ_TO_RST |\
678 ISR_DMAW_TO_RST |\
679 ISR_PHY_LINKDOWN)
680
681#define REG_INT_RETRIG_TIMER 0x1608
682#define INT_RETRIG_TIMER_MASK 0xFFFF
683
684#define REG_HDS_CTRL 0x160C
685#define HDS_CTRL_EN 0x0001
686#define HDS_CTRL_BACKFILLSIZE_SHIFT 8
687#define HDS_CTRL_BACKFILLSIZE_MASK 0x0FFF
688#define HDS_CTRL_MAX_HDRSIZE_SHIFT 20
689#define HDS_CTRL_MAC_HDRSIZE_MASK 0x0FFF
690
691#define REG_MAC_RX_STATUS_BIN 0x1700
692#define REG_MAC_RX_STATUS_END 0x175c
693#define REG_MAC_TX_STATUS_BIN 0x1760
694#define REG_MAC_TX_STATUS_END 0x17c0
695
696/* DEBUG ADDR */
697#define REG_DEBUG_DATA0 0x1900
698#define REG_DEBUG_DATA1 0x1904
699
700/* PHY Control Register */
701#define MII_BMCR 0x00
702#define BMCR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100, 00=10 */
703#define BMCR_COLL_TEST_ENABLE 0x0080 /* Collision test enable */
704#define BMCR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */
705#define BMCR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */
706#define BMCR_ISOLATE 0x0400 /* Isolate PHY from MII */
707#define BMCR_POWER_DOWN 0x0800 /* Power down */
708#define BMCR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */
709#define BMCR_SPEED_SELECT_LSB 0x2000 /* bits 6,13: 10=1000, 01=100, 00=10 */
710#define BMCR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */
711#define BMCR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */
712#define BMCR_SPEED_MASK 0x2040
713#define BMCR_SPEED_1000 0x0040
714#define BMCR_SPEED_100 0x2000
715#define BMCR_SPEED_10 0x0000
716
717/* PHY Status Register */
718#define MII_BMSR 0x01
719#define BMMSR_EXTENDED_CAPS 0x0001 /* Extended register capabilities */
720#define BMSR_JABBER_DETECT 0x0002 /* Jabber Detected */
721#define BMSR_LINK_STATUS 0x0004 /* Link Status 1 = link */
722#define BMSR_AUTONEG_CAPS 0x0008 /* Auto Neg Capable */
723#define BMSR_REMOTE_FAULT 0x0010 /* Remote Fault Detect */
724#define BMSR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */
725#define BMSR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */
726#define BMSR_EXTENDED_STATUS 0x0100 /* Ext. status info in Reg 0x0F */
727#define BMSR_100T2_HD_CAPS 0x0200 /* 100T2 Half Duplex Capable */
728#define BMSR_100T2_FD_CAPS 0x0400 /* 100T2 Full Duplex Capable */
729#define BMSR_10T_HD_CAPS 0x0800 /* 10T Half Duplex Capable */
730#define BMSR_10T_FD_CAPS 0x1000 /* 10T Full Duplex Capable */
731#define BMSR_100X_HD_CAPS 0x2000 /* 100X Half Duplex Capable */
732#define BMMII_SR_100X_FD_CAPS 0x4000 /* 100X Full Duplex Capable */
733#define BMMII_SR_100T4_CAPS 0x8000 /* 100T4 Capable */
734
735#define MII_PHYSID1 0x02
736#define MII_PHYSID2 0x03
737
738/* Autoneg Advertisement Register */
739#define MII_ADVERTISE 0x04
740#define ADVERTISE_SPEED_MASK 0x01E0
741#define ADVERTISE_DEFAULT_CAP 0x0DE0
742
743/* 1000BASE-T Control Register */
744#define MII_GIGA_CR 0x09
745#define GIGA_CR_1000T_REPEATER_DTE 0x0400 /* 1=Repeater/switch device port 0=DTE device */
746
747#define GIGA_CR_1000T_MS_VALUE 0x0800 /* 1=Configure PHY as Master 0=Configure PHY as Slave */
748#define GIGA_CR_1000T_MS_ENABLE 0x1000 /* 1=Master/Slave manual config value 0=Automatic Master/Slave config */
749#define GIGA_CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */
750#define GIGA_CR_1000T_TEST_MODE_1 0x2000 /* Transmit Waveform test */
751#define GIGA_CR_1000T_TEST_MODE_2 0x4000 /* Master Transmit Jitter test */
752#define GIGA_CR_1000T_TEST_MODE_3 0x6000 /* Slave Transmit Jitter test */
753#define GIGA_CR_1000T_TEST_MODE_4 0x8000 /* Transmitter Distortion test */
754#define GIGA_CR_1000T_SPEED_MASK 0x0300
755#define GIGA_CR_1000T_DEFAULT_CAP 0x0300
756
757/* PHY Specific Status Register */
758#define MII_GIGA_PSSR 0x11
759#define GIGA_PSSR_SPD_DPLX_RESOLVED 0x0800 /* 1=Speed & Duplex resolved */
760#define GIGA_PSSR_DPLX 0x2000 /* 1=Duplex 0=Half Duplex */
761#define GIGA_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */
762#define GIGA_PSSR_10MBS 0x0000 /* 00=10Mbs */
763#define GIGA_PSSR_100MBS 0x4000 /* 01=100Mbs */
764#define GIGA_PSSR_1000MBS 0x8000 /* 10=1000Mbs */
765
766/* PHY Interrupt Enable Register */
767#define MII_IER 0x12
768#define IER_LINK_UP 0x0400
769#define IER_LINK_DOWN 0x0800
770
771/* PHY Interrupt Status Register */
772#define MII_ISR 0x13
773#define ISR_LINK_UP 0x0400
774#define ISR_LINK_DOWN 0x0800
775
776/* Cable-Detect-Test Control Register */
777#define MII_CDTC 0x16
778#define CDTC_EN_OFF 0 /* sc */
779#define CDTC_EN_BITS 1
780#define CDTC_PAIR_OFF 8
781#define CDTC_PAIR_BIT 2
782
783/* Cable-Detect-Test Status Register */
784#define MII_CDTS 0x1C
785#define CDTS_STATUS_OFF 8
786#define CDTS_STATUS_BITS 2
787#define CDTS_STATUS_NORMAL 0
788#define CDTS_STATUS_SHORT 1
789#define CDTS_STATUS_OPEN 2
790#define CDTS_STATUS_INVALID 3
791
792#define MII_DBG_ADDR 0x1D
793#define MII_DBG_DATA 0x1E
794
795#define MII_ANA_CTRL_0 0x0
796#define ANA_RESTART_CAL 0x0001
797#define ANA_MANUL_SWICH_ON_SHIFT 0x1
798#define ANA_MANUL_SWICH_ON_MASK 0xF
799#define ANA_MAN_ENABLE 0x0020
800#define ANA_SEL_HSP 0x0040
801#define ANA_EN_HB 0x0080
802#define ANA_EN_HBIAS 0x0100
803#define ANA_OEN_125M 0x0200
804#define ANA_EN_LCKDT 0x0400
805#define ANA_LCKDT_PHY 0x0800
806#define ANA_AFE_MODE 0x1000
807#define ANA_VCO_SLOW 0x2000
808#define ANA_VCO_FAST 0x4000
809#define ANA_SEL_CLK125M_DSP 0x8000
810
811#define MII_ANA_CTRL_4 0x4
812#define ANA_IECHO_ADJ_MASK 0xF
813#define ANA_IECHO_ADJ_3_SHIFT 0
814#define ANA_IECHO_ADJ_2_SHIFT 4
815#define ANA_IECHO_ADJ_1_SHIFT 8
816#define ANA_IECHO_ADJ_0_SHIFT 12
817
818#define MII_ANA_CTRL_5 0x5
819#define ANA_SERDES_CDR_BW_SHIFT 0
820#define ANA_SERDES_CDR_BW_MASK 0x3
821#define ANA_MS_PAD_DBG 0x0004
822#define ANA_SPEEDUP_DBG 0x0008
823#define ANA_SERDES_TH_LOS_SHIFT 4
824#define ANA_SERDES_TH_LOS_MASK 0x3
825#define ANA_SERDES_EN_DEEM 0x0040
826#define ANA_SERDES_TXELECIDLE 0x0080
827#define ANA_SERDES_BEACON 0x0100
828#define ANA_SERDES_HALFTXDR 0x0200
829#define ANA_SERDES_SEL_HSP 0x0400
830#define ANA_SERDES_EN_PLL 0x0800
831#define ANA_SERDES_EN 0x1000
832#define ANA_SERDES_EN_LCKDT 0x2000
833
834#define MII_ANA_CTRL_11 0xB
835#define ANA_PS_HIB_EN 0x8000
836
837#define MII_ANA_CTRL_18 0x12
838#define ANA_TEST_MODE_10BT_01SHIFT 0
839#define ANA_TEST_MODE_10BT_01MASK 0x3
840#define ANA_LOOP_SEL_10BT 0x0004
841#define ANA_RGMII_MODE_SW 0x0008
842#define ANA_EN_LONGECABLE 0x0010
843#define ANA_TEST_MODE_10BT_2 0x0020
844#define ANA_EN_10BT_IDLE 0x0400
845#define ANA_EN_MASK_TB 0x0800
846#define ANA_TRIGGER_SEL_TIMER_SHIFT 12
847#define ANA_TRIGGER_SEL_TIMER_MASK 0x3
848#define ANA_INTERVAL_SEL_TIMER_SHIFT 14
849#define ANA_INTERVAL_SEL_TIMER_MASK 0x3
850
851#define MII_ANA_CTRL_41 0x29
852#define ANA_TOP_PS_EN 0x8000
853
854#define MII_ANA_CTRL_54 0x36
855#define ANA_LONG_CABLE_TH_100_SHIFT 0
856#define ANA_LONG_CABLE_TH_100_MASK 0x3F
857#define ANA_DESERVED 0x0040
858#define ANA_EN_LIT_CH 0x0080
859#define ANA_SHORT_CABLE_TH_100_SHIFT 8
860#define ANA_SHORT_CABLE_TH_100_MASK 0x3F
861#define ANA_BP_BAD_LINK_ACCUM 0x4000
862#define ANA_BP_SMALL_BW 0x8000
863
864#endif /*_ATL1C_HW_H_*/