Paul Burton | b066303 | 2015-05-24 16:11:35 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Ingenic SoC CGU driver |
| 3 | * |
| 4 | * Copyright (c) 2013-2015 Imagination Technologies |
| 5 | * Author: Paul Burton <paul.burton@imgtec.com> |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or |
| 8 | * modify it under the terms of the GNU General Public License as |
| 9 | * published by the Free Software Foundation; either version 2 of |
| 10 | * the License, or (at your option) any later version. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | */ |
| 17 | |
| 18 | #ifndef __DRIVERS_CLK_INGENIC_CGU_H__ |
| 19 | #define __DRIVERS_CLK_INGENIC_CGU_H__ |
| 20 | |
| 21 | #include <linux/bitops.h> |
| 22 | #include <linux/of.h> |
| 23 | #include <linux/spinlock.h> |
| 24 | |
| 25 | /** |
| 26 | * struct ingenic_cgu_pll_info - information about a PLL |
| 27 | * @reg: the offset of the PLL's control register within the CGU |
| 28 | * @m_shift: the number of bits to shift the multiplier value by (ie. the |
| 29 | * index of the lowest bit of the multiplier value in the PLL's |
| 30 | * control register) |
| 31 | * @m_bits: the size of the multiplier field in bits |
| 32 | * @m_offset: the multiplier value which encodes to 0 in the PLL's control |
| 33 | * register |
| 34 | * @n_shift: the number of bits to shift the divider value by (ie. the |
| 35 | * index of the lowest bit of the divider value in the PLL's |
| 36 | * control register) |
| 37 | * @n_bits: the size of the divider field in bits |
| 38 | * @n_offset: the divider value which encodes to 0 in the PLL's control |
| 39 | * register |
| 40 | * @od_shift: the number of bits to shift the post-VCO divider value by (ie. |
| 41 | * the index of the lowest bit of the post-VCO divider value in |
| 42 | * the PLL's control register) |
| 43 | * @od_bits: the size of the post-VCO divider field in bits |
| 44 | * @od_max: the maximum post-VCO divider value |
| 45 | * @od_encoding: a pointer to an array mapping post-VCO divider values to |
| 46 | * their encoded values in the PLL control register, or -1 for |
| 47 | * unsupported values |
| 48 | * @bypass_bit: the index of the bypass bit in the PLL control register |
| 49 | * @enable_bit: the index of the enable bit in the PLL control register |
| 50 | * @stable_bit: the index of the stable bit in the PLL control register |
| 51 | */ |
| 52 | struct ingenic_cgu_pll_info { |
| 53 | unsigned reg; |
| 54 | const s8 *od_encoding; |
| 55 | u8 m_shift, m_bits, m_offset; |
| 56 | u8 n_shift, n_bits, n_offset; |
| 57 | u8 od_shift, od_bits, od_max; |
| 58 | u8 bypass_bit; |
| 59 | u8 enable_bit; |
| 60 | u8 stable_bit; |
| 61 | }; |
| 62 | |
| 63 | /** |
| 64 | * struct ingenic_cgu_mux_info - information about a clock mux |
| 65 | * @reg: offset of the mux control register within the CGU |
| 66 | * @shift: number of bits to shift the mux value by (ie. the index of |
| 67 | * the lowest bit of the mux value within its control register) |
| 68 | * @bits: the size of the mux value in bits |
| 69 | */ |
| 70 | struct ingenic_cgu_mux_info { |
| 71 | unsigned reg; |
| 72 | u8 shift; |
| 73 | u8 bits; |
| 74 | }; |
| 75 | |
| 76 | /** |
| 77 | * struct ingenic_cgu_div_info - information about a divider |
| 78 | * @reg: offset of the divider control register within the CGU |
Harvey Hunt | 4afe2d1 | 2016-05-09 17:29:52 +0100 | [diff] [blame] | 79 | * @shift: number of bits to left shift the divide value by (ie. the index of |
Paul Burton | b066303 | 2015-05-24 16:11:35 +0100 | [diff] [blame] | 80 | * the lowest bit of the divide value within its control register) |
Harvey Hunt | 4afe2d1 | 2016-05-09 17:29:52 +0100 | [diff] [blame] | 81 | * @div: number of bits to divide the divider value by (i.e. if the |
| 82 | * effective divider value is the value written to the register |
| 83 | * multiplied by some constant) |
Paul Burton | b066303 | 2015-05-24 16:11:35 +0100 | [diff] [blame] | 84 | * @bits: the size of the divide value in bits |
| 85 | * @ce_bit: the index of the change enable bit within reg, or -1 if there |
| 86 | * isn't one |
| 87 | * @busy_bit: the index of the busy bit within reg, or -1 if there isn't one |
| 88 | * @stop_bit: the index of the stop bit within reg, or -1 if there isn't one |
| 89 | */ |
| 90 | struct ingenic_cgu_div_info { |
| 91 | unsigned reg; |
| 92 | u8 shift; |
Harvey Hunt | 4afe2d1 | 2016-05-09 17:29:52 +0100 | [diff] [blame] | 93 | u8 div; |
Paul Burton | b066303 | 2015-05-24 16:11:35 +0100 | [diff] [blame] | 94 | u8 bits; |
| 95 | s8 ce_bit; |
| 96 | s8 busy_bit; |
| 97 | s8 stop_bit; |
| 98 | }; |
| 99 | |
| 100 | /** |
| 101 | * struct ingenic_cgu_fixdiv_info - information about a fixed divider |
| 102 | * @div: the divider applied to the parent clock |
| 103 | */ |
| 104 | struct ingenic_cgu_fixdiv_info { |
| 105 | unsigned div; |
| 106 | }; |
| 107 | |
| 108 | /** |
| 109 | * struct ingenic_cgu_gate_info - information about a clock gate |
| 110 | * @reg: offset of the gate control register within the CGU |
| 111 | * @bit: offset of the bit in the register that controls the gate |
| 112 | */ |
| 113 | struct ingenic_cgu_gate_info { |
| 114 | unsigned reg; |
| 115 | u8 bit; |
| 116 | }; |
| 117 | |
| 118 | /** |
| 119 | * struct ingenic_cgu_custom_info - information about a custom (SoC) clock |
| 120 | * @clk_ops: custom clock operation callbacks |
| 121 | */ |
| 122 | struct ingenic_cgu_custom_info { |
| 123 | struct clk_ops *clk_ops; |
| 124 | }; |
| 125 | |
| 126 | /** |
| 127 | * struct ingenic_cgu_clk_info - information about a clock |
| 128 | * @name: name of the clock |
| 129 | * @type: a bitmask formed from CGU_CLK_* values |
| 130 | * @parents: an array of the indices of potential parents of this clock |
| 131 | * within the clock_info array of the CGU, or -1 in entries |
| 132 | * which correspond to no valid parent |
| 133 | * @pll: information valid if type includes CGU_CLK_PLL |
| 134 | * @gate: information valid if type includes CGU_CLK_GATE |
| 135 | * @mux: information valid if type includes CGU_CLK_MUX |
| 136 | * @div: information valid if type includes CGU_CLK_DIV |
| 137 | * @fixdiv: information valid if type includes CGU_CLK_FIXDIV |
| 138 | * @custom: information valid if type includes CGU_CLK_CUSTOM |
| 139 | */ |
| 140 | struct ingenic_cgu_clk_info { |
| 141 | const char *name; |
| 142 | |
| 143 | enum { |
| 144 | CGU_CLK_NONE = 0, |
| 145 | CGU_CLK_EXT = BIT(0), |
| 146 | CGU_CLK_PLL = BIT(1), |
| 147 | CGU_CLK_GATE = BIT(2), |
| 148 | CGU_CLK_MUX = BIT(3), |
| 149 | CGU_CLK_MUX_GLITCHFREE = BIT(4), |
| 150 | CGU_CLK_DIV = BIT(5), |
| 151 | CGU_CLK_FIXDIV = BIT(6), |
| 152 | CGU_CLK_CUSTOM = BIT(7), |
| 153 | } type; |
| 154 | |
| 155 | int parents[4]; |
| 156 | |
| 157 | union { |
| 158 | struct ingenic_cgu_pll_info pll; |
| 159 | |
| 160 | struct { |
| 161 | struct ingenic_cgu_gate_info gate; |
| 162 | struct ingenic_cgu_mux_info mux; |
| 163 | struct ingenic_cgu_div_info div; |
| 164 | struct ingenic_cgu_fixdiv_info fixdiv; |
| 165 | }; |
| 166 | |
| 167 | struct ingenic_cgu_custom_info custom; |
| 168 | }; |
| 169 | }; |
| 170 | |
| 171 | /** |
| 172 | * struct ingenic_cgu - data about the CGU |
| 173 | * @np: the device tree node that caused the CGU to be probed |
| 174 | * @base: the ioremap'ed base address of the CGU registers |
| 175 | * @clock_info: an array containing information about implemented clocks |
| 176 | * @clocks: used to provide clocks to DT, allows lookup of struct clk* |
| 177 | * @lock: lock to be held whilst manipulating CGU registers |
| 178 | */ |
| 179 | struct ingenic_cgu { |
| 180 | struct device_node *np; |
| 181 | void __iomem *base; |
| 182 | |
| 183 | const struct ingenic_cgu_clk_info *clock_info; |
| 184 | struct clk_onecell_data clocks; |
| 185 | |
| 186 | spinlock_t lock; |
| 187 | }; |
| 188 | |
| 189 | /** |
| 190 | * struct ingenic_clk - private data for a clock |
| 191 | * @hw: see Documentation/clk.txt |
| 192 | * @cgu: a pointer to the CGU data |
| 193 | * @idx: the index of this clock in cgu->clock_info |
| 194 | */ |
| 195 | struct ingenic_clk { |
| 196 | struct clk_hw hw; |
| 197 | struct ingenic_cgu *cgu; |
| 198 | unsigned idx; |
| 199 | }; |
| 200 | |
| 201 | #define to_ingenic_clk(_hw) container_of(_hw, struct ingenic_clk, hw) |
| 202 | |
| 203 | /** |
| 204 | * ingenic_cgu_new() - create a new CGU instance |
| 205 | * @clock_info: an array of clock information structures describing the clocks |
| 206 | * which are implemented by the CGU |
| 207 | * @num_clocks: the number of entries in clock_info |
| 208 | * @np: the device tree node which causes this CGU to be probed |
| 209 | * |
| 210 | * Return: a pointer to the CGU instance if initialisation is successful, |
| 211 | * otherwise NULL. |
| 212 | */ |
| 213 | struct ingenic_cgu * |
| 214 | ingenic_cgu_new(const struct ingenic_cgu_clk_info *clock_info, |
| 215 | unsigned num_clocks, struct device_node *np); |
| 216 | |
| 217 | /** |
| 218 | * ingenic_cgu_register_clocks() - Registers the clocks |
| 219 | * @cgu: pointer to cgu data |
| 220 | * |
| 221 | * Register the clocks described by the CGU with the common clock framework. |
| 222 | * |
| 223 | * Return: 0 on success or -errno if unsuccesful. |
| 224 | */ |
| 225 | int ingenic_cgu_register_clocks(struct ingenic_cgu *cgu); |
| 226 | |
| 227 | #endif /* __DRIVERS_CLK_INGENIC_CGU_H__ */ |