blob: 86cf10815db0c838ea92cfe9ff6727b2e07c94d2 [file] [log] [blame]
Atul Deshmukh7ec0eff2013-08-27 01:37:28 -04001/*
2 * QLogic Fibre Channel HBA Driver
3 * Copyright (c) 2003-2013 QLogic Corporation
4 *
5 * See LICENSE.qla2xxx for copyright and licensing details.
6 */
7
8#include <linux/vmalloc.h>
9
10#include "qla_def.h"
11#include "qla_gbl.h"
12
13#include <linux/delay.h>
14
15/* 8044 Flash Read/Write functions */
16uint32_t
17qla8044_rd_reg(struct qla_hw_data *ha, ulong addr)
18{
19 return readl((void __iomem *) (ha->nx_pcibase + addr));
20}
21
22void
23qla8044_wr_reg(struct qla_hw_data *ha, ulong addr, uint32_t val)
24{
25 writel(val, (void __iomem *)((ha)->nx_pcibase + addr));
26}
27
28int
29qla8044_rd_direct(struct scsi_qla_host *vha,
30 const uint32_t crb_reg)
31{
32 struct qla_hw_data *ha = vha->hw;
33
34 if (crb_reg < CRB_REG_INDEX_MAX)
35 return qla8044_rd_reg(ha, qla8044_reg_tbl[crb_reg]);
36 else
37 return QLA_FUNCTION_FAILED;
38}
39
40void
41qla8044_wr_direct(struct scsi_qla_host *vha,
42 const uint32_t crb_reg,
43 const uint32_t value)
44{
45 struct qla_hw_data *ha = vha->hw;
46
47 if (crb_reg < CRB_REG_INDEX_MAX)
48 qla8044_wr_reg(ha, qla8044_reg_tbl[crb_reg], value);
49}
50
51static int
52qla8044_set_win_base(scsi_qla_host_t *vha, uint32_t addr)
53{
54 uint32_t val;
55 int ret_val = QLA_SUCCESS;
56 struct qla_hw_data *ha = vha->hw;
57
58 qla8044_wr_reg(ha, QLA8044_CRB_WIN_FUNC(ha->portnum), addr);
59 val = qla8044_rd_reg(ha, QLA8044_CRB_WIN_FUNC(ha->portnum));
60
61 if (val != addr) {
62 ql_log(ql_log_warn, vha, 0xb087,
63 "%s: Failed to set register window : "
64 "addr written 0x%x, read 0x%x!\n",
65 __func__, addr, val);
66 ret_val = QLA_FUNCTION_FAILED;
67 }
68 return ret_val;
69}
70
71static int
72qla8044_rd_reg_indirect(scsi_qla_host_t *vha, uint32_t addr, uint32_t *data)
73{
74 int ret_val = QLA_SUCCESS;
75 struct qla_hw_data *ha = vha->hw;
76
77 ret_val = qla8044_set_win_base(vha, addr);
78 if (!ret_val)
79 *data = qla8044_rd_reg(ha, QLA8044_WILDCARD);
80 else
81 ql_log(ql_log_warn, vha, 0xb088,
82 "%s: failed read of addr 0x%x!\n", __func__, addr);
83 return ret_val;
84}
85
86static int
87qla8044_wr_reg_indirect(scsi_qla_host_t *vha, uint32_t addr, uint32_t data)
88{
89 int ret_val = QLA_SUCCESS;
90 struct qla_hw_data *ha = vha->hw;
91
92 ret_val = qla8044_set_win_base(vha, addr);
93 if (!ret_val)
94 qla8044_wr_reg(ha, QLA8044_WILDCARD, data);
95 else
96 ql_log(ql_log_warn, vha, 0xb089,
97 "%s: failed wrt to addr 0x%x, data 0x%x\n",
98 __func__, addr, data);
99 return ret_val;
100}
101
102/*
103 * qla8044_read_write_crb_reg - Read from raddr and write value to waddr.
104 *
105 * @ha : Pointer to adapter structure
106 * @raddr : CRB address to read from
107 * @waddr : CRB address to write to
108 *
109 */
110static void
111qla8044_read_write_crb_reg(struct scsi_qla_host *vha,
112 uint32_t raddr, uint32_t waddr)
113{
114 uint32_t value;
115
116 qla8044_rd_reg_indirect(vha, raddr, &value);
117 qla8044_wr_reg_indirect(vha, waddr, value);
118}
119
120/*
121 * qla8044_rmw_crb_reg - Read value from raddr, AND with test_mask,
122 * Shift Left,Right/OR/XOR with values RMW header and write value to waddr.
123 *
124 * @vha : Pointer to adapter structure
125 * @raddr : CRB address to read from
126 * @waddr : CRB address to write to
127 * @p_rmw_hdr : header with shift/or/xor values.
128 *
129 */
130static void
131qla8044_rmw_crb_reg(struct scsi_qla_host *vha,
132 uint32_t raddr, uint32_t waddr, struct qla8044_rmw *p_rmw_hdr)
133{
134 uint32_t value;
135
136 if (p_rmw_hdr->index_a)
137 value = vha->reset_tmplt.array[p_rmw_hdr->index_a];
138 else
139 qla8044_rd_reg_indirect(vha, raddr, &value);
140 value &= p_rmw_hdr->test_mask;
141 value <<= p_rmw_hdr->shl;
142 value >>= p_rmw_hdr->shr;
143 value |= p_rmw_hdr->or_value;
144 value ^= p_rmw_hdr->xor_value;
145 qla8044_wr_reg_indirect(vha, waddr, value);
146 return;
147}
148
149inline void
150qla8044_set_qsnt_ready(struct scsi_qla_host *vha)
151{
152 uint32_t qsnt_state;
153 struct qla_hw_data *ha = vha->hw;
154
155 qsnt_state = qla8044_rd_direct(vha, QLA8044_CRB_DRV_STATE_INDEX);
156 qsnt_state |= (1 << ha->portnum);
157 qla8044_wr_direct(vha, QLA8044_CRB_DRV_STATE_INDEX, qsnt_state);
158 ql_log(ql_log_info, vha, 0xb08e, "%s(%ld): qsnt_state: 0x%08x\n",
159 __func__, vha->host_no, qsnt_state);
160}
161
162void
163qla8044_clear_qsnt_ready(struct scsi_qla_host *vha)
164{
165 uint32_t qsnt_state;
166 struct qla_hw_data *ha = vha->hw;
167
168 qsnt_state = qla8044_rd_direct(vha, QLA8044_CRB_DRV_STATE_INDEX);
169 qsnt_state &= ~(1 << ha->portnum);
170 qla8044_wr_direct(vha, QLA8044_CRB_DRV_STATE_INDEX, qsnt_state);
171 ql_log(ql_log_info, vha, 0xb08f, "%s(%ld): qsnt_state: 0x%08x\n",
172 __func__, vha->host_no, qsnt_state);
173}
174
175/**
176 *
177 * qla8044_lock_recovery - Recovers the idc_lock.
178 * @ha : Pointer to adapter structure
179 *
180 * Lock Recovery Register
181 * 5-2 Lock recovery owner: Function ID of driver doing lock recovery,
182 * valid if bits 1..0 are set by driver doing lock recovery.
183 * 1-0 1 - Driver intends to force unlock the IDC lock.
184 * 2 - Driver is moving forward to unlock the IDC lock. Driver clears
185 * this field after force unlocking the IDC lock.
186 *
187 * Lock Recovery process
188 * a. Read the IDC_LOCK_RECOVERY register. If the value in bits 1..0 is
189 * greater than 0, then wait for the other driver to unlock otherwise
190 * move to the next step.
191 * b. Indicate intent to force-unlock by writing 1h to the IDC_LOCK_RECOVERY
192 * register bits 1..0 and also set the function# in bits 5..2.
193 * c. Read the IDC_LOCK_RECOVERY register again after a delay of 200ms.
194 * Wait for the other driver to perform lock recovery if the function
195 * number in bits 5..2 has changed, otherwise move to the next step.
196 * d. Write a value of 2h to the IDC_LOCK_RECOVERY register bits 1..0
197 * leaving your function# in bits 5..2.
198 * e. Force unlock using the DRIVER_UNLOCK register and immediately clear
199 * the IDC_LOCK_RECOVERY bits 5..0 by writing 0.
200 **/
201static int
202qla8044_lock_recovery(struct scsi_qla_host *vha)
203{
204 uint32_t lock = 0, lockid;
205 struct qla_hw_data *ha = vha->hw;
206
207 lockid = qla8044_rd_reg(ha, QLA8044_DRV_LOCKRECOVERY);
208
209 /* Check for other Recovery in progress, go wait */
210 if ((lockid & IDC_LOCK_RECOVERY_STATE_MASK) != 0)
211 return QLA_FUNCTION_FAILED;
212
213 /* Intent to Recover */
214 qla8044_wr_reg(ha, QLA8044_DRV_LOCKRECOVERY,
215 (ha->portnum <<
216 IDC_LOCK_RECOVERY_STATE_SHIFT_BITS) | INTENT_TO_RECOVER);
217 msleep(200);
218
219 /* Check Intent to Recover is advertised */
220 lockid = qla8044_rd_reg(ha, QLA8044_DRV_LOCKRECOVERY);
221 if ((lockid & IDC_LOCK_RECOVERY_OWNER_MASK) != (ha->portnum <<
222 IDC_LOCK_RECOVERY_STATE_SHIFT_BITS))
223 return QLA_FUNCTION_FAILED;
224
225 ql_dbg(ql_dbg_p3p, vha, 0xb08B, "%s:%d: IDC Lock recovery initiated\n"
226 , __func__, ha->portnum);
227
228 /* Proceed to Recover */
229 qla8044_wr_reg(ha, QLA8044_DRV_LOCKRECOVERY,
230 (ha->portnum << IDC_LOCK_RECOVERY_STATE_SHIFT_BITS) |
231 PROCEED_TO_RECOVER);
232
233 /* Force Unlock() */
234 qla8044_wr_reg(ha, QLA8044_DRV_LOCK_ID, 0xFF);
235 qla8044_rd_reg(ha, QLA8044_DRV_UNLOCK);
236
237 /* Clear bits 0-5 in IDC_RECOVERY register*/
238 qla8044_wr_reg(ha, QLA8044_DRV_LOCKRECOVERY, 0);
239
240 /* Get lock() */
241 lock = qla8044_rd_reg(ha, QLA8044_DRV_LOCK);
242 if (lock) {
243 lockid = qla8044_rd_reg(ha, QLA8044_DRV_LOCK_ID);
244 lockid = ((lockid + (1 << 8)) & ~0xFF) | ha->portnum;
245 qla8044_wr_reg(ha, QLA8044_DRV_LOCK_ID, lockid);
246 return QLA_SUCCESS;
247 } else
248 return QLA_FUNCTION_FAILED;
249}
250
251int
252qla8044_idc_lock(struct qla_hw_data *ha)
253{
254 uint32_t ret_val = QLA_SUCCESS, timeout = 0, status = 0;
255 uint32_t lock_id, lock_cnt, func_num, tmo_owner = 0, first_owner = 0;
256 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
257
258 while (status == 0) {
259 /* acquire semaphore5 from PCI HW block */
260 status = qla8044_rd_reg(ha, QLA8044_DRV_LOCK);
261
262 if (status) {
263 /* Increment Counter (8-31) and update func_num (0-7) on
264 * getting a successful lock */
265 lock_id = qla8044_rd_reg(ha, QLA8044_DRV_LOCK_ID);
266 lock_id = ((lock_id + (1 << 8)) & ~0xFF) | ha->portnum;
267 qla8044_wr_reg(ha, QLA8044_DRV_LOCK_ID, lock_id);
268 break;
269 }
270
271 if (timeout == 0)
272 first_owner = qla8044_rd_reg(ha, QLA8044_DRV_LOCK_ID);
273
274 if (++timeout >=
275 (QLA8044_DRV_LOCK_TIMEOUT / QLA8044_DRV_LOCK_MSLEEP)) {
276 tmo_owner = qla8044_rd_reg(ha, QLA8044_DRV_LOCK_ID);
277 func_num = tmo_owner & 0xFF;
278 lock_cnt = tmo_owner >> 8;
279 ql_log(ql_log_warn, vha, 0xb114,
280 "%s: Lock by func %d failed after 2s, lock held "
281 "by func %d, lock count %d, first_owner %d\n",
282 __func__, ha->portnum, func_num, lock_cnt,
283 (first_owner & 0xFF));
284 if (first_owner != tmo_owner) {
285 /* Some other driver got lock,
286 * OR same driver got lock again (counter
287 * value changed), when we were waiting for
288 * lock. Retry for another 2 sec */
289 ql_dbg(ql_dbg_p3p, vha, 0xb115,
290 "%s: %d: IDC lock failed\n",
291 __func__, ha->portnum);
292 timeout = 0;
293 } else {
294 /* Same driver holding lock > 2sec.
295 * Force Recovery */
296 if (qla8044_lock_recovery(vha) == QLA_SUCCESS) {
297 /* Recovered and got lock */
298 ret_val = QLA_SUCCESS;
299 ql_dbg(ql_dbg_p3p, vha, 0xb116,
300 "%s:IDC lock Recovery by %d"
301 "successful...\n", __func__,
302 ha->portnum);
303 }
304 /* Recovery Failed, some other function
305 * has the lock, wait for 2secs
306 * and retry
307 */
308 ql_dbg(ql_dbg_p3p, vha, 0xb08a,
309 "%s: IDC lock Recovery by %d "
310 "failed, Retrying timout\n", __func__,
311 ha->portnum);
312 timeout = 0;
313 }
314 }
315 msleep(QLA8044_DRV_LOCK_MSLEEP);
316 }
317 return ret_val;
318}
319
320void
321qla8044_idc_unlock(struct qla_hw_data *ha)
322{
323 int id;
324 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
325
326 id = qla8044_rd_reg(ha, QLA8044_DRV_LOCK_ID);
327
328 if ((id & 0xFF) != ha->portnum) {
329 ql_log(ql_log_warn, vha, 0xb118,
330 "%s: IDC Unlock by %d failed, lock owner is %d!\n",
331 __func__, ha->portnum, (id & 0xFF));
332 return;
333 }
334
335 /* Keep lock counter value, update the ha->func_num to 0xFF */
336 qla8044_wr_reg(ha, QLA8044_DRV_LOCK_ID, (id | 0xFF));
337 qla8044_rd_reg(ha, QLA8044_DRV_UNLOCK);
338}
339
340/* 8044 Flash Lock/Unlock functions */
341static int
342qla8044_flash_lock(scsi_qla_host_t *vha)
343{
344 int lock_owner;
345 int timeout = 0;
346 uint32_t lock_status = 0;
347 int ret_val = QLA_SUCCESS;
348 struct qla_hw_data *ha = vha->hw;
349
350 while (lock_status == 0) {
351 lock_status = qla8044_rd_reg(ha, QLA8044_FLASH_LOCK);
352 if (lock_status)
353 break;
354
355 if (++timeout >= QLA8044_FLASH_LOCK_TIMEOUT / 20) {
356 lock_owner = qla8044_rd_reg(ha,
357 QLA8044_FLASH_LOCK_ID);
358 ql_log(ql_log_warn, vha, 0xb113,
359 "%s: flash lock by %d failed, held by %d\n",
360 __func__, ha->portnum, lock_owner);
361 ret_val = QLA_FUNCTION_FAILED;
362 break;
363 }
364 msleep(20);
365 }
366 qla8044_wr_reg(ha, QLA8044_FLASH_LOCK_ID, ha->portnum);
367 return ret_val;
368}
369
370static void
371qla8044_flash_unlock(scsi_qla_host_t *vha)
372{
373 int ret_val;
374 struct qla_hw_data *ha = vha->hw;
375
376 /* Reading FLASH_UNLOCK register unlocks the Flash */
377 qla8044_wr_reg(ha, QLA8044_FLASH_LOCK_ID, 0xFF);
378 ret_val = qla8044_rd_reg(ha, QLA8044_FLASH_UNLOCK);
379}
380
381
382static
383void qla8044_flash_lock_recovery(struct scsi_qla_host *vha)
384{
385
386 if (qla8044_flash_lock(vha)) {
387 /* Someone else is holding the lock. */
388 ql_log(ql_log_warn, vha, 0xb120, "Resetting flash_lock\n");
389 }
390
391 /*
392 * Either we got the lock, or someone
393 * else died while holding it.
394 * In either case, unlock.
395 */
396 qla8044_flash_unlock(vha);
397}
398
399/*
400 * Address and length are byte address
401 */
402static int
403qla8044_read_flash_data(scsi_qla_host_t *vha, uint8_t *p_data,
404 uint32_t flash_addr, int u32_word_count)
405{
406 int i, ret_val = QLA_SUCCESS;
407 uint32_t u32_word;
408
409 if (qla8044_flash_lock(vha) != QLA_SUCCESS) {
410 ret_val = QLA_FUNCTION_FAILED;
411 goto exit_lock_error;
412 }
413
414 if (flash_addr & 0x03) {
415 ql_log(ql_log_warn, vha, 0xb117,
416 "%s: Illegal addr = 0x%x\n", __func__, flash_addr);
417 ret_val = QLA_FUNCTION_FAILED;
418 goto exit_flash_read;
419 }
420
421 for (i = 0; i < u32_word_count; i++) {
422 if (qla8044_wr_reg_indirect(vha, QLA8044_FLASH_DIRECT_WINDOW,
423 (flash_addr & 0xFFFF0000))) {
424 ql_log(ql_log_warn, vha, 0xb119,
425 "%s: failed to write addr 0x%x to "
426 "FLASH_DIRECT_WINDOW\n! ",
427 __func__, flash_addr);
428 ret_val = QLA_FUNCTION_FAILED;
429 goto exit_flash_read;
430 }
431
432 ret_val = qla8044_rd_reg_indirect(vha,
433 QLA8044_FLASH_DIRECT_DATA(flash_addr),
434 &u32_word);
435 if (ret_val != QLA_SUCCESS) {
436 ql_log(ql_log_warn, vha, 0xb08c,
437 "%s: failed to read addr 0x%x!\n",
438 __func__, flash_addr);
439 goto exit_flash_read;
440 }
441
442 *(uint32_t *)p_data = u32_word;
443 p_data = p_data + 4;
444 flash_addr = flash_addr + 4;
445 }
446
447exit_flash_read:
448 qla8044_flash_unlock(vha);
449
450exit_lock_error:
451 return ret_val;
452}
453
454/*
455 * Address and length are byte address
456 */
457uint8_t *
458qla8044_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
459 uint32_t offset, uint32_t length)
460{
461 scsi_block_requests(vha->host);
462 if (qla8044_read_flash_data(vha, (uint8_t *)buf, offset, length / 4)
463 != QLA_SUCCESS) {
464 ql_log(ql_log_warn, vha, 0xb08d,
465 "%s: Failed to read from flash\n",
466 __func__);
467 }
468 scsi_unblock_requests(vha->host);
469 return buf;
470}
471
472inline int
473qla8044_need_reset(struct scsi_qla_host *vha)
474{
475 uint32_t drv_state, drv_active;
476 int rval;
477 struct qla_hw_data *ha = vha->hw;
478
479 drv_active = qla8044_rd_direct(vha, QLA8044_CRB_DRV_ACTIVE_INDEX);
480 drv_state = qla8044_rd_direct(vha, QLA8044_CRB_DRV_STATE_INDEX);
481
482 rval = drv_state & (1 << ha->portnum);
483
484 if (ha->flags.eeh_busy && drv_active)
485 rval = 1;
486 return rval;
487}
488
489/*
490 * qla8044_write_list - Write the value (p_entry->arg2) to address specified
491 * by p_entry->arg1 for all entries in header with delay of p_hdr->delay between
492 * entries.
493 *
494 * @vha : Pointer to adapter structure
495 * @p_hdr : reset_entry header for WRITE_LIST opcode.
496 *
497 */
498static void
499qla8044_write_list(struct scsi_qla_host *vha,
500 struct qla8044_reset_entry_hdr *p_hdr)
501{
502 struct qla8044_entry *p_entry;
503 uint32_t i;
504
505 p_entry = (struct qla8044_entry *)((char *)p_hdr +
506 sizeof(struct qla8044_reset_entry_hdr));
507
508 for (i = 0; i < p_hdr->count; i++, p_entry++) {
509 qla8044_wr_reg_indirect(vha, p_entry->arg1, p_entry->arg2);
510 if (p_hdr->delay)
511 udelay((uint32_t)(p_hdr->delay));
512 }
513}
514
515/*
516 * qla8044_read_write_list - Read from address specified by p_entry->arg1,
517 * write value read to address specified by p_entry->arg2, for all entries in
518 * header with delay of p_hdr->delay between entries.
519 *
520 * @vha : Pointer to adapter structure
521 * @p_hdr : reset_entry header for READ_WRITE_LIST opcode.
522 *
523 */
524static void
525qla8044_read_write_list(struct scsi_qla_host *vha,
526 struct qla8044_reset_entry_hdr *p_hdr)
527{
528 struct qla8044_entry *p_entry;
529 uint32_t i;
530
531 p_entry = (struct qla8044_entry *)((char *)p_hdr +
532 sizeof(struct qla8044_reset_entry_hdr));
533
534 for (i = 0; i < p_hdr->count; i++, p_entry++) {
535 qla8044_read_write_crb_reg(vha, p_entry->arg1,
536 p_entry->arg2);
537 if (p_hdr->delay)
538 udelay((uint32_t)(p_hdr->delay));
539 }
540}
541
542/*
543 * qla8044_poll_reg - Poll the given CRB addr for duration msecs till
544 * value read ANDed with test_mask is equal to test_result.
545 *
546 * @ha : Pointer to adapter structure
547 * @addr : CRB register address
548 * @duration : Poll for total of "duration" msecs
549 * @test_mask : Mask value read with "test_mask"
550 * @test_result : Compare (value&test_mask) with test_result.
551 *
552 * Return Value - QLA_SUCCESS/QLA_FUNCTION_FAILED
553 */
554static int
555qla8044_poll_reg(struct scsi_qla_host *vha, uint32_t addr,
556 int duration, uint32_t test_mask, uint32_t test_result)
557{
558 uint32_t value;
559 int timeout_error;
560 uint8_t retries;
561 int ret_val = QLA_SUCCESS;
562
563 ret_val = qla8044_rd_reg_indirect(vha, addr, &value);
564 if (ret_val == QLA_FUNCTION_FAILED) {
565 timeout_error = 1;
566 goto exit_poll_reg;
567 }
568
569 /* poll every 1/10 of the total duration */
570 retries = duration/10;
571
572 do {
573 if ((value & test_mask) != test_result) {
574 timeout_error = 1;
575 msleep(duration/10);
576 ret_val = qla8044_rd_reg_indirect(vha, addr, &value);
577 if (ret_val == QLA_FUNCTION_FAILED) {
578 timeout_error = 1;
579 goto exit_poll_reg;
580 }
581 } else {
582 timeout_error = 0;
583 break;
584 }
585 } while (retries--);
586
587exit_poll_reg:
588 if (timeout_error) {
589 vha->reset_tmplt.seq_error++;
590 ql_log(ql_log_fatal, vha, 0xb090,
591 "%s: Poll Failed: 0x%08x 0x%08x 0x%08x\n",
592 __func__, value, test_mask, test_result);
593 }
594
595 return timeout_error;
596}
597
598/*
599 * qla8044_poll_list - For all entries in the POLL_LIST header, poll read CRB
600 * register specified by p_entry->arg1 and compare (value AND test_mask) with
601 * test_result to validate it. Wait for p_hdr->delay between processing entries.
602 *
603 * @ha : Pointer to adapter structure
604 * @p_hdr : reset_entry header for POLL_LIST opcode.
605 *
606 */
607static void
608qla8044_poll_list(struct scsi_qla_host *vha,
609 struct qla8044_reset_entry_hdr *p_hdr)
610{
611 long delay;
612 struct qla8044_entry *p_entry;
613 struct qla8044_poll *p_poll;
614 uint32_t i;
615 uint32_t value;
616
617 p_poll = (struct qla8044_poll *)
618 ((char *)p_hdr + sizeof(struct qla8044_reset_entry_hdr));
619
620 /* Entries start after 8 byte qla8044_poll, poll header contains
621 * the test_mask, test_value.
622 */
623 p_entry = (struct qla8044_entry *)((char *)p_poll +
624 sizeof(struct qla8044_poll));
625
626 delay = (long)p_hdr->delay;
627
628 if (!delay) {
629 for (i = 0; i < p_hdr->count; i++, p_entry++)
630 qla8044_poll_reg(vha, p_entry->arg1,
631 delay, p_poll->test_mask, p_poll->test_value);
632 } else {
633 for (i = 0; i < p_hdr->count; i++, p_entry++) {
634 if (delay) {
635 if (qla8044_poll_reg(vha,
636 p_entry->arg1, delay,
637 p_poll->test_mask,
638 p_poll->test_value)) {
639 /*If
640 * (data_read&test_mask != test_value)
641 * read TIMEOUT_ADDR (arg1) and
642 * ADDR (arg2) registers
643 */
644 qla8044_rd_reg_indirect(vha,
645 p_entry->arg1, &value);
646 qla8044_rd_reg_indirect(vha,
647 p_entry->arg2, &value);
648 }
649 }
650 }
651 }
652}
653
654/*
655 * qla8044_poll_write_list - Write dr_value, ar_value to dr_addr/ar_addr,
656 * read ar_addr, if (value& test_mask != test_mask) re-read till timeout
657 * expires.
658 *
659 * @vha : Pointer to adapter structure
660 * @p_hdr : reset entry header for POLL_WRITE_LIST opcode.
661 *
662 */
663static void
664qla8044_poll_write_list(struct scsi_qla_host *vha,
665 struct qla8044_reset_entry_hdr *p_hdr)
666{
667 long delay;
668 struct qla8044_quad_entry *p_entry;
669 struct qla8044_poll *p_poll;
670 uint32_t i;
671
672 p_poll = (struct qla8044_poll *)((char *)p_hdr +
673 sizeof(struct qla8044_reset_entry_hdr));
674
675 p_entry = (struct qla8044_quad_entry *)((char *)p_poll +
676 sizeof(struct qla8044_poll));
677
678 delay = (long)p_hdr->delay;
679
680 for (i = 0; i < p_hdr->count; i++, p_entry++) {
681 qla8044_wr_reg_indirect(vha,
682 p_entry->dr_addr, p_entry->dr_value);
683 qla8044_wr_reg_indirect(vha,
684 p_entry->ar_addr, p_entry->ar_value);
685 if (delay) {
686 if (qla8044_poll_reg(vha,
687 p_entry->ar_addr, delay,
688 p_poll->test_mask,
689 p_poll->test_value)) {
690 ql_dbg(ql_dbg_p3p, vha, 0xb091,
691 "%s: Timeout Error: poll list, ",
692 __func__);
693 ql_dbg(ql_dbg_p3p, vha, 0xb092,
694 "item_num %d, entry_num %d\n", i,
695 vha->reset_tmplt.seq_index);
696 }
697 }
698 }
699}
700
701/*
702 * qla8044_read_modify_write - Read value from p_entry->arg1, modify the
703 * value, write value to p_entry->arg2. Process entries with p_hdr->delay
704 * between entries.
705 *
706 * @vha : Pointer to adapter structure
707 * @p_hdr : header with shift/or/xor values.
708 *
709 */
710static void
711qla8044_read_modify_write(struct scsi_qla_host *vha,
712 struct qla8044_reset_entry_hdr *p_hdr)
713{
714 struct qla8044_entry *p_entry;
715 struct qla8044_rmw *p_rmw_hdr;
716 uint32_t i;
717
718 p_rmw_hdr = (struct qla8044_rmw *)((char *)p_hdr +
719 sizeof(struct qla8044_reset_entry_hdr));
720
721 p_entry = (struct qla8044_entry *)((char *)p_rmw_hdr +
722 sizeof(struct qla8044_rmw));
723
724 for (i = 0; i < p_hdr->count; i++, p_entry++) {
725 qla8044_rmw_crb_reg(vha, p_entry->arg1,
726 p_entry->arg2, p_rmw_hdr);
727 if (p_hdr->delay)
728 udelay((uint32_t)(p_hdr->delay));
729 }
730}
731
732/*
733 * qla8044_pause - Wait for p_hdr->delay msecs, called between processing
734 * two entries of a sequence.
735 *
736 * @vha : Pointer to adapter structure
737 * @p_hdr : Common reset entry header.
738 *
739 */
740static
741void qla8044_pause(struct scsi_qla_host *vha,
742 struct qla8044_reset_entry_hdr *p_hdr)
743{
744 if (p_hdr->delay)
745 mdelay((uint32_t)((long)p_hdr->delay));
746}
747
748/*
749 * qla8044_template_end - Indicates end of reset sequence processing.
750 *
751 * @vha : Pointer to adapter structure
752 * @p_hdr : Common reset entry header.
753 *
754 */
755static void
756qla8044_template_end(struct scsi_qla_host *vha,
757 struct qla8044_reset_entry_hdr *p_hdr)
758{
759 vha->reset_tmplt.template_end = 1;
760
761 if (vha->reset_tmplt.seq_error == 0) {
762 ql_dbg(ql_dbg_p3p, vha, 0xb093,
763 "%s: Reset sequence completed SUCCESSFULLY.\n", __func__);
764 } else {
765 ql_log(ql_log_fatal, vha, 0xb094,
766 "%s: Reset sequence completed with some timeout "
767 "errors.\n", __func__);
768 }
769}
770
771/*
772 * qla8044_poll_read_list - Write ar_value to ar_addr register, read ar_addr,
773 * if (value & test_mask != test_value) re-read till timeout value expires,
774 * read dr_addr register and assign to reset_tmplt.array.
775 *
776 * @vha : Pointer to adapter structure
777 * @p_hdr : Common reset entry header.
778 *
779 */
780static void
781qla8044_poll_read_list(struct scsi_qla_host *vha,
782 struct qla8044_reset_entry_hdr *p_hdr)
783{
784 long delay;
785 int index;
786 struct qla8044_quad_entry *p_entry;
787 struct qla8044_poll *p_poll;
788 uint32_t i;
789 uint32_t value;
790
791 p_poll = (struct qla8044_poll *)
792 ((char *)p_hdr + sizeof(struct qla8044_reset_entry_hdr));
793
794 p_entry = (struct qla8044_quad_entry *)
795 ((char *)p_poll + sizeof(struct qla8044_poll));
796
797 delay = (long)p_hdr->delay;
798
799 for (i = 0; i < p_hdr->count; i++, p_entry++) {
800 qla8044_wr_reg_indirect(vha, p_entry->ar_addr,
801 p_entry->ar_value);
802 if (delay) {
803 if (qla8044_poll_reg(vha, p_entry->ar_addr, delay,
804 p_poll->test_mask, p_poll->test_value)) {
805 ql_dbg(ql_dbg_p3p, vha, 0xb095,
806 "%s: Timeout Error: poll "
807 "list, ", __func__);
808 ql_dbg(ql_dbg_p3p, vha, 0xb096,
809 "Item_num %d, "
810 "entry_num %d\n", i,
811 vha->reset_tmplt.seq_index);
812 } else {
813 index = vha->reset_tmplt.array_index;
814 qla8044_rd_reg_indirect(vha,
815 p_entry->dr_addr, &value);
816 vha->reset_tmplt.array[index++] = value;
817 if (index == QLA8044_MAX_RESET_SEQ_ENTRIES)
818 vha->reset_tmplt.array_index = 1;
819 }
820 }
821 }
822}
823
824/*
825 * qla8031_process_reset_template - Process all entries in reset template
826 * till entry with SEQ_END opcode, which indicates end of the reset template
827 * processing. Each entry has a Reset Entry header, entry opcode/command, with
828 * size of the entry, number of entries in sub-sequence and delay in microsecs
829 * or timeout in millisecs.
830 *
831 * @ha : Pointer to adapter structure
832 * @p_buff : Common reset entry header.
833 *
834 */
835static void
836qla8044_process_reset_template(struct scsi_qla_host *vha,
837 char *p_buff)
838{
839 int index, entries;
840 struct qla8044_reset_entry_hdr *p_hdr;
841 char *p_entry = p_buff;
842
843 vha->reset_tmplt.seq_end = 0;
844 vha->reset_tmplt.template_end = 0;
845 entries = vha->reset_tmplt.hdr->entries;
846 index = vha->reset_tmplt.seq_index;
847
848 for (; (!vha->reset_tmplt.seq_end) && (index < entries); index++) {
849 p_hdr = (struct qla8044_reset_entry_hdr *)p_entry;
850 switch (p_hdr->cmd) {
851 case OPCODE_NOP:
852 break;
853 case OPCODE_WRITE_LIST:
854 qla8044_write_list(vha, p_hdr);
855 break;
856 case OPCODE_READ_WRITE_LIST:
857 qla8044_read_write_list(vha, p_hdr);
858 break;
859 case OPCODE_POLL_LIST:
860 qla8044_poll_list(vha, p_hdr);
861 break;
862 case OPCODE_POLL_WRITE_LIST:
863 qla8044_poll_write_list(vha, p_hdr);
864 break;
865 case OPCODE_READ_MODIFY_WRITE:
866 qla8044_read_modify_write(vha, p_hdr);
867 break;
868 case OPCODE_SEQ_PAUSE:
869 qla8044_pause(vha, p_hdr);
870 break;
871 case OPCODE_SEQ_END:
872 vha->reset_tmplt.seq_end = 1;
873 break;
874 case OPCODE_TMPL_END:
875 qla8044_template_end(vha, p_hdr);
876 break;
877 case OPCODE_POLL_READ_LIST:
878 qla8044_poll_read_list(vha, p_hdr);
879 break;
880 default:
881 ql_log(ql_log_fatal, vha, 0xb097,
882 "%s: Unknown command ==> 0x%04x on "
883 "entry = %d\n", __func__, p_hdr->cmd, index);
884 break;
885 }
886 /*
887 *Set pointer to next entry in the sequence.
888 */
889 p_entry += p_hdr->size;
890 }
891 vha->reset_tmplt.seq_index = index;
892}
893
894static void
895qla8044_process_init_seq(struct scsi_qla_host *vha)
896{
897 qla8044_process_reset_template(vha,
898 vha->reset_tmplt.init_offset);
899 if (vha->reset_tmplt.seq_end != 1)
900 ql_log(ql_log_fatal, vha, 0xb098,
901 "%s: Abrupt INIT Sub-Sequence end.\n",
902 __func__);
903}
904
905static void
906qla8044_process_stop_seq(struct scsi_qla_host *vha)
907{
908 vha->reset_tmplt.seq_index = 0;
909 qla8044_process_reset_template(vha, vha->reset_tmplt.stop_offset);
910 if (vha->reset_tmplt.seq_end != 1)
911 ql_log(ql_log_fatal, vha, 0xb099,
912 "%s: Abrupt STOP Sub-Sequence end.\n", __func__);
913}
914
915static void
916qla8044_process_start_seq(struct scsi_qla_host *vha)
917{
918 qla8044_process_reset_template(vha, vha->reset_tmplt.start_offset);
919 if (vha->reset_tmplt.template_end != 1)
920 ql_log(ql_log_fatal, vha, 0xb09a,
921 "%s: Abrupt START Sub-Sequence end.\n",
922 __func__);
923}
924
925static int
926qla8044_lockless_flash_read_u32(struct scsi_qla_host *vha,
927 uint32_t flash_addr, uint8_t *p_data, int u32_word_count)
928{
929 uint32_t i;
930 uint32_t u32_word;
931 uint32_t flash_offset;
932 uint32_t addr = flash_addr;
933 int ret_val = QLA_SUCCESS;
934
935 flash_offset = addr & (QLA8044_FLASH_SECTOR_SIZE - 1);
936
937 if (addr & 0x3) {
938 ql_log(ql_log_fatal, vha, 0xb09b, "%s: Illegal addr = 0x%x\n",
939 __func__, addr);
940 ret_val = QLA_FUNCTION_FAILED;
941 goto exit_lockless_read;
942 }
943
944 ret_val = qla8044_wr_reg_indirect(vha,
945 QLA8044_FLASH_DIRECT_WINDOW, (addr));
946
947 if (ret_val != QLA_SUCCESS) {
948 ql_log(ql_log_fatal, vha, 0xb09c,
949 "%s: failed to write addr 0x%x to FLASH_DIRECT_WINDOW!\n",
950 __func__, addr);
951 goto exit_lockless_read;
952 }
953
954 /* Check if data is spread across multiple sectors */
955 if ((flash_offset + (u32_word_count * sizeof(uint32_t))) >
956 (QLA8044_FLASH_SECTOR_SIZE - 1)) {
957 /* Multi sector read */
958 for (i = 0; i < u32_word_count; i++) {
959 ret_val = qla8044_rd_reg_indirect(vha,
960 QLA8044_FLASH_DIRECT_DATA(addr), &u32_word);
961 if (ret_val != QLA_SUCCESS) {
962 ql_log(ql_log_fatal, vha, 0xb09d,
963 "%s: failed to read addr 0x%x!\n",
964 __func__, addr);
965 goto exit_lockless_read;
966 }
967 *(uint32_t *)p_data = u32_word;
968 p_data = p_data + 4;
969 addr = addr + 4;
970 flash_offset = flash_offset + 4;
971 if (flash_offset > (QLA8044_FLASH_SECTOR_SIZE - 1)) {
972 /* This write is needed once for each sector */
973 ret_val = qla8044_wr_reg_indirect(vha,
974 QLA8044_FLASH_DIRECT_WINDOW, (addr));
975 if (ret_val != QLA_SUCCESS) {
976 ql_log(ql_log_fatal, vha, 0xb09f,
977 "%s: failed to write addr "
978 "0x%x to FLASH_DIRECT_WINDOW!\n",
979 __func__, addr);
980 goto exit_lockless_read;
981 }
982 flash_offset = 0;
983 }
984 }
985 } else {
986 /* Single sector read */
987 for (i = 0; i < u32_word_count; i++) {
988 ret_val = qla8044_rd_reg_indirect(vha,
989 QLA8044_FLASH_DIRECT_DATA(addr), &u32_word);
990 if (ret_val != QLA_SUCCESS) {
991 ql_log(ql_log_fatal, vha, 0xb0a0,
992 "%s: failed to read addr 0x%x!\n",
993 __func__, addr);
994 goto exit_lockless_read;
995 }
996 *(uint32_t *)p_data = u32_word;
997 p_data = p_data + 4;
998 addr = addr + 4;
999 }
1000 }
1001
1002exit_lockless_read:
1003 return ret_val;
1004}
1005
1006/*
1007 * qla8044_ms_mem_write_128b - Writes data to MS/off-chip memory
1008 *
1009 * @vha : Pointer to adapter structure
1010 * addr : Flash address to write to
1011 * data : Data to be written
1012 * count : word_count to be written
1013 *
1014 * Return Value - QLA_SUCCESS/QLA_FUNCTION_FAILED
1015 */
1016static int
1017qla8044_ms_mem_write_128b(struct scsi_qla_host *vha,
1018 uint64_t addr, uint32_t *data, uint32_t count)
1019{
1020 int i, j, ret_val = QLA_SUCCESS;
1021 uint32_t agt_ctrl;
1022 unsigned long flags;
1023 struct qla_hw_data *ha = vha->hw;
1024
1025 /* Only 128-bit aligned access */
1026 if (addr & 0xF) {
1027 ret_val = QLA_FUNCTION_FAILED;
1028 goto exit_ms_mem_write;
1029 }
1030 write_lock_irqsave(&ha->hw_lock, flags);
1031
1032 /* Write address */
1033 ret_val = qla8044_wr_reg_indirect(vha, MD_MIU_TEST_AGT_ADDR_HI, 0);
1034 if (ret_val == QLA_FUNCTION_FAILED) {
1035 ql_log(ql_log_fatal, vha, 0xb0a1,
1036 "%s: write to AGT_ADDR_HI failed!\n", __func__);
1037 goto exit_ms_mem_write_unlock;
1038 }
1039
1040 for (i = 0; i < count; i++, addr += 16) {
1041 if (!((QLA8044_ADDR_IN_RANGE(addr, QLA8044_ADDR_QDR_NET,
1042 QLA8044_ADDR_QDR_NET_MAX)) ||
1043 (QLA8044_ADDR_IN_RANGE(addr, QLA8044_ADDR_DDR_NET,
1044 QLA8044_ADDR_DDR_NET_MAX)))) {
1045 ret_val = QLA_FUNCTION_FAILED;
1046 goto exit_ms_mem_write_unlock;
1047 }
1048
1049 ret_val = qla8044_wr_reg_indirect(vha,
1050 MD_MIU_TEST_AGT_ADDR_LO, addr);
1051
1052 /* Write data */
1053 ret_val += qla8044_wr_reg_indirect(vha,
1054 MD_MIU_TEST_AGT_WRDATA_LO, *data++);
1055 ret_val += qla8044_wr_reg_indirect(vha,
1056 MD_MIU_TEST_AGT_WRDATA_HI, *data++);
1057 ret_val += qla8044_wr_reg_indirect(vha,
1058 MD_MIU_TEST_AGT_WRDATA_ULO, *data++);
1059 ret_val += qla8044_wr_reg_indirect(vha,
1060 MD_MIU_TEST_AGT_WRDATA_UHI, *data++);
1061 if (ret_val == QLA_FUNCTION_FAILED) {
1062 ql_log(ql_log_fatal, vha, 0xb0a2,
1063 "%s: write to AGT_WRDATA failed!\n",
1064 __func__);
1065 goto exit_ms_mem_write_unlock;
1066 }
1067
1068 /* Check write status */
1069 ret_val = qla8044_wr_reg_indirect(vha, MD_MIU_TEST_AGT_CTRL,
1070 MIU_TA_CTL_WRITE_ENABLE);
1071 ret_val += qla8044_wr_reg_indirect(vha, MD_MIU_TEST_AGT_CTRL,
1072 MIU_TA_CTL_WRITE_START);
1073 if (ret_val == QLA_FUNCTION_FAILED) {
1074 ql_log(ql_log_fatal, vha, 0xb0a3,
1075 "%s: write to AGT_CTRL failed!\n", __func__);
1076 goto exit_ms_mem_write_unlock;
1077 }
1078
1079 for (j = 0; j < MAX_CTL_CHECK; j++) {
1080 ret_val = qla8044_rd_reg_indirect(vha,
1081 MD_MIU_TEST_AGT_CTRL, &agt_ctrl);
1082 if (ret_val == QLA_FUNCTION_FAILED) {
1083 ql_log(ql_log_fatal, vha, 0xb0a4,
1084 "%s: failed to read "
1085 "MD_MIU_TEST_AGT_CTRL!\n", __func__);
1086 goto exit_ms_mem_write_unlock;
1087 }
1088 if ((agt_ctrl & MIU_TA_CTL_BUSY) == 0)
1089 break;
1090 }
1091
1092 /* Status check failed */
1093 if (j >= MAX_CTL_CHECK) {
1094 ql_log(ql_log_fatal, vha, 0xb0a5,
1095 "%s: MS memory write failed!\n",
1096 __func__);
1097 ret_val = QLA_FUNCTION_FAILED;
1098 goto exit_ms_mem_write_unlock;
1099 }
1100 }
1101
1102exit_ms_mem_write_unlock:
1103 write_unlock_irqrestore(&ha->hw_lock, flags);
1104
1105exit_ms_mem_write:
1106 return ret_val;
1107}
1108
1109static int
1110qla8044_copy_bootloader(struct scsi_qla_host *vha)
1111{
1112 uint8_t *p_cache;
1113 uint32_t src, count, size;
1114 uint64_t dest;
1115 int ret_val = QLA_SUCCESS;
1116 struct qla_hw_data *ha = vha->hw;
1117
1118 src = QLA8044_BOOTLOADER_FLASH_ADDR;
1119 dest = qla8044_rd_reg(ha, QLA8044_BOOTLOADER_ADDR);
1120 size = qla8044_rd_reg(ha, QLA8044_BOOTLOADER_SIZE);
1121
1122 /* 128 bit alignment check */
1123 if (size & 0xF)
1124 size = (size + 16) & ~0xF;
1125
1126 /* 16 byte count */
1127 count = size/16;
1128
1129 p_cache = vmalloc(size);
1130 if (p_cache == NULL) {
1131 ql_log(ql_log_fatal, vha, 0xb0a6,
1132 "%s: Failed to allocate memory for "
1133 "boot loader cache\n", __func__);
1134 ret_val = QLA_FUNCTION_FAILED;
1135 goto exit_copy_bootloader;
1136 }
1137
1138 ret_val = qla8044_lockless_flash_read_u32(vha, src,
1139 p_cache, size/sizeof(uint32_t));
1140 if (ret_val == QLA_FUNCTION_FAILED) {
1141 ql_log(ql_log_fatal, vha, 0xb0a7,
1142 "%s: Error reading F/W from flash!!!\n", __func__);
1143 goto exit_copy_error;
1144 }
1145 ql_dbg(ql_dbg_p3p, vha, 0xb0a8, "%s: Read F/W from flash!\n",
1146 __func__);
1147
1148 /* 128 bit/16 byte write to MS memory */
1149 ret_val = qla8044_ms_mem_write_128b(vha, dest,
1150 (uint32_t *)p_cache, count);
1151 if (ret_val == QLA_FUNCTION_FAILED) {
1152 ql_log(ql_log_fatal, vha, 0xb0a9,
1153 "%s: Error writing F/W to MS !!!\n", __func__);
1154 goto exit_copy_error;
1155 }
1156 ql_dbg(ql_dbg_p3p, vha, 0xb0aa,
1157 "%s: Wrote F/W (size %d) to MS !!!\n",
1158 __func__, size);
1159
1160exit_copy_error:
1161 vfree(p_cache);
1162
1163exit_copy_bootloader:
1164 return ret_val;
1165}
1166
1167static int
1168qla8044_restart(struct scsi_qla_host *vha)
1169{
1170 int ret_val = QLA_SUCCESS;
1171 struct qla_hw_data *ha = vha->hw;
1172
1173 qla8044_process_stop_seq(vha);
1174
1175 /* Collect minidump */
1176 if (ql2xmdenable)
1177 qla8044_get_minidump(vha);
1178 else
1179 ql_log(ql_log_fatal, vha, 0xb14c,
1180 "Minidump disabled.\n");
1181
1182 qla8044_process_init_seq(vha);
1183
1184 if (qla8044_copy_bootloader(vha)) {
1185 ql_log(ql_log_fatal, vha, 0xb0ab,
1186 "%s: Copy bootloader, firmware restart failed!\n",
1187 __func__);
1188 ret_val = QLA_FUNCTION_FAILED;
1189 goto exit_restart;
1190 }
1191
1192 /*
1193 * Loads F/W from flash
1194 */
1195 qla8044_wr_reg(ha, QLA8044_FW_IMAGE_VALID, QLA8044_BOOT_FROM_FLASH);
1196
1197 qla8044_process_start_seq(vha);
1198
1199exit_restart:
1200 return ret_val;
1201}
1202
1203/*
1204 * qla8044_check_cmd_peg_status - Check peg status to see if Peg is
1205 * initialized.
1206 *
1207 * @ha : Pointer to adapter structure
1208 *
1209 * Return Value - QLA_SUCCESS/QLA_FUNCTION_FAILED
1210 */
1211static int
1212qla8044_check_cmd_peg_status(struct scsi_qla_host *vha)
1213{
1214 uint32_t val, ret_val = QLA_FUNCTION_FAILED;
1215 int retries = CRB_CMDPEG_CHECK_RETRY_COUNT;
1216 struct qla_hw_data *ha = vha->hw;
1217
1218 do {
1219 val = qla8044_rd_reg(ha, QLA8044_CMDPEG_STATE);
1220 if (val == PHAN_INITIALIZE_COMPLETE) {
1221 ql_dbg(ql_dbg_p3p, vha, 0xb0ac,
1222 "%s: Command Peg initialization "
1223 "complete! state=0x%x\n", __func__, val);
1224 ret_val = QLA_SUCCESS;
1225 break;
1226 }
1227 msleep(CRB_CMDPEG_CHECK_DELAY);
1228 } while (--retries);
1229
1230 return ret_val;
1231}
1232
1233static int
1234qla8044_start_firmware(struct scsi_qla_host *vha)
1235{
1236 int ret_val = QLA_SUCCESS;
1237
1238 if (qla8044_restart(vha)) {
1239 ql_log(ql_log_fatal, vha, 0xb0ad,
1240 "%s: Restart Error!!!, Need Reset!!!\n",
1241 __func__);
1242 ret_val = QLA_FUNCTION_FAILED;
1243 goto exit_start_fw;
1244 } else
1245 ql_dbg(ql_dbg_p3p, vha, 0xb0af,
1246 "%s: Restart done!\n", __func__);
1247
1248 ret_val = qla8044_check_cmd_peg_status(vha);
1249 if (ret_val) {
1250 ql_log(ql_log_fatal, vha, 0xb0b0,
1251 "%s: Peg not initialized!\n", __func__);
1252 ret_val = QLA_FUNCTION_FAILED;
1253 }
1254
1255exit_start_fw:
1256 return ret_val;
1257}
1258
1259void
Saurav Kashyapc41afc92013-11-07 02:54:56 -05001260qla8044_clear_drv_active(struct qla_hw_data *ha)
Atul Deshmukh7ec0eff2013-08-27 01:37:28 -04001261{
1262 uint32_t drv_active;
Saurav Kashyapc41afc92013-11-07 02:54:56 -05001263 struct scsi_qla_host *vha = pci_get_drvdata(ha->pdev);
Atul Deshmukh7ec0eff2013-08-27 01:37:28 -04001264
1265 drv_active = qla8044_rd_direct(vha, QLA8044_CRB_DRV_ACTIVE_INDEX);
1266 drv_active &= ~(1 << (ha->portnum));
1267
1268 ql_log(ql_log_info, vha, 0xb0b1,
1269 "%s(%ld): drv_active: 0x%08x\n",
1270 __func__, vha->host_no, drv_active);
1271
1272 qla8044_wr_direct(vha, QLA8044_CRB_DRV_ACTIVE_INDEX, drv_active);
1273}
1274
1275/*
1276 * qla8044_device_bootstrap - Initialize device, set DEV_READY, start fw
1277 * @ha: pointer to adapter structure
1278 *
1279 * Note: IDC lock must be held upon entry
1280 **/
1281static int
1282qla8044_device_bootstrap(struct scsi_qla_host *vha)
1283{
1284 int rval = QLA_FUNCTION_FAILED;
1285 int i;
1286 uint32_t old_count = 0, count = 0;
1287 int need_reset = 0;
1288 uint32_t idc_ctrl;
1289 struct qla_hw_data *ha = vha->hw;
1290
1291 need_reset = qla8044_need_reset(vha);
1292
1293 if (!need_reset) {
1294 old_count = qla8044_rd_direct(vha,
1295 QLA8044_PEG_ALIVE_COUNTER_INDEX);
1296
1297 for (i = 0; i < 10; i++) {
1298 msleep(200);
1299
1300 count = qla8044_rd_direct(vha,
1301 QLA8044_PEG_ALIVE_COUNTER_INDEX);
1302 if (count != old_count) {
1303 rval = QLA_SUCCESS;
1304 goto dev_ready;
1305 }
1306 }
1307 qla8044_flash_lock_recovery(vha);
1308 } else {
1309 /* We are trying to perform a recovery here. */
1310 if (ha->flags.isp82xx_fw_hung)
1311 qla8044_flash_lock_recovery(vha);
1312 }
1313
1314 /* set to DEV_INITIALIZING */
1315 ql_log(ql_log_info, vha, 0xb0b2,
1316 "%s: HW State: INITIALIZING\n", __func__);
1317 qla8044_wr_direct(vha, QLA8044_CRB_DEV_STATE_INDEX,
1318 QLA8XXX_DEV_INITIALIZING);
1319
1320 qla8044_idc_unlock(ha);
1321 rval = qla8044_start_firmware(vha);
1322 qla8044_idc_lock(ha);
1323
1324 if (rval != QLA_SUCCESS) {
1325 ql_log(ql_log_info, vha, 0xb0b3,
1326 "%s: HW State: FAILED\n", __func__);
Saurav Kashyapc41afc92013-11-07 02:54:56 -05001327 qla8044_clear_drv_active(ha);
Atul Deshmukh7ec0eff2013-08-27 01:37:28 -04001328 qla8044_wr_direct(vha, QLA8044_CRB_DEV_STATE_INDEX,
1329 QLA8XXX_DEV_FAILED);
1330 return rval;
1331 }
1332
1333 /* For ISP8044, If IDC_CTRL GRACEFUL_RESET_BIT1 is set , reset it after
1334 * device goes to INIT state. */
1335 idc_ctrl = qla8044_rd_reg(ha, QLA8044_IDC_DRV_CTRL);
1336 if (idc_ctrl & GRACEFUL_RESET_BIT1) {
1337 qla8044_wr_reg(ha, QLA8044_IDC_DRV_CTRL,
1338 (idc_ctrl & ~GRACEFUL_RESET_BIT1));
1339 ha->fw_dumped = 0;
1340 }
1341
1342dev_ready:
1343 ql_log(ql_log_info, vha, 0xb0b4,
1344 "%s: HW State: READY\n", __func__);
1345 qla8044_wr_direct(vha, QLA8044_CRB_DEV_STATE_INDEX, QLA8XXX_DEV_READY);
1346
1347 return rval;
1348}
1349
1350/*-------------------------Reset Sequence Functions-----------------------*/
1351static void
1352qla8044_dump_reset_seq_hdr(struct scsi_qla_host *vha)
1353{
1354 u8 *phdr;
1355
1356 if (!vha->reset_tmplt.buff) {
1357 ql_log(ql_log_fatal, vha, 0xb0b5,
1358 "%s: Error Invalid reset_seq_template\n", __func__);
1359 return;
1360 }
1361
1362 phdr = vha->reset_tmplt.buff;
1363 ql_dbg(ql_dbg_p3p, vha, 0xb0b6,
1364 "Reset Template :\n\t0x%X 0x%X 0x%X 0x%X"
1365 "0x%X 0x%X 0x%X 0x%X 0x%X 0x%X\n"
1366 "\t0x%X 0x%X 0x%X 0x%X 0x%X 0x%X\n\n",
1367 *phdr, *(phdr+1), *(phdr+2), *(phdr+3), *(phdr+4),
1368 *(phdr+5), *(phdr+6), *(phdr+7), *(phdr + 8),
1369 *(phdr+9), *(phdr+10), *(phdr+11), *(phdr+12),
1370 *(phdr+13), *(phdr+14), *(phdr+15));
1371}
1372
1373/*
1374 * qla8044_reset_seq_checksum_test - Validate Reset Sequence template.
1375 *
1376 * @ha : Pointer to adapter structure
1377 *
1378 * Return Value - QLA_SUCCESS/QLA_FUNCTION_FAILED
1379 */
1380static int
1381qla8044_reset_seq_checksum_test(struct scsi_qla_host *vha)
1382{
1383 uint32_t sum = 0;
1384 uint16_t *buff = (uint16_t *)vha->reset_tmplt.buff;
1385 int u16_count = vha->reset_tmplt.hdr->size / sizeof(uint16_t);
1386
1387 while (u16_count-- > 0)
1388 sum += *buff++;
1389
1390 while (sum >> 16)
1391 sum = (sum & 0xFFFF) + (sum >> 16);
1392
1393 /* checksum of 0 indicates a valid template */
1394 if (~sum) {
1395 return QLA_SUCCESS;
1396 } else {
1397 ql_log(ql_log_fatal, vha, 0xb0b7,
1398 "%s: Reset seq checksum failed\n", __func__);
1399 return QLA_FUNCTION_FAILED;
1400 }
1401}
1402
1403/*
1404 * qla8044_read_reset_template - Read Reset Template from Flash, validate
1405 * the template and store offsets of stop/start/init offsets in ha->reset_tmplt.
1406 *
1407 * @ha : Pointer to adapter structure
1408 */
1409void
1410qla8044_read_reset_template(struct scsi_qla_host *vha)
1411{
1412 uint8_t *p_buff;
1413 uint32_t addr, tmplt_hdr_def_size, tmplt_hdr_size;
1414
1415 vha->reset_tmplt.seq_error = 0;
1416 vha->reset_tmplt.buff = vmalloc(QLA8044_RESTART_TEMPLATE_SIZE);
1417 if (vha->reset_tmplt.buff == NULL) {
1418 ql_log(ql_log_fatal, vha, 0xb0b8,
1419 "%s: Failed to allocate reset template resources\n",
1420 __func__);
1421 goto exit_read_reset_template;
1422 }
1423
1424 p_buff = vha->reset_tmplt.buff;
1425 addr = QLA8044_RESET_TEMPLATE_ADDR;
1426
1427 tmplt_hdr_def_size =
1428 sizeof(struct qla8044_reset_template_hdr) / sizeof(uint32_t);
1429
1430 ql_dbg(ql_dbg_p3p, vha, 0xb0b9,
1431 "%s: Read template hdr size %d from Flash\n",
1432 __func__, tmplt_hdr_def_size);
1433
1434 /* Copy template header from flash */
1435 if (qla8044_read_flash_data(vha, p_buff, addr, tmplt_hdr_def_size)) {
1436 ql_log(ql_log_fatal, vha, 0xb0ba,
1437 "%s: Failed to read reset template\n", __func__);
1438 goto exit_read_template_error;
1439 }
1440
1441 vha->reset_tmplt.hdr =
1442 (struct qla8044_reset_template_hdr *) vha->reset_tmplt.buff;
1443
1444 /* Validate the template header size and signature */
1445 tmplt_hdr_size = vha->reset_tmplt.hdr->hdr_size/sizeof(uint32_t);
1446 if ((tmplt_hdr_size != tmplt_hdr_def_size) ||
1447 (vha->reset_tmplt.hdr->signature != RESET_TMPLT_HDR_SIGNATURE)) {
1448 ql_log(ql_log_fatal, vha, 0xb0bb,
1449 "%s: Template Header size invalid %d "
1450 "tmplt_hdr_def_size %d!!!\n", __func__,
1451 tmplt_hdr_size, tmplt_hdr_def_size);
1452 goto exit_read_template_error;
1453 }
1454
1455 addr = QLA8044_RESET_TEMPLATE_ADDR + vha->reset_tmplt.hdr->hdr_size;
1456 p_buff = vha->reset_tmplt.buff + vha->reset_tmplt.hdr->hdr_size;
1457 tmplt_hdr_def_size = (vha->reset_tmplt.hdr->size -
1458 vha->reset_tmplt.hdr->hdr_size)/sizeof(uint32_t);
1459
1460 ql_dbg(ql_dbg_p3p, vha, 0xb0bc,
1461 "%s: Read rest of the template size %d\n",
1462 __func__, vha->reset_tmplt.hdr->size);
1463
1464 /* Copy rest of the template */
1465 if (qla8044_read_flash_data(vha, p_buff, addr, tmplt_hdr_def_size)) {
1466 ql_log(ql_log_fatal, vha, 0xb0bd,
1467 "%s: Failed to read reset tempelate\n", __func__);
1468 goto exit_read_template_error;
1469 }
1470
1471 /* Integrity check */
1472 if (qla8044_reset_seq_checksum_test(vha)) {
1473 ql_log(ql_log_fatal, vha, 0xb0be,
1474 "%s: Reset Seq checksum failed!\n", __func__);
1475 goto exit_read_template_error;
1476 }
1477
1478 ql_dbg(ql_dbg_p3p, vha, 0xb0bf,
1479 "%s: Reset Seq checksum passed! Get stop, "
1480 "start and init seq offsets\n", __func__);
1481
1482 /* Get STOP, START, INIT sequence offsets */
1483 vha->reset_tmplt.init_offset = vha->reset_tmplt.buff +
1484 vha->reset_tmplt.hdr->init_seq_offset;
1485
1486 vha->reset_tmplt.start_offset = vha->reset_tmplt.buff +
1487 vha->reset_tmplt.hdr->start_seq_offset;
1488
1489 vha->reset_tmplt.stop_offset = vha->reset_tmplt.buff +
1490 vha->reset_tmplt.hdr->hdr_size;
1491
1492 qla8044_dump_reset_seq_hdr(vha);
1493
1494 goto exit_read_reset_template;
1495
1496exit_read_template_error:
1497 vfree(vha->reset_tmplt.buff);
1498
1499exit_read_reset_template:
1500 return;
1501}
1502
1503void
1504qla8044_set_idc_dontreset(struct scsi_qla_host *vha)
1505{
1506 uint32_t idc_ctrl;
1507 struct qla_hw_data *ha = vha->hw;
1508
1509 idc_ctrl = qla8044_rd_reg(ha, QLA8044_IDC_DRV_CTRL);
1510 idc_ctrl |= DONTRESET_BIT0;
1511 ql_dbg(ql_dbg_p3p, vha, 0xb0c0,
1512 "%s: idc_ctrl = %d\n", __func__, idc_ctrl);
1513 qla8044_wr_reg(ha, QLA8044_IDC_DRV_CTRL, idc_ctrl);
1514}
1515
1516inline void
1517qla8044_set_rst_ready(struct scsi_qla_host *vha)
1518{
1519 uint32_t drv_state;
1520 struct qla_hw_data *ha = vha->hw;
1521
1522 drv_state = qla8044_rd_direct(vha, QLA8044_CRB_DRV_STATE_INDEX);
1523
1524 /* For ISP8044, drv_active register has 1 bit per function,
1525 * shift 1 by func_num to set a bit for the function.*/
1526 drv_state |= (1 << ha->portnum);
1527
1528 ql_log(ql_log_info, vha, 0xb0c1,
1529 "%s(%ld): drv_state: 0x%08x\n",
1530 __func__, vha->host_no, drv_state);
1531 qla8044_wr_direct(vha, QLA8044_CRB_DRV_STATE_INDEX, drv_state);
1532}
1533
1534/**
1535 * qla8044_need_reset_handler - Code to start reset sequence
1536 * @ha: pointer to adapter structure
1537 *
1538 * Note: IDC lock must be held upon entry
1539 **/
1540static void
1541qla8044_need_reset_handler(struct scsi_qla_host *vha)
1542{
1543 uint32_t dev_state = 0, drv_state, drv_active;
1544 unsigned long reset_timeout, dev_init_timeout;
1545 struct qla_hw_data *ha = vha->hw;
1546
1547 ql_log(ql_log_fatal, vha, 0xb0c2,
1548 "%s: Performing ISP error recovery\n", __func__);
1549
1550 if (vha->flags.online) {
1551 qla8044_idc_unlock(ha);
1552 qla2x00_abort_isp_cleanup(vha);
1553 ha->isp_ops->get_flash_version(vha, vha->req->ring);
1554 ha->isp_ops->nvram_config(vha);
1555 qla8044_idc_lock(ha);
1556 }
1557
Saurav Kashyap8f476112013-10-30 03:38:13 -04001558 drv_state = qla8044_rd_direct(vha,
1559 QLA8044_CRB_DRV_STATE_INDEX);
1560 drv_active = qla8044_rd_direct(vha,
1561 QLA8044_CRB_DRV_ACTIVE_INDEX);
1562
1563 ql_log(ql_log_info, vha, 0xb0c5,
1564 "%s(%ld): drv_state = 0x%x, drv_active = 0x%x\n",
1565 __func__, vha->host_no, drv_state, drv_active);
1566
Atul Deshmukh7ec0eff2013-08-27 01:37:28 -04001567 if (!ha->flags.nic_core_reset_owner) {
1568 ql_dbg(ql_dbg_p3p, vha, 0xb0c3,
1569 "%s(%ld): reset acknowledged\n",
1570 __func__, vha->host_no);
1571 qla8044_set_rst_ready(vha);
1572
1573 /* Non-reset owners ACK Reset and wait for device INIT state
1574 * as part of Reset Recovery by Reset Owner
1575 */
1576 dev_init_timeout = jiffies + (ha->fcoe_reset_timeout * HZ);
1577
1578 do {
1579 if (time_after_eq(jiffies, dev_init_timeout)) {
1580 ql_log(ql_log_info, vha, 0xb0c4,
Atul Deshmukh145083e2014-02-26 04:14:59 -05001581 "%s: Non Reset owner: Reset Ack Timeout!\n",
1582 __func__);
Atul Deshmukh7ec0eff2013-08-27 01:37:28 -04001583 break;
1584 }
1585
1586 qla8044_idc_unlock(ha);
1587 msleep(1000);
1588 qla8044_idc_lock(ha);
1589
1590 dev_state = qla8044_rd_direct(vha,
1591 QLA8044_CRB_DEV_STATE_INDEX);
Saurav Kashyap8f476112013-10-30 03:38:13 -04001592 } while (((drv_state & drv_active) != drv_active) &&
1593 (dev_state == QLA8XXX_DEV_NEED_RESET));
Atul Deshmukh7ec0eff2013-08-27 01:37:28 -04001594 } else {
1595 qla8044_set_rst_ready(vha);
1596
1597 /* wait for 10 seconds for reset ack from all functions */
1598 reset_timeout = jiffies + (ha->fcoe_reset_timeout * HZ);
1599
Saurav Kashyap8f476112013-10-30 03:38:13 -04001600 while ((drv_state & drv_active) != drv_active) {
Atul Deshmukh7ec0eff2013-08-27 01:37:28 -04001601 if (time_after_eq(jiffies, reset_timeout)) {
1602 ql_log(ql_log_info, vha, 0xb0c6,
1603 "%s: RESET TIMEOUT!"
1604 "drv_state: 0x%08x, drv_active: 0x%08x\n",
1605 QLA2XXX_DRIVER_NAME, drv_state, drv_active);
1606 break;
1607 }
1608
1609 qla8044_idc_unlock(ha);
1610 msleep(1000);
1611 qla8044_idc_lock(ha);
1612
1613 drv_state = qla8044_rd_direct(vha,
1614 QLA8044_CRB_DRV_STATE_INDEX);
1615 drv_active = qla8044_rd_direct(vha,
1616 QLA8044_CRB_DRV_ACTIVE_INDEX);
1617 }
1618
1619 if (drv_state != drv_active) {
1620 ql_log(ql_log_info, vha, 0xb0c7,
1621 "%s(%ld): Reset_owner turning off drv_active "
1622 "of non-acking function 0x%x\n", __func__,
1623 vha->host_no, (drv_active ^ drv_state));
1624 drv_active = drv_active & drv_state;
1625 qla8044_wr_direct(vha, QLA8044_CRB_DRV_ACTIVE_INDEX,
1626 drv_active);
1627 }
1628
1629 /*
1630 * Clear RESET OWNER, will be set at next reset
1631 * by next RST_OWNER
1632 */
1633 ha->flags.nic_core_reset_owner = 0;
1634
1635 /* Start Reset Recovery */
1636 qla8044_device_bootstrap(vha);
1637 }
1638}
1639
1640static void
1641qla8044_set_drv_active(struct scsi_qla_host *vha)
1642{
1643 uint32_t drv_active;
1644 struct qla_hw_data *ha = vha->hw;
1645
1646 drv_active = qla8044_rd_direct(vha, QLA8044_CRB_DRV_ACTIVE_INDEX);
1647
1648 /* For ISP8044, drv_active register has 1 bit per function,
1649 * shift 1 by func_num to set a bit for the function.*/
1650 drv_active |= (1 << ha->portnum);
1651
1652 ql_log(ql_log_info, vha, 0xb0c8,
1653 "%s(%ld): drv_active: 0x%08x\n",
1654 __func__, vha->host_no, drv_active);
1655 qla8044_wr_direct(vha, QLA8044_CRB_DRV_ACTIVE_INDEX, drv_active);
1656}
1657
1658static void
1659qla8044_clear_idc_dontreset(struct scsi_qla_host *vha)
1660{
1661 uint32_t idc_ctrl;
1662 struct qla_hw_data *ha = vha->hw;
1663
1664 idc_ctrl = qla8044_rd_reg(ha, QLA8044_IDC_DRV_CTRL);
1665 idc_ctrl &= ~DONTRESET_BIT0;
1666 ql_log(ql_log_info, vha, 0xb0c9,
1667 "%s: idc_ctrl = %d\n", __func__,
1668 idc_ctrl);
1669 qla8044_wr_reg(ha, QLA8044_IDC_DRV_CTRL, idc_ctrl);
1670}
1671
1672static int
1673qla8044_set_idc_ver(struct scsi_qla_host *vha)
1674{
1675 int idc_ver;
1676 uint32_t drv_active;
1677 int rval = QLA_SUCCESS;
1678 struct qla_hw_data *ha = vha->hw;
1679
1680 drv_active = qla8044_rd_direct(vha, QLA8044_CRB_DRV_ACTIVE_INDEX);
1681 if (drv_active == (1 << ha->portnum)) {
1682 idc_ver = qla8044_rd_direct(vha,
1683 QLA8044_CRB_DRV_IDC_VERSION_INDEX);
1684 idc_ver &= (~0xFF);
1685 idc_ver |= QLA8044_IDC_VER_MAJ_VALUE;
1686 qla8044_wr_direct(vha, QLA8044_CRB_DRV_IDC_VERSION_INDEX,
1687 idc_ver);
1688 ql_log(ql_log_info, vha, 0xb0ca,
1689 "%s: IDC version updated to %d\n",
1690 __func__, idc_ver);
1691 } else {
1692 idc_ver = qla8044_rd_direct(vha,
1693 QLA8044_CRB_DRV_IDC_VERSION_INDEX);
1694 idc_ver &= 0xFF;
1695 if (QLA8044_IDC_VER_MAJ_VALUE != idc_ver) {
1696 ql_log(ql_log_info, vha, 0xb0cb,
1697 "%s: qla4xxx driver IDC version %d "
1698 "is not compatible with IDC version %d "
1699 "of other drivers!\n",
1700 __func__, QLA8044_IDC_VER_MAJ_VALUE,
1701 idc_ver);
1702 rval = QLA_FUNCTION_FAILED;
1703 goto exit_set_idc_ver;
1704 }
1705 }
1706
1707 /* Update IDC_MINOR_VERSION */
1708 idc_ver = qla8044_rd_reg(ha, QLA8044_CRB_IDC_VER_MINOR);
1709 idc_ver &= ~(0x03 << (ha->portnum * 2));
1710 idc_ver |= (QLA8044_IDC_VER_MIN_VALUE << (ha->portnum * 2));
1711 qla8044_wr_reg(ha, QLA8044_CRB_IDC_VER_MINOR, idc_ver);
1712
1713exit_set_idc_ver:
1714 return rval;
1715}
1716
1717static int
1718qla8044_update_idc_reg(struct scsi_qla_host *vha)
1719{
1720 uint32_t drv_active;
1721 int rval = QLA_SUCCESS;
1722 struct qla_hw_data *ha = vha->hw;
1723
1724 if (vha->flags.init_done)
1725 goto exit_update_idc_reg;
1726
1727 qla8044_idc_lock(ha);
1728 qla8044_set_drv_active(vha);
1729
1730 drv_active = qla8044_rd_direct(vha,
1731 QLA8044_CRB_DRV_ACTIVE_INDEX);
1732
1733 /* If we are the first driver to load and
1734 * ql2xdontresethba is not set, clear IDC_CTRL BIT0. */
1735 if ((drv_active == (1 << ha->portnum)) && !ql2xdontresethba)
1736 qla8044_clear_idc_dontreset(vha);
1737
1738 rval = qla8044_set_idc_ver(vha);
1739 if (rval == QLA_FUNCTION_FAILED)
Saurav Kashyapc41afc92013-11-07 02:54:56 -05001740 qla8044_clear_drv_active(ha);
Atul Deshmukh7ec0eff2013-08-27 01:37:28 -04001741 qla8044_idc_unlock(ha);
1742
1743exit_update_idc_reg:
1744 return rval;
1745}
1746
1747/**
1748 * qla8044_need_qsnt_handler - Code to start qsnt
1749 * @ha: pointer to adapter structure
1750 **/
1751static void
1752qla8044_need_qsnt_handler(struct scsi_qla_host *vha)
1753{
1754 unsigned long qsnt_timeout;
1755 uint32_t drv_state, drv_active, dev_state;
1756 struct qla_hw_data *ha = vha->hw;
1757
1758 if (vha->flags.online)
1759 qla2x00_quiesce_io(vha);
1760 else
1761 return;
1762
1763 qla8044_set_qsnt_ready(vha);
1764
1765 /* Wait for 30 secs for all functions to ack qsnt mode */
1766 qsnt_timeout = jiffies + (QSNT_ACK_TOV * HZ);
1767 drv_state = qla8044_rd_direct(vha, QLA8044_CRB_DRV_STATE_INDEX);
1768 drv_active = qla8044_rd_direct(vha, QLA8044_CRB_DRV_ACTIVE_INDEX);
1769
1770 /* Shift drv_active by 1 to match drv_state. As quiescent ready bit
1771 position is at bit 1 and drv active is at bit 0 */
1772 drv_active = drv_active << 1;
1773
1774 while (drv_state != drv_active) {
1775 if (time_after_eq(jiffies, qsnt_timeout)) {
1776 /* Other functions did not ack, changing state to
1777 * DEV_READY
1778 */
1779 clear_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags);
1780 qla8044_wr_direct(vha, QLA8044_CRB_DEV_STATE_INDEX,
1781 QLA8XXX_DEV_READY);
1782 qla8044_clear_qsnt_ready(vha);
1783 ql_log(ql_log_info, vha, 0xb0cc,
1784 "Timeout waiting for quiescent ack!!!\n");
1785 return;
1786 }
1787 qla8044_idc_unlock(ha);
1788 msleep(1000);
1789 qla8044_idc_lock(ha);
1790
1791 drv_state = qla8044_rd_direct(vha,
1792 QLA8044_CRB_DRV_STATE_INDEX);
1793 drv_active = qla8044_rd_direct(vha,
1794 QLA8044_CRB_DRV_ACTIVE_INDEX);
1795 drv_active = drv_active << 1;
1796 }
1797
1798 /* All functions have Acked. Set quiescent state */
1799 dev_state = qla8044_rd_direct(vha, QLA8044_CRB_DEV_STATE_INDEX);
1800
1801 if (dev_state == QLA8XXX_DEV_NEED_QUIESCENT) {
1802 qla8044_wr_direct(vha, QLA8044_CRB_DEV_STATE_INDEX,
1803 QLA8XXX_DEV_QUIESCENT);
1804 ql_log(ql_log_info, vha, 0xb0cd,
1805 "%s: HW State: QUIESCENT\n", __func__);
1806 }
1807}
1808
1809/*
1810 * qla8044_device_state_handler - Adapter state machine
1811 * @ha: pointer to host adapter structure.
1812 *
1813 * Note: IDC lock must be UNLOCKED upon entry
1814 **/
1815int
1816qla8044_device_state_handler(struct scsi_qla_host *vha)
1817{
1818 uint32_t dev_state;
1819 int rval = QLA_SUCCESS;
1820 unsigned long dev_init_timeout;
1821 struct qla_hw_data *ha = vha->hw;
1822
1823 rval = qla8044_update_idc_reg(vha);
1824 if (rval == QLA_FUNCTION_FAILED)
1825 goto exit_error;
1826
1827 dev_state = qla8044_rd_direct(vha, QLA8044_CRB_DEV_STATE_INDEX);
1828 ql_dbg(ql_dbg_p3p, vha, 0xb0ce,
1829 "Device state is 0x%x = %s\n",
1830 dev_state, dev_state < MAX_STATES ?
1831 qdev_state(dev_state) : "Unknown");
1832
1833 /* wait for 30 seconds for device to go ready */
1834 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ);
1835
1836 qla8044_idc_lock(ha);
1837
1838 while (1) {
1839 if (time_after_eq(jiffies, dev_init_timeout)) {
1840 ql_log(ql_log_warn, vha, 0xb0cf,
1841 "%s: Device Init Failed 0x%x = %s\n",
1842 QLA2XXX_DRIVER_NAME, dev_state,
1843 dev_state < MAX_STATES ?
1844 qdev_state(dev_state) : "Unknown");
1845
1846 qla8044_wr_direct(vha, QLA8044_CRB_DEV_STATE_INDEX,
1847 QLA8XXX_DEV_FAILED);
1848 }
1849
1850 dev_state = qla8044_rd_direct(vha, QLA8044_CRB_DEV_STATE_INDEX);
1851 ql_log(ql_log_info, vha, 0xb0d0,
1852 "Device state is 0x%x = %s\n",
1853 dev_state, dev_state < MAX_STATES ?
1854 qdev_state(dev_state) : "Unknown");
1855
1856 /* NOTE: Make sure idc unlocked upon exit of switch statement */
1857 switch (dev_state) {
1858 case QLA8XXX_DEV_READY:
1859 ha->flags.nic_core_reset_owner = 0;
1860 goto exit;
1861 case QLA8XXX_DEV_COLD:
1862 rval = qla8044_device_bootstrap(vha);
Sawan Chandak37460782013-10-30 03:38:26 -04001863 break;
Atul Deshmukh7ec0eff2013-08-27 01:37:28 -04001864 case QLA8XXX_DEV_INITIALIZING:
1865 qla8044_idc_unlock(ha);
1866 msleep(1000);
1867 qla8044_idc_lock(ha);
1868 break;
1869 case QLA8XXX_DEV_NEED_RESET:
1870 /* For ISP8044, if NEED_RESET is set by any driver,
1871 * it should be honored, irrespective of IDC_CTRL
1872 * DONTRESET_BIT0 */
1873 qla8044_need_reset_handler(vha);
1874 break;
1875 case QLA8XXX_DEV_NEED_QUIESCENT:
1876 /* idc locked/unlocked in handler */
1877 qla8044_need_qsnt_handler(vha);
1878
1879 /* Reset the init timeout after qsnt handler */
1880 dev_init_timeout = jiffies +
1881 (ha->fcoe_reset_timeout * HZ);
1882 break;
1883 case QLA8XXX_DEV_QUIESCENT:
1884 ql_log(ql_log_info, vha, 0xb0d1,
1885 "HW State: QUIESCENT\n");
1886
1887 qla8044_idc_unlock(ha);
1888 msleep(1000);
1889 qla8044_idc_lock(ha);
1890
1891 /* Reset the init timeout after qsnt handler */
1892 dev_init_timeout = jiffies +
1893 (ha->fcoe_reset_timeout * HZ);
1894 break;
1895 case QLA8XXX_DEV_FAILED:
1896 ha->flags.nic_core_reset_owner = 0;
1897 qla8044_idc_unlock(ha);
1898 qla8xxx_dev_failed_handler(vha);
1899 rval = QLA_FUNCTION_FAILED;
1900 qla8044_idc_lock(ha);
1901 goto exit;
1902 default:
1903 qla8044_idc_unlock(ha);
1904 qla8xxx_dev_failed_handler(vha);
1905 rval = QLA_FUNCTION_FAILED;
1906 qla8044_idc_lock(ha);
1907 goto exit;
1908 }
1909 }
1910exit:
1911 qla8044_idc_unlock(ha);
1912
1913exit_error:
1914 return rval;
1915}
1916
1917/**
1918 * qla4_8xxx_check_temp - Check the ISP82XX temperature.
1919 * @ha: adapter block pointer.
1920 *
1921 * Note: The caller should not hold the idc lock.
1922 **/
1923static int
1924qla8044_check_temp(struct scsi_qla_host *vha)
1925{
1926 uint32_t temp, temp_state, temp_val;
1927 int status = QLA_SUCCESS;
1928
1929 temp = qla8044_rd_direct(vha, QLA8044_CRB_TEMP_STATE_INDEX);
1930 temp_state = qla82xx_get_temp_state(temp);
1931 temp_val = qla82xx_get_temp_val(temp);
1932
1933 if (temp_state == QLA82XX_TEMP_PANIC) {
1934 ql_log(ql_log_warn, vha, 0xb0d2,
1935 "Device temperature %d degrees C"
1936 " exceeds maximum allowed. Hardware has been shut"
1937 " down\n", temp_val);
1938 status = QLA_FUNCTION_FAILED;
1939 return status;
1940 } else if (temp_state == QLA82XX_TEMP_WARN) {
1941 ql_log(ql_log_warn, vha, 0xb0d3,
1942 "Device temperature %d"
1943 " degrees C exceeds operating range."
1944 " Immediate action needed.\n", temp_val);
1945 }
1946 return 0;
1947}
1948
Joe Carnuccio1ae47cf2013-08-27 01:37:36 -04001949int qla8044_read_temperature(scsi_qla_host_t *vha)
1950{
1951 uint32_t temp;
1952
1953 temp = qla8044_rd_direct(vha, QLA8044_CRB_TEMP_STATE_INDEX);
1954 return qla82xx_get_temp_val(temp);
1955}
1956
Atul Deshmukh7ec0eff2013-08-27 01:37:28 -04001957/**
1958 * qla8044_check_fw_alive - Check firmware health
1959 * @ha: Pointer to host adapter structure.
1960 *
1961 * Context: Interrupt
1962 **/
1963int
1964qla8044_check_fw_alive(struct scsi_qla_host *vha)
1965{
1966 uint32_t fw_heartbeat_counter;
1967 uint32_t halt_status1, halt_status2;
1968 int status = QLA_SUCCESS;
1969
1970 fw_heartbeat_counter = qla8044_rd_direct(vha,
1971 QLA8044_PEG_ALIVE_COUNTER_INDEX);
1972
1973 /* If PEG_ALIVE_COUNTER is 0xffffffff, AER/EEH is in progress, ignore */
1974 if (fw_heartbeat_counter == 0xffffffff) {
1975 ql_dbg(ql_dbg_p3p, vha, 0xb0d4,
1976 "scsi%ld: %s: Device in frozen "
1977 "state, QLA82XX_PEG_ALIVE_COUNTER is 0xffffffff\n",
1978 vha->host_no, __func__);
1979 return status;
1980 }
1981
1982 if (vha->fw_heartbeat_counter == fw_heartbeat_counter) {
1983 vha->seconds_since_last_heartbeat++;
1984 /* FW not alive after 2 seconds */
1985 if (vha->seconds_since_last_heartbeat == 2) {
1986 vha->seconds_since_last_heartbeat = 0;
1987 halt_status1 = qla8044_rd_direct(vha,
1988 QLA8044_PEG_HALT_STATUS1_INDEX);
1989 halt_status2 = qla8044_rd_direct(vha,
1990 QLA8044_PEG_HALT_STATUS2_INDEX);
1991
1992 ql_log(ql_log_info, vha, 0xb0d5,
1993 "scsi(%ld): %s, ISP8044 "
1994 "Dumping hw/fw registers:\n"
1995 " PEG_HALT_STATUS1: 0x%x, "
1996 "PEG_HALT_STATUS2: 0x%x,\n",
1997 vha->host_no, __func__, halt_status1,
1998 halt_status2);
1999 status = QLA_FUNCTION_FAILED;
2000 }
2001 } else
2002 vha->seconds_since_last_heartbeat = 0;
2003
2004 vha->fw_heartbeat_counter = fw_heartbeat_counter;
2005 return status;
2006}
2007
2008void
2009qla8044_watchdog(struct scsi_qla_host *vha)
2010{
2011 uint32_t dev_state, halt_status;
2012 int halt_status_unrecoverable = 0;
2013 struct qla_hw_data *ha = vha->hw;
2014
2015 /* don't poll if reset is going on or FW hang in quiescent state */
2016 if (!(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) ||
Atul Deshmukh7ec0eff2013-08-27 01:37:28 -04002017 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags))) {
2018 dev_state = qla8044_rd_direct(vha, QLA8044_CRB_DEV_STATE_INDEX);
2019
2020 if (qla8044_check_temp(vha)) {
2021 set_bit(ISP_UNRECOVERABLE, &vha->dpc_flags);
2022 ha->flags.isp82xx_fw_hung = 1;
2023 qla2xxx_wake_dpc(vha);
2024 } else if (dev_state == QLA8XXX_DEV_NEED_RESET &&
2025 !test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags)) {
2026 ql_log(ql_log_info, vha, 0xb0d6,
2027 "%s: HW State: NEED RESET!\n",
2028 __func__);
2029 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2030 qla2xxx_wake_dpc(vha);
2031 } else if (dev_state == QLA8XXX_DEV_NEED_QUIESCENT &&
2032 !test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags)) {
2033 ql_log(ql_log_info, vha, 0xb0d7,
2034 "%s: HW State: NEED QUIES detected!\n",
2035 __func__);
2036 set_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags);
2037 qla2xxx_wake_dpc(vha);
2038 } else {
2039 /* Check firmware health */
2040 if (qla8044_check_fw_alive(vha)) {
2041 halt_status = qla8044_rd_direct(vha,
2042 QLA8044_PEG_HALT_STATUS1_INDEX);
2043 if (halt_status &
2044 QLA8044_HALT_STATUS_FW_RESET) {
2045 ql_log(ql_log_fatal, vha,
2046 0xb0d8, "%s: Firmware "
2047 "error detected device "
2048 "is being reset\n",
2049 __func__);
2050 } else if (halt_status &
2051 QLA8044_HALT_STATUS_UNRECOVERABLE) {
2052 halt_status_unrecoverable = 1;
2053 }
2054
2055 /* Since we cannot change dev_state in interrupt
2056 * context, set appropriate DPC flag then wakeup
2057 * DPC */
2058 if (halt_status_unrecoverable) {
2059 set_bit(ISP_UNRECOVERABLE,
2060 &vha->dpc_flags);
2061 } else {
2062 if (dev_state ==
2063 QLA8XXX_DEV_QUIESCENT) {
2064 set_bit(FCOE_CTX_RESET_NEEDED,
2065 &vha->dpc_flags);
2066 ql_log(ql_log_info, vha, 0xb0d9,
2067 "%s: FW CONTEXT Reset "
2068 "needed!\n", __func__);
2069 } else {
2070 ql_log(ql_log_info, vha,
2071 0xb0da, "%s: "
2072 "detect abort needed\n",
2073 __func__);
2074 set_bit(ISP_ABORT_NEEDED,
2075 &vha->dpc_flags);
2076 qla82xx_clear_pending_mbx(vha);
2077 }
2078 }
2079 ha->flags.isp82xx_fw_hung = 1;
2080 ql_log(ql_log_warn, vha, 0xb10a,
2081 "Firmware hung.\n");
2082 qla2xxx_wake_dpc(vha);
2083 }
2084 }
2085
2086 }
2087}
2088
2089static int
2090qla8044_minidump_process_control(struct scsi_qla_host *vha,
2091 struct qla8044_minidump_entry_hdr *entry_hdr)
2092{
2093 struct qla8044_minidump_entry_crb *crb_entry;
2094 uint32_t read_value, opcode, poll_time, addr, index;
2095 uint32_t crb_addr, rval = QLA_SUCCESS;
2096 unsigned long wtime;
2097 struct qla8044_minidump_template_hdr *tmplt_hdr;
2098 int i;
2099 struct qla_hw_data *ha = vha->hw;
2100
2101 ql_dbg(ql_dbg_p3p, vha, 0xb0dd, "Entering fn: %s\n", __func__);
2102 tmplt_hdr = (struct qla8044_minidump_template_hdr *)
2103 ha->md_tmplt_hdr;
2104 crb_entry = (struct qla8044_minidump_entry_crb *)entry_hdr;
2105
2106 crb_addr = crb_entry->addr;
2107 for (i = 0; i < crb_entry->op_count; i++) {
2108 opcode = crb_entry->crb_ctrl.opcode;
2109
2110 if (opcode & QLA82XX_DBG_OPCODE_WR) {
2111 qla8044_wr_reg_indirect(vha, crb_addr,
2112 crb_entry->value_1);
2113 opcode &= ~QLA82XX_DBG_OPCODE_WR;
2114 }
2115
2116 if (opcode & QLA82XX_DBG_OPCODE_RW) {
2117 qla8044_rd_reg_indirect(vha, crb_addr, &read_value);
2118 qla8044_wr_reg_indirect(vha, crb_addr, read_value);
2119 opcode &= ~QLA82XX_DBG_OPCODE_RW;
2120 }
2121
2122 if (opcode & QLA82XX_DBG_OPCODE_AND) {
2123 qla8044_rd_reg_indirect(vha, crb_addr, &read_value);
2124 read_value &= crb_entry->value_2;
2125 opcode &= ~QLA82XX_DBG_OPCODE_AND;
2126 if (opcode & QLA82XX_DBG_OPCODE_OR) {
2127 read_value |= crb_entry->value_3;
2128 opcode &= ~QLA82XX_DBG_OPCODE_OR;
2129 }
2130 qla8044_wr_reg_indirect(vha, crb_addr, read_value);
2131 }
2132 if (opcode & QLA82XX_DBG_OPCODE_OR) {
2133 qla8044_rd_reg_indirect(vha, crb_addr, &read_value);
2134 read_value |= crb_entry->value_3;
2135 qla8044_wr_reg_indirect(vha, crb_addr, read_value);
2136 opcode &= ~QLA82XX_DBG_OPCODE_OR;
2137 }
2138 if (opcode & QLA82XX_DBG_OPCODE_POLL) {
2139 poll_time = crb_entry->crb_strd.poll_timeout;
2140 wtime = jiffies + poll_time;
2141 qla8044_rd_reg_indirect(vha, crb_addr, &read_value);
2142
2143 do {
2144 if ((read_value & crb_entry->value_2) ==
2145 crb_entry->value_1) {
2146 break;
2147 } else if (time_after_eq(jiffies, wtime)) {
2148 /* capturing dump failed */
2149 rval = QLA_FUNCTION_FAILED;
2150 break;
2151 } else {
2152 qla8044_rd_reg_indirect(vha,
2153 crb_addr, &read_value);
2154 }
2155 } while (1);
2156 opcode &= ~QLA82XX_DBG_OPCODE_POLL;
2157 }
2158
2159 if (opcode & QLA82XX_DBG_OPCODE_RDSTATE) {
2160 if (crb_entry->crb_strd.state_index_a) {
2161 index = crb_entry->crb_strd.state_index_a;
2162 addr = tmplt_hdr->saved_state_array[index];
2163 } else {
2164 addr = crb_addr;
2165 }
2166
2167 qla8044_rd_reg_indirect(vha, addr, &read_value);
2168 index = crb_entry->crb_ctrl.state_index_v;
2169 tmplt_hdr->saved_state_array[index] = read_value;
2170 opcode &= ~QLA82XX_DBG_OPCODE_RDSTATE;
2171 }
2172
2173 if (opcode & QLA82XX_DBG_OPCODE_WRSTATE) {
2174 if (crb_entry->crb_strd.state_index_a) {
2175 index = crb_entry->crb_strd.state_index_a;
2176 addr = tmplt_hdr->saved_state_array[index];
2177 } else {
2178 addr = crb_addr;
2179 }
2180
2181 if (crb_entry->crb_ctrl.state_index_v) {
2182 index = crb_entry->crb_ctrl.state_index_v;
2183 read_value =
2184 tmplt_hdr->saved_state_array[index];
2185 } else {
2186 read_value = crb_entry->value_1;
2187 }
2188
2189 qla8044_wr_reg_indirect(vha, addr, read_value);
2190 opcode &= ~QLA82XX_DBG_OPCODE_WRSTATE;
2191 }
2192
2193 if (opcode & QLA82XX_DBG_OPCODE_MDSTATE) {
2194 index = crb_entry->crb_ctrl.state_index_v;
2195 read_value = tmplt_hdr->saved_state_array[index];
2196 read_value <<= crb_entry->crb_ctrl.shl;
2197 read_value >>= crb_entry->crb_ctrl.shr;
2198 if (crb_entry->value_2)
2199 read_value &= crb_entry->value_2;
2200 read_value |= crb_entry->value_3;
2201 read_value += crb_entry->value_1;
2202 tmplt_hdr->saved_state_array[index] = read_value;
2203 opcode &= ~QLA82XX_DBG_OPCODE_MDSTATE;
2204 }
2205 crb_addr += crb_entry->crb_strd.addr_stride;
2206 }
2207 return rval;
2208}
2209
2210static void
2211qla8044_minidump_process_rdcrb(struct scsi_qla_host *vha,
2212 struct qla8044_minidump_entry_hdr *entry_hdr, uint32_t **d_ptr)
2213{
2214 uint32_t r_addr, r_stride, loop_cnt, i, r_value;
2215 struct qla8044_minidump_entry_crb *crb_hdr;
2216 uint32_t *data_ptr = *d_ptr;
2217
2218 ql_dbg(ql_dbg_p3p, vha, 0xb0de, "Entering fn: %s\n", __func__);
2219 crb_hdr = (struct qla8044_minidump_entry_crb *)entry_hdr;
2220 r_addr = crb_hdr->addr;
2221 r_stride = crb_hdr->crb_strd.addr_stride;
2222 loop_cnt = crb_hdr->op_count;
2223
2224 for (i = 0; i < loop_cnt; i++) {
2225 qla8044_rd_reg_indirect(vha, r_addr, &r_value);
2226 *data_ptr++ = r_addr;
2227 *data_ptr++ = r_value;
2228 r_addr += r_stride;
2229 }
2230 *d_ptr = data_ptr;
2231}
2232
2233static int
2234qla8044_minidump_process_rdmem(struct scsi_qla_host *vha,
2235 struct qla8044_minidump_entry_hdr *entry_hdr, uint32_t **d_ptr)
2236{
2237 uint32_t r_addr, r_value, r_data;
2238 uint32_t i, j, loop_cnt;
2239 struct qla8044_minidump_entry_rdmem *m_hdr;
2240 unsigned long flags;
2241 uint32_t *data_ptr = *d_ptr;
2242 struct qla_hw_data *ha = vha->hw;
2243
2244 ql_dbg(ql_dbg_p3p, vha, 0xb0df, "Entering fn: %s\n", __func__);
2245 m_hdr = (struct qla8044_minidump_entry_rdmem *)entry_hdr;
2246 r_addr = m_hdr->read_addr;
2247 loop_cnt = m_hdr->read_data_size/16;
2248
2249 ql_dbg(ql_dbg_p3p, vha, 0xb0f0,
2250 "[%s]: Read addr: 0x%x, read_data_size: 0x%x\n",
2251 __func__, r_addr, m_hdr->read_data_size);
2252
2253 if (r_addr & 0xf) {
2254 ql_dbg(ql_dbg_p3p, vha, 0xb0f1,
Masanari Iida8faaaea2014-01-07 21:58:06 +09002255 "[%s]: Read addr 0x%x not 16 bytes aligned\n",
Atul Deshmukh7ec0eff2013-08-27 01:37:28 -04002256 __func__, r_addr);
2257 return QLA_FUNCTION_FAILED;
2258 }
2259
2260 if (m_hdr->read_data_size % 16) {
2261 ql_dbg(ql_dbg_p3p, vha, 0xb0f2,
2262 "[%s]: Read data[0x%x] not multiple of 16 bytes\n",
2263 __func__, m_hdr->read_data_size);
2264 return QLA_FUNCTION_FAILED;
2265 }
2266
2267 ql_dbg(ql_dbg_p3p, vha, 0xb0f3,
2268 "[%s]: rdmem_addr: 0x%x, read_data_size: 0x%x, loop_cnt: 0x%x\n",
2269 __func__, r_addr, m_hdr->read_data_size, loop_cnt);
2270
2271 write_lock_irqsave(&ha->hw_lock, flags);
2272 for (i = 0; i < loop_cnt; i++) {
2273 qla8044_wr_reg_indirect(vha, MD_MIU_TEST_AGT_ADDR_LO, r_addr);
2274 r_value = 0;
2275 qla8044_wr_reg_indirect(vha, MD_MIU_TEST_AGT_ADDR_HI, r_value);
2276 r_value = MIU_TA_CTL_ENABLE;
2277 qla8044_wr_reg_indirect(vha, MD_MIU_TEST_AGT_CTRL, r_value);
2278 r_value = MIU_TA_CTL_START_ENABLE;
2279 qla8044_wr_reg_indirect(vha, MD_MIU_TEST_AGT_CTRL, r_value);
2280
2281 for (j = 0; j < MAX_CTL_CHECK; j++) {
2282 qla8044_rd_reg_indirect(vha, MD_MIU_TEST_AGT_CTRL,
2283 &r_value);
2284 if ((r_value & MIU_TA_CTL_BUSY) == 0)
2285 break;
2286 }
2287
2288 if (j >= MAX_CTL_CHECK) {
2289 printk_ratelimited(KERN_ERR
2290 "%s: failed to read through agent\n", __func__);
2291 write_unlock_irqrestore(&ha->hw_lock, flags);
2292 return QLA_SUCCESS;
2293 }
2294
2295 for (j = 0; j < 4; j++) {
2296 qla8044_rd_reg_indirect(vha, MD_MIU_TEST_AGT_RDDATA[j],
2297 &r_data);
2298 *data_ptr++ = r_data;
2299 }
2300
2301 r_addr += 16;
2302 }
2303 write_unlock_irqrestore(&ha->hw_lock, flags);
2304
2305 ql_dbg(ql_dbg_p3p, vha, 0xb0f4,
2306 "Leaving fn: %s datacount: 0x%x\n",
2307 __func__, (loop_cnt * 16));
2308
2309 *d_ptr = data_ptr;
2310 return QLA_SUCCESS;
2311}
2312
2313/* ISP83xx flash read for _RDROM _BOARD */
2314static uint32_t
2315qla8044_minidump_process_rdrom(struct scsi_qla_host *vha,
2316 struct qla8044_minidump_entry_hdr *entry_hdr, uint32_t **d_ptr)
2317{
2318 uint32_t fl_addr, u32_count, rval;
2319 struct qla8044_minidump_entry_rdrom *rom_hdr;
2320 uint32_t *data_ptr = *d_ptr;
2321
2322 rom_hdr = (struct qla8044_minidump_entry_rdrom *)entry_hdr;
2323 fl_addr = rom_hdr->read_addr;
2324 u32_count = (rom_hdr->read_data_size)/sizeof(uint32_t);
2325
2326 ql_dbg(ql_dbg_p3p, vha, 0xb0f5, "[%s]: fl_addr: 0x%x, count: 0x%x\n",
2327 __func__, fl_addr, u32_count);
2328
2329 rval = qla8044_lockless_flash_read_u32(vha, fl_addr,
2330 (u8 *)(data_ptr), u32_count);
2331
2332 if (rval != QLA_SUCCESS) {
2333 ql_log(ql_log_fatal, vha, 0xb0f6,
2334 "%s: Flash Read Error,Count=%d\n", __func__, u32_count);
2335 return QLA_FUNCTION_FAILED;
2336 } else {
2337 data_ptr += u32_count;
2338 *d_ptr = data_ptr;
2339 return QLA_SUCCESS;
2340 }
2341}
2342
2343static void
2344qla8044_mark_entry_skipped(struct scsi_qla_host *vha,
2345 struct qla8044_minidump_entry_hdr *entry_hdr, int index)
2346{
2347 entry_hdr->d_ctrl.driver_flags |= QLA82XX_DBG_SKIPPED_FLAG;
2348
2349 ql_log(ql_log_info, vha, 0xb0f7,
2350 "scsi(%ld): Skipping entry[%d]: ETYPE[0x%x]-ELEVEL[0x%x]\n",
2351 vha->host_no, index, entry_hdr->entry_type,
2352 entry_hdr->d_ctrl.entry_capture_mask);
2353}
2354
2355static int
2356qla8044_minidump_process_l2tag(struct scsi_qla_host *vha,
2357 struct qla8044_minidump_entry_hdr *entry_hdr,
2358 uint32_t **d_ptr)
2359{
2360 uint32_t addr, r_addr, c_addr, t_r_addr;
2361 uint32_t i, k, loop_count, t_value, r_cnt, r_value;
2362 unsigned long p_wait, w_time, p_mask;
2363 uint32_t c_value_w, c_value_r;
2364 struct qla8044_minidump_entry_cache *cache_hdr;
2365 int rval = QLA_FUNCTION_FAILED;
2366 uint32_t *data_ptr = *d_ptr;
2367
2368 ql_dbg(ql_dbg_p3p, vha, 0xb0f8, "Entering fn: %s\n", __func__);
2369 cache_hdr = (struct qla8044_minidump_entry_cache *)entry_hdr;
2370
2371 loop_count = cache_hdr->op_count;
2372 r_addr = cache_hdr->read_addr;
2373 c_addr = cache_hdr->control_addr;
2374 c_value_w = cache_hdr->cache_ctrl.write_value;
2375
2376 t_r_addr = cache_hdr->tag_reg_addr;
2377 t_value = cache_hdr->addr_ctrl.init_tag_value;
2378 r_cnt = cache_hdr->read_ctrl.read_addr_cnt;
2379 p_wait = cache_hdr->cache_ctrl.poll_wait;
2380 p_mask = cache_hdr->cache_ctrl.poll_mask;
2381
2382 for (i = 0; i < loop_count; i++) {
2383 qla8044_wr_reg_indirect(vha, t_r_addr, t_value);
2384 if (c_value_w)
2385 qla8044_wr_reg_indirect(vha, c_addr, c_value_w);
2386
2387 if (p_mask) {
2388 w_time = jiffies + p_wait;
2389 do {
2390 qla8044_rd_reg_indirect(vha, c_addr,
2391 &c_value_r);
2392 if ((c_value_r & p_mask) == 0) {
2393 break;
2394 } else if (time_after_eq(jiffies, w_time)) {
2395 /* capturing dump failed */
2396 return rval;
2397 }
2398 } while (1);
2399 }
2400
2401 addr = r_addr;
2402 for (k = 0; k < r_cnt; k++) {
2403 qla8044_rd_reg_indirect(vha, addr, &r_value);
2404 *data_ptr++ = r_value;
2405 addr += cache_hdr->read_ctrl.read_addr_stride;
2406 }
2407 t_value += cache_hdr->addr_ctrl.tag_value_stride;
2408 }
2409 *d_ptr = data_ptr;
2410 return QLA_SUCCESS;
2411}
2412
2413static void
2414qla8044_minidump_process_l1cache(struct scsi_qla_host *vha,
2415 struct qla8044_minidump_entry_hdr *entry_hdr, uint32_t **d_ptr)
2416{
2417 uint32_t addr, r_addr, c_addr, t_r_addr;
2418 uint32_t i, k, loop_count, t_value, r_cnt, r_value;
2419 uint32_t c_value_w;
2420 struct qla8044_minidump_entry_cache *cache_hdr;
2421 uint32_t *data_ptr = *d_ptr;
2422
2423 cache_hdr = (struct qla8044_minidump_entry_cache *)entry_hdr;
2424 loop_count = cache_hdr->op_count;
2425 r_addr = cache_hdr->read_addr;
2426 c_addr = cache_hdr->control_addr;
2427 c_value_w = cache_hdr->cache_ctrl.write_value;
2428
2429 t_r_addr = cache_hdr->tag_reg_addr;
2430 t_value = cache_hdr->addr_ctrl.init_tag_value;
2431 r_cnt = cache_hdr->read_ctrl.read_addr_cnt;
2432
2433 for (i = 0; i < loop_count; i++) {
2434 qla8044_wr_reg_indirect(vha, t_r_addr, t_value);
2435 qla8044_wr_reg_indirect(vha, c_addr, c_value_w);
2436 addr = r_addr;
2437 for (k = 0; k < r_cnt; k++) {
2438 qla8044_rd_reg_indirect(vha, addr, &r_value);
2439 *data_ptr++ = r_value;
2440 addr += cache_hdr->read_ctrl.read_addr_stride;
2441 }
2442 t_value += cache_hdr->addr_ctrl.tag_value_stride;
2443 }
2444 *d_ptr = data_ptr;
2445}
2446
2447static void
2448qla8044_minidump_process_rdocm(struct scsi_qla_host *vha,
2449 struct qla8044_minidump_entry_hdr *entry_hdr, uint32_t **d_ptr)
2450{
2451 uint32_t r_addr, r_stride, loop_cnt, i, r_value;
2452 struct qla8044_minidump_entry_rdocm *ocm_hdr;
2453 uint32_t *data_ptr = *d_ptr;
2454 struct qla_hw_data *ha = vha->hw;
2455
2456 ql_dbg(ql_dbg_p3p, vha, 0xb0f9, "Entering fn: %s\n", __func__);
2457
2458 ocm_hdr = (struct qla8044_minidump_entry_rdocm *)entry_hdr;
2459 r_addr = ocm_hdr->read_addr;
2460 r_stride = ocm_hdr->read_addr_stride;
2461 loop_cnt = ocm_hdr->op_count;
2462
2463 ql_dbg(ql_dbg_p3p, vha, 0xb0fa,
2464 "[%s]: r_addr: 0x%x, r_stride: 0x%x, loop_cnt: 0x%x\n",
2465 __func__, r_addr, r_stride, loop_cnt);
2466
2467 for (i = 0; i < loop_cnt; i++) {
2468 r_value = readl((void __iomem *)(r_addr + ha->nx_pcibase));
2469 *data_ptr++ = r_value;
2470 r_addr += r_stride;
2471 }
2472 ql_dbg(ql_dbg_p3p, vha, 0xb0fb, "Leaving fn: %s datacount: 0x%lx\n",
2473 __func__, (long unsigned int) (loop_cnt * sizeof(uint32_t)));
2474
2475 *d_ptr = data_ptr;
2476}
2477
2478static void
2479qla8044_minidump_process_rdmux(struct scsi_qla_host *vha,
2480 struct qla8044_minidump_entry_hdr *entry_hdr,
2481 uint32_t **d_ptr)
2482{
2483 uint32_t r_addr, s_stride, s_addr, s_value, loop_cnt, i, r_value;
2484 struct qla8044_minidump_entry_mux *mux_hdr;
2485 uint32_t *data_ptr = *d_ptr;
2486
2487 ql_dbg(ql_dbg_p3p, vha, 0xb0fc, "Entering fn: %s\n", __func__);
2488
2489 mux_hdr = (struct qla8044_minidump_entry_mux *)entry_hdr;
2490 r_addr = mux_hdr->read_addr;
2491 s_addr = mux_hdr->select_addr;
2492 s_stride = mux_hdr->select_value_stride;
2493 s_value = mux_hdr->select_value;
2494 loop_cnt = mux_hdr->op_count;
2495
2496 for (i = 0; i < loop_cnt; i++) {
2497 qla8044_wr_reg_indirect(vha, s_addr, s_value);
2498 qla8044_rd_reg_indirect(vha, r_addr, &r_value);
2499 *data_ptr++ = s_value;
2500 *data_ptr++ = r_value;
2501 s_value += s_stride;
2502 }
2503 *d_ptr = data_ptr;
2504}
2505
2506static void
2507qla8044_minidump_process_queue(struct scsi_qla_host *vha,
2508 struct qla8044_minidump_entry_hdr *entry_hdr,
2509 uint32_t **d_ptr)
2510{
2511 uint32_t s_addr, r_addr;
2512 uint32_t r_stride, r_value, r_cnt, qid = 0;
2513 uint32_t i, k, loop_cnt;
2514 struct qla8044_minidump_entry_queue *q_hdr;
2515 uint32_t *data_ptr = *d_ptr;
2516
2517 ql_dbg(ql_dbg_p3p, vha, 0xb0fd, "Entering fn: %s\n", __func__);
2518 q_hdr = (struct qla8044_minidump_entry_queue *)entry_hdr;
2519 s_addr = q_hdr->select_addr;
2520 r_cnt = q_hdr->rd_strd.read_addr_cnt;
2521 r_stride = q_hdr->rd_strd.read_addr_stride;
2522 loop_cnt = q_hdr->op_count;
2523
2524 for (i = 0; i < loop_cnt; i++) {
2525 qla8044_wr_reg_indirect(vha, s_addr, qid);
2526 r_addr = q_hdr->read_addr;
2527 for (k = 0; k < r_cnt; k++) {
2528 qla8044_rd_reg_indirect(vha, r_addr, &r_value);
2529 *data_ptr++ = r_value;
2530 r_addr += r_stride;
2531 }
2532 qid += q_hdr->q_strd.queue_id_stride;
2533 }
2534 *d_ptr = data_ptr;
2535}
2536
2537/* ISP83xx functions to process new minidump entries... */
2538static uint32_t
2539qla8044_minidump_process_pollrd(struct scsi_qla_host *vha,
2540 struct qla8044_minidump_entry_hdr *entry_hdr,
2541 uint32_t **d_ptr)
2542{
2543 uint32_t r_addr, s_addr, s_value, r_value, poll_wait, poll_mask;
2544 uint16_t s_stride, i;
2545 struct qla8044_minidump_entry_pollrd *pollrd_hdr;
2546 uint32_t *data_ptr = *d_ptr;
2547
2548 pollrd_hdr = (struct qla8044_minidump_entry_pollrd *) entry_hdr;
2549 s_addr = pollrd_hdr->select_addr;
2550 r_addr = pollrd_hdr->read_addr;
2551 s_value = pollrd_hdr->select_value;
2552 s_stride = pollrd_hdr->select_value_stride;
2553
2554 poll_wait = pollrd_hdr->poll_wait;
2555 poll_mask = pollrd_hdr->poll_mask;
2556
2557 for (i = 0; i < pollrd_hdr->op_count; i++) {
2558 qla8044_wr_reg_indirect(vha, s_addr, s_value);
2559 poll_wait = pollrd_hdr->poll_wait;
2560 while (1) {
2561 qla8044_rd_reg_indirect(vha, s_addr, &r_value);
2562 if ((r_value & poll_mask) != 0) {
2563 break;
2564 } else {
2565 usleep_range(1000, 1100);
2566 if (--poll_wait == 0) {
2567 ql_log(ql_log_fatal, vha, 0xb0fe,
2568 "%s: TIMEOUT\n", __func__);
2569 goto error;
2570 }
2571 }
2572 }
2573 qla8044_rd_reg_indirect(vha, r_addr, &r_value);
2574 *data_ptr++ = s_value;
2575 *data_ptr++ = r_value;
2576
2577 s_value += s_stride;
2578 }
2579 *d_ptr = data_ptr;
2580 return QLA_SUCCESS;
2581
2582error:
2583 return QLA_FUNCTION_FAILED;
2584}
2585
2586static void
2587qla8044_minidump_process_rdmux2(struct scsi_qla_host *vha,
2588 struct qla8044_minidump_entry_hdr *entry_hdr, uint32_t **d_ptr)
2589{
2590 uint32_t sel_val1, sel_val2, t_sel_val, data, i;
2591 uint32_t sel_addr1, sel_addr2, sel_val_mask, read_addr;
2592 struct qla8044_minidump_entry_rdmux2 *rdmux2_hdr;
2593 uint32_t *data_ptr = *d_ptr;
2594
2595 rdmux2_hdr = (struct qla8044_minidump_entry_rdmux2 *) entry_hdr;
2596 sel_val1 = rdmux2_hdr->select_value_1;
2597 sel_val2 = rdmux2_hdr->select_value_2;
2598 sel_addr1 = rdmux2_hdr->select_addr_1;
2599 sel_addr2 = rdmux2_hdr->select_addr_2;
2600 sel_val_mask = rdmux2_hdr->select_value_mask;
2601 read_addr = rdmux2_hdr->read_addr;
2602
2603 for (i = 0; i < rdmux2_hdr->op_count; i++) {
2604 qla8044_wr_reg_indirect(vha, sel_addr1, sel_val1);
2605 t_sel_val = sel_val1 & sel_val_mask;
2606 *data_ptr++ = t_sel_val;
2607
2608 qla8044_wr_reg_indirect(vha, sel_addr2, t_sel_val);
2609 qla8044_rd_reg_indirect(vha, read_addr, &data);
2610
2611 *data_ptr++ = data;
2612
2613 qla8044_wr_reg_indirect(vha, sel_addr1, sel_val2);
2614 t_sel_val = sel_val2 & sel_val_mask;
2615 *data_ptr++ = t_sel_val;
2616
2617 qla8044_wr_reg_indirect(vha, sel_addr2, t_sel_val);
2618 qla8044_rd_reg_indirect(vha, read_addr, &data);
2619
2620 *data_ptr++ = data;
2621
2622 sel_val1 += rdmux2_hdr->select_value_stride;
2623 sel_val2 += rdmux2_hdr->select_value_stride;
2624 }
2625
2626 *d_ptr = data_ptr;
2627}
2628
2629static uint32_t
2630qla8044_minidump_process_pollrdmwr(struct scsi_qla_host *vha,
2631 struct qla8044_minidump_entry_hdr *entry_hdr,
2632 uint32_t **d_ptr)
2633{
2634 uint32_t poll_wait, poll_mask, r_value, data;
2635 uint32_t addr_1, addr_2, value_1, value_2;
2636 struct qla8044_minidump_entry_pollrdmwr *poll_hdr;
2637 uint32_t *data_ptr = *d_ptr;
2638
2639 poll_hdr = (struct qla8044_minidump_entry_pollrdmwr *) entry_hdr;
2640 addr_1 = poll_hdr->addr_1;
2641 addr_2 = poll_hdr->addr_2;
2642 value_1 = poll_hdr->value_1;
2643 value_2 = poll_hdr->value_2;
2644 poll_mask = poll_hdr->poll_mask;
2645
2646 qla8044_wr_reg_indirect(vha, addr_1, value_1);
2647
2648 poll_wait = poll_hdr->poll_wait;
2649 while (1) {
2650 qla8044_rd_reg_indirect(vha, addr_1, &r_value);
2651
2652 if ((r_value & poll_mask) != 0) {
2653 break;
2654 } else {
2655 usleep_range(1000, 1100);
2656 if (--poll_wait == 0) {
2657 ql_log(ql_log_fatal, vha, 0xb0ff,
2658 "%s: TIMEOUT\n", __func__);
2659 goto error;
2660 }
2661 }
2662 }
2663
2664 qla8044_rd_reg_indirect(vha, addr_2, &data);
2665 data &= poll_hdr->modify_mask;
2666 qla8044_wr_reg_indirect(vha, addr_2, data);
2667 qla8044_wr_reg_indirect(vha, addr_1, value_2);
2668
2669 poll_wait = poll_hdr->poll_wait;
2670 while (1) {
2671 qla8044_rd_reg_indirect(vha, addr_1, &r_value);
2672
2673 if ((r_value & poll_mask) != 0) {
2674 break;
2675 } else {
2676 usleep_range(1000, 1100);
2677 if (--poll_wait == 0) {
2678 ql_log(ql_log_fatal, vha, 0xb100,
2679 "%s: TIMEOUT2\n", __func__);
2680 goto error;
2681 }
2682 }
2683 }
2684
2685 *data_ptr++ = addr_2;
2686 *data_ptr++ = data;
2687
2688 *d_ptr = data_ptr;
2689
2690 return QLA_SUCCESS;
2691
2692error:
2693 return QLA_FUNCTION_FAILED;
2694}
2695
2696#define ISP8044_PEX_DMA_ENGINE_INDEX 8
2697#define ISP8044_PEX_DMA_BASE_ADDRESS 0x77320000
2698#define ISP8044_PEX_DMA_NUM_OFFSET 0x10000
2699#define ISP8044_PEX_DMA_CMD_ADDR_LOW 0x0
2700#define ISP8044_PEX_DMA_CMD_ADDR_HIGH 0x04
2701#define ISP8044_PEX_DMA_CMD_STS_AND_CNTRL 0x08
2702
2703#define ISP8044_PEX_DMA_READ_SIZE (16 * 1024)
2704#define ISP8044_PEX_DMA_MAX_WAIT (100 * 100) /* Max wait of 100 msecs */
2705
2706static int
2707qla8044_check_dma_engine_state(struct scsi_qla_host *vha)
2708{
2709 struct qla_hw_data *ha = vha->hw;
2710 int rval = QLA_SUCCESS;
2711 uint32_t dma_eng_num = 0, cmd_sts_and_cntrl = 0;
2712 uint64_t dma_base_addr = 0;
2713 struct qla8044_minidump_template_hdr *tmplt_hdr = NULL;
2714
2715 tmplt_hdr = ha->md_tmplt_hdr;
2716 dma_eng_num =
2717 tmplt_hdr->saved_state_array[ISP8044_PEX_DMA_ENGINE_INDEX];
2718 dma_base_addr = ISP8044_PEX_DMA_BASE_ADDRESS +
2719 (dma_eng_num * ISP8044_PEX_DMA_NUM_OFFSET);
2720
2721 /* Read the pex-dma's command-status-and-control register. */
2722 rval = qla8044_rd_reg_indirect(vha,
2723 (dma_base_addr + ISP8044_PEX_DMA_CMD_STS_AND_CNTRL),
2724 &cmd_sts_and_cntrl);
2725 if (rval)
2726 return QLA_FUNCTION_FAILED;
2727
2728 /* Check if requested pex-dma engine is available. */
2729 if (cmd_sts_and_cntrl & BIT_31)
2730 return QLA_SUCCESS;
2731
2732 return QLA_FUNCTION_FAILED;
2733}
2734
2735static int
2736qla8044_start_pex_dma(struct scsi_qla_host *vha,
2737 struct qla8044_minidump_entry_rdmem_pex_dma *m_hdr)
2738{
2739 struct qla_hw_data *ha = vha->hw;
2740 int rval = QLA_SUCCESS, wait = 0;
2741 uint32_t dma_eng_num = 0, cmd_sts_and_cntrl = 0;
2742 uint64_t dma_base_addr = 0;
2743 struct qla8044_minidump_template_hdr *tmplt_hdr = NULL;
2744
2745 tmplt_hdr = ha->md_tmplt_hdr;
2746 dma_eng_num =
2747 tmplt_hdr->saved_state_array[ISP8044_PEX_DMA_ENGINE_INDEX];
2748 dma_base_addr = ISP8044_PEX_DMA_BASE_ADDRESS +
2749 (dma_eng_num * ISP8044_PEX_DMA_NUM_OFFSET);
2750
2751 rval = qla8044_wr_reg_indirect(vha,
2752 dma_base_addr + ISP8044_PEX_DMA_CMD_ADDR_LOW,
2753 m_hdr->desc_card_addr);
2754 if (rval)
2755 goto error_exit;
2756
2757 rval = qla8044_wr_reg_indirect(vha,
2758 dma_base_addr + ISP8044_PEX_DMA_CMD_ADDR_HIGH, 0);
2759 if (rval)
2760 goto error_exit;
2761
2762 rval = qla8044_wr_reg_indirect(vha,
2763 dma_base_addr + ISP8044_PEX_DMA_CMD_STS_AND_CNTRL,
2764 m_hdr->start_dma_cmd);
2765 if (rval)
2766 goto error_exit;
2767
2768 /* Wait for dma operation to complete. */
2769 for (wait = 0; wait < ISP8044_PEX_DMA_MAX_WAIT; wait++) {
2770 rval = qla8044_rd_reg_indirect(vha,
2771 (dma_base_addr + ISP8044_PEX_DMA_CMD_STS_AND_CNTRL),
2772 &cmd_sts_and_cntrl);
2773 if (rval)
2774 goto error_exit;
2775
2776 if ((cmd_sts_and_cntrl & BIT_1) == 0)
2777 break;
2778
2779 udelay(10);
2780 }
2781
2782 /* Wait a max of 100 ms, otherwise fallback to rdmem entry read */
2783 if (wait >= ISP8044_PEX_DMA_MAX_WAIT) {
2784 rval = QLA_FUNCTION_FAILED;
2785 goto error_exit;
2786 }
2787
2788error_exit:
2789 return rval;
2790}
2791
2792static int
2793qla8044_minidump_pex_dma_read(struct scsi_qla_host *vha,
2794 struct qla8044_minidump_entry_hdr *entry_hdr, uint32_t **d_ptr)
2795{
2796 struct qla_hw_data *ha = vha->hw;
2797 int rval = QLA_SUCCESS;
2798 struct qla8044_minidump_entry_rdmem_pex_dma *m_hdr = NULL;
2799 uint32_t chunk_size, read_size;
2800 uint8_t *data_ptr = (uint8_t *)*d_ptr;
2801 void *rdmem_buffer = NULL;
2802 dma_addr_t rdmem_dma;
2803 struct qla8044_pex_dma_descriptor dma_desc;
2804
2805 rval = qla8044_check_dma_engine_state(vha);
2806 if (rval != QLA_SUCCESS) {
2807 ql_dbg(ql_dbg_p3p, vha, 0xb147,
2808 "DMA engine not available. Fallback to rdmem-read.\n");
2809 return QLA_FUNCTION_FAILED;
2810 }
2811
2812 m_hdr = (void *)entry_hdr;
2813
2814 rdmem_buffer = dma_alloc_coherent(&ha->pdev->dev,
2815 ISP8044_PEX_DMA_READ_SIZE, &rdmem_dma, GFP_KERNEL);
2816 if (!rdmem_buffer) {
2817 ql_dbg(ql_dbg_p3p, vha, 0xb148,
2818 "Unable to allocate rdmem dma buffer\n");
2819 return QLA_FUNCTION_FAILED;
2820 }
2821
2822 /* Prepare pex-dma descriptor to be written to MS memory. */
2823 /* dma-desc-cmd layout:
2824 * 0-3: dma-desc-cmd 0-3
2825 * 4-7: pcid function number
2826 * 8-15: dma-desc-cmd 8-15
2827 * dma_bus_addr: dma buffer address
2828 * cmd.read_data_size: amount of data-chunk to be read.
2829 */
2830 dma_desc.cmd.dma_desc_cmd = (m_hdr->dma_desc_cmd & 0xff0f);
2831 dma_desc.cmd.dma_desc_cmd |=
2832 ((PCI_FUNC(ha->pdev->devfn) & 0xf) << 0x4);
2833
2834 dma_desc.dma_bus_addr = rdmem_dma;
2835 dma_desc.cmd.read_data_size = chunk_size = ISP8044_PEX_DMA_READ_SIZE;
2836 read_size = 0;
2837
2838 /*
2839 * Perform rdmem operation using pex-dma.
2840 * Prepare dma in chunks of ISP8044_PEX_DMA_READ_SIZE.
2841 */
2842 while (read_size < m_hdr->read_data_size) {
2843 if (m_hdr->read_data_size - read_size <
2844 ISP8044_PEX_DMA_READ_SIZE) {
2845 chunk_size = (m_hdr->read_data_size - read_size);
2846 dma_desc.cmd.read_data_size = chunk_size;
2847 }
2848
2849 dma_desc.src_addr = m_hdr->read_addr + read_size;
2850
2851 /* Prepare: Write pex-dma descriptor to MS memory. */
2852 rval = qla8044_ms_mem_write_128b(vha,
2853 m_hdr->desc_card_addr, (void *)&dma_desc,
2854 (sizeof(struct qla8044_pex_dma_descriptor)/16));
2855 if (rval) {
2856 ql_log(ql_log_warn, vha, 0xb14a,
2857 "%s: Error writing rdmem-dma-init to MS !!!\n",
2858 __func__);
2859 goto error_exit;
2860 }
2861 ql_dbg(ql_dbg_p3p, vha, 0xb14b,
2862 "%s: Dma-descriptor: Instruct for rdmem dma "
2863 "(chunk_size 0x%x).\n", __func__, chunk_size);
2864
2865 /* Execute: Start pex-dma operation. */
2866 rval = qla8044_start_pex_dma(vha, m_hdr);
2867 if (rval)
2868 goto error_exit;
2869
2870 memcpy(data_ptr, rdmem_buffer, chunk_size);
2871 data_ptr += chunk_size;
2872 read_size += chunk_size;
2873 }
2874
2875 *d_ptr = (void *)data_ptr;
2876
2877error_exit:
2878 if (rdmem_buffer)
2879 dma_free_coherent(&ha->pdev->dev, ISP8044_PEX_DMA_READ_SIZE,
2880 rdmem_buffer, rdmem_dma);
2881
2882 return rval;
2883}
2884
2885/*
2886 *
2887 * qla8044_collect_md_data - Retrieve firmware minidump data.
2888 * @ha: pointer to adapter structure
2889 **/
2890int
2891qla8044_collect_md_data(struct scsi_qla_host *vha)
2892{
2893 int num_entry_hdr = 0;
2894 struct qla8044_minidump_entry_hdr *entry_hdr;
2895 struct qla8044_minidump_template_hdr *tmplt_hdr;
2896 uint32_t *data_ptr;
2897 uint32_t data_collected = 0, f_capture_mask;
2898 int i, rval = QLA_FUNCTION_FAILED;
2899 uint64_t now;
2900 uint32_t timestamp, idc_control;
2901 struct qla_hw_data *ha = vha->hw;
2902
2903 if (!ha->md_dump) {
2904 ql_log(ql_log_info, vha, 0xb101,
2905 "%s(%ld) No buffer to dump\n",
2906 __func__, vha->host_no);
2907 return rval;
2908 }
2909
2910 if (ha->fw_dumped) {
2911 ql_log(ql_log_warn, vha, 0xb10d,
2912 "Firmware has been previously dumped (%p) "
2913 "-- ignoring request.\n", ha->fw_dump);
2914 goto md_failed;
2915 }
2916
2917 ha->fw_dumped = 0;
2918
2919 if (!ha->md_tmplt_hdr || !ha->md_dump) {
2920 ql_log(ql_log_warn, vha, 0xb10e,
2921 "Memory not allocated for minidump capture\n");
2922 goto md_failed;
2923 }
2924
2925 qla8044_idc_lock(ha);
2926 idc_control = qla8044_rd_reg(ha, QLA8044_IDC_DRV_CTRL);
2927 if (idc_control & GRACEFUL_RESET_BIT1) {
2928 ql_log(ql_log_warn, vha, 0xb112,
2929 "Forced reset from application, "
2930 "ignore minidump capture\n");
2931 qla8044_wr_reg(ha, QLA8044_IDC_DRV_CTRL,
2932 (idc_control & ~GRACEFUL_RESET_BIT1));
2933 qla8044_idc_unlock(ha);
2934
2935 goto md_failed;
2936 }
2937 qla8044_idc_unlock(ha);
2938
2939 if (qla82xx_validate_template_chksum(vha)) {
2940 ql_log(ql_log_info, vha, 0xb109,
2941 "Template checksum validation error\n");
2942 goto md_failed;
2943 }
2944
2945 tmplt_hdr = (struct qla8044_minidump_template_hdr *)
2946 ha->md_tmplt_hdr;
2947 data_ptr = (uint32_t *)((uint8_t *)ha->md_dump);
2948 num_entry_hdr = tmplt_hdr->num_of_entries;
2949
2950 ql_dbg(ql_dbg_p3p, vha, 0xb11a,
2951 "Capture Mask obtained: 0x%x\n", tmplt_hdr->capture_debug_level);
2952
2953 f_capture_mask = tmplt_hdr->capture_debug_level & 0xFF;
2954
2955 /* Validate whether required debug level is set */
2956 if ((f_capture_mask & 0x3) != 0x3) {
2957 ql_log(ql_log_warn, vha, 0xb10f,
2958 "Minimum required capture mask[0x%x] level not set\n",
2959 f_capture_mask);
2960
2961 }
2962 tmplt_hdr->driver_capture_mask = ql2xmdcapmask;
2963 ql_log(ql_log_info, vha, 0xb102,
2964 "[%s]: starting data ptr: %p\n",
2965 __func__, data_ptr);
2966 ql_log(ql_log_info, vha, 0xb10b,
2967 "[%s]: no of entry headers in Template: 0x%x\n",
2968 __func__, num_entry_hdr);
2969 ql_log(ql_log_info, vha, 0xb10c,
2970 "[%s]: Total_data_size 0x%x, %d obtained\n",
2971 __func__, ha->md_dump_size, ha->md_dump_size);
2972
2973 /* Update current timestamp before taking dump */
2974 now = get_jiffies_64();
2975 timestamp = (u32)(jiffies_to_msecs(now) / 1000);
2976 tmplt_hdr->driver_timestamp = timestamp;
2977
2978 entry_hdr = (struct qla8044_minidump_entry_hdr *)
2979 (((uint8_t *)ha->md_tmplt_hdr) + tmplt_hdr->first_entry_offset);
2980 tmplt_hdr->saved_state_array[QLA8044_SS_OCM_WNDREG_INDEX] =
2981 tmplt_hdr->ocm_window_reg[ha->portnum];
2982
2983 /* Walk through the entry headers - validate/perform required action */
2984 for (i = 0; i < num_entry_hdr; i++) {
2985 if (data_collected > ha->md_dump_size) {
2986 ql_log(ql_log_info, vha, 0xb103,
2987 "Data collected: [0x%x], "
2988 "Total Dump size: [0x%x]\n",
2989 data_collected, ha->md_dump_size);
2990 return rval;
2991 }
2992
2993 if (!(entry_hdr->d_ctrl.entry_capture_mask &
2994 ql2xmdcapmask)) {
2995 entry_hdr->d_ctrl.driver_flags |=
2996 QLA82XX_DBG_SKIPPED_FLAG;
2997 goto skip_nxt_entry;
2998 }
2999
3000 ql_dbg(ql_dbg_p3p, vha, 0xb104,
3001 "Data collected: [0x%x], Dump size left:[0x%x]\n",
3002 data_collected,
3003 (ha->md_dump_size - data_collected));
3004
3005 /* Decode the entry type and take required action to capture
3006 * debug data
3007 */
3008 switch (entry_hdr->entry_type) {
3009 case QLA82XX_RDEND:
3010 qla8044_mark_entry_skipped(vha, entry_hdr, i);
3011 break;
3012 case QLA82XX_CNTRL:
3013 rval = qla8044_minidump_process_control(vha,
3014 entry_hdr);
3015 if (rval != QLA_SUCCESS) {
3016 qla8044_mark_entry_skipped(vha, entry_hdr, i);
3017 goto md_failed;
3018 }
3019 break;
3020 case QLA82XX_RDCRB:
3021 qla8044_minidump_process_rdcrb(vha,
3022 entry_hdr, &data_ptr);
3023 break;
3024 case QLA82XX_RDMEM:
3025 rval = qla8044_minidump_pex_dma_read(vha,
3026 entry_hdr, &data_ptr);
3027 if (rval != QLA_SUCCESS) {
3028 rval = qla8044_minidump_process_rdmem(vha,
3029 entry_hdr, &data_ptr);
3030 if (rval != QLA_SUCCESS) {
3031 qla8044_mark_entry_skipped(vha,
3032 entry_hdr, i);
3033 goto md_failed;
3034 }
3035 }
3036 break;
3037 case QLA82XX_BOARD:
3038 case QLA82XX_RDROM:
3039 rval = qla8044_minidump_process_rdrom(vha,
3040 entry_hdr, &data_ptr);
3041 if (rval != QLA_SUCCESS) {
3042 qla8044_mark_entry_skipped(vha,
3043 entry_hdr, i);
3044 }
3045 break;
3046 case QLA82XX_L2DTG:
3047 case QLA82XX_L2ITG:
3048 case QLA82XX_L2DAT:
3049 case QLA82XX_L2INS:
3050 rval = qla8044_minidump_process_l2tag(vha,
3051 entry_hdr, &data_ptr);
3052 if (rval != QLA_SUCCESS) {
3053 qla8044_mark_entry_skipped(vha, entry_hdr, i);
3054 goto md_failed;
3055 }
3056 break;
3057 case QLA8044_L1DTG:
3058 case QLA8044_L1ITG:
3059 case QLA82XX_L1DAT:
3060 case QLA82XX_L1INS:
3061 qla8044_minidump_process_l1cache(vha,
3062 entry_hdr, &data_ptr);
3063 break;
3064 case QLA82XX_RDOCM:
3065 qla8044_minidump_process_rdocm(vha,
3066 entry_hdr, &data_ptr);
3067 break;
3068 case QLA82XX_RDMUX:
3069 qla8044_minidump_process_rdmux(vha,
3070 entry_hdr, &data_ptr);
3071 break;
3072 case QLA82XX_QUEUE:
3073 qla8044_minidump_process_queue(vha,
3074 entry_hdr, &data_ptr);
3075 break;
3076 case QLA8044_POLLRD:
3077 rval = qla8044_minidump_process_pollrd(vha,
3078 entry_hdr, &data_ptr);
3079 if (rval != QLA_SUCCESS)
3080 qla8044_mark_entry_skipped(vha, entry_hdr, i);
3081 break;
3082 case QLA8044_RDMUX2:
3083 qla8044_minidump_process_rdmux2(vha,
3084 entry_hdr, &data_ptr);
3085 break;
3086 case QLA8044_POLLRDMWR:
3087 rval = qla8044_minidump_process_pollrdmwr(vha,
3088 entry_hdr, &data_ptr);
3089 if (rval != QLA_SUCCESS)
3090 qla8044_mark_entry_skipped(vha, entry_hdr, i);
3091 break;
3092 case QLA82XX_RDNOP:
3093 default:
3094 qla8044_mark_entry_skipped(vha, entry_hdr, i);
3095 break;
3096 }
3097
3098 data_collected = (uint8_t *)data_ptr -
3099 (uint8_t *)((uint8_t *)ha->md_dump);
3100skip_nxt_entry:
3101 /*
3102 * next entry in the template
3103 */
3104 entry_hdr = (struct qla8044_minidump_entry_hdr *)
3105 (((uint8_t *)entry_hdr) + entry_hdr->entry_size);
3106 }
3107
3108 if (data_collected != ha->md_dump_size) {
3109 ql_log(ql_log_info, vha, 0xb105,
3110 "Dump data mismatch: Data collected: "
3111 "[0x%x], total_data_size:[0x%x]\n",
3112 data_collected, ha->md_dump_size);
3113 goto md_failed;
3114 }
3115
3116 ql_log(ql_log_info, vha, 0xb110,
3117 "Firmware dump saved to temp buffer (%ld/%p %ld/%p).\n",
3118 vha->host_no, ha->md_tmplt_hdr, vha->host_no, ha->md_dump);
3119 ha->fw_dumped = 1;
3120 qla2x00_post_uevent_work(vha, QLA_UEVENT_CODE_FW_DUMP);
3121
3122
3123 ql_log(ql_log_info, vha, 0xb106,
3124 "Leaving fn: %s Last entry: 0x%x\n",
3125 __func__, i);
3126md_failed:
3127 return rval;
3128}
3129
3130void
3131qla8044_get_minidump(struct scsi_qla_host *vha)
3132{
3133 struct qla_hw_data *ha = vha->hw;
3134
3135 if (!qla8044_collect_md_data(vha)) {
3136 ha->fw_dumped = 1;
3137 } else {
3138 ql_log(ql_log_fatal, vha, 0xb0db,
3139 "%s: Unable to collect minidump\n",
3140 __func__);
3141 }
3142}
3143
3144static int
3145qla8044_poll_flash_status_reg(struct scsi_qla_host *vha)
3146{
3147 uint32_t flash_status;
3148 int retries = QLA8044_FLASH_READ_RETRY_COUNT;
3149 int ret_val = QLA_SUCCESS;
3150
3151 while (retries--) {
3152 ret_val = qla8044_rd_reg_indirect(vha, QLA8044_FLASH_STATUS,
3153 &flash_status);
3154 if (ret_val) {
Saurav Kashyap6ddcfef2013-08-27 01:37:53 -04003155 ql_log(ql_log_warn, vha, 0xb13c,
Atul Deshmukh7ec0eff2013-08-27 01:37:28 -04003156 "%s: Failed to read FLASH_STATUS reg.\n",
3157 __func__);
3158 break;
3159 }
3160 if ((flash_status & QLA8044_FLASH_STATUS_READY) ==
3161 QLA8044_FLASH_STATUS_READY)
3162 break;
3163 msleep(QLA8044_FLASH_STATUS_REG_POLL_DELAY);
3164 }
3165
3166 if (!retries)
3167 ret_val = QLA_FUNCTION_FAILED;
3168
3169 return ret_val;
3170}
3171
3172static int
3173qla8044_write_flash_status_reg(struct scsi_qla_host *vha,
3174 uint32_t data)
3175{
3176 int ret_val = QLA_SUCCESS;
3177 uint32_t cmd;
3178
3179 cmd = vha->hw->fdt_wrt_sts_reg_cmd;
3180
3181 ret_val = qla8044_wr_reg_indirect(vha, QLA8044_FLASH_ADDR,
3182 QLA8044_FLASH_STATUS_WRITE_DEF_SIG | cmd);
3183 if (ret_val) {
3184 ql_log(ql_log_warn, vha, 0xb125,
3185 "%s: Failed to write to FLASH_ADDR.\n", __func__);
3186 goto exit_func;
3187 }
3188
3189 ret_val = qla8044_wr_reg_indirect(vha, QLA8044_FLASH_WRDATA, data);
3190 if (ret_val) {
3191 ql_log(ql_log_warn, vha, 0xb126,
3192 "%s: Failed to write to FLASH_WRDATA.\n", __func__);
3193 goto exit_func;
3194 }
3195
3196 ret_val = qla8044_wr_reg_indirect(vha, QLA8044_FLASH_CONTROL,
3197 QLA8044_FLASH_SECOND_ERASE_MS_VAL);
3198 if (ret_val) {
3199 ql_log(ql_log_warn, vha, 0xb127,
3200 "%s: Failed to write to FLASH_CONTROL.\n", __func__);
3201 goto exit_func;
3202 }
3203
3204 ret_val = qla8044_poll_flash_status_reg(vha);
3205 if (ret_val)
3206 ql_log(ql_log_warn, vha, 0xb128,
3207 "%s: Error polling flash status reg.\n", __func__);
3208
3209exit_func:
3210 return ret_val;
3211}
3212
3213/*
3214 * This function assumes that the flash lock is held.
3215 */
3216static int
3217qla8044_unprotect_flash(scsi_qla_host_t *vha)
3218{
3219 int ret_val;
3220 struct qla_hw_data *ha = vha->hw;
3221
3222 ret_val = qla8044_write_flash_status_reg(vha, ha->fdt_wrt_enable);
3223 if (ret_val)
3224 ql_log(ql_log_warn, vha, 0xb139,
3225 "%s: Write flash status failed.\n", __func__);
3226
3227 return ret_val;
3228}
3229
3230/*
3231 * This function assumes that the flash lock is held.
3232 */
3233static int
3234qla8044_protect_flash(scsi_qla_host_t *vha)
3235{
3236 int ret_val;
3237 struct qla_hw_data *ha = vha->hw;
3238
3239 ret_val = qla8044_write_flash_status_reg(vha, ha->fdt_wrt_disable);
3240 if (ret_val)
3241 ql_log(ql_log_warn, vha, 0xb13b,
3242 "%s: Write flash status failed.\n", __func__);
3243
3244 return ret_val;
3245}
3246
3247
3248static int
3249qla8044_erase_flash_sector(struct scsi_qla_host *vha,
3250 uint32_t sector_start_addr)
3251{
3252 uint32_t reversed_addr;
3253 int ret_val = QLA_SUCCESS;
3254
3255 ret_val = qla8044_poll_flash_status_reg(vha);
3256 if (ret_val) {
3257 ql_log(ql_log_warn, vha, 0xb12e,
3258 "%s: Poll flash status after erase failed..\n", __func__);
3259 }
3260
3261 reversed_addr = (((sector_start_addr & 0xFF) << 16) |
3262 (sector_start_addr & 0xFF00) |
3263 ((sector_start_addr & 0xFF0000) >> 16));
3264
3265 ret_val = qla8044_wr_reg_indirect(vha,
3266 QLA8044_FLASH_WRDATA, reversed_addr);
3267 if (ret_val) {
3268 ql_log(ql_log_warn, vha, 0xb12f,
3269 "%s: Failed to write to FLASH_WRDATA.\n", __func__);
3270 }
3271 ret_val = qla8044_wr_reg_indirect(vha, QLA8044_FLASH_ADDR,
3272 QLA8044_FLASH_ERASE_SIG | vha->hw->fdt_erase_cmd);
3273 if (ret_val) {
3274 ql_log(ql_log_warn, vha, 0xb130,
3275 "%s: Failed to write to FLASH_ADDR.\n", __func__);
3276 }
3277 ret_val = qla8044_wr_reg_indirect(vha, QLA8044_FLASH_CONTROL,
3278 QLA8044_FLASH_LAST_ERASE_MS_VAL);
3279 if (ret_val) {
3280 ql_log(ql_log_warn, vha, 0xb131,
3281 "%s: Failed write to FLASH_CONTROL.\n", __func__);
3282 }
3283 ret_val = qla8044_poll_flash_status_reg(vha);
3284 if (ret_val) {
3285 ql_log(ql_log_warn, vha, 0xb132,
3286 "%s: Poll flash status failed.\n", __func__);
3287 }
3288
3289
3290 return ret_val;
3291}
3292
3293/*
3294 * qla8044_flash_write_u32 - Write data to flash
3295 *
3296 * @ha : Pointer to adapter structure
3297 * addr : Flash address to write to
3298 * p_data : Data to be written
3299 *
3300 * Return Value - QLA_SUCCESS/QLA_FUNCTION_FAILED
3301 *
3302 * NOTE: Lock should be held on entry
3303 */
3304static int
3305qla8044_flash_write_u32(struct scsi_qla_host *vha, uint32_t addr,
3306 uint32_t *p_data)
3307{
3308 int ret_val = QLA_SUCCESS;
3309
3310 ret_val = qla8044_wr_reg_indirect(vha, QLA8044_FLASH_ADDR,
3311 0x00800000 | (addr >> 2));
3312 if (ret_val) {
3313 ql_log(ql_log_warn, vha, 0xb134,
3314 "%s: Failed write to FLASH_ADDR.\n", __func__);
3315 goto exit_func;
3316 }
3317 ret_val = qla8044_wr_reg_indirect(vha, QLA8044_FLASH_WRDATA, *p_data);
3318 if (ret_val) {
3319 ql_log(ql_log_warn, vha, 0xb135,
3320 "%s: Failed write to FLASH_WRDATA.\n", __func__);
3321 goto exit_func;
3322 }
3323 ret_val = qla8044_wr_reg_indirect(vha, QLA8044_FLASH_CONTROL, 0x3D);
3324 if (ret_val) {
3325 ql_log(ql_log_warn, vha, 0xb136,
3326 "%s: Failed write to FLASH_CONTROL.\n", __func__);
3327 goto exit_func;
3328 }
3329 ret_val = qla8044_poll_flash_status_reg(vha);
3330 if (ret_val) {
3331 ql_log(ql_log_warn, vha, 0xb137,
3332 "%s: Poll flash status failed.\n", __func__);
3333 }
3334
3335exit_func:
3336 return ret_val;
3337}
3338
3339static int
3340qla8044_write_flash_buffer_mode(scsi_qla_host_t *vha, uint32_t *dwptr,
3341 uint32_t faddr, uint32_t dwords)
3342{
3343 int ret = QLA_FUNCTION_FAILED;
3344 uint32_t spi_val;
3345
3346 if (dwords < QLA8044_MIN_OPTROM_BURST_DWORDS ||
3347 dwords > QLA8044_MAX_OPTROM_BURST_DWORDS) {
3348 ql_dbg(ql_dbg_user, vha, 0xb123,
3349 "Got unsupported dwords = 0x%x.\n",
3350 dwords);
3351 return QLA_FUNCTION_FAILED;
3352 }
3353
3354 qla8044_rd_reg_indirect(vha, QLA8044_FLASH_SPI_CONTROL, &spi_val);
3355 qla8044_wr_reg_indirect(vha, QLA8044_FLASH_SPI_CONTROL,
3356 spi_val | QLA8044_FLASH_SPI_CTL);
3357 qla8044_wr_reg_indirect(vha, QLA8044_FLASH_ADDR,
3358 QLA8044_FLASH_FIRST_TEMP_VAL);
3359
3360 /* First DWORD write to FLASH_WRDATA */
3361 ret = qla8044_wr_reg_indirect(vha, QLA8044_FLASH_WRDATA,
3362 *dwptr++);
3363 qla8044_wr_reg_indirect(vha, QLA8044_FLASH_CONTROL,
3364 QLA8044_FLASH_FIRST_MS_PATTERN);
3365
3366 ret = qla8044_poll_flash_status_reg(vha);
3367 if (ret) {
3368 ql_log(ql_log_warn, vha, 0xb124,
3369 "%s: Failed.\n", __func__);
3370 goto exit_func;
3371 }
3372
3373 dwords--;
3374
3375 qla8044_wr_reg_indirect(vha, QLA8044_FLASH_ADDR,
3376 QLA8044_FLASH_SECOND_TEMP_VAL);
3377
3378
3379 /* Second to N-1 DWORDS writes */
3380 while (dwords != 1) {
3381 qla8044_wr_reg_indirect(vha, QLA8044_FLASH_WRDATA, *dwptr++);
3382 qla8044_wr_reg_indirect(vha, QLA8044_FLASH_CONTROL,
3383 QLA8044_FLASH_SECOND_MS_PATTERN);
3384 ret = qla8044_poll_flash_status_reg(vha);
3385 if (ret) {
3386 ql_log(ql_log_warn, vha, 0xb129,
3387 "%s: Failed.\n", __func__);
3388 goto exit_func;
3389 }
3390 dwords--;
3391 }
3392
3393 qla8044_wr_reg_indirect(vha, QLA8044_FLASH_ADDR,
3394 QLA8044_FLASH_FIRST_TEMP_VAL | (faddr >> 2));
3395
3396 /* Last DWORD write */
3397 qla8044_wr_reg_indirect(vha, QLA8044_FLASH_WRDATA, *dwptr++);
3398 qla8044_wr_reg_indirect(vha, QLA8044_FLASH_CONTROL,
3399 QLA8044_FLASH_LAST_MS_PATTERN);
3400 ret = qla8044_poll_flash_status_reg(vha);
3401 if (ret) {
3402 ql_log(ql_log_warn, vha, 0xb12a,
3403 "%s: Failed.\n", __func__);
3404 goto exit_func;
3405 }
3406 qla8044_rd_reg_indirect(vha, QLA8044_FLASH_SPI_STATUS, &spi_val);
3407
3408 if ((spi_val & QLA8044_FLASH_SPI_CTL) == QLA8044_FLASH_SPI_CTL) {
3409 ql_log(ql_log_warn, vha, 0xb12b,
3410 "%s: Failed.\n", __func__);
3411 spi_val = 0;
3412 /* Operation failed, clear error bit. */
3413 qla8044_rd_reg_indirect(vha, QLA8044_FLASH_SPI_CONTROL,
3414 &spi_val);
3415 qla8044_wr_reg_indirect(vha, QLA8044_FLASH_SPI_CONTROL,
3416 spi_val | QLA8044_FLASH_SPI_CTL);
3417 }
3418exit_func:
3419 return ret;
3420}
3421
3422static int
3423qla8044_write_flash_dword_mode(scsi_qla_host_t *vha, uint32_t *dwptr,
3424 uint32_t faddr, uint32_t dwords)
3425{
3426 int ret = QLA_FUNCTION_FAILED;
3427 uint32_t liter;
3428
3429 for (liter = 0; liter < dwords; liter++, faddr += 4, dwptr++) {
3430 ret = qla8044_flash_write_u32(vha, faddr, dwptr);
3431 if (ret) {
3432 ql_dbg(ql_dbg_p3p, vha, 0xb141,
3433 "%s: flash address=%x data=%x.\n", __func__,
3434 faddr, *dwptr);
3435 break;
3436 }
3437 }
3438
3439 return ret;
3440}
3441
3442int
3443qla8044_write_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
3444 uint32_t offset, uint32_t length)
3445{
3446 int rval = QLA_FUNCTION_FAILED, i, burst_iter_count;
3447 int dword_count, erase_sec_count;
3448 uint32_t erase_offset;
3449 uint8_t *p_cache, *p_src;
3450
3451 erase_offset = offset;
3452
3453 p_cache = kcalloc(length, sizeof(uint8_t), GFP_KERNEL);
3454 if (!p_cache)
3455 return QLA_FUNCTION_FAILED;
3456
3457 memcpy(p_cache, buf, length);
3458 p_src = p_cache;
3459 dword_count = length / sizeof(uint32_t);
3460 /* Since the offset and legth are sector aligned, it will be always
3461 * multiple of burst_iter_count (64)
3462 */
3463 burst_iter_count = dword_count / QLA8044_MAX_OPTROM_BURST_DWORDS;
3464 erase_sec_count = length / QLA8044_SECTOR_SIZE;
3465
3466 /* Suspend HBA. */
3467 scsi_block_requests(vha->host);
3468 /* Lock and enable write for whole operation. */
3469 qla8044_flash_lock(vha);
3470 qla8044_unprotect_flash(vha);
3471
3472 /* Erasing the sectors */
3473 for (i = 0; i < erase_sec_count; i++) {
3474 rval = qla8044_erase_flash_sector(vha, erase_offset);
3475 ql_dbg(ql_dbg_user, vha, 0xb138,
3476 "Done erase of sector=0x%x.\n",
3477 erase_offset);
3478 if (rval) {
3479 ql_log(ql_log_warn, vha, 0xb121,
3480 "Failed to erase the sector having address: "
3481 "0x%x.\n", erase_offset);
3482 goto out;
3483 }
3484 erase_offset += QLA8044_SECTOR_SIZE;
3485 }
Saurav Kashyap6ddcfef2013-08-27 01:37:53 -04003486 ql_dbg(ql_dbg_user, vha, 0xb13f,
Atul Deshmukh7ec0eff2013-08-27 01:37:28 -04003487 "Got write for addr = 0x%x length=0x%x.\n",
3488 offset, length);
3489
3490 for (i = 0; i < burst_iter_count; i++) {
3491
3492 /* Go with write. */
3493 rval = qla8044_write_flash_buffer_mode(vha, (uint32_t *)p_src,
3494 offset, QLA8044_MAX_OPTROM_BURST_DWORDS);
3495 if (rval) {
3496 /* Buffer Mode failed skip to dword mode */
3497 ql_log(ql_log_warn, vha, 0xb122,
3498 "Failed to write flash in buffer mode, "
3499 "Reverting to slow-write.\n");
3500 rval = qla8044_write_flash_dword_mode(vha,
3501 (uint32_t *)p_src, offset,
3502 QLA8044_MAX_OPTROM_BURST_DWORDS);
3503 }
3504 p_src += sizeof(uint32_t) * QLA8044_MAX_OPTROM_BURST_DWORDS;
3505 offset += sizeof(uint32_t) * QLA8044_MAX_OPTROM_BURST_DWORDS;
3506 }
3507 ql_dbg(ql_dbg_user, vha, 0xb133,
3508 "Done writing.\n");
3509
3510out:
3511 qla8044_protect_flash(vha);
3512 qla8044_flash_unlock(vha);
3513 scsi_unblock_requests(vha->host);
3514 kfree(p_cache);
3515
3516 return rval;
3517}
3518
3519#define LEG_INT_PTR_B31 (1 << 31)
3520#define LEG_INT_PTR_B30 (1 << 30)
3521#define PF_BITS_MASK (0xF << 16)
3522/**
3523 * qla8044_intr_handler() - Process interrupts for the ISP8044
3524 * @irq:
3525 * @dev_id: SCSI driver HA context
3526 *
3527 * Called by system whenever the host adapter generates an interrupt.
3528 *
3529 * Returns handled flag.
3530 */
3531irqreturn_t
3532qla8044_intr_handler(int irq, void *dev_id)
3533{
3534 scsi_qla_host_t *vha;
3535 struct qla_hw_data *ha;
3536 struct rsp_que *rsp;
3537 struct device_reg_82xx __iomem *reg;
3538 int status = 0;
3539 unsigned long flags;
3540 unsigned long iter;
3541 uint32_t stat;
3542 uint16_t mb[4];
3543 uint32_t leg_int_ptr = 0, pf_bit;
3544
3545 rsp = (struct rsp_que *) dev_id;
3546 if (!rsp) {
3547 ql_log(ql_log_info, NULL, 0xb143,
3548 "%s(): NULL response queue pointer\n", __func__);
3549 return IRQ_NONE;
3550 }
3551 ha = rsp->hw;
3552 vha = pci_get_drvdata(ha->pdev);
3553
3554 if (unlikely(pci_channel_offline(ha->pdev)))
3555 return IRQ_HANDLED;
3556
3557 leg_int_ptr = qla8044_rd_reg(ha, LEG_INTR_PTR_OFFSET);
3558
3559 /* Legacy interrupt is valid if bit31 of leg_int_ptr is set */
3560 if (!(leg_int_ptr & (LEG_INT_PTR_B31))) {
3561 ql_dbg(ql_dbg_p3p, vha, 0xb144,
3562 "%s: Legacy Interrupt Bit 31 not set, "
3563 "spurious interrupt!\n", __func__);
3564 return IRQ_NONE;
3565 }
3566
3567 pf_bit = ha->portnum << 16;
3568 /* Validate the PCIE function ID set in leg_int_ptr bits [19..16] */
3569 if ((leg_int_ptr & (PF_BITS_MASK)) != pf_bit) {
3570 ql_dbg(ql_dbg_p3p, vha, 0xb145,
3571 "%s: Incorrect function ID 0x%x in "
3572 "legacy interrupt register, "
3573 "ha->pf_bit = 0x%x\n", __func__,
3574 (leg_int_ptr & (PF_BITS_MASK)), pf_bit);
3575 return IRQ_NONE;
3576 }
3577
3578 /* To de-assert legacy interrupt, write 0 to Legacy Interrupt Trigger
3579 * Control register and poll till Legacy Interrupt Pointer register
3580 * bit32 is 0.
3581 */
3582 qla8044_wr_reg(ha, LEG_INTR_TRIG_OFFSET, 0);
3583 do {
3584 leg_int_ptr = qla8044_rd_reg(ha, LEG_INTR_PTR_OFFSET);
3585 if ((leg_int_ptr & (PF_BITS_MASK)) != pf_bit)
3586 break;
3587 } while (leg_int_ptr & (LEG_INT_PTR_B30));
3588
3589 reg = &ha->iobase->isp82;
3590 spin_lock_irqsave(&ha->hardware_lock, flags);
3591 for (iter = 1; iter--; ) {
3592
3593 if (RD_REG_DWORD(&reg->host_int)) {
3594 stat = RD_REG_DWORD(&reg->host_status);
3595 if ((stat & HSRX_RISC_INT) == 0)
3596 break;
3597
3598 switch (stat & 0xff) {
3599 case 0x1:
3600 case 0x2:
3601 case 0x10:
3602 case 0x11:
3603 qla82xx_mbx_completion(vha, MSW(stat));
3604 status |= MBX_INTERRUPT;
3605 break;
3606 case 0x12:
3607 mb[0] = MSW(stat);
3608 mb[1] = RD_REG_WORD(&reg->mailbox_out[1]);
3609 mb[2] = RD_REG_WORD(&reg->mailbox_out[2]);
3610 mb[3] = RD_REG_WORD(&reg->mailbox_out[3]);
3611 qla2x00_async_event(vha, rsp, mb);
3612 break;
3613 case 0x13:
3614 qla24xx_process_response_queue(vha, rsp);
3615 break;
3616 default:
3617 ql_dbg(ql_dbg_p3p, vha, 0xb146,
3618 "Unrecognized interrupt type "
3619 "(%d).\n", stat & 0xff);
3620 break;
3621 }
3622 }
3623 WRT_REG_DWORD(&reg->host_int, 0);
3624 }
3625
3626 qla2x00_handle_mbx_completion(ha, status);
3627 spin_unlock_irqrestore(&ha->hardware_lock, flags);
3628
3629 return IRQ_HANDLED;
3630}
3631
3632static int
3633qla8044_idc_dontreset(struct qla_hw_data *ha)
3634{
3635 uint32_t idc_ctrl;
3636
3637 idc_ctrl = qla8044_rd_reg(ha, QLA8044_IDC_DRV_CTRL);
3638 return idc_ctrl & DONTRESET_BIT0;
3639}
3640
3641static void
3642qla8044_clear_rst_ready(scsi_qla_host_t *vha)
3643{
3644 uint32_t drv_state;
3645
3646 drv_state = qla8044_rd_direct(vha, QLA8044_CRB_DRV_STATE_INDEX);
3647
3648 /*
3649 * For ISP8044, drv_active register has 1 bit per function,
3650 * shift 1 by func_num to set a bit for the function.
3651 * For ISP82xx, drv_active has 4 bits per function
3652 */
3653 drv_state &= ~(1 << vha->hw->portnum);
3654
Saurav Kashyap6ddcfef2013-08-27 01:37:53 -04003655 ql_dbg(ql_dbg_p3p, vha, 0xb13d,
Atul Deshmukh7ec0eff2013-08-27 01:37:28 -04003656 "drv_state: 0x%08x\n", drv_state);
3657 qla8044_wr_direct(vha, QLA8044_CRB_DRV_STATE_INDEX, drv_state);
3658}
3659
3660int
3661qla8044_abort_isp(scsi_qla_host_t *vha)
3662{
3663 int rval;
3664 uint32_t dev_state;
3665 struct qla_hw_data *ha = vha->hw;
3666
3667 qla8044_idc_lock(ha);
3668 dev_state = qla8044_rd_direct(vha, QLA8044_CRB_DEV_STATE_INDEX);
3669
3670 if (ql2xdontresethba)
3671 qla8044_set_idc_dontreset(vha);
3672
3673 /* If device_state is NEED_RESET, go ahead with
3674 * Reset,irrespective of ql2xdontresethba. This is to allow a
3675 * non-reset-owner to force a reset. Non-reset-owner sets
3676 * the IDC_CTRL BIT0 to prevent Reset-owner from doing a Reset
3677 * and then forces a Reset by setting device_state to
3678 * NEED_RESET. */
3679 if (dev_state == QLA8XXX_DEV_READY) {
3680 /* If IDC_CTRL DONTRESETHBA_BIT0 is set don't do reset
3681 * recovery */
3682 if (qla8044_idc_dontreset(ha) == DONTRESET_BIT0) {
Saurav Kashyap6ddcfef2013-08-27 01:37:53 -04003683 ql_dbg(ql_dbg_p3p, vha, 0xb13e,
Atul Deshmukh7ec0eff2013-08-27 01:37:28 -04003684 "Reset recovery disabled\n");
3685 rval = QLA_FUNCTION_FAILED;
3686 goto exit_isp_reset;
3687 }
3688
Saurav Kashyap6ddcfef2013-08-27 01:37:53 -04003689 ql_dbg(ql_dbg_p3p, vha, 0xb140,
Atul Deshmukh7ec0eff2013-08-27 01:37:28 -04003690 "HW State: NEED RESET\n");
3691 qla8044_wr_direct(vha, QLA8044_CRB_DEV_STATE_INDEX,
3692 QLA8XXX_DEV_NEED_RESET);
3693 }
3694
3695 /* For ISP8044, Reset owner is NIC, iSCSI or FCOE based on priority
3696 * and which drivers are present. Unlike ISP82XX, the function setting
3697 * NEED_RESET, may not be the Reset owner. */
3698 qla83xx_reset_ownership(vha);
3699
3700 qla8044_idc_unlock(ha);
3701 rval = qla8044_device_state_handler(vha);
3702 qla8044_idc_lock(ha);
3703 qla8044_clear_rst_ready(vha);
3704
3705exit_isp_reset:
3706 qla8044_idc_unlock(ha);
3707 if (rval == QLA_SUCCESS) {
3708 ha->flags.isp82xx_fw_hung = 0;
3709 ha->flags.nic_core_reset_hdlr_active = 0;
3710 rval = qla82xx_restart_isp(vha);
3711 }
3712
3713 return rval;
3714}
3715
Chad Dupuisa1b23c52014-02-26 04:15:12 -05003716void
3717qla8044_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
3718{
3719 struct qla_hw_data *ha = vha->hw;
3720
3721 if (!ha->allow_cna_fw_dump)
3722 return;
3723
3724 scsi_block_requests(vha->host);
3725 ha->flags.isp82xx_no_md_cap = 1;
3726 qla8044_idc_lock(ha);
3727 qla82xx_set_reset_owner(vha);
3728 qla8044_idc_unlock(ha);
3729 qla2x00_wait_for_chip_reset(vha);
3730 scsi_unblock_requests(vha->host);
3731}