blob: 4969dc10684a4c48135a12e46823be3afc7c5c56 [file] [log] [blame]
Maxime Ripardb5f65172014-02-22 22:35:53 +01001/*
2 * Copyright (C) 2012 - 2014 Allwinner Tech
3 * Pan Nan <pannan@allwinnertech.com>
4 *
5 * Copyright (C) 2014 Maxime Ripard
6 * Maxime Ripard <maxime.ripard@free-electrons.com>
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 */
13
14#include <linux/clk.h>
15#include <linux/delay.h>
16#include <linux/device.h>
17#include <linux/interrupt.h>
18#include <linux/io.h>
19#include <linux/module.h>
20#include <linux/platform_device.h>
21#include <linux/pm_runtime.h>
Maxime Ripardb5f65172014-02-22 22:35:53 +010022
23#include <linux/spi/spi.h>
24
25#define SUN4I_FIFO_DEPTH 64
26
27#define SUN4I_RXDATA_REG 0x00
28
29#define SUN4I_TXDATA_REG 0x04
30
31#define SUN4I_CTL_REG 0x08
32#define SUN4I_CTL_ENABLE BIT(0)
33#define SUN4I_CTL_MASTER BIT(1)
34#define SUN4I_CTL_CPHA BIT(2)
35#define SUN4I_CTL_CPOL BIT(3)
36#define SUN4I_CTL_CS_ACTIVE_LOW BIT(4)
37#define SUN4I_CTL_LMTF BIT(6)
38#define SUN4I_CTL_TF_RST BIT(8)
39#define SUN4I_CTL_RF_RST BIT(9)
40#define SUN4I_CTL_XCH BIT(10)
41#define SUN4I_CTL_CS_MASK 0x3000
42#define SUN4I_CTL_CS(cs) (((cs) << 12) & SUN4I_CTL_CS_MASK)
43#define SUN4I_CTL_DHB BIT(15)
44#define SUN4I_CTL_CS_MANUAL BIT(16)
45#define SUN4I_CTL_CS_LEVEL BIT(17)
46#define SUN4I_CTL_TP BIT(18)
47
48#define SUN4I_INT_CTL_REG 0x0c
49#define SUN4I_INT_CTL_TC BIT(16)
50
51#define SUN4I_INT_STA_REG 0x10
52
53#define SUN4I_DMA_CTL_REG 0x14
54
55#define SUN4I_WAIT_REG 0x18
56
57#define SUN4I_CLK_CTL_REG 0x1c
58#define SUN4I_CLK_CTL_CDR2_MASK 0xff
59#define SUN4I_CLK_CTL_CDR2(div) ((div) & SUN4I_CLK_CTL_CDR2_MASK)
60#define SUN4I_CLK_CTL_CDR1_MASK 0xf
61#define SUN4I_CLK_CTL_CDR1(div) (((div) & SUN4I_CLK_CTL_CDR1_MASK) << 8)
62#define SUN4I_CLK_CTL_DRS BIT(12)
63
64#define SUN4I_BURST_CNT_REG 0x20
65#define SUN4I_BURST_CNT(cnt) ((cnt) & 0xffffff)
66
67#define SUN4I_XMIT_CNT_REG 0x24
68#define SUN4I_XMIT_CNT(cnt) ((cnt) & 0xffffff)
69
70#define SUN4I_FIFO_STA_REG 0x28
71#define SUN4I_FIFO_STA_RF_CNT_MASK 0x7f
72#define SUN4I_FIFO_STA_RF_CNT_BITS 0
73#define SUN4I_FIFO_STA_TF_CNT_MASK 0x7f
74#define SUN4I_FIFO_STA_TF_CNT_BITS 16
75
76struct sun4i_spi {
77 struct spi_master *master;
78 void __iomem *base_addr;
79 struct clk *hclk;
80 struct clk *mclk;
81
82 struct completion done;
83
84 const u8 *tx_buf;
85 u8 *rx_buf;
86 int len;
87};
88
89static inline u32 sun4i_spi_read(struct sun4i_spi *sspi, u32 reg)
90{
91 return readl(sspi->base_addr + reg);
92}
93
94static inline void sun4i_spi_write(struct sun4i_spi *sspi, u32 reg, u32 value)
95{
96 writel(value, sspi->base_addr + reg);
97}
98
99static inline void sun4i_spi_drain_fifo(struct sun4i_spi *sspi, int len)
100{
101 u32 reg, cnt;
102 u8 byte;
103
104 /* See how much data is available */
105 reg = sun4i_spi_read(sspi, SUN4I_FIFO_STA_REG);
106 reg &= SUN4I_FIFO_STA_RF_CNT_MASK;
107 cnt = reg >> SUN4I_FIFO_STA_RF_CNT_BITS;
108
109 if (len > cnt)
110 len = cnt;
111
112 while (len--) {
113 byte = readb(sspi->base_addr + SUN4I_RXDATA_REG);
114 if (sspi->rx_buf)
115 *sspi->rx_buf++ = byte;
116 }
117}
118
119static inline void sun4i_spi_fill_fifo(struct sun4i_spi *sspi, int len)
120{
121 u8 byte;
122
123 if (len > sspi->len)
124 len = sspi->len;
125
126 while (len--) {
127 byte = sspi->tx_buf ? *sspi->tx_buf++ : 0;
128 writeb(byte, sspi->base_addr + SUN4I_TXDATA_REG);
129 sspi->len--;
130 }
131}
132
133static void sun4i_spi_set_cs(struct spi_device *spi, bool enable)
134{
135 struct sun4i_spi *sspi = spi_master_get_devdata(spi->master);
136 u32 reg;
137
138 reg = sun4i_spi_read(sspi, SUN4I_CTL_REG);
139
140 reg &= ~SUN4I_CTL_CS_MASK;
141 reg |= SUN4I_CTL_CS(spi->chip_select);
142
Marcus Weseloh218e0b52016-01-05 21:46:20 +0100143 /* We want to control the chip select manually */
144 reg |= SUN4I_CTL_CS_MANUAL;
145
Maxime Ripardb5f65172014-02-22 22:35:53 +0100146 if (enable)
147 reg |= SUN4I_CTL_CS_LEVEL;
148 else
149 reg &= ~SUN4I_CTL_CS_LEVEL;
150
151 /*
152 * Even though this looks irrelevant since we are supposed to
153 * be controlling the chip select manually, this bit also
154 * controls the levels of the chip select for inactive
155 * devices.
156 *
157 * If we don't set it, the chip select level will go low by
158 * default when the device is idle, which is not really
159 * expected in the common case where the chip select is active
160 * low.
161 */
162 if (spi->mode & SPI_CS_HIGH)
163 reg &= ~SUN4I_CTL_CS_ACTIVE_LOW;
164 else
165 reg |= SUN4I_CTL_CS_ACTIVE_LOW;
166
167 sun4i_spi_write(sspi, SUN4I_CTL_REG, reg);
168}
169
Michal Suchanek794912c2016-06-13 17:46:50 +0000170static size_t sun4i_spi_max_transfer_size(struct spi_device *spi)
171{
172 return SUN4I_FIFO_DEPTH - 1;
173}
174
Maxime Ripardb5f65172014-02-22 22:35:53 +0100175static int sun4i_spi_transfer_one(struct spi_master *master,
176 struct spi_device *spi,
177 struct spi_transfer *tfr)
178{
179 struct sun4i_spi *sspi = spi_master_get_devdata(master);
180 unsigned int mclk_rate, div, timeout;
Michal Suchanek719bd652016-06-13 17:46:49 +0000181 unsigned int start, end, tx_time;
Maxime Ripardb5f65172014-02-22 22:35:53 +0100182 unsigned int tx_len = 0;
183 int ret = 0;
184 u32 reg;
185
186 /* We don't support transfer larger than the FIFO */
187 if (tfr->len > SUN4I_FIFO_DEPTH)
Michal Suchanek6d9fe442016-06-13 17:46:49 +0000188 return -EMSGSIZE;
189
190 if (tfr->tx_buf && tfr->len >= SUN4I_FIFO_DEPTH)
191 return -EMSGSIZE;
Maxime Ripardb5f65172014-02-22 22:35:53 +0100192
193 reinit_completion(&sspi->done);
194 sspi->tx_buf = tfr->tx_buf;
195 sspi->rx_buf = tfr->rx_buf;
196 sspi->len = tfr->len;
197
198 /* Clear pending interrupts */
199 sun4i_spi_write(sspi, SUN4I_INT_STA_REG, ~0);
200
201
202 reg = sun4i_spi_read(sspi, SUN4I_CTL_REG);
203
204 /* Reset FIFOs */
205 sun4i_spi_write(sspi, SUN4I_CTL_REG,
206 reg | SUN4I_CTL_RF_RST | SUN4I_CTL_TF_RST);
207
208 /*
209 * Setup the transfer control register: Chip Select,
210 * polarities, etc.
211 */
212 if (spi->mode & SPI_CPOL)
213 reg |= SUN4I_CTL_CPOL;
214 else
215 reg &= ~SUN4I_CTL_CPOL;
216
217 if (spi->mode & SPI_CPHA)
218 reg |= SUN4I_CTL_CPHA;
219 else
220 reg &= ~SUN4I_CTL_CPHA;
221
222 if (spi->mode & SPI_LSB_FIRST)
223 reg |= SUN4I_CTL_LMTF;
224 else
225 reg &= ~SUN4I_CTL_LMTF;
226
227
228 /*
229 * If it's a TX only transfer, we don't want to fill the RX
230 * FIFO with bogus data
231 */
232 if (sspi->rx_buf)
233 reg &= ~SUN4I_CTL_DHB;
234 else
235 reg |= SUN4I_CTL_DHB;
236
Maxime Ripardb5f65172014-02-22 22:35:53 +0100237 sun4i_spi_write(sspi, SUN4I_CTL_REG, reg);
238
239 /* Ensure that we have a parent clock fast enough */
240 mclk_rate = clk_get_rate(sspi->mclk);
Marcus Weseloh47284e32015-11-08 12:03:23 +0100241 if (mclk_rate < (2 * tfr->speed_hz)) {
242 clk_set_rate(sspi->mclk, 2 * tfr->speed_hz);
Maxime Ripardb5f65172014-02-22 22:35:53 +0100243 mclk_rate = clk_get_rate(sspi->mclk);
244 }
245
246 /*
247 * Setup clock divider.
248 *
249 * We have two choices there. Either we can use the clock
250 * divide rate 1, which is calculated thanks to this formula:
251 * SPI_CLK = MOD_CLK / (2 ^ (cdr + 1))
252 * Or we can use CDR2, which is calculated with the formula:
253 * SPI_CLK = MOD_CLK / (2 * (cdr + 1))
254 * Wether we use the former or the latter is set through the
255 * DRS bit.
256 *
257 * First try CDR2, and if we can't reach the expected
258 * frequency, fall back to CDR1.
259 */
Marcus Weseloh47284e32015-11-08 12:03:23 +0100260 div = mclk_rate / (2 * tfr->speed_hz);
Maxime Ripardb5f65172014-02-22 22:35:53 +0100261 if (div <= (SUN4I_CLK_CTL_CDR2_MASK + 1)) {
262 if (div > 0)
263 div--;
264
265 reg = SUN4I_CLK_CTL_CDR2(div) | SUN4I_CLK_CTL_DRS;
266 } else {
Marcus Weseloh47284e32015-11-08 12:03:23 +0100267 div = ilog2(mclk_rate) - ilog2(tfr->speed_hz);
Maxime Ripardb5f65172014-02-22 22:35:53 +0100268 reg = SUN4I_CLK_CTL_CDR1(div);
269 }
270
271 sun4i_spi_write(sspi, SUN4I_CLK_CTL_REG, reg);
272
273 /* Setup the transfer now... */
274 if (sspi->tx_buf)
275 tx_len = tfr->len;
276
277 /* Setup the counters */
278 sun4i_spi_write(sspi, SUN4I_BURST_CNT_REG, SUN4I_BURST_CNT(tfr->len));
279 sun4i_spi_write(sspi, SUN4I_XMIT_CNT_REG, SUN4I_XMIT_CNT(tx_len));
280
Michal Suchanek6d9fe442016-06-13 17:46:49 +0000281 /*
282 * Fill the TX FIFO
283 * Filling the FIFO fully causes timeout for some reason
284 * at least on spi2 on A10s
285 */
286 sun4i_spi_fill_fifo(sspi, SUN4I_FIFO_DEPTH - 1);
Maxime Ripardb5f65172014-02-22 22:35:53 +0100287
288 /* Enable the interrupts */
289 sun4i_spi_write(sspi, SUN4I_INT_CTL_REG, SUN4I_INT_CTL_TC);
290
291 /* Start the transfer */
292 reg = sun4i_spi_read(sspi, SUN4I_CTL_REG);
293 sun4i_spi_write(sspi, SUN4I_CTL_REG, reg | SUN4I_CTL_XCH);
294
Michal Suchanek719bd652016-06-13 17:46:49 +0000295 tx_time = max(tfr->len * 8 * 2 / (tfr->speed_hz / 1000), 100U);
296 start = jiffies;
Maxime Ripardb5f65172014-02-22 22:35:53 +0100297 timeout = wait_for_completion_timeout(&sspi->done,
Michal Suchanek719bd652016-06-13 17:46:49 +0000298 msecs_to_jiffies(tx_time));
299 end = jiffies;
Maxime Ripardb5f65172014-02-22 22:35:53 +0100300 if (!timeout) {
Michal Suchanek719bd652016-06-13 17:46:49 +0000301 dev_warn(&master->dev,
302 "%s: timeout transferring %u bytes@%iHz for %i(%i)ms",
303 dev_name(&spi->dev), tfr->len, tfr->speed_hz,
304 jiffies_to_msecs(end - start), tx_time);
Maxime Ripardb5f65172014-02-22 22:35:53 +0100305 ret = -ETIMEDOUT;
306 goto out;
307 }
308
309 sun4i_spi_drain_fifo(sspi, SUN4I_FIFO_DEPTH);
310
311out:
312 sun4i_spi_write(sspi, SUN4I_INT_CTL_REG, 0);
313
314 return ret;
315}
316
317static irqreturn_t sun4i_spi_handler(int irq, void *dev_id)
318{
319 struct sun4i_spi *sspi = dev_id;
320 u32 status = sun4i_spi_read(sspi, SUN4I_INT_STA_REG);
321
322 /* Transfer complete */
323 if (status & SUN4I_INT_CTL_TC) {
324 sun4i_spi_write(sspi, SUN4I_INT_STA_REG, SUN4I_INT_CTL_TC);
325 complete(&sspi->done);
326 return IRQ_HANDLED;
327 }
328
329 return IRQ_NONE;
330}
331
332static int sun4i_spi_runtime_resume(struct device *dev)
333{
334 struct spi_master *master = dev_get_drvdata(dev);
335 struct sun4i_spi *sspi = spi_master_get_devdata(master);
336 int ret;
337
338 ret = clk_prepare_enable(sspi->hclk);
339 if (ret) {
340 dev_err(dev, "Couldn't enable AHB clock\n");
341 goto out;
342 }
343
344 ret = clk_prepare_enable(sspi->mclk);
345 if (ret) {
346 dev_err(dev, "Couldn't enable module clock\n");
347 goto err;
348 }
349
350 sun4i_spi_write(sspi, SUN4I_CTL_REG,
351 SUN4I_CTL_ENABLE | SUN4I_CTL_MASTER | SUN4I_CTL_TP);
352
353 return 0;
354
355err:
356 clk_disable_unprepare(sspi->hclk);
357out:
358 return ret;
359}
360
361static int sun4i_spi_runtime_suspend(struct device *dev)
362{
363 struct spi_master *master = dev_get_drvdata(dev);
364 struct sun4i_spi *sspi = spi_master_get_devdata(master);
365
366 clk_disable_unprepare(sspi->mclk);
367 clk_disable_unprepare(sspi->hclk);
368
369 return 0;
370}
371
372static int sun4i_spi_probe(struct platform_device *pdev)
373{
374 struct spi_master *master;
375 struct sun4i_spi *sspi;
376 struct resource *res;
377 int ret = 0, irq;
378
379 master = spi_alloc_master(&pdev->dev, sizeof(struct sun4i_spi));
380 if (!master) {
381 dev_err(&pdev->dev, "Unable to allocate SPI Master\n");
382 return -ENOMEM;
383 }
384
385 platform_set_drvdata(pdev, master);
386 sspi = spi_master_get_devdata(master);
387
388 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
389 sspi->base_addr = devm_ioremap_resource(&pdev->dev, res);
390 if (IS_ERR(sspi->base_addr)) {
391 ret = PTR_ERR(sspi->base_addr);
392 goto err_free_master;
393 }
394
395 irq = platform_get_irq(pdev, 0);
396 if (irq < 0) {
397 dev_err(&pdev->dev, "No spi IRQ specified\n");
398 ret = -ENXIO;
399 goto err_free_master;
400 }
401
402 ret = devm_request_irq(&pdev->dev, irq, sun4i_spi_handler,
403 0, "sun4i-spi", sspi);
404 if (ret) {
405 dev_err(&pdev->dev, "Cannot request IRQ\n");
406 goto err_free_master;
407 }
408
409 sspi->master = master;
Michal Suchanek0b06d8c2016-06-14 12:10:04 +0000410 master->max_speed_hz = 100 * 1000 * 1000;
411 master->min_speed_hz = 3 * 1000;
Maxime Ripardb5f65172014-02-22 22:35:53 +0100412 master->set_cs = sun4i_spi_set_cs;
413 master->transfer_one = sun4i_spi_transfer_one;
414 master->num_chipselect = 4;
415 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST;
Axel Linba476442014-03-02 22:25:10 +0800416 master->bits_per_word_mask = SPI_BPW_MASK(8);
Maxime Ripardb5f65172014-02-22 22:35:53 +0100417 master->dev.of_node = pdev->dev.of_node;
418 master->auto_runtime_pm = true;
Michal Suchanek794912c2016-06-13 17:46:50 +0000419 master->max_transfer_size = sun4i_spi_max_transfer_size;
Maxime Ripardb5f65172014-02-22 22:35:53 +0100420
421 sspi->hclk = devm_clk_get(&pdev->dev, "ahb");
422 if (IS_ERR(sspi->hclk)) {
423 dev_err(&pdev->dev, "Unable to acquire AHB clock\n");
424 ret = PTR_ERR(sspi->hclk);
425 goto err_free_master;
426 }
427
428 sspi->mclk = devm_clk_get(&pdev->dev, "mod");
429 if (IS_ERR(sspi->mclk)) {
430 dev_err(&pdev->dev, "Unable to acquire module clock\n");
431 ret = PTR_ERR(sspi->mclk);
432 goto err_free_master;
433 }
434
435 init_completion(&sspi->done);
436
437 /*
438 * This wake-up/shutdown pattern is to be able to have the
439 * device woken up, even if runtime_pm is disabled
440 */
441 ret = sun4i_spi_runtime_resume(&pdev->dev);
442 if (ret) {
443 dev_err(&pdev->dev, "Couldn't resume the device\n");
444 goto err_free_master;
445 }
446
447 pm_runtime_set_active(&pdev->dev);
448 pm_runtime_enable(&pdev->dev);
449 pm_runtime_idle(&pdev->dev);
450
451 ret = devm_spi_register_master(&pdev->dev, master);
452 if (ret) {
453 dev_err(&pdev->dev, "cannot register SPI master\n");
454 goto err_pm_disable;
455 }
456
457 return 0;
458
459err_pm_disable:
460 pm_runtime_disable(&pdev->dev);
461 sun4i_spi_runtime_suspend(&pdev->dev);
462err_free_master:
463 spi_master_put(master);
464 return ret;
465}
466
467static int sun4i_spi_remove(struct platform_device *pdev)
468{
469 pm_runtime_disable(&pdev->dev);
470
471 return 0;
472}
473
474static const struct of_device_id sun4i_spi_match[] = {
475 { .compatible = "allwinner,sun4i-a10-spi", },
476 {}
477};
478MODULE_DEVICE_TABLE(of, sun4i_spi_match);
479
480static const struct dev_pm_ops sun4i_spi_pm_ops = {
481 .runtime_resume = sun4i_spi_runtime_resume,
482 .runtime_suspend = sun4i_spi_runtime_suspend,
483};
484
485static struct platform_driver sun4i_spi_driver = {
486 .probe = sun4i_spi_probe,
487 .remove = sun4i_spi_remove,
488 .driver = {
489 .name = "sun4i-spi",
Maxime Ripardb5f65172014-02-22 22:35:53 +0100490 .of_match_table = sun4i_spi_match,
491 .pm = &sun4i_spi_pm_ops,
492 },
493};
494module_platform_driver(sun4i_spi_driver);
495
496MODULE_AUTHOR("Pan Nan <pannan@allwinnertech.com>");
497MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
498MODULE_DESCRIPTION("Allwinner A1X/A20 SPI controller driver");
499MODULE_LICENSE("GPL");