Pratik Patel | 2e1cdfe | 2015-05-13 10:34:09 -0600 | [diff] [blame] | 1 | /* Copyright (c) 2014, The Linux Foundation. All rights reserved. |
| 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | */ |
| 12 | |
| 13 | #include <linux/kernel.h> |
| 14 | #include <linux/moduleparam.h> |
| 15 | #include <linux/init.h> |
| 16 | #include <linux/types.h> |
| 17 | #include <linux/device.h> |
| 18 | #include <linux/io.h> |
| 19 | #include <linux/err.h> |
| 20 | #include <linux/fs.h> |
| 21 | #include <linux/slab.h> |
| 22 | #include <linux/delay.h> |
| 23 | #include <linux/smp.h> |
| 24 | #include <linux/sysfs.h> |
| 25 | #include <linux/stat.h> |
| 26 | #include <linux/clk.h> |
| 27 | #include <linux/cpu.h> |
| 28 | #include <linux/coresight.h> |
Mathieu Poirier | fc208ab | 2016-04-05 11:53:45 -0600 | [diff] [blame] | 29 | #include <linux/coresight-pmu.h> |
Pratik Patel | 2e1cdfe | 2015-05-13 10:34:09 -0600 | [diff] [blame] | 30 | #include <linux/pm_wakeup.h> |
| 31 | #include <linux/amba/bus.h> |
| 32 | #include <linux/seq_file.h> |
| 33 | #include <linux/uaccess.h> |
Mathieu Poirier | 37fbbdb | 2016-04-05 11:53:49 -0600 | [diff] [blame] | 34 | #include <linux/perf_event.h> |
Pratik Patel | 2e1cdfe | 2015-05-13 10:34:09 -0600 | [diff] [blame] | 35 | #include <linux/pm_runtime.h> |
Mathieu Poirier | 882d5e1 | 2016-02-17 17:51:57 -0700 | [diff] [blame] | 36 | #include <linux/perf_event.h> |
Pratik Patel | 2e1cdfe | 2015-05-13 10:34:09 -0600 | [diff] [blame] | 37 | #include <asm/sections.h> |
Mathieu Poirier | c38a9ec | 2016-04-05 11:53:47 -0600 | [diff] [blame] | 38 | #include <asm/local.h> |
Pratik Patel | 2e1cdfe | 2015-05-13 10:34:09 -0600 | [diff] [blame] | 39 | |
| 40 | #include "coresight-etm4x.h" |
Mathieu Poirier | 37fbbdb | 2016-04-05 11:53:49 -0600 | [diff] [blame] | 41 | #include "coresight-etm-perf.h" |
Pratik Patel | 2e1cdfe | 2015-05-13 10:34:09 -0600 | [diff] [blame] | 42 | |
| 43 | static int boot_enable; |
| 44 | module_param_named(boot_enable, boot_enable, int, S_IRUGO); |
| 45 | |
| 46 | /* The number of ETMv4 currently registered */ |
| 47 | static int etm4_count; |
| 48 | static struct etmv4_drvdata *etmdrvdata[NR_CPUS]; |
Mathieu Poirier | 37fbbdb | 2016-04-05 11:53:49 -0600 | [diff] [blame] | 49 | static void etm4_set_default(struct etmv4_config *config); |
Pratik Patel | 2e1cdfe | 2015-05-13 10:34:09 -0600 | [diff] [blame] | 50 | |
Sebastian Andrzej Siewior | 58eb457 | 2016-07-13 17:16:55 +0000 | [diff] [blame] | 51 | static enum cpuhp_state hp_online; |
| 52 | |
Mathieu Poirier | 66bbbb7 | 2016-04-05 11:53:46 -0600 | [diff] [blame] | 53 | static void etm4_os_unlock(struct etmv4_drvdata *drvdata) |
Pratik Patel | 2e1cdfe | 2015-05-13 10:34:09 -0600 | [diff] [blame] | 54 | { |
Pratik Patel | 2e1cdfe | 2015-05-13 10:34:09 -0600 | [diff] [blame] | 55 | /* Writing any value to ETMOSLAR unlocks the trace registers */ |
| 56 | writel_relaxed(0x0, drvdata->base + TRCOSLAR); |
Mathieu Poirier | 66bbbb7 | 2016-04-05 11:53:46 -0600 | [diff] [blame] | 57 | drvdata->os_unlock = true; |
Pratik Patel | 2e1cdfe | 2015-05-13 10:34:09 -0600 | [diff] [blame] | 58 | isb(); |
| 59 | } |
| 60 | |
| 61 | static bool etm4_arch_supported(u8 arch) |
| 62 | { |
| 63 | switch (arch) { |
| 64 | case ETM_ARCH_V4: |
| 65 | break; |
| 66 | default: |
| 67 | return false; |
| 68 | } |
| 69 | return true; |
| 70 | } |
| 71 | |
Mathieu Poirier | 52210c8 | 2016-02-02 14:14:01 -0700 | [diff] [blame] | 72 | static int etm4_cpu_id(struct coresight_device *csdev) |
| 73 | { |
| 74 | struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); |
| 75 | |
| 76 | return drvdata->cpu; |
| 77 | } |
| 78 | |
Pratik Patel | 2e1cdfe | 2015-05-13 10:34:09 -0600 | [diff] [blame] | 79 | static int etm4_trace_id(struct coresight_device *csdev) |
| 80 | { |
| 81 | struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); |
| 82 | unsigned long flags; |
| 83 | int trace_id = -1; |
| 84 | |
Mathieu Poirier | c38a9ec | 2016-04-05 11:53:47 -0600 | [diff] [blame] | 85 | if (!local_read(&drvdata->mode)) |
Pratik Patel | 2e1cdfe | 2015-05-13 10:34:09 -0600 | [diff] [blame] | 86 | return drvdata->trcid; |
| 87 | |
Pratik Patel | 2e1cdfe | 2015-05-13 10:34:09 -0600 | [diff] [blame] | 88 | spin_lock_irqsave(&drvdata->spinlock, flags); |
| 89 | |
| 90 | CS_UNLOCK(drvdata->base); |
| 91 | trace_id = readl_relaxed(drvdata->base + TRCTRACEIDR); |
| 92 | trace_id &= ETM_TRACEID_MASK; |
| 93 | CS_LOCK(drvdata->base); |
| 94 | |
| 95 | spin_unlock_irqrestore(&drvdata->spinlock, flags); |
Pratik Patel | 2e1cdfe | 2015-05-13 10:34:09 -0600 | [diff] [blame] | 96 | |
| 97 | return trace_id; |
| 98 | } |
| 99 | |
| 100 | static void etm4_enable_hw(void *info) |
| 101 | { |
| 102 | int i; |
| 103 | struct etmv4_drvdata *drvdata = info; |
Mathieu Poirier | 54ff892 | 2016-04-05 11:53:44 -0600 | [diff] [blame] | 104 | struct etmv4_config *config = &drvdata->config; |
Pratik Patel | 2e1cdfe | 2015-05-13 10:34:09 -0600 | [diff] [blame] | 105 | |
| 106 | CS_UNLOCK(drvdata->base); |
| 107 | |
| 108 | etm4_os_unlock(drvdata); |
| 109 | |
| 110 | /* Disable the trace unit before programming trace registers */ |
| 111 | writel_relaxed(0, drvdata->base + TRCPRGCTLR); |
| 112 | |
| 113 | /* wait for TRCSTATR.IDLE to go up */ |
| 114 | if (coresight_timeout(drvdata->base, TRCSTATR, TRCSTATR_IDLE_BIT, 1)) |
| 115 | dev_err(drvdata->dev, |
| 116 | "timeout observed when probing at offset %#x\n", |
| 117 | TRCSTATR); |
| 118 | |
Mathieu Poirier | 54ff892 | 2016-04-05 11:53:44 -0600 | [diff] [blame] | 119 | writel_relaxed(config->pe_sel, drvdata->base + TRCPROCSELR); |
| 120 | writel_relaxed(config->cfg, drvdata->base + TRCCONFIGR); |
Pratik Patel | 2e1cdfe | 2015-05-13 10:34:09 -0600 | [diff] [blame] | 121 | /* nothing specific implemented */ |
| 122 | writel_relaxed(0x0, drvdata->base + TRCAUXCTLR); |
Mathieu Poirier | 54ff892 | 2016-04-05 11:53:44 -0600 | [diff] [blame] | 123 | writel_relaxed(config->eventctrl0, drvdata->base + TRCEVENTCTL0R); |
| 124 | writel_relaxed(config->eventctrl1, drvdata->base + TRCEVENTCTL1R); |
| 125 | writel_relaxed(config->stall_ctrl, drvdata->base + TRCSTALLCTLR); |
| 126 | writel_relaxed(config->ts_ctrl, drvdata->base + TRCTSCTLR); |
| 127 | writel_relaxed(config->syncfreq, drvdata->base + TRCSYNCPR); |
| 128 | writel_relaxed(config->ccctlr, drvdata->base + TRCCCCTLR); |
| 129 | writel_relaxed(config->bb_ctrl, drvdata->base + TRCBBCTLR); |
Pratik Patel | 2e1cdfe | 2015-05-13 10:34:09 -0600 | [diff] [blame] | 130 | writel_relaxed(drvdata->trcid, drvdata->base + TRCTRACEIDR); |
Mathieu Poirier | 54ff892 | 2016-04-05 11:53:44 -0600 | [diff] [blame] | 131 | writel_relaxed(config->vinst_ctrl, drvdata->base + TRCVICTLR); |
| 132 | writel_relaxed(config->viiectlr, drvdata->base + TRCVIIECTLR); |
| 133 | writel_relaxed(config->vissctlr, |
Pratik Patel | 2e1cdfe | 2015-05-13 10:34:09 -0600 | [diff] [blame] | 134 | drvdata->base + TRCVISSCTLR); |
Mathieu Poirier | 54ff892 | 2016-04-05 11:53:44 -0600 | [diff] [blame] | 135 | writel_relaxed(config->vipcssctlr, |
Pratik Patel | 2e1cdfe | 2015-05-13 10:34:09 -0600 | [diff] [blame] | 136 | drvdata->base + TRCVIPCSSCTLR); |
| 137 | for (i = 0; i < drvdata->nrseqstate - 1; i++) |
Mathieu Poirier | 54ff892 | 2016-04-05 11:53:44 -0600 | [diff] [blame] | 138 | writel_relaxed(config->seq_ctrl[i], |
Pratik Patel | 2e1cdfe | 2015-05-13 10:34:09 -0600 | [diff] [blame] | 139 | drvdata->base + TRCSEQEVRn(i)); |
Mathieu Poirier | 54ff892 | 2016-04-05 11:53:44 -0600 | [diff] [blame] | 140 | writel_relaxed(config->seq_rst, drvdata->base + TRCSEQRSTEVR); |
| 141 | writel_relaxed(config->seq_state, drvdata->base + TRCSEQSTR); |
| 142 | writel_relaxed(config->ext_inp, drvdata->base + TRCEXTINSELR); |
Pratik Patel | 2e1cdfe | 2015-05-13 10:34:09 -0600 | [diff] [blame] | 143 | for (i = 0; i < drvdata->nr_cntr; i++) { |
Mathieu Poirier | 54ff892 | 2016-04-05 11:53:44 -0600 | [diff] [blame] | 144 | writel_relaxed(config->cntrldvr[i], |
Pratik Patel | 2e1cdfe | 2015-05-13 10:34:09 -0600 | [diff] [blame] | 145 | drvdata->base + TRCCNTRLDVRn(i)); |
Mathieu Poirier | 54ff892 | 2016-04-05 11:53:44 -0600 | [diff] [blame] | 146 | writel_relaxed(config->cntr_ctrl[i], |
Pratik Patel | 2e1cdfe | 2015-05-13 10:34:09 -0600 | [diff] [blame] | 147 | drvdata->base + TRCCNTCTLRn(i)); |
Mathieu Poirier | 54ff892 | 2016-04-05 11:53:44 -0600 | [diff] [blame] | 148 | writel_relaxed(config->cntr_val[i], |
Pratik Patel | 2e1cdfe | 2015-05-13 10:34:09 -0600 | [diff] [blame] | 149 | drvdata->base + TRCCNTVRn(i)); |
| 150 | } |
Chunyan Zhang | 497b595 | 2015-10-07 09:26:38 -0600 | [diff] [blame] | 151 | |
| 152 | /* Resource selector pair 0 is always implemented and reserved */ |
Mathieu Poirier | 54ff892 | 2016-04-05 11:53:44 -0600 | [diff] [blame] | 153 | for (i = 0; i < drvdata->nr_resource * 2; i++) |
| 154 | writel_relaxed(config->res_ctrl[i], |
Pratik Patel | 2e1cdfe | 2015-05-13 10:34:09 -0600 | [diff] [blame] | 155 | drvdata->base + TRCRSCTLRn(i)); |
| 156 | |
| 157 | for (i = 0; i < drvdata->nr_ss_cmp; i++) { |
Mathieu Poirier | 54ff892 | 2016-04-05 11:53:44 -0600 | [diff] [blame] | 158 | writel_relaxed(config->ss_ctrl[i], |
Pratik Patel | 2e1cdfe | 2015-05-13 10:34:09 -0600 | [diff] [blame] | 159 | drvdata->base + TRCSSCCRn(i)); |
Mathieu Poirier | 54ff892 | 2016-04-05 11:53:44 -0600 | [diff] [blame] | 160 | writel_relaxed(config->ss_status[i], |
Pratik Patel | 2e1cdfe | 2015-05-13 10:34:09 -0600 | [diff] [blame] | 161 | drvdata->base + TRCSSCSRn(i)); |
Mathieu Poirier | 54ff892 | 2016-04-05 11:53:44 -0600 | [diff] [blame] | 162 | writel_relaxed(config->ss_pe_cmp[i], |
Pratik Patel | 2e1cdfe | 2015-05-13 10:34:09 -0600 | [diff] [blame] | 163 | drvdata->base + TRCSSPCICRn(i)); |
| 164 | } |
| 165 | for (i = 0; i < drvdata->nr_addr_cmp; i++) { |
Mathieu Poirier | 54ff892 | 2016-04-05 11:53:44 -0600 | [diff] [blame] | 166 | writeq_relaxed(config->addr_val[i], |
Pratik Patel | 2e1cdfe | 2015-05-13 10:34:09 -0600 | [diff] [blame] | 167 | drvdata->base + TRCACVRn(i)); |
Mathieu Poirier | 54ff892 | 2016-04-05 11:53:44 -0600 | [diff] [blame] | 168 | writeq_relaxed(config->addr_acc[i], |
Pratik Patel | 2e1cdfe | 2015-05-13 10:34:09 -0600 | [diff] [blame] | 169 | drvdata->base + TRCACATRn(i)); |
| 170 | } |
| 171 | for (i = 0; i < drvdata->numcidc; i++) |
Mathieu Poirier | 54ff892 | 2016-04-05 11:53:44 -0600 | [diff] [blame] | 172 | writeq_relaxed(config->ctxid_pid[i], |
Pratik Patel | 2e1cdfe | 2015-05-13 10:34:09 -0600 | [diff] [blame] | 173 | drvdata->base + TRCCIDCVRn(i)); |
Mathieu Poirier | 54ff892 | 2016-04-05 11:53:44 -0600 | [diff] [blame] | 174 | writel_relaxed(config->ctxid_mask0, drvdata->base + TRCCIDCCTLR0); |
| 175 | writel_relaxed(config->ctxid_mask1, drvdata->base + TRCCIDCCTLR1); |
Pratik Patel | 2e1cdfe | 2015-05-13 10:34:09 -0600 | [diff] [blame] | 176 | |
| 177 | for (i = 0; i < drvdata->numvmidc; i++) |
Mathieu Poirier | 54ff892 | 2016-04-05 11:53:44 -0600 | [diff] [blame] | 178 | writeq_relaxed(config->vmid_val[i], |
Pratik Patel | 2e1cdfe | 2015-05-13 10:34:09 -0600 | [diff] [blame] | 179 | drvdata->base + TRCVMIDCVRn(i)); |
Mathieu Poirier | 54ff892 | 2016-04-05 11:53:44 -0600 | [diff] [blame] | 180 | writel_relaxed(config->vmid_mask0, drvdata->base + TRCVMIDCCTLR0); |
| 181 | writel_relaxed(config->vmid_mask1, drvdata->base + TRCVMIDCCTLR1); |
Pratik Patel | 2e1cdfe | 2015-05-13 10:34:09 -0600 | [diff] [blame] | 182 | |
| 183 | /* Enable the trace unit */ |
| 184 | writel_relaxed(1, drvdata->base + TRCPRGCTLR); |
| 185 | |
| 186 | /* wait for TRCSTATR.IDLE to go back down to '0' */ |
| 187 | if (coresight_timeout(drvdata->base, TRCSTATR, TRCSTATR_IDLE_BIT, 0)) |
| 188 | dev_err(drvdata->dev, |
| 189 | "timeout observed when probing at offset %#x\n", |
| 190 | TRCSTATR); |
| 191 | |
| 192 | CS_LOCK(drvdata->base); |
| 193 | |
| 194 | dev_dbg(drvdata->dev, "cpu: %d enable smp call done\n", drvdata->cpu); |
| 195 | } |
| 196 | |
Mathieu Poirier | 37fbbdb | 2016-04-05 11:53:49 -0600 | [diff] [blame] | 197 | static int etm4_parse_event_config(struct etmv4_drvdata *drvdata, |
| 198 | struct perf_event_attr *attr) |
| 199 | { |
| 200 | struct etmv4_config *config = &drvdata->config; |
| 201 | |
| 202 | if (!attr) |
| 203 | return -EINVAL; |
| 204 | |
| 205 | /* Clear configuration from previous run */ |
| 206 | memset(config, 0, sizeof(struct etmv4_config)); |
| 207 | |
| 208 | if (attr->exclude_kernel) |
| 209 | config->mode = ETM_MODE_EXCL_KERN; |
| 210 | |
| 211 | if (attr->exclude_user) |
| 212 | config->mode = ETM_MODE_EXCL_USER; |
| 213 | |
| 214 | /* Always start from the default config */ |
| 215 | etm4_set_default(config); |
| 216 | |
| 217 | /* |
| 218 | * By default the tracers are configured to trace the whole address |
| 219 | * range. Narrow the field only if requested by user space. |
| 220 | */ |
| 221 | if (config->mode) |
| 222 | etm4_config_trace_mode(config); |
| 223 | |
| 224 | /* Go from generic option to ETMv4 specifics */ |
| 225 | if (attr->config & BIT(ETM_OPT_CYCACC)) |
| 226 | config->cfg |= ETMv4_MODE_CYCACC; |
| 227 | if (attr->config & BIT(ETM_OPT_TS)) |
| 228 | config->cfg |= ETMv4_MODE_TIMESTAMP; |
| 229 | |
| 230 | return 0; |
| 231 | } |
| 232 | |
| 233 | static int etm4_enable_perf(struct coresight_device *csdev, |
| 234 | struct perf_event_attr *attr) |
| 235 | { |
| 236 | struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); |
| 237 | |
| 238 | if (WARN_ON_ONCE(drvdata->cpu != smp_processor_id())) |
| 239 | return -EINVAL; |
| 240 | |
| 241 | /* Configure the tracer based on the session's specifics */ |
| 242 | etm4_parse_event_config(drvdata, attr); |
| 243 | /* And enable it */ |
| 244 | etm4_enable_hw(drvdata); |
| 245 | |
| 246 | return 0; |
| 247 | } |
| 248 | |
Mathieu Poirier | c38a9ec | 2016-04-05 11:53:47 -0600 | [diff] [blame] | 249 | static int etm4_enable_sysfs(struct coresight_device *csdev) |
Pratik Patel | 2e1cdfe | 2015-05-13 10:34:09 -0600 | [diff] [blame] | 250 | { |
| 251 | struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); |
| 252 | int ret; |
| 253 | |
Pratik Patel | 2e1cdfe | 2015-05-13 10:34:09 -0600 | [diff] [blame] | 254 | spin_lock(&drvdata->spinlock); |
| 255 | |
| 256 | /* |
| 257 | * Executing etm4_enable_hw on the cpu whose ETM is being enabled |
| 258 | * ensures that register writes occur when cpu is powered. |
| 259 | */ |
| 260 | ret = smp_call_function_single(drvdata->cpu, |
| 261 | etm4_enable_hw, drvdata, 1); |
| 262 | if (ret) |
| 263 | goto err; |
Pratik Patel | 2e1cdfe | 2015-05-13 10:34:09 -0600 | [diff] [blame] | 264 | |
Mathieu Poirier | c38a9ec | 2016-04-05 11:53:47 -0600 | [diff] [blame] | 265 | drvdata->sticky_enable = true; |
Pratik Patel | 2e1cdfe | 2015-05-13 10:34:09 -0600 | [diff] [blame] | 266 | spin_unlock(&drvdata->spinlock); |
| 267 | |
| 268 | dev_info(drvdata->dev, "ETM tracing enabled\n"); |
| 269 | return 0; |
Mathieu Poirier | c38a9ec | 2016-04-05 11:53:47 -0600 | [diff] [blame] | 270 | |
Pratik Patel | 2e1cdfe | 2015-05-13 10:34:09 -0600 | [diff] [blame] | 271 | err: |
| 272 | spin_unlock(&drvdata->spinlock); |
Pratik Patel | 2e1cdfe | 2015-05-13 10:34:09 -0600 | [diff] [blame] | 273 | return ret; |
| 274 | } |
| 275 | |
Mathieu Poirier | c38a9ec | 2016-04-05 11:53:47 -0600 | [diff] [blame] | 276 | static int etm4_enable(struct coresight_device *csdev, |
| 277 | struct perf_event_attr *attr, u32 mode) |
| 278 | { |
| 279 | int ret; |
| 280 | u32 val; |
| 281 | struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); |
| 282 | |
| 283 | val = local_cmpxchg(&drvdata->mode, CS_MODE_DISABLED, mode); |
| 284 | |
| 285 | /* Someone is already using the tracer */ |
| 286 | if (val) |
| 287 | return -EBUSY; |
| 288 | |
| 289 | switch (mode) { |
| 290 | case CS_MODE_SYSFS: |
| 291 | ret = etm4_enable_sysfs(csdev); |
| 292 | break; |
Mathieu Poirier | 37fbbdb | 2016-04-05 11:53:49 -0600 | [diff] [blame] | 293 | case CS_MODE_PERF: |
| 294 | ret = etm4_enable_perf(csdev, attr); |
| 295 | break; |
Mathieu Poirier | c38a9ec | 2016-04-05 11:53:47 -0600 | [diff] [blame] | 296 | default: |
| 297 | ret = -EINVAL; |
| 298 | } |
| 299 | |
| 300 | /* The tracer didn't start */ |
| 301 | if (ret) |
| 302 | local_set(&drvdata->mode, CS_MODE_DISABLED); |
| 303 | |
| 304 | return ret; |
| 305 | } |
| 306 | |
Pratik Patel | 2e1cdfe | 2015-05-13 10:34:09 -0600 | [diff] [blame] | 307 | static void etm4_disable_hw(void *info) |
| 308 | { |
| 309 | u32 control; |
| 310 | struct etmv4_drvdata *drvdata = info; |
| 311 | |
| 312 | CS_UNLOCK(drvdata->base); |
| 313 | |
| 314 | control = readl_relaxed(drvdata->base + TRCPRGCTLR); |
| 315 | |
| 316 | /* EN, bit[0] Trace unit enable bit */ |
| 317 | control &= ~0x1; |
| 318 | |
| 319 | /* make sure everything completes before disabling */ |
| 320 | mb(); |
| 321 | isb(); |
| 322 | writel_relaxed(control, drvdata->base + TRCPRGCTLR); |
| 323 | |
| 324 | CS_LOCK(drvdata->base); |
| 325 | |
| 326 | dev_dbg(drvdata->dev, "cpu: %d disable smp call done\n", drvdata->cpu); |
| 327 | } |
| 328 | |
Mathieu Poirier | 37fbbdb | 2016-04-05 11:53:49 -0600 | [diff] [blame] | 329 | static int etm4_disable_perf(struct coresight_device *csdev) |
| 330 | { |
| 331 | struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); |
| 332 | |
| 333 | if (WARN_ON_ONCE(drvdata->cpu != smp_processor_id())) |
| 334 | return -EINVAL; |
| 335 | |
| 336 | etm4_disable_hw(drvdata); |
| 337 | return 0; |
| 338 | } |
| 339 | |
Mathieu Poirier | c38a9ec | 2016-04-05 11:53:47 -0600 | [diff] [blame] | 340 | static void etm4_disable_sysfs(struct coresight_device *csdev) |
Pratik Patel | 2e1cdfe | 2015-05-13 10:34:09 -0600 | [diff] [blame] | 341 | { |
| 342 | struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); |
| 343 | |
| 344 | /* |
| 345 | * Taking hotplug lock here protects from clocks getting disabled |
| 346 | * with tracing being left on (crash scenario) if user disable occurs |
| 347 | * after cpu online mask indicates the cpu is offline but before the |
| 348 | * DYING hotplug callback is serviced by the ETM driver. |
| 349 | */ |
| 350 | get_online_cpus(); |
| 351 | spin_lock(&drvdata->spinlock); |
| 352 | |
| 353 | /* |
| 354 | * Executing etm4_disable_hw on the cpu whose ETM is being disabled |
| 355 | * ensures that register writes occur when cpu is powered. |
| 356 | */ |
| 357 | smp_call_function_single(drvdata->cpu, etm4_disable_hw, drvdata, 1); |
Pratik Patel | 2e1cdfe | 2015-05-13 10:34:09 -0600 | [diff] [blame] | 358 | |
| 359 | spin_unlock(&drvdata->spinlock); |
| 360 | put_online_cpus(); |
| 361 | |
Pratik Patel | 2e1cdfe | 2015-05-13 10:34:09 -0600 | [diff] [blame] | 362 | dev_info(drvdata->dev, "ETM tracing disabled\n"); |
| 363 | } |
| 364 | |
Mathieu Poirier | c38a9ec | 2016-04-05 11:53:47 -0600 | [diff] [blame] | 365 | static void etm4_disable(struct coresight_device *csdev) |
| 366 | { |
| 367 | u32 mode; |
| 368 | struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); |
| 369 | |
| 370 | /* |
| 371 | * For as long as the tracer isn't disabled another entity can't |
| 372 | * change its status. As such we can read the status here without |
| 373 | * fearing it will change under us. |
| 374 | */ |
| 375 | mode = local_read(&drvdata->mode); |
| 376 | |
| 377 | switch (mode) { |
| 378 | case CS_MODE_DISABLED: |
| 379 | break; |
| 380 | case CS_MODE_SYSFS: |
| 381 | etm4_disable_sysfs(csdev); |
| 382 | break; |
Mathieu Poirier | 37fbbdb | 2016-04-05 11:53:49 -0600 | [diff] [blame] | 383 | case CS_MODE_PERF: |
| 384 | etm4_disable_perf(csdev); |
| 385 | break; |
Mathieu Poirier | c38a9ec | 2016-04-05 11:53:47 -0600 | [diff] [blame] | 386 | } |
| 387 | |
| 388 | if (mode) |
| 389 | local_set(&drvdata->mode, CS_MODE_DISABLED); |
| 390 | } |
| 391 | |
Pratik Patel | 2e1cdfe | 2015-05-13 10:34:09 -0600 | [diff] [blame] | 392 | static const struct coresight_ops_source etm4_source_ops = { |
Mathieu Poirier | 52210c8 | 2016-02-02 14:14:01 -0700 | [diff] [blame] | 393 | .cpu_id = etm4_cpu_id, |
Pratik Patel | 2e1cdfe | 2015-05-13 10:34:09 -0600 | [diff] [blame] | 394 | .trace_id = etm4_trace_id, |
| 395 | .enable = etm4_enable, |
| 396 | .disable = etm4_disable, |
| 397 | }; |
| 398 | |
| 399 | static const struct coresight_ops etm4_cs_ops = { |
| 400 | .source_ops = &etm4_source_ops, |
| 401 | }; |
| 402 | |
Pratik Patel | 2e1cdfe | 2015-05-13 10:34:09 -0600 | [diff] [blame] | 403 | static void etm4_init_arch_data(void *info) |
| 404 | { |
| 405 | u32 etmidr0; |
| 406 | u32 etmidr1; |
| 407 | u32 etmidr2; |
| 408 | u32 etmidr3; |
| 409 | u32 etmidr4; |
| 410 | u32 etmidr5; |
| 411 | struct etmv4_drvdata *drvdata = info; |
| 412 | |
Mathieu Poirier | 66bbbb7 | 2016-04-05 11:53:46 -0600 | [diff] [blame] | 413 | /* Make sure all registers are accessible */ |
| 414 | etm4_os_unlock(drvdata); |
| 415 | |
Pratik Patel | 2e1cdfe | 2015-05-13 10:34:09 -0600 | [diff] [blame] | 416 | CS_UNLOCK(drvdata->base); |
| 417 | |
| 418 | /* find all capabilities of the tracing unit */ |
| 419 | etmidr0 = readl_relaxed(drvdata->base + TRCIDR0); |
| 420 | |
| 421 | /* INSTP0, bits[2:1] P0 tracing support field */ |
| 422 | if (BMVAL(etmidr0, 1, 1) && BMVAL(etmidr0, 2, 2)) |
| 423 | drvdata->instrp0 = true; |
| 424 | else |
| 425 | drvdata->instrp0 = false; |
| 426 | |
| 427 | /* TRCBB, bit[5] Branch broadcast tracing support bit */ |
| 428 | if (BMVAL(etmidr0, 5, 5)) |
| 429 | drvdata->trcbb = true; |
| 430 | else |
| 431 | drvdata->trcbb = false; |
| 432 | |
| 433 | /* TRCCOND, bit[6] Conditional instruction tracing support bit */ |
| 434 | if (BMVAL(etmidr0, 6, 6)) |
| 435 | drvdata->trccond = true; |
| 436 | else |
| 437 | drvdata->trccond = false; |
| 438 | |
| 439 | /* TRCCCI, bit[7] Cycle counting instruction bit */ |
| 440 | if (BMVAL(etmidr0, 7, 7)) |
| 441 | drvdata->trccci = true; |
| 442 | else |
| 443 | drvdata->trccci = false; |
| 444 | |
| 445 | /* RETSTACK, bit[9] Return stack bit */ |
| 446 | if (BMVAL(etmidr0, 9, 9)) |
| 447 | drvdata->retstack = true; |
| 448 | else |
| 449 | drvdata->retstack = false; |
| 450 | |
| 451 | /* NUMEVENT, bits[11:10] Number of events field */ |
| 452 | drvdata->nr_event = BMVAL(etmidr0, 10, 11); |
| 453 | /* QSUPP, bits[16:15] Q element support field */ |
| 454 | drvdata->q_support = BMVAL(etmidr0, 15, 16); |
| 455 | /* TSSIZE, bits[28:24] Global timestamp size field */ |
| 456 | drvdata->ts_size = BMVAL(etmidr0, 24, 28); |
| 457 | |
| 458 | /* base architecture of trace unit */ |
| 459 | etmidr1 = readl_relaxed(drvdata->base + TRCIDR1); |
| 460 | /* |
| 461 | * TRCARCHMIN, bits[7:4] architecture the minor version number |
| 462 | * TRCARCHMAJ, bits[11:8] architecture major versin number |
| 463 | */ |
| 464 | drvdata->arch = BMVAL(etmidr1, 4, 11); |
| 465 | |
| 466 | /* maximum size of resources */ |
| 467 | etmidr2 = readl_relaxed(drvdata->base + TRCIDR2); |
| 468 | /* CIDSIZE, bits[9:5] Indicates the Context ID size */ |
| 469 | drvdata->ctxid_size = BMVAL(etmidr2, 5, 9); |
| 470 | /* VMIDSIZE, bits[14:10] Indicates the VMID size */ |
| 471 | drvdata->vmid_size = BMVAL(etmidr2, 10, 14); |
| 472 | /* CCSIZE, bits[28:25] size of the cycle counter in bits minus 12 */ |
| 473 | drvdata->ccsize = BMVAL(etmidr2, 25, 28); |
| 474 | |
| 475 | etmidr3 = readl_relaxed(drvdata->base + TRCIDR3); |
| 476 | /* CCITMIN, bits[11:0] minimum threshold value that can be programmed */ |
| 477 | drvdata->ccitmin = BMVAL(etmidr3, 0, 11); |
| 478 | /* EXLEVEL_S, bits[19:16] Secure state instruction tracing */ |
| 479 | drvdata->s_ex_level = BMVAL(etmidr3, 16, 19); |
| 480 | /* EXLEVEL_NS, bits[23:20] Non-secure state instruction tracing */ |
| 481 | drvdata->ns_ex_level = BMVAL(etmidr3, 20, 23); |
| 482 | |
| 483 | /* |
| 484 | * TRCERR, bit[24] whether a trace unit can trace a |
| 485 | * system error exception. |
| 486 | */ |
| 487 | if (BMVAL(etmidr3, 24, 24)) |
| 488 | drvdata->trc_error = true; |
| 489 | else |
| 490 | drvdata->trc_error = false; |
| 491 | |
| 492 | /* SYNCPR, bit[25] implementation has a fixed synchronization period? */ |
| 493 | if (BMVAL(etmidr3, 25, 25)) |
| 494 | drvdata->syncpr = true; |
| 495 | else |
| 496 | drvdata->syncpr = false; |
| 497 | |
| 498 | /* STALLCTL, bit[26] is stall control implemented? */ |
| 499 | if (BMVAL(etmidr3, 26, 26)) |
| 500 | drvdata->stallctl = true; |
| 501 | else |
| 502 | drvdata->stallctl = false; |
| 503 | |
| 504 | /* SYSSTALL, bit[27] implementation can support stall control? */ |
| 505 | if (BMVAL(etmidr3, 27, 27)) |
| 506 | drvdata->sysstall = true; |
| 507 | else |
| 508 | drvdata->sysstall = false; |
| 509 | |
| 510 | /* NUMPROC, bits[30:28] the number of PEs available for tracing */ |
| 511 | drvdata->nr_pe = BMVAL(etmidr3, 28, 30); |
| 512 | |
| 513 | /* NOOVERFLOW, bit[31] is trace overflow prevention supported */ |
| 514 | if (BMVAL(etmidr3, 31, 31)) |
| 515 | drvdata->nooverflow = true; |
| 516 | else |
| 517 | drvdata->nooverflow = false; |
| 518 | |
| 519 | /* number of resources trace unit supports */ |
| 520 | etmidr4 = readl_relaxed(drvdata->base + TRCIDR4); |
| 521 | /* NUMACPAIRS, bits[0:3] number of addr comparator pairs for tracing */ |
| 522 | drvdata->nr_addr_cmp = BMVAL(etmidr4, 0, 3); |
| 523 | /* NUMPC, bits[15:12] number of PE comparator inputs for tracing */ |
| 524 | drvdata->nr_pe_cmp = BMVAL(etmidr4, 12, 15); |
Chunyan Zhang | 497b595 | 2015-10-07 09:26:38 -0600 | [diff] [blame] | 525 | /* |
| 526 | * NUMRSPAIR, bits[19:16] |
| 527 | * The number of resource pairs conveyed by the HW starts at 0, i.e a |
| 528 | * value of 0x0 indicate 1 resource pair, 0x1 indicate two and so on. |
| 529 | * As such add 1 to the value of NUMRSPAIR for a better representation. |
| 530 | */ |
| 531 | drvdata->nr_resource = BMVAL(etmidr4, 16, 19) + 1; |
Pratik Patel | 2e1cdfe | 2015-05-13 10:34:09 -0600 | [diff] [blame] | 532 | /* |
| 533 | * NUMSSCC, bits[23:20] the number of single-shot |
| 534 | * comparator control for tracing |
| 535 | */ |
| 536 | drvdata->nr_ss_cmp = BMVAL(etmidr4, 20, 23); |
| 537 | /* NUMCIDC, bits[27:24] number of Context ID comparators for tracing */ |
| 538 | drvdata->numcidc = BMVAL(etmidr4, 24, 27); |
| 539 | /* NUMVMIDC, bits[31:28] number of VMID comparators for tracing */ |
| 540 | drvdata->numvmidc = BMVAL(etmidr4, 28, 31); |
| 541 | |
| 542 | etmidr5 = readl_relaxed(drvdata->base + TRCIDR5); |
| 543 | /* NUMEXTIN, bits[8:0] number of external inputs implemented */ |
| 544 | drvdata->nr_ext_inp = BMVAL(etmidr5, 0, 8); |
| 545 | /* TRACEIDSIZE, bits[21:16] indicates the trace ID width */ |
| 546 | drvdata->trcid_size = BMVAL(etmidr5, 16, 21); |
| 547 | /* ATBTRIG, bit[22] implementation can support ATB triggers? */ |
| 548 | if (BMVAL(etmidr5, 22, 22)) |
| 549 | drvdata->atbtrig = true; |
| 550 | else |
| 551 | drvdata->atbtrig = false; |
| 552 | /* |
| 553 | * LPOVERRIDE, bit[23] implementation supports |
| 554 | * low-power state override |
| 555 | */ |
| 556 | if (BMVAL(etmidr5, 23, 23)) |
| 557 | drvdata->lpoverride = true; |
| 558 | else |
| 559 | drvdata->lpoverride = false; |
| 560 | /* NUMSEQSTATE, bits[27:25] number of sequencer states implemented */ |
| 561 | drvdata->nrseqstate = BMVAL(etmidr5, 25, 27); |
| 562 | /* NUMCNTR, bits[30:28] number of counters available for tracing */ |
| 563 | drvdata->nr_cntr = BMVAL(etmidr5, 28, 30); |
| 564 | CS_LOCK(drvdata->base); |
| 565 | } |
| 566 | |
Mathieu Poirier | fc208ab | 2016-04-05 11:53:45 -0600 | [diff] [blame] | 567 | static void etm4_set_default(struct etmv4_config *config) |
Pratik Patel | 2e1cdfe | 2015-05-13 10:34:09 -0600 | [diff] [blame] | 568 | { |
Mathieu Poirier | fc208ab | 2016-04-05 11:53:45 -0600 | [diff] [blame] | 569 | if (WARN_ON_ONCE(!config)) |
| 570 | return; |
Pratik Patel | 2e1cdfe | 2015-05-13 10:34:09 -0600 | [diff] [blame] | 571 | |
Mathieu Poirier | fc208ab | 2016-04-05 11:53:45 -0600 | [diff] [blame] | 572 | /* |
| 573 | * Make default initialisation trace everything |
| 574 | * |
| 575 | * Select the "always true" resource selector on the |
| 576 | * "Enablign Event" line and configure address range comparator |
| 577 | * '0' to trace all the possible address range. From there |
| 578 | * configure the "include/exclude" engine to include address |
| 579 | * range comparator '0'. |
| 580 | */ |
Pratik Patel | 2e1cdfe | 2015-05-13 10:34:09 -0600 | [diff] [blame] | 581 | |
| 582 | /* disable all events tracing */ |
Mathieu Poirier | 54ff892 | 2016-04-05 11:53:44 -0600 | [diff] [blame] | 583 | config->eventctrl0 = 0x0; |
| 584 | config->eventctrl1 = 0x0; |
Pratik Patel | 2e1cdfe | 2015-05-13 10:34:09 -0600 | [diff] [blame] | 585 | |
| 586 | /* disable stalling */ |
Mathieu Poirier | 54ff892 | 2016-04-05 11:53:44 -0600 | [diff] [blame] | 587 | config->stall_ctrl = 0x0; |
Pratik Patel | 2e1cdfe | 2015-05-13 10:34:09 -0600 | [diff] [blame] | 588 | |
Mathieu Poirier | fc208ab | 2016-04-05 11:53:45 -0600 | [diff] [blame] | 589 | /* enable trace synchronization every 4096 bytes, if available */ |
| 590 | config->syncfreq = 0xC; |
| 591 | |
Pratik Patel | 2e1cdfe | 2015-05-13 10:34:09 -0600 | [diff] [blame] | 592 | /* disable timestamp event */ |
Mathieu Poirier | 54ff892 | 2016-04-05 11:53:44 -0600 | [diff] [blame] | 593 | config->ts_ctrl = 0x0; |
Pratik Patel | 2e1cdfe | 2015-05-13 10:34:09 -0600 | [diff] [blame] | 594 | |
Mathieu Poirier | fc208ab | 2016-04-05 11:53:45 -0600 | [diff] [blame] | 595 | /* TRCVICTLR::EVENT = 0x01, select the always on logic */ |
| 596 | config->vinst_ctrl |= BIT(0); |
Pratik Patel | 2e1cdfe | 2015-05-13 10:34:09 -0600 | [diff] [blame] | 597 | |
| 598 | /* |
Mathieu Poirier | fc208ab | 2016-04-05 11:53:45 -0600 | [diff] [blame] | 599 | * TRCVICTLR::SSSTATUS == 1, the start-stop logic is |
| 600 | * in the started state |
Pratik Patel | 2e1cdfe | 2015-05-13 10:34:09 -0600 | [diff] [blame] | 601 | */ |
Mathieu Poirier | fc208ab | 2016-04-05 11:53:45 -0600 | [diff] [blame] | 602 | config->vinst_ctrl |= BIT(9); |
Pratik Patel | 2e1cdfe | 2015-05-13 10:34:09 -0600 | [diff] [blame] | 603 | |
Mathieu Poirier | fc208ab | 2016-04-05 11:53:45 -0600 | [diff] [blame] | 604 | /* |
| 605 | * Configure address range comparator '0' to encompass all |
| 606 | * possible addresses. |
| 607 | */ |
| 608 | |
| 609 | /* First half of default address comparator: start at address 0 */ |
| 610 | config->addr_val[ETM_DEFAULT_ADDR_COMP] = 0x0; |
| 611 | /* trace instruction addresses */ |
| 612 | config->addr_acc[ETM_DEFAULT_ADDR_COMP] &= ~(BIT(0) | BIT(1)); |
| 613 | /* EXLEVEL_NS, bits[12:15], only trace application and kernel space */ |
| 614 | config->addr_acc[ETM_DEFAULT_ADDR_COMP] |= ETM_EXLEVEL_NS_HYP; |
| 615 | /* EXLEVEL_S, bits[11:8], don't trace anything in secure state */ |
| 616 | config->addr_acc[ETM_DEFAULT_ADDR_COMP] |= (ETM_EXLEVEL_S_APP | |
| 617 | ETM_EXLEVEL_S_OS | |
| 618 | ETM_EXLEVEL_S_HYP); |
| 619 | config->addr_type[ETM_DEFAULT_ADDR_COMP] = ETM_ADDR_TYPE_RANGE; |
| 620 | |
| 621 | /* |
| 622 | * Second half of default address comparator: go all |
| 623 | * the way to the top. |
| 624 | */ |
| 625 | config->addr_val[ETM_DEFAULT_ADDR_COMP + 1] = ~0x0; |
| 626 | /* trace instruction addresses */ |
| 627 | config->addr_acc[ETM_DEFAULT_ADDR_COMP + 1] &= ~(BIT(0) | BIT(1)); |
| 628 | /* Address comparator type must be equal for both halves */ |
| 629 | config->addr_acc[ETM_DEFAULT_ADDR_COMP + 1] = |
| 630 | config->addr_acc[ETM_DEFAULT_ADDR_COMP]; |
| 631 | config->addr_type[ETM_DEFAULT_ADDR_COMP + 1] = ETM_ADDR_TYPE_RANGE; |
| 632 | |
| 633 | /* |
| 634 | * Configure the ViewInst function to filter on address range |
| 635 | * comparator '0'. |
| 636 | */ |
| 637 | config->viiectlr = BIT(0); |
| 638 | |
Pratik Patel | 2e1cdfe | 2015-05-13 10:34:09 -0600 | [diff] [blame] | 639 | /* no start-stop filtering for ViewInst */ |
Mathieu Poirier | 54ff892 | 2016-04-05 11:53:44 -0600 | [diff] [blame] | 640 | config->vissctlr = 0x0; |
Pratik Patel | 2e1cdfe | 2015-05-13 10:34:09 -0600 | [diff] [blame] | 641 | } |
| 642 | |
Mathieu Poirier | 4f6fce5 | 2016-04-05 11:53:48 -0600 | [diff] [blame] | 643 | void etm4_config_trace_mode(struct etmv4_config *config) |
| 644 | { |
| 645 | u32 addr_acc, mode; |
| 646 | |
| 647 | mode = config->mode; |
| 648 | mode &= (ETM_MODE_EXCL_KERN | ETM_MODE_EXCL_USER); |
| 649 | |
| 650 | /* excluding kernel AND user space doesn't make sense */ |
| 651 | WARN_ON_ONCE(mode == (ETM_MODE_EXCL_KERN | ETM_MODE_EXCL_USER)); |
| 652 | |
| 653 | /* nothing to do if neither flags are set */ |
| 654 | if (!(mode & ETM_MODE_EXCL_KERN) && !(mode & ETM_MODE_EXCL_USER)) |
| 655 | return; |
| 656 | |
| 657 | addr_acc = config->addr_acc[ETM_DEFAULT_ADDR_COMP]; |
| 658 | /* clear default config */ |
| 659 | addr_acc &= ~(ETM_EXLEVEL_NS_APP | ETM_EXLEVEL_NS_OS); |
| 660 | |
| 661 | /* |
| 662 | * EXLEVEL_NS, bits[15:12] |
| 663 | * The Exception levels are: |
| 664 | * Bit[12] Exception level 0 - Application |
| 665 | * Bit[13] Exception level 1 - OS |
| 666 | * Bit[14] Exception level 2 - Hypervisor |
| 667 | * Bit[15] Never implemented |
| 668 | */ |
| 669 | if (mode & ETM_MODE_EXCL_KERN) |
| 670 | addr_acc |= ETM_EXLEVEL_NS_OS; |
| 671 | else |
| 672 | addr_acc |= ETM_EXLEVEL_NS_APP; |
| 673 | |
| 674 | config->addr_acc[ETM_DEFAULT_ADDR_COMP] = addr_acc; |
| 675 | config->addr_acc[ETM_DEFAULT_ADDR_COMP + 1] = addr_acc; |
| 676 | } |
| 677 | |
Sebastian Andrzej Siewior | 58eb457 | 2016-07-13 17:16:55 +0000 | [diff] [blame] | 678 | static int etm4_online_cpu(unsigned int cpu) |
Pratik Patel | 2e1cdfe | 2015-05-13 10:34:09 -0600 | [diff] [blame] | 679 | { |
Pratik Patel | 2e1cdfe | 2015-05-13 10:34:09 -0600 | [diff] [blame] | 680 | if (!etmdrvdata[cpu]) |
Sebastian Andrzej Siewior | 58eb457 | 2016-07-13 17:16:55 +0000 | [diff] [blame] | 681 | return 0; |
Pratik Patel | 2e1cdfe | 2015-05-13 10:34:09 -0600 | [diff] [blame] | 682 | |
Sebastian Andrzej Siewior | 58eb457 | 2016-07-13 17:16:55 +0000 | [diff] [blame] | 683 | if (etmdrvdata[cpu]->boot_enable && !etmdrvdata[cpu]->sticky_enable) |
| 684 | coresight_enable(etmdrvdata[cpu]->csdev); |
| 685 | return 0; |
Pratik Patel | 2e1cdfe | 2015-05-13 10:34:09 -0600 | [diff] [blame] | 686 | } |
| 687 | |
Sebastian Andrzej Siewior | 58eb457 | 2016-07-13 17:16:55 +0000 | [diff] [blame] | 688 | static int etm4_starting_cpu(unsigned int cpu) |
| 689 | { |
| 690 | if (!etmdrvdata[cpu]) |
| 691 | return 0; |
| 692 | |
| 693 | spin_lock(&etmdrvdata[cpu]->spinlock); |
| 694 | if (!etmdrvdata[cpu]->os_unlock) { |
| 695 | etm4_os_unlock(etmdrvdata[cpu]); |
| 696 | etmdrvdata[cpu]->os_unlock = true; |
| 697 | } |
| 698 | |
| 699 | if (local_read(&etmdrvdata[cpu]->mode)) |
| 700 | etm4_enable_hw(etmdrvdata[cpu]); |
| 701 | spin_unlock(&etmdrvdata[cpu]->spinlock); |
| 702 | return 0; |
| 703 | } |
| 704 | |
| 705 | static int etm4_dying_cpu(unsigned int cpu) |
| 706 | { |
| 707 | if (!etmdrvdata[cpu]) |
| 708 | return 0; |
| 709 | |
| 710 | spin_lock(&etmdrvdata[cpu]->spinlock); |
| 711 | if (local_read(&etmdrvdata[cpu]->mode)) |
| 712 | etm4_disable_hw(etmdrvdata[cpu]); |
| 713 | spin_unlock(&etmdrvdata[cpu]->spinlock); |
| 714 | return 0; |
| 715 | } |
Pratik Patel | 2e1cdfe | 2015-05-13 10:34:09 -0600 | [diff] [blame] | 716 | |
Mathieu Poirier | fc208ab | 2016-04-05 11:53:45 -0600 | [diff] [blame] | 717 | static void etm4_init_trace_id(struct etmv4_drvdata *drvdata) |
| 718 | { |
| 719 | drvdata->trcid = coresight_get_trace_id(drvdata->cpu); |
| 720 | } |
| 721 | |
Pratik Patel | 2e1cdfe | 2015-05-13 10:34:09 -0600 | [diff] [blame] | 722 | static int etm4_probe(struct amba_device *adev, const struct amba_id *id) |
| 723 | { |
| 724 | int ret; |
| 725 | void __iomem *base; |
| 726 | struct device *dev = &adev->dev; |
| 727 | struct coresight_platform_data *pdata = NULL; |
| 728 | struct etmv4_drvdata *drvdata; |
| 729 | struct resource *res = &adev->res; |
| 730 | struct coresight_desc *desc; |
| 731 | struct device_node *np = adev->dev.of_node; |
| 732 | |
| 733 | desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL); |
| 734 | if (!desc) |
| 735 | return -ENOMEM; |
| 736 | |
| 737 | drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); |
| 738 | if (!drvdata) |
| 739 | return -ENOMEM; |
| 740 | |
| 741 | if (np) { |
| 742 | pdata = of_get_coresight_platform_data(dev, np); |
| 743 | if (IS_ERR(pdata)) |
| 744 | return PTR_ERR(pdata); |
| 745 | adev->dev.platform_data = pdata; |
| 746 | } |
| 747 | |
| 748 | drvdata->dev = &adev->dev; |
| 749 | dev_set_drvdata(dev, drvdata); |
| 750 | |
| 751 | /* Validity for the resource is already checked by the AMBA core */ |
| 752 | base = devm_ioremap_resource(dev, res); |
| 753 | if (IS_ERR(base)) |
| 754 | return PTR_ERR(base); |
| 755 | |
| 756 | drvdata->base = base; |
| 757 | |
| 758 | spin_lock_init(&drvdata->spinlock); |
| 759 | |
| 760 | drvdata->cpu = pdata ? pdata->cpu : 0; |
| 761 | |
| 762 | get_online_cpus(); |
| 763 | etmdrvdata[drvdata->cpu] = drvdata; |
| 764 | |
Pratik Patel | 2e1cdfe | 2015-05-13 10:34:09 -0600 | [diff] [blame] | 765 | if (smp_call_function_single(drvdata->cpu, |
| 766 | etm4_init_arch_data, drvdata, 1)) |
| 767 | dev_err(dev, "ETM arch init failed\n"); |
| 768 | |
Sebastian Andrzej Siewior | 58eb457 | 2016-07-13 17:16:55 +0000 | [diff] [blame] | 769 | if (!etm4_count++) { |
| 770 | cpuhp_setup_state_nocalls(CPUHP_AP_ARM_CORESIGHT4_STARTING, |
| 771 | "AP_ARM_CORESIGHT4_STARTING", |
| 772 | etm4_starting_cpu, etm4_dying_cpu); |
| 773 | ret = cpuhp_setup_state_nocalls(CPUHP_AP_ONLINE_DYN, |
| 774 | "AP_ARM_CORESIGHT4_ONLINE", |
| 775 | etm4_online_cpu, NULL); |
| 776 | if (ret < 0) |
| 777 | goto err_arch_supported; |
| 778 | hp_online = ret; |
| 779 | } |
Pratik Patel | 2e1cdfe | 2015-05-13 10:34:09 -0600 | [diff] [blame] | 780 | |
| 781 | put_online_cpus(); |
| 782 | |
| 783 | if (etm4_arch_supported(drvdata->arch) == false) { |
| 784 | ret = -EINVAL; |
| 785 | goto err_arch_supported; |
| 786 | } |
Mathieu Poirier | fc208ab | 2016-04-05 11:53:45 -0600 | [diff] [blame] | 787 | |
| 788 | etm4_init_trace_id(drvdata); |
| 789 | etm4_set_default(&drvdata->config); |
Pratik Patel | 2e1cdfe | 2015-05-13 10:34:09 -0600 | [diff] [blame] | 790 | |
Pratik Patel | 2e1cdfe | 2015-05-13 10:34:09 -0600 | [diff] [blame] | 791 | desc->type = CORESIGHT_DEV_TYPE_SOURCE; |
| 792 | desc->subtype.source_subtype = CORESIGHT_DEV_SUBTYPE_SOURCE_PROC; |
| 793 | desc->ops = &etm4_cs_ops; |
| 794 | desc->pdata = pdata; |
| 795 | desc->dev = dev; |
| 796 | desc->groups = coresight_etmv4_groups; |
| 797 | drvdata->csdev = coresight_register(desc); |
| 798 | if (IS_ERR(drvdata->csdev)) { |
| 799 | ret = PTR_ERR(drvdata->csdev); |
Mathieu Poirier | 37fbbdb | 2016-04-05 11:53:49 -0600 | [diff] [blame] | 800 | goto err_arch_supported; |
Pratik Patel | 2e1cdfe | 2015-05-13 10:34:09 -0600 | [diff] [blame] | 801 | } |
| 802 | |
Mathieu Poirier | 37fbbdb | 2016-04-05 11:53:49 -0600 | [diff] [blame] | 803 | ret = etm_perf_symlink(drvdata->csdev, true); |
| 804 | if (ret) { |
| 805 | coresight_unregister(drvdata->csdev); |
| 806 | goto err_arch_supported; |
| 807 | } |
| 808 | |
| 809 | pm_runtime_put(&adev->dev); |
Pratik Patel | 2e1cdfe | 2015-05-13 10:34:09 -0600 | [diff] [blame] | 810 | dev_info(dev, "%s initialized\n", (char *)id->data); |
| 811 | |
| 812 | if (boot_enable) { |
| 813 | coresight_enable(drvdata->csdev); |
| 814 | drvdata->boot_enable = true; |
| 815 | } |
| 816 | |
| 817 | return 0; |
| 818 | |
| 819 | err_arch_supported: |
Sebastian Andrzej Siewior | 58eb457 | 2016-07-13 17:16:55 +0000 | [diff] [blame] | 820 | if (--etm4_count == 0) { |
| 821 | cpuhp_remove_state_nocalls(CPUHP_AP_ARM_CORESIGHT4_STARTING); |
| 822 | if (hp_online) |
| 823 | cpuhp_remove_state_nocalls(hp_online); |
| 824 | } |
Pratik Patel | 2e1cdfe | 2015-05-13 10:34:09 -0600 | [diff] [blame] | 825 | return ret; |
| 826 | } |
| 827 | |
Pratik Patel | 2e1cdfe | 2015-05-13 10:34:09 -0600 | [diff] [blame] | 828 | static struct amba_id etm4_ids[] = { |
| 829 | { /* ETM 4.0 - Qualcomm */ |
| 830 | .id = 0x0003b95d, |
| 831 | .mask = 0x0003ffff, |
| 832 | .data = "ETM 4.0", |
| 833 | }, |
| 834 | { /* ETM 4.0 - Juno board */ |
| 835 | .id = 0x000bb95e, |
| 836 | .mask = 0x000fffff, |
| 837 | .data = "ETM 4.0", |
| 838 | }, |
Li Pengcheng | 960e309 | 2016-05-03 11:33:42 -0600 | [diff] [blame] | 839 | { /* ETM 4.0 - A72, Maia, HiSilicon */ |
| 840 | .id = 0x000bb95a, |
| 841 | .mask = 0x000fffff, |
| 842 | .data = "ETM 4.0", |
| 843 | }, |
Pratik Patel | 2e1cdfe | 2015-05-13 10:34:09 -0600 | [diff] [blame] | 844 | { 0, 0}, |
| 845 | }; |
| 846 | |
| 847 | static struct amba_driver etm4x_driver = { |
| 848 | .drv = { |
| 849 | .name = "coresight-etm4x", |
Mathieu Poirier | b15f0fb | 2016-02-02 14:14:00 -0700 | [diff] [blame] | 850 | .suppress_bind_attrs = true, |
Pratik Patel | 2e1cdfe | 2015-05-13 10:34:09 -0600 | [diff] [blame] | 851 | }, |
| 852 | .probe = etm4_probe, |
Pratik Patel | 2e1cdfe | 2015-05-13 10:34:09 -0600 | [diff] [blame] | 853 | .id_table = etm4_ids, |
| 854 | }; |
Paul Gortmaker | 941943c | 2016-02-17 17:52:03 -0700 | [diff] [blame] | 855 | builtin_amba_driver(etm4x_driver); |