Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2012 Red Hat Inc. |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice shall be included in |
| 12 | * all copies or substantial portions of the Software. |
| 13 | * |
| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 20 | * OTHER DEALINGS IN THE SOFTWARE. |
| 21 | * |
| 22 | * Authors: Ben Skeggs |
| 23 | */ |
| 24 | |
Ben Skeggs | 370c00f | 2012-08-14 14:11:49 +1000 | [diff] [blame] | 25 | #include <core/object.h> |
| 26 | #include <core/parent.h> |
| 27 | #include <core/handle.h> |
| 28 | #include <core/class.h> |
| 29 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 30 | #include <engine/disp.h> |
| 31 | |
Ben Skeggs | 186ecad | 2012-11-09 12:09:48 +1000 | [diff] [blame] | 32 | #include <subdev/bios.h> |
| 33 | #include <subdev/bios/dcb.h> |
| 34 | #include <subdev/bios/disp.h> |
| 35 | #include <subdev/bios/init.h> |
| 36 | #include <subdev/bios/pll.h> |
Ben Skeggs | 446b05a | 2012-08-14 12:50:14 +1000 | [diff] [blame] | 37 | #include <subdev/timer.h> |
Ben Skeggs | 370c00f | 2012-08-14 14:11:49 +1000 | [diff] [blame] | 38 | #include <subdev/fb.h> |
Ben Skeggs | 186ecad | 2012-11-09 12:09:48 +1000 | [diff] [blame] | 39 | #include <subdev/clock.h> |
Ben Skeggs | 446b05a | 2012-08-14 12:50:14 +1000 | [diff] [blame] | 40 | |
Ben Skeggs | 70cabe4 | 2012-08-14 10:04:04 +1000 | [diff] [blame] | 41 | #include "nv50.h" |
| 42 | |
| 43 | /******************************************************************************* |
Ben Skeggs | 370c00f | 2012-08-14 14:11:49 +1000 | [diff] [blame] | 44 | * EVO channel base class |
Ben Skeggs | 70cabe4 | 2012-08-14 10:04:04 +1000 | [diff] [blame] | 45 | ******************************************************************************/ |
| 46 | |
Ben Skeggs | 370c00f | 2012-08-14 14:11:49 +1000 | [diff] [blame] | 47 | int |
| 48 | nv50_disp_chan_create_(struct nouveau_object *parent, |
| 49 | struct nouveau_object *engine, |
| 50 | struct nouveau_oclass *oclass, int chid, |
| 51 | int length, void **pobject) |
| 52 | { |
| 53 | struct nv50_disp_base *base = (void *)parent; |
| 54 | struct nv50_disp_chan *chan; |
| 55 | int ret; |
| 56 | |
| 57 | if (base->chan & (1 << chid)) |
| 58 | return -EBUSY; |
| 59 | base->chan |= (1 << chid); |
| 60 | |
| 61 | ret = nouveau_namedb_create_(parent, engine, oclass, 0, NULL, |
| 62 | (1ULL << NVDEV_ENGINE_DMAOBJ), |
| 63 | length, pobject); |
| 64 | chan = *pobject; |
| 65 | if (ret) |
| 66 | return ret; |
| 67 | |
| 68 | chan->chid = chid; |
| 69 | return 0; |
| 70 | } |
| 71 | |
| 72 | void |
| 73 | nv50_disp_chan_destroy(struct nv50_disp_chan *chan) |
| 74 | { |
| 75 | struct nv50_disp_base *base = (void *)nv_object(chan)->parent; |
| 76 | base->chan &= ~(1 << chan->chid); |
| 77 | nouveau_namedb_destroy(&chan->base); |
| 78 | } |
| 79 | |
| 80 | u32 |
Ben Skeggs | 70cabe4 | 2012-08-14 10:04:04 +1000 | [diff] [blame] | 81 | nv50_disp_chan_rd32(struct nouveau_object *object, u64 addr) |
| 82 | { |
Ben Skeggs | 370c00f | 2012-08-14 14:11:49 +1000 | [diff] [blame] | 83 | struct nv50_disp_priv *priv = (void *)object->engine; |
| 84 | struct nv50_disp_chan *chan = (void *)object; |
| 85 | return nv_rd32(priv, 0x640000 + (chan->chid * 0x1000) + addr); |
| 86 | } |
| 87 | |
| 88 | void |
| 89 | nv50_disp_chan_wr32(struct nouveau_object *object, u64 addr, u32 data) |
| 90 | { |
| 91 | struct nv50_disp_priv *priv = (void *)object->engine; |
| 92 | struct nv50_disp_chan *chan = (void *)object; |
| 93 | nv_wr32(priv, 0x640000 + (chan->chid * 0x1000) + addr, data); |
| 94 | } |
| 95 | |
| 96 | /******************************************************************************* |
| 97 | * EVO DMA channel base class |
| 98 | ******************************************************************************/ |
| 99 | |
| 100 | static int |
| 101 | nv50_disp_dmac_object_attach(struct nouveau_object *parent, |
| 102 | struct nouveau_object *object, u32 name) |
| 103 | { |
| 104 | struct nv50_disp_base *base = (void *)parent->parent; |
| 105 | struct nv50_disp_chan *chan = (void *)parent; |
| 106 | u32 addr = nv_gpuobj(object)->node->offset; |
| 107 | u32 chid = chan->chid; |
| 108 | u32 data = (chid << 28) | (addr << 10) | chid; |
| 109 | return nouveau_ramht_insert(base->ramht, chid, name, data); |
Ben Skeggs | 70cabe4 | 2012-08-14 10:04:04 +1000 | [diff] [blame] | 110 | } |
| 111 | |
| 112 | static void |
Ben Skeggs | 370c00f | 2012-08-14 14:11:49 +1000 | [diff] [blame] | 113 | nv50_disp_dmac_object_detach(struct nouveau_object *parent, int cookie) |
Ben Skeggs | 70cabe4 | 2012-08-14 10:04:04 +1000 | [diff] [blame] | 114 | { |
Ben Skeggs | 370c00f | 2012-08-14 14:11:49 +1000 | [diff] [blame] | 115 | struct nv50_disp_base *base = (void *)parent->parent; |
| 116 | nouveau_ramht_remove(base->ramht, cookie); |
| 117 | } |
| 118 | |
| 119 | int |
| 120 | nv50_disp_dmac_create_(struct nouveau_object *parent, |
| 121 | struct nouveau_object *engine, |
| 122 | struct nouveau_oclass *oclass, u32 pushbuf, int chid, |
| 123 | int length, void **pobject) |
| 124 | { |
| 125 | struct nv50_disp_dmac *dmac; |
| 126 | int ret; |
| 127 | |
| 128 | ret = nv50_disp_chan_create_(parent, engine, oclass, chid, |
| 129 | length, pobject); |
| 130 | dmac = *pobject; |
| 131 | if (ret) |
| 132 | return ret; |
| 133 | |
| 134 | dmac->pushdma = (void *)nouveau_handle_ref(parent, pushbuf); |
| 135 | if (!dmac->pushdma) |
| 136 | return -ENOENT; |
| 137 | |
| 138 | switch (nv_mclass(dmac->pushdma)) { |
| 139 | case 0x0002: |
| 140 | case 0x003d: |
| 141 | if (dmac->pushdma->limit - dmac->pushdma->start != 0xfff) |
| 142 | return -EINVAL; |
| 143 | |
| 144 | switch (dmac->pushdma->target) { |
| 145 | case NV_MEM_TARGET_VRAM: |
| 146 | dmac->push = 0x00000000 | dmac->pushdma->start >> 8; |
| 147 | break; |
Ben Skeggs | 944234d | 2012-10-30 10:03:38 +1000 | [diff] [blame] | 148 | case NV_MEM_TARGET_PCI_NOSNOOP: |
| 149 | dmac->push = 0x00000003 | dmac->pushdma->start >> 8; |
| 150 | break; |
Ben Skeggs | 370c00f | 2012-08-14 14:11:49 +1000 | [diff] [blame] | 151 | default: |
| 152 | return -EINVAL; |
| 153 | } |
| 154 | break; |
| 155 | default: |
| 156 | return -EINVAL; |
| 157 | } |
| 158 | |
| 159 | return 0; |
| 160 | } |
| 161 | |
| 162 | void |
| 163 | nv50_disp_dmac_dtor(struct nouveau_object *object) |
| 164 | { |
| 165 | struct nv50_disp_dmac *dmac = (void *)object; |
| 166 | nouveau_object_ref(NULL, (struct nouveau_object **)&dmac->pushdma); |
| 167 | nv50_disp_chan_destroy(&dmac->base); |
| 168 | } |
| 169 | |
| 170 | static int |
| 171 | nv50_disp_dmac_init(struct nouveau_object *object) |
| 172 | { |
| 173 | struct nv50_disp_priv *priv = (void *)object->engine; |
| 174 | struct nv50_disp_dmac *dmac = (void *)object; |
| 175 | int chid = dmac->base.chid; |
| 176 | int ret; |
| 177 | |
| 178 | ret = nv50_disp_chan_init(&dmac->base); |
| 179 | if (ret) |
| 180 | return ret; |
| 181 | |
| 182 | /* enable error reporting */ |
| 183 | nv_mask(priv, 0x610028, 0x00010001 << chid, 0x00010001 << chid); |
| 184 | |
| 185 | /* initialise channel for dma command submission */ |
| 186 | nv_wr32(priv, 0x610204 + (chid * 0x0010), dmac->push); |
| 187 | nv_wr32(priv, 0x610208 + (chid * 0x0010), 0x00010000); |
| 188 | nv_wr32(priv, 0x61020c + (chid * 0x0010), chid); |
| 189 | nv_mask(priv, 0x610200 + (chid * 0x0010), 0x00000010, 0x00000010); |
| 190 | nv_wr32(priv, 0x640000 + (chid * 0x1000), 0x00000000); |
| 191 | nv_wr32(priv, 0x610200 + (chid * 0x0010), 0x00000013); |
| 192 | |
| 193 | /* wait for it to go inactive */ |
| 194 | if (!nv_wait(priv, 0x610200 + (chid * 0x10), 0x80000000, 0x00000000)) { |
| 195 | nv_error(dmac, "init timeout, 0x%08x\n", |
| 196 | nv_rd32(priv, 0x610200 + (chid * 0x10))); |
| 197 | return -EBUSY; |
| 198 | } |
| 199 | |
| 200 | return 0; |
| 201 | } |
| 202 | |
| 203 | static int |
| 204 | nv50_disp_dmac_fini(struct nouveau_object *object, bool suspend) |
| 205 | { |
| 206 | struct nv50_disp_priv *priv = (void *)object->engine; |
| 207 | struct nv50_disp_dmac *dmac = (void *)object; |
| 208 | int chid = dmac->base.chid; |
| 209 | |
| 210 | /* deactivate channel */ |
| 211 | nv_mask(priv, 0x610200 + (chid * 0x0010), 0x00001010, 0x00001000); |
| 212 | nv_mask(priv, 0x610200 + (chid * 0x0010), 0x00000003, 0x00000000); |
| 213 | if (!nv_wait(priv, 0x610200 + (chid * 0x10), 0x001e0000, 0x00000000)) { |
| 214 | nv_error(dmac, "fini timeout, 0x%08x\n", |
| 215 | nv_rd32(priv, 0x610200 + (chid * 0x10))); |
| 216 | if (suspend) |
| 217 | return -EBUSY; |
| 218 | } |
| 219 | |
| 220 | /* disable error reporting */ |
| 221 | nv_mask(priv, 0x610028, 0x00010001 << chid, 0x00000000 << chid); |
| 222 | |
| 223 | return nv50_disp_chan_fini(&dmac->base, suspend); |
Ben Skeggs | 70cabe4 | 2012-08-14 10:04:04 +1000 | [diff] [blame] | 224 | } |
| 225 | |
| 226 | /******************************************************************************* |
| 227 | * EVO master channel object |
| 228 | ******************************************************************************/ |
| 229 | |
| 230 | static int |
| 231 | nv50_disp_mast_ctor(struct nouveau_object *parent, |
| 232 | struct nouveau_object *engine, |
| 233 | struct nouveau_oclass *oclass, void *data, u32 size, |
| 234 | struct nouveau_object **pobject) |
| 235 | { |
Ben Skeggs | 370c00f | 2012-08-14 14:11:49 +1000 | [diff] [blame] | 236 | struct nv50_display_mast_class *args = data; |
| 237 | struct nv50_disp_dmac *mast; |
Ben Skeggs | 70cabe4 | 2012-08-14 10:04:04 +1000 | [diff] [blame] | 238 | int ret; |
| 239 | |
Ben Skeggs | 370c00f | 2012-08-14 14:11:49 +1000 | [diff] [blame] | 240 | if (size < sizeof(*args)) |
| 241 | return -EINVAL; |
| 242 | |
| 243 | ret = nv50_disp_dmac_create_(parent, engine, oclass, args->pushbuf, |
| 244 | 0, sizeof(*mast), (void **)&mast); |
| 245 | *pobject = nv_object(mast); |
Ben Skeggs | 70cabe4 | 2012-08-14 10:04:04 +1000 | [diff] [blame] | 246 | if (ret) |
| 247 | return ret; |
| 248 | |
Ben Skeggs | 370c00f | 2012-08-14 14:11:49 +1000 | [diff] [blame] | 249 | nv_parent(mast)->object_attach = nv50_disp_dmac_object_attach; |
| 250 | nv_parent(mast)->object_detach = nv50_disp_dmac_object_detach; |
Ben Skeggs | 70cabe4 | 2012-08-14 10:04:04 +1000 | [diff] [blame] | 251 | return 0; |
| 252 | } |
| 253 | |
Ben Skeggs | 70cabe4 | 2012-08-14 10:04:04 +1000 | [diff] [blame] | 254 | static int |
| 255 | nv50_disp_mast_init(struct nouveau_object *object) |
| 256 | { |
Ben Skeggs | 370c00f | 2012-08-14 14:11:49 +1000 | [diff] [blame] | 257 | struct nv50_disp_priv *priv = (void *)object->engine; |
| 258 | struct nv50_disp_dmac *mast = (void *)object; |
Ben Skeggs | 70cabe4 | 2012-08-14 10:04:04 +1000 | [diff] [blame] | 259 | int ret; |
| 260 | |
Ben Skeggs | 370c00f | 2012-08-14 14:11:49 +1000 | [diff] [blame] | 261 | ret = nv50_disp_chan_init(&mast->base); |
Ben Skeggs | 70cabe4 | 2012-08-14 10:04:04 +1000 | [diff] [blame] | 262 | if (ret) |
| 263 | return ret; |
| 264 | |
Ben Skeggs | 370c00f | 2012-08-14 14:11:49 +1000 | [diff] [blame] | 265 | /* enable error reporting */ |
| 266 | nv_mask(priv, 0x610028, 0x00010001, 0x00010001); |
| 267 | |
| 268 | /* attempt to unstick channel from some unknown state */ |
| 269 | if ((nv_rd32(priv, 0x610200) & 0x009f0000) == 0x00020000) |
| 270 | nv_mask(priv, 0x610200, 0x00800000, 0x00800000); |
| 271 | if ((nv_rd32(priv, 0x610200) & 0x003f0000) == 0x00030000) |
| 272 | nv_mask(priv, 0x610200, 0x00600000, 0x00600000); |
| 273 | |
| 274 | /* initialise channel for dma command submission */ |
| 275 | nv_wr32(priv, 0x610204, mast->push); |
| 276 | nv_wr32(priv, 0x610208, 0x00010000); |
| 277 | nv_wr32(priv, 0x61020c, 0x00000000); |
| 278 | nv_mask(priv, 0x610200, 0x00000010, 0x00000010); |
| 279 | nv_wr32(priv, 0x640000, 0x00000000); |
| 280 | nv_wr32(priv, 0x610200, 0x01000013); |
| 281 | |
| 282 | /* wait for it to go inactive */ |
| 283 | if (!nv_wait(priv, 0x610200, 0x80000000, 0x00000000)) { |
| 284 | nv_error(mast, "init: 0x%08x\n", nv_rd32(priv, 0x610200)); |
| 285 | return -EBUSY; |
| 286 | } |
| 287 | |
Ben Skeggs | 70cabe4 | 2012-08-14 10:04:04 +1000 | [diff] [blame] | 288 | return 0; |
| 289 | } |
| 290 | |
| 291 | static int |
| 292 | nv50_disp_mast_fini(struct nouveau_object *object, bool suspend) |
| 293 | { |
Ben Skeggs | 370c00f | 2012-08-14 14:11:49 +1000 | [diff] [blame] | 294 | struct nv50_disp_priv *priv = (void *)object->engine; |
| 295 | struct nv50_disp_dmac *mast = (void *)object; |
| 296 | |
| 297 | /* deactivate channel */ |
| 298 | nv_mask(priv, 0x610200, 0x00000010, 0x00000000); |
| 299 | nv_mask(priv, 0x610200, 0x00000003, 0x00000000); |
| 300 | if (!nv_wait(priv, 0x610200, 0x001e0000, 0x00000000)) { |
| 301 | nv_error(mast, "fini: 0x%08x\n", nv_rd32(priv, 0x610200)); |
| 302 | if (suspend) |
| 303 | return -EBUSY; |
| 304 | } |
| 305 | |
| 306 | /* disable error reporting */ |
| 307 | nv_mask(priv, 0x610028, 0x00010001, 0x00000000); |
| 308 | |
| 309 | return nv50_disp_chan_fini(&mast->base, suspend); |
Ben Skeggs | 70cabe4 | 2012-08-14 10:04:04 +1000 | [diff] [blame] | 310 | } |
| 311 | |
| 312 | struct nouveau_ofuncs |
| 313 | nv50_disp_mast_ofuncs = { |
| 314 | .ctor = nv50_disp_mast_ctor, |
Ben Skeggs | 370c00f | 2012-08-14 14:11:49 +1000 | [diff] [blame] | 315 | .dtor = nv50_disp_dmac_dtor, |
Ben Skeggs | 70cabe4 | 2012-08-14 10:04:04 +1000 | [diff] [blame] | 316 | .init = nv50_disp_mast_init, |
| 317 | .fini = nv50_disp_mast_fini, |
| 318 | .rd32 = nv50_disp_chan_rd32, |
| 319 | .wr32 = nv50_disp_chan_wr32, |
| 320 | }; |
| 321 | |
| 322 | /******************************************************************************* |
Ben Skeggs | 370c00f | 2012-08-14 14:11:49 +1000 | [diff] [blame] | 323 | * EVO sync channel objects |
Ben Skeggs | 70cabe4 | 2012-08-14 10:04:04 +1000 | [diff] [blame] | 324 | ******************************************************************************/ |
| 325 | |
| 326 | static int |
Ben Skeggs | 370c00f | 2012-08-14 14:11:49 +1000 | [diff] [blame] | 327 | nv50_disp_sync_ctor(struct nouveau_object *parent, |
Ben Skeggs | 70cabe4 | 2012-08-14 10:04:04 +1000 | [diff] [blame] | 328 | struct nouveau_object *engine, |
| 329 | struct nouveau_oclass *oclass, void *data, u32 size, |
| 330 | struct nouveau_object **pobject) |
| 331 | { |
Ben Skeggs | 370c00f | 2012-08-14 14:11:49 +1000 | [diff] [blame] | 332 | struct nv50_display_sync_class *args = data; |
| 333 | struct nv50_disp_dmac *dmac; |
Ben Skeggs | 70cabe4 | 2012-08-14 10:04:04 +1000 | [diff] [blame] | 334 | int ret; |
| 335 | |
Dan Carpenter | af1ac18 | 2013-01-23 11:27:56 +0300 | [diff] [blame] | 336 | if (size < sizeof(*args) || args->head > 1) |
Ben Skeggs | 370c00f | 2012-08-14 14:11:49 +1000 | [diff] [blame] | 337 | return -EINVAL; |
| 338 | |
| 339 | ret = nv50_disp_dmac_create_(parent, engine, oclass, args->pushbuf, |
| 340 | 1 + args->head, sizeof(*dmac), |
| 341 | (void **)&dmac); |
| 342 | *pobject = nv_object(dmac); |
Ben Skeggs | 70cabe4 | 2012-08-14 10:04:04 +1000 | [diff] [blame] | 343 | if (ret) |
| 344 | return ret; |
| 345 | |
Ben Skeggs | 370c00f | 2012-08-14 14:11:49 +1000 | [diff] [blame] | 346 | nv_parent(dmac)->object_attach = nv50_disp_dmac_object_attach; |
| 347 | nv_parent(dmac)->object_detach = nv50_disp_dmac_object_detach; |
Ben Skeggs | 70cabe4 | 2012-08-14 10:04:04 +1000 | [diff] [blame] | 348 | return 0; |
| 349 | } |
| 350 | |
Ben Skeggs | 70cabe4 | 2012-08-14 10:04:04 +1000 | [diff] [blame] | 351 | struct nouveau_ofuncs |
Ben Skeggs | 370c00f | 2012-08-14 14:11:49 +1000 | [diff] [blame] | 352 | nv50_disp_sync_ofuncs = { |
| 353 | .ctor = nv50_disp_sync_ctor, |
Ben Skeggs | 70cabe4 | 2012-08-14 10:04:04 +1000 | [diff] [blame] | 354 | .dtor = nv50_disp_dmac_dtor, |
| 355 | .init = nv50_disp_dmac_init, |
| 356 | .fini = nv50_disp_dmac_fini, |
| 357 | .rd32 = nv50_disp_chan_rd32, |
| 358 | .wr32 = nv50_disp_chan_wr32, |
| 359 | }; |
| 360 | |
| 361 | /******************************************************************************* |
Ben Skeggs | 370c00f | 2012-08-14 14:11:49 +1000 | [diff] [blame] | 362 | * EVO overlay channel objects |
Ben Skeggs | 70cabe4 | 2012-08-14 10:04:04 +1000 | [diff] [blame] | 363 | ******************************************************************************/ |
| 364 | |
| 365 | static int |
Ben Skeggs | 370c00f | 2012-08-14 14:11:49 +1000 | [diff] [blame] | 366 | nv50_disp_ovly_ctor(struct nouveau_object *parent, |
Ben Skeggs | 70cabe4 | 2012-08-14 10:04:04 +1000 | [diff] [blame] | 367 | struct nouveau_object *engine, |
| 368 | struct nouveau_oclass *oclass, void *data, u32 size, |
| 369 | struct nouveau_object **pobject) |
| 370 | { |
Ben Skeggs | 370c00f | 2012-08-14 14:11:49 +1000 | [diff] [blame] | 371 | struct nv50_display_ovly_class *args = data; |
| 372 | struct nv50_disp_dmac *dmac; |
Ben Skeggs | 70cabe4 | 2012-08-14 10:04:04 +1000 | [diff] [blame] | 373 | int ret; |
| 374 | |
Dan Carpenter | af1ac18 | 2013-01-23 11:27:56 +0300 | [diff] [blame] | 375 | if (size < sizeof(*args) || args->head > 1) |
Ben Skeggs | 370c00f | 2012-08-14 14:11:49 +1000 | [diff] [blame] | 376 | return -EINVAL; |
| 377 | |
| 378 | ret = nv50_disp_dmac_create_(parent, engine, oclass, args->pushbuf, |
| 379 | 3 + args->head, sizeof(*dmac), |
| 380 | (void **)&dmac); |
| 381 | *pobject = nv_object(dmac); |
Ben Skeggs | 70cabe4 | 2012-08-14 10:04:04 +1000 | [diff] [blame] | 382 | if (ret) |
| 383 | return ret; |
| 384 | |
Ben Skeggs | 370c00f | 2012-08-14 14:11:49 +1000 | [diff] [blame] | 385 | nv_parent(dmac)->object_attach = nv50_disp_dmac_object_attach; |
| 386 | nv_parent(dmac)->object_detach = nv50_disp_dmac_object_detach; |
Ben Skeggs | 70cabe4 | 2012-08-14 10:04:04 +1000 | [diff] [blame] | 387 | return 0; |
| 388 | } |
| 389 | |
Ben Skeggs | 370c00f | 2012-08-14 14:11:49 +1000 | [diff] [blame] | 390 | struct nouveau_ofuncs |
| 391 | nv50_disp_ovly_ofuncs = { |
| 392 | .ctor = nv50_disp_ovly_ctor, |
| 393 | .dtor = nv50_disp_dmac_dtor, |
| 394 | .init = nv50_disp_dmac_init, |
| 395 | .fini = nv50_disp_dmac_fini, |
| 396 | .rd32 = nv50_disp_chan_rd32, |
| 397 | .wr32 = nv50_disp_chan_wr32, |
| 398 | }; |
| 399 | |
| 400 | /******************************************************************************* |
| 401 | * EVO PIO channel base class |
| 402 | ******************************************************************************/ |
| 403 | |
| 404 | static int |
| 405 | nv50_disp_pioc_create_(struct nouveau_object *parent, |
| 406 | struct nouveau_object *engine, |
| 407 | struct nouveau_oclass *oclass, int chid, |
| 408 | int length, void **pobject) |
| 409 | { |
| 410 | return nv50_disp_chan_create_(parent, engine, oclass, chid, |
| 411 | length, pobject); |
| 412 | } |
| 413 | |
Ben Skeggs | 70cabe4 | 2012-08-14 10:04:04 +1000 | [diff] [blame] | 414 | static void |
| 415 | nv50_disp_pioc_dtor(struct nouveau_object *object) |
| 416 | { |
Ben Skeggs | 370c00f | 2012-08-14 14:11:49 +1000 | [diff] [blame] | 417 | struct nv50_disp_pioc *pioc = (void *)object; |
| 418 | nv50_disp_chan_destroy(&pioc->base); |
Ben Skeggs | 70cabe4 | 2012-08-14 10:04:04 +1000 | [diff] [blame] | 419 | } |
| 420 | |
| 421 | static int |
| 422 | nv50_disp_pioc_init(struct nouveau_object *object) |
| 423 | { |
Ben Skeggs | 370c00f | 2012-08-14 14:11:49 +1000 | [diff] [blame] | 424 | struct nv50_disp_priv *priv = (void *)object->engine; |
| 425 | struct nv50_disp_pioc *pioc = (void *)object; |
| 426 | int chid = pioc->base.chid; |
Ben Skeggs | 70cabe4 | 2012-08-14 10:04:04 +1000 | [diff] [blame] | 427 | int ret; |
| 428 | |
Ben Skeggs | 370c00f | 2012-08-14 14:11:49 +1000 | [diff] [blame] | 429 | ret = nv50_disp_chan_init(&pioc->base); |
Ben Skeggs | 70cabe4 | 2012-08-14 10:04:04 +1000 | [diff] [blame] | 430 | if (ret) |
| 431 | return ret; |
| 432 | |
Ben Skeggs | 370c00f | 2012-08-14 14:11:49 +1000 | [diff] [blame] | 433 | nv_wr32(priv, 0x610200 + (chid * 0x10), 0x00002000); |
| 434 | if (!nv_wait(priv, 0x610200 + (chid * 0x10), 0x00000000, 0x00000000)) { |
| 435 | nv_error(pioc, "timeout0: 0x%08x\n", |
| 436 | nv_rd32(priv, 0x610200 + (chid * 0x10))); |
| 437 | return -EBUSY; |
| 438 | } |
| 439 | |
| 440 | nv_wr32(priv, 0x610200 + (chid * 0x10), 0x00000001); |
| 441 | if (!nv_wait(priv, 0x610200 + (chid * 0x10), 0x00030000, 0x00010000)) { |
| 442 | nv_error(pioc, "timeout1: 0x%08x\n", |
| 443 | nv_rd32(priv, 0x610200 + (chid * 0x10))); |
| 444 | return -EBUSY; |
| 445 | } |
| 446 | |
Ben Skeggs | 70cabe4 | 2012-08-14 10:04:04 +1000 | [diff] [blame] | 447 | return 0; |
| 448 | } |
| 449 | |
| 450 | static int |
| 451 | nv50_disp_pioc_fini(struct nouveau_object *object, bool suspend) |
| 452 | { |
Ben Skeggs | 370c00f | 2012-08-14 14:11:49 +1000 | [diff] [blame] | 453 | struct nv50_disp_priv *priv = (void *)object->engine; |
| 454 | struct nv50_disp_pioc *pioc = (void *)object; |
| 455 | int chid = pioc->base.chid; |
| 456 | |
| 457 | nv_mask(priv, 0x610200 + (chid * 0x10), 0x00000001, 0x00000000); |
| 458 | if (!nv_wait(priv, 0x610200 + (chid * 0x10), 0x00030000, 0x00000000)) { |
| 459 | nv_error(pioc, "timeout: 0x%08x\n", |
| 460 | nv_rd32(priv, 0x610200 + (chid * 0x10))); |
| 461 | if (suspend) |
| 462 | return -EBUSY; |
| 463 | } |
| 464 | |
| 465 | return nv50_disp_chan_fini(&pioc->base, suspend); |
| 466 | } |
| 467 | |
| 468 | /******************************************************************************* |
| 469 | * EVO immediate overlay channel objects |
| 470 | ******************************************************************************/ |
| 471 | |
| 472 | static int |
| 473 | nv50_disp_oimm_ctor(struct nouveau_object *parent, |
| 474 | struct nouveau_object *engine, |
| 475 | struct nouveau_oclass *oclass, void *data, u32 size, |
| 476 | struct nouveau_object **pobject) |
| 477 | { |
| 478 | struct nv50_display_oimm_class *args = data; |
| 479 | struct nv50_disp_pioc *pioc; |
| 480 | int ret; |
| 481 | |
| 482 | if (size < sizeof(*args) || args->head > 1) |
| 483 | return -EINVAL; |
| 484 | |
| 485 | ret = nv50_disp_pioc_create_(parent, engine, oclass, 5 + args->head, |
| 486 | sizeof(*pioc), (void **)&pioc); |
| 487 | *pobject = nv_object(pioc); |
| 488 | if (ret) |
| 489 | return ret; |
| 490 | |
| 491 | return 0; |
Ben Skeggs | 70cabe4 | 2012-08-14 10:04:04 +1000 | [diff] [blame] | 492 | } |
| 493 | |
| 494 | struct nouveau_ofuncs |
Ben Skeggs | 370c00f | 2012-08-14 14:11:49 +1000 | [diff] [blame] | 495 | nv50_disp_oimm_ofuncs = { |
| 496 | .ctor = nv50_disp_oimm_ctor, |
| 497 | .dtor = nv50_disp_pioc_dtor, |
| 498 | .init = nv50_disp_pioc_init, |
| 499 | .fini = nv50_disp_pioc_fini, |
| 500 | .rd32 = nv50_disp_chan_rd32, |
| 501 | .wr32 = nv50_disp_chan_wr32, |
| 502 | }; |
| 503 | |
| 504 | /******************************************************************************* |
| 505 | * EVO cursor channel objects |
| 506 | ******************************************************************************/ |
| 507 | |
| 508 | static int |
| 509 | nv50_disp_curs_ctor(struct nouveau_object *parent, |
| 510 | struct nouveau_object *engine, |
| 511 | struct nouveau_oclass *oclass, void *data, u32 size, |
| 512 | struct nouveau_object **pobject) |
| 513 | { |
| 514 | struct nv50_display_curs_class *args = data; |
| 515 | struct nv50_disp_pioc *pioc; |
| 516 | int ret; |
| 517 | |
| 518 | if (size < sizeof(*args) || args->head > 1) |
| 519 | return -EINVAL; |
| 520 | |
| 521 | ret = nv50_disp_pioc_create_(parent, engine, oclass, 7 + args->head, |
| 522 | sizeof(*pioc), (void **)&pioc); |
| 523 | *pobject = nv_object(pioc); |
| 524 | if (ret) |
| 525 | return ret; |
| 526 | |
| 527 | return 0; |
| 528 | } |
| 529 | |
| 530 | struct nouveau_ofuncs |
| 531 | nv50_disp_curs_ofuncs = { |
| 532 | .ctor = nv50_disp_curs_ctor, |
Ben Skeggs | 70cabe4 | 2012-08-14 10:04:04 +1000 | [diff] [blame] | 533 | .dtor = nv50_disp_pioc_dtor, |
| 534 | .init = nv50_disp_pioc_init, |
| 535 | .fini = nv50_disp_pioc_fini, |
| 536 | .rd32 = nv50_disp_chan_rd32, |
| 537 | .wr32 = nv50_disp_chan_wr32, |
| 538 | }; |
| 539 | |
| 540 | /******************************************************************************* |
| 541 | * Base display object |
| 542 | ******************************************************************************/ |
| 543 | |
Ben Skeggs | 1d7c71a | 2013-01-31 09:23:34 +1000 | [diff] [blame] | 544 | static void |
| 545 | nv50_disp_base_vblank_enable(struct nouveau_event *event, int head) |
| 546 | { |
| 547 | nv_mask(event->priv, 0x61002c, (1 << head), (1 << head)); |
| 548 | } |
| 549 | |
| 550 | static void |
| 551 | nv50_disp_base_vblank_disable(struct nouveau_event *event, int head) |
| 552 | { |
| 553 | nv_mask(event->priv, 0x61002c, (1 << head), (0 << head)); |
| 554 | } |
| 555 | |
Ben Skeggs | 70cabe4 | 2012-08-14 10:04:04 +1000 | [diff] [blame] | 556 | static int |
| 557 | nv50_disp_base_ctor(struct nouveau_object *parent, |
| 558 | struct nouveau_object *engine, |
| 559 | struct nouveau_oclass *oclass, void *data, u32 size, |
| 560 | struct nouveau_object **pobject) |
| 561 | { |
| 562 | struct nv50_disp_priv *priv = (void *)engine; |
| 563 | struct nv50_disp_base *base; |
| 564 | int ret; |
| 565 | |
| 566 | ret = nouveau_parent_create(parent, engine, oclass, 0, |
| 567 | priv->sclass, 0, &base); |
| 568 | *pobject = nv_object(base); |
| 569 | if (ret) |
| 570 | return ret; |
| 571 | |
Ben Skeggs | 1d7c71a | 2013-01-31 09:23:34 +1000 | [diff] [blame] | 572 | priv->base.vblank->priv = priv; |
| 573 | priv->base.vblank->enable = nv50_disp_base_vblank_enable; |
| 574 | priv->base.vblank->disable = nv50_disp_base_vblank_disable; |
Ben Skeggs | 370c00f | 2012-08-14 14:11:49 +1000 | [diff] [blame] | 575 | return nouveau_ramht_new(parent, parent, 0x1000, 0, &base->ramht); |
Ben Skeggs | 70cabe4 | 2012-08-14 10:04:04 +1000 | [diff] [blame] | 576 | } |
| 577 | |
| 578 | static void |
| 579 | nv50_disp_base_dtor(struct nouveau_object *object) |
| 580 | { |
| 581 | struct nv50_disp_base *base = (void *)object; |
Ben Skeggs | 370c00f | 2012-08-14 14:11:49 +1000 | [diff] [blame] | 582 | nouveau_ramht_ref(NULL, &base->ramht); |
Ben Skeggs | 70cabe4 | 2012-08-14 10:04:04 +1000 | [diff] [blame] | 583 | nouveau_parent_destroy(&base->base); |
| 584 | } |
| 585 | |
| 586 | static int |
| 587 | nv50_disp_base_init(struct nouveau_object *object) |
| 588 | { |
Ben Skeggs | ab77214 | 2012-08-14 11:29:57 +1000 | [diff] [blame] | 589 | struct nv50_disp_priv *priv = (void *)object->engine; |
Ben Skeggs | 70cabe4 | 2012-08-14 10:04:04 +1000 | [diff] [blame] | 590 | struct nv50_disp_base *base = (void *)object; |
Ben Skeggs | ab77214 | 2012-08-14 11:29:57 +1000 | [diff] [blame] | 591 | int ret, i; |
| 592 | u32 tmp; |
Ben Skeggs | 70cabe4 | 2012-08-14 10:04:04 +1000 | [diff] [blame] | 593 | |
| 594 | ret = nouveau_parent_init(&base->base); |
| 595 | if (ret) |
| 596 | return ret; |
| 597 | |
Ben Skeggs | ab77214 | 2012-08-14 11:29:57 +1000 | [diff] [blame] | 598 | /* The below segments of code copying values from one register to |
| 599 | * another appear to inform EVO of the display capabilities or |
| 600 | * something similar. NFI what the 0x614004 caps are for.. |
| 601 | */ |
| 602 | tmp = nv_rd32(priv, 0x614004); |
| 603 | nv_wr32(priv, 0x610184, tmp); |
| 604 | |
| 605 | /* ... CRTC caps */ |
| 606 | for (i = 0; i < priv->head.nr; i++) { |
| 607 | tmp = nv_rd32(priv, 0x616100 + (i * 0x800)); |
| 608 | nv_wr32(priv, 0x610190 + (i * 0x10), tmp); |
| 609 | tmp = nv_rd32(priv, 0x616104 + (i * 0x800)); |
| 610 | nv_wr32(priv, 0x610194 + (i * 0x10), tmp); |
| 611 | tmp = nv_rd32(priv, 0x616108 + (i * 0x800)); |
| 612 | nv_wr32(priv, 0x610198 + (i * 0x10), tmp); |
| 613 | tmp = nv_rd32(priv, 0x61610c + (i * 0x800)); |
| 614 | nv_wr32(priv, 0x61019c + (i * 0x10), tmp); |
| 615 | } |
| 616 | |
| 617 | /* ... DAC caps */ |
| 618 | for (i = 0; i < priv->dac.nr; i++) { |
| 619 | tmp = nv_rd32(priv, 0x61a000 + (i * 0x800)); |
| 620 | nv_wr32(priv, 0x6101d0 + (i * 0x04), tmp); |
| 621 | } |
| 622 | |
| 623 | /* ... SOR caps */ |
| 624 | for (i = 0; i < priv->sor.nr; i++) { |
| 625 | tmp = nv_rd32(priv, 0x61c000 + (i * 0x800)); |
| 626 | nv_wr32(priv, 0x6101e0 + (i * 0x04), tmp); |
| 627 | } |
| 628 | |
| 629 | /* ... EXT caps */ |
| 630 | for (i = 0; i < 3; i++) { |
| 631 | tmp = nv_rd32(priv, 0x61e000 + (i * 0x800)); |
| 632 | nv_wr32(priv, 0x6101f0 + (i * 0x04), tmp); |
| 633 | } |
| 634 | |
Ben Skeggs | 446b05a | 2012-08-14 12:50:14 +1000 | [diff] [blame] | 635 | /* steal display away from vbios, or something like that */ |
| 636 | if (nv_rd32(priv, 0x610024) & 0x00000100) { |
| 637 | nv_wr32(priv, 0x610024, 0x00000100); |
| 638 | nv_mask(priv, 0x6194e8, 0x00000001, 0x00000000); |
| 639 | if (!nv_wait(priv, 0x6194e8, 0x00000002, 0x00000000)) { |
| 640 | nv_error(priv, "timeout acquiring display\n"); |
| 641 | return -EBUSY; |
| 642 | } |
| 643 | } |
| 644 | |
| 645 | /* point at display engine memory area (hash table, objects) */ |
Ben Skeggs | 370c00f | 2012-08-14 14:11:49 +1000 | [diff] [blame] | 646 | nv_wr32(priv, 0x610010, (nv_gpuobj(base->ramht)->addr >> 8) | 9); |
Ben Skeggs | 446b05a | 2012-08-14 12:50:14 +1000 | [diff] [blame] | 647 | |
| 648 | /* enable supervisor interrupts, disable everything else */ |
Ben Skeggs | 370c00f | 2012-08-14 14:11:49 +1000 | [diff] [blame] | 649 | nv_wr32(priv, 0x61002c, 0x00000370); |
| 650 | nv_wr32(priv, 0x610028, 0x00000000); |
Ben Skeggs | 70cabe4 | 2012-08-14 10:04:04 +1000 | [diff] [blame] | 651 | return 0; |
| 652 | } |
| 653 | |
| 654 | static int |
| 655 | nv50_disp_base_fini(struct nouveau_object *object, bool suspend) |
| 656 | { |
Ben Skeggs | 446b05a | 2012-08-14 12:50:14 +1000 | [diff] [blame] | 657 | struct nv50_disp_priv *priv = (void *)object->engine; |
Ben Skeggs | 70cabe4 | 2012-08-14 10:04:04 +1000 | [diff] [blame] | 658 | struct nv50_disp_base *base = (void *)object; |
Ben Skeggs | 446b05a | 2012-08-14 12:50:14 +1000 | [diff] [blame] | 659 | |
| 660 | /* disable all interrupts */ |
| 661 | nv_wr32(priv, 0x610024, 0x00000000); |
| 662 | nv_wr32(priv, 0x610020, 0x00000000); |
| 663 | |
Ben Skeggs | 70cabe4 | 2012-08-14 10:04:04 +1000 | [diff] [blame] | 664 | return nouveau_parent_fini(&base->base, suspend); |
| 665 | } |
| 666 | |
| 667 | struct nouveau_ofuncs |
| 668 | nv50_disp_base_ofuncs = { |
| 669 | .ctor = nv50_disp_base_ctor, |
| 670 | .dtor = nv50_disp_base_dtor, |
| 671 | .init = nv50_disp_base_init, |
| 672 | .fini = nv50_disp_base_fini, |
| 673 | }; |
| 674 | |
Ben Skeggs | ef22c8b | 2012-11-09 09:32:56 +1000 | [diff] [blame] | 675 | static struct nouveau_omthds |
| 676 | nv50_disp_base_omthds[] = { |
| 677 | { SOR_MTHD(NV50_DISP_SOR_PWR) , nv50_sor_mthd }, |
Ben Skeggs | 4a230fa | 2012-11-09 11:25:37 +1000 | [diff] [blame] | 678 | { SOR_MTHD(NV50_DISP_SOR_LVDS_SCRIPT) , nv50_sor_mthd }, |
Ben Skeggs | ef22c8b | 2012-11-09 09:32:56 +1000 | [diff] [blame] | 679 | { DAC_MTHD(NV50_DISP_DAC_PWR) , nv50_dac_mthd }, |
| 680 | { DAC_MTHD(NV50_DISP_DAC_LOAD) , nv50_dac_mthd }, |
Ben Skeggs | a2bc283 | 2013-02-11 09:11:08 +1000 | [diff] [blame^] | 681 | { PIOR_MTHD(NV50_DISP_PIOR_PWR) , nv50_pior_mthd }, |
| 682 | { PIOR_MTHD(NV50_DISP_PIOR_TMDS_PWR) , nv50_pior_mthd }, |
| 683 | { PIOR_MTHD(NV50_DISP_PIOR_DP_PWR) , nv50_pior_mthd }, |
Ben Skeggs | ef22c8b | 2012-11-09 09:32:56 +1000 | [diff] [blame] | 684 | {}, |
| 685 | }; |
| 686 | |
Ben Skeggs | 70cabe4 | 2012-08-14 10:04:04 +1000 | [diff] [blame] | 687 | static struct nouveau_oclass |
| 688 | nv50_disp_base_oclass[] = { |
Ben Skeggs | ef22c8b | 2012-11-09 09:32:56 +1000 | [diff] [blame] | 689 | { NV50_DISP_CLASS, &nv50_disp_base_ofuncs, nv50_disp_base_omthds }, |
Ben Skeggs | 370c00f | 2012-08-14 14:11:49 +1000 | [diff] [blame] | 690 | {} |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 691 | }; |
| 692 | |
| 693 | static struct nouveau_oclass |
| 694 | nv50_disp_sclass[] = { |
Ben Skeggs | 370c00f | 2012-08-14 14:11:49 +1000 | [diff] [blame] | 695 | { NV50_DISP_MAST_CLASS, &nv50_disp_mast_ofuncs }, |
| 696 | { NV50_DISP_SYNC_CLASS, &nv50_disp_sync_ofuncs }, |
| 697 | { NV50_DISP_OVLY_CLASS, &nv50_disp_ovly_ofuncs }, |
| 698 | { NV50_DISP_OIMM_CLASS, &nv50_disp_oimm_ofuncs }, |
| 699 | { NV50_DISP_CURS_CLASS, &nv50_disp_curs_ofuncs }, |
Ben Skeggs | 70cabe4 | 2012-08-14 10:04:04 +1000 | [diff] [blame] | 700 | {} |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 701 | }; |
| 702 | |
Ben Skeggs | 70cabe4 | 2012-08-14 10:04:04 +1000 | [diff] [blame] | 703 | /******************************************************************************* |
| 704 | * Display context, tracks instmem allocation and prevents more than one |
| 705 | * client using the display hardware at any time. |
| 706 | ******************************************************************************/ |
| 707 | |
| 708 | static int |
| 709 | nv50_disp_data_ctor(struct nouveau_object *parent, |
| 710 | struct nouveau_object *engine, |
| 711 | struct nouveau_oclass *oclass, void *data, u32 size, |
| 712 | struct nouveau_object **pobject) |
| 713 | { |
Ben Skeggs | 370c00f | 2012-08-14 14:11:49 +1000 | [diff] [blame] | 714 | struct nv50_disp_priv *priv = (void *)engine; |
Ben Skeggs | 70cabe4 | 2012-08-14 10:04:04 +1000 | [diff] [blame] | 715 | struct nouveau_engctx *ectx; |
Ben Skeggs | 370c00f | 2012-08-14 14:11:49 +1000 | [diff] [blame] | 716 | int ret = -EBUSY; |
Ben Skeggs | 70cabe4 | 2012-08-14 10:04:04 +1000 | [diff] [blame] | 717 | |
Ben Skeggs | 370c00f | 2012-08-14 14:11:49 +1000 | [diff] [blame] | 718 | /* no context needed for channel objects... */ |
| 719 | if (nv_mclass(parent) != NV_DEVICE_CLASS) { |
| 720 | atomic_inc(&parent->refcount); |
| 721 | *pobject = parent; |
| 722 | return 0; |
| 723 | } |
Ben Skeggs | 70cabe4 | 2012-08-14 10:04:04 +1000 | [diff] [blame] | 724 | |
Ben Skeggs | 370c00f | 2012-08-14 14:11:49 +1000 | [diff] [blame] | 725 | /* allocate display hardware to client */ |
| 726 | mutex_lock(&nv_subdev(priv)->mutex); |
| 727 | if (list_empty(&nv_engine(priv)->contexts)) { |
| 728 | ret = nouveau_engctx_create(parent, engine, oclass, NULL, |
| 729 | 0x10000, 0x10000, |
| 730 | NVOBJ_FLAG_HEAP, &ectx); |
| 731 | *pobject = nv_object(ectx); |
| 732 | } |
| 733 | mutex_unlock(&nv_subdev(priv)->mutex); |
| 734 | return ret; |
Ben Skeggs | 70cabe4 | 2012-08-14 10:04:04 +1000 | [diff] [blame] | 735 | } |
| 736 | |
| 737 | struct nouveau_oclass |
| 738 | nv50_disp_cclass = { |
| 739 | .handle = NV_ENGCTX(DISP, 0x50), |
| 740 | .ofuncs = &(struct nouveau_ofuncs) { |
| 741 | .ctor = nv50_disp_data_ctor, |
| 742 | .dtor = _nouveau_engctx_dtor, |
| 743 | .init = _nouveau_engctx_init, |
| 744 | .fini = _nouveau_engctx_fini, |
| 745 | .rd32 = _nouveau_engctx_rd32, |
| 746 | .wr32 = _nouveau_engctx_wr32, |
| 747 | }, |
| 748 | }; |
| 749 | |
| 750 | /******************************************************************************* |
| 751 | * Display engine implementation |
| 752 | ******************************************************************************/ |
| 753 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 754 | static void |
Ben Skeggs | 186ecad | 2012-11-09 12:09:48 +1000 | [diff] [blame] | 755 | nv50_disp_intr_error(struct nv50_disp_priv *priv) |
| 756 | { |
| 757 | u32 channels = (nv_rd32(priv, 0x610020) & 0x001f0000) >> 16; |
| 758 | u32 addr, data; |
| 759 | int chid; |
| 760 | |
| 761 | for (chid = 0; chid < 5; chid++) { |
| 762 | if (!(channels & (1 << chid))) |
| 763 | continue; |
| 764 | |
| 765 | nv_wr32(priv, 0x610020, 0x00010000 << chid); |
| 766 | addr = nv_rd32(priv, 0x610080 + (chid * 0x08)); |
| 767 | data = nv_rd32(priv, 0x610084 + (chid * 0x08)); |
| 768 | nv_wr32(priv, 0x610080 + (chid * 0x08), 0x90000000); |
| 769 | |
| 770 | nv_error(priv, "chid %d mthd 0x%04x data 0x%08x 0x%08x\n", |
| 771 | chid, addr & 0xffc, data, addr); |
| 772 | } |
| 773 | } |
| 774 | |
Ben Skeggs | 186ecad | 2012-11-09 12:09:48 +1000 | [diff] [blame] | 775 | static u16 |
| 776 | exec_lookup(struct nv50_disp_priv *priv, int head, int outp, u32 ctrl, |
| 777 | struct dcb_output *dcb, u8 *ver, u8 *hdr, u8 *cnt, u8 *len, |
| 778 | struct nvbios_outp *info) |
| 779 | { |
| 780 | struct nouveau_bios *bios = nouveau_bios(priv); |
| 781 | u16 mask, type, data; |
| 782 | |
| 783 | if (outp < 4) { |
| 784 | type = DCB_OUTPUT_ANALOG; |
| 785 | mask = 0; |
| 786 | } else { |
| 787 | outp -= 4; |
| 788 | switch (ctrl & 0x00000f00) { |
| 789 | case 0x00000000: type = DCB_OUTPUT_LVDS; mask = 1; break; |
| 790 | case 0x00000100: type = DCB_OUTPUT_TMDS; mask = 1; break; |
| 791 | case 0x00000200: type = DCB_OUTPUT_TMDS; mask = 2; break; |
| 792 | case 0x00000500: type = DCB_OUTPUT_TMDS; mask = 3; break; |
| 793 | case 0x00000800: type = DCB_OUTPUT_DP; mask = 1; break; |
| 794 | case 0x00000900: type = DCB_OUTPUT_DP; mask = 2; break; |
| 795 | default: |
| 796 | nv_error(priv, "unknown SOR mc 0x%08x\n", ctrl); |
| 797 | return 0x0000; |
| 798 | } |
| 799 | } |
| 800 | |
| 801 | mask = 0x00c0 & (mask << 6); |
| 802 | mask |= 0x0001 << outp; |
| 803 | mask |= 0x0100 << head; |
| 804 | |
| 805 | data = dcb_outp_match(bios, type, mask, ver, hdr, dcb); |
| 806 | if (!data) |
| 807 | return 0x0000; |
| 808 | |
| 809 | return nvbios_outp_match(bios, type, mask, ver, hdr, cnt, len, info); |
| 810 | } |
| 811 | |
| 812 | static bool |
| 813 | exec_script(struct nv50_disp_priv *priv, int head, int id) |
| 814 | { |
| 815 | struct nouveau_bios *bios = nouveau_bios(priv); |
| 816 | struct nvbios_outp info; |
| 817 | struct dcb_output dcb; |
| 818 | u8 ver, hdr, cnt, len; |
| 819 | u16 data; |
| 820 | u32 ctrl = 0x00000000; |
| 821 | int i; |
| 822 | |
| 823 | for (i = 0; !(ctrl & (1 << head)) && i < 3; i++) |
| 824 | ctrl = nv_rd32(priv, 0x610b5c + (i * 8)); |
| 825 | |
Marcin Slusarz | c684cef | 2013-01-03 19:38:45 +0100 | [diff] [blame] | 826 | if (!(ctrl & (1 << head))) { |
| 827 | if (nv_device(priv)->chipset < 0x90 || |
| 828 | nv_device(priv)->chipset == 0x92 || |
| 829 | nv_device(priv)->chipset == 0xa0) { |
| 830 | for (i = 0; !(ctrl & (1 << head)) && i < 2; i++) |
| 831 | ctrl = nv_rd32(priv, 0x610b74 + (i * 8)); |
| 832 | i += 4; |
| 833 | } else { |
| 834 | for (i = 0; !(ctrl & (1 << head)) && i < 4; i++) |
| 835 | ctrl = nv_rd32(priv, 0x610798 + (i * 8)); |
| 836 | i += 4; |
| 837 | } |
Ben Skeggs | 186ecad | 2012-11-09 12:09:48 +1000 | [diff] [blame] | 838 | } |
| 839 | |
| 840 | if (!(ctrl & (1 << head))) |
| 841 | return false; |
Marcin Slusarz | c684cef | 2013-01-03 19:38:45 +0100 | [diff] [blame] | 842 | i--; |
Ben Skeggs | 186ecad | 2012-11-09 12:09:48 +1000 | [diff] [blame] | 843 | |
| 844 | data = exec_lookup(priv, head, i, ctrl, &dcb, &ver, &hdr, &cnt, &len, &info); |
| 845 | if (data) { |
| 846 | struct nvbios_init init = { |
| 847 | .subdev = nv_subdev(priv), |
| 848 | .bios = bios, |
| 849 | .offset = info.script[id], |
| 850 | .outp = &dcb, |
| 851 | .crtc = head, |
| 852 | .execute = 1, |
| 853 | }; |
| 854 | |
| 855 | return nvbios_exec(&init) == 0; |
| 856 | } |
| 857 | |
| 858 | return false; |
| 859 | } |
| 860 | |
| 861 | static u32 |
| 862 | exec_clkcmp(struct nv50_disp_priv *priv, int head, int id, u32 pclk, |
| 863 | struct dcb_output *outp) |
| 864 | { |
| 865 | struct nouveau_bios *bios = nouveau_bios(priv); |
| 866 | struct nvbios_outp info1; |
| 867 | struct nvbios_ocfg info2; |
| 868 | u8 ver, hdr, cnt, len; |
Ben Skeggs | 186ecad | 2012-11-09 12:09:48 +1000 | [diff] [blame] | 869 | u32 ctrl = 0x00000000; |
Ben Skeggs | 46c13c1 | 2013-02-16 13:49:21 +1000 | [diff] [blame] | 870 | u32 data, conf = ~0; |
Ben Skeggs | 186ecad | 2012-11-09 12:09:48 +1000 | [diff] [blame] | 871 | int i; |
| 872 | |
| 873 | for (i = 0; !(ctrl & (1 << head)) && i < 3; i++) |
| 874 | ctrl = nv_rd32(priv, 0x610b58 + (i * 8)); |
| 875 | |
Marcin Slusarz | c684cef | 2013-01-03 19:38:45 +0100 | [diff] [blame] | 876 | if (!(ctrl & (1 << head))) { |
| 877 | if (nv_device(priv)->chipset < 0x90 || |
| 878 | nv_device(priv)->chipset == 0x92 || |
| 879 | nv_device(priv)->chipset == 0xa0) { |
| 880 | for (i = 0; !(ctrl & (1 << head)) && i < 2; i++) |
| 881 | ctrl = nv_rd32(priv, 0x610b70 + (i * 8)); |
| 882 | i += 4; |
| 883 | } else { |
| 884 | for (i = 0; !(ctrl & (1 << head)) && i < 4; i++) |
| 885 | ctrl = nv_rd32(priv, 0x610794 + (i * 8)); |
| 886 | i += 4; |
| 887 | } |
Ben Skeggs | 186ecad | 2012-11-09 12:09:48 +1000 | [diff] [blame] | 888 | } |
| 889 | |
| 890 | if (!(ctrl & (1 << head))) |
Ben Skeggs | 46c13c1 | 2013-02-16 13:49:21 +1000 | [diff] [blame] | 891 | return conf; |
Marcin Slusarz | c684cef | 2013-01-03 19:38:45 +0100 | [diff] [blame] | 892 | i--; |
Ben Skeggs | 186ecad | 2012-11-09 12:09:48 +1000 | [diff] [blame] | 893 | |
| 894 | data = exec_lookup(priv, head, i, ctrl, outp, &ver, &hdr, &cnt, &len, &info1); |
| 895 | if (!data) |
Ben Skeggs | 46c13c1 | 2013-02-16 13:49:21 +1000 | [diff] [blame] | 896 | return conf; |
Ben Skeggs | 186ecad | 2012-11-09 12:09:48 +1000 | [diff] [blame] | 897 | |
| 898 | switch (outp->type) { |
| 899 | case DCB_OUTPUT_TMDS: |
| 900 | conf = (ctrl & 0x00000f00) >> 8; |
| 901 | if (pclk >= 165000) |
| 902 | conf |= 0x0100; |
| 903 | break; |
| 904 | case DCB_OUTPUT_LVDS: |
| 905 | conf = priv->sor.lvdsconf; |
| 906 | break; |
| 907 | case DCB_OUTPUT_DP: |
| 908 | conf = (ctrl & 0x00000f00) >> 8; |
| 909 | break; |
| 910 | case DCB_OUTPUT_ANALOG: |
| 911 | default: |
| 912 | conf = 0x00ff; |
| 913 | break; |
| 914 | } |
| 915 | |
| 916 | data = nvbios_ocfg_match(bios, data, conf, &ver, &hdr, &cnt, &len, &info2); |
Ben Skeggs | 0a0afd2 | 2013-02-18 23:17:53 -0500 | [diff] [blame] | 917 | if (data && id < 0xff) { |
Ben Skeggs | 186ecad | 2012-11-09 12:09:48 +1000 | [diff] [blame] | 918 | data = nvbios_oclk_match(bios, info2.clkcmp[id], pclk); |
| 919 | if (data) { |
| 920 | struct nvbios_init init = { |
| 921 | .subdev = nv_subdev(priv), |
| 922 | .bios = bios, |
| 923 | .offset = data, |
| 924 | .outp = outp, |
| 925 | .crtc = head, |
| 926 | .execute = 1, |
| 927 | }; |
| 928 | |
Ben Skeggs | 46c13c1 | 2013-02-16 13:49:21 +1000 | [diff] [blame] | 929 | nvbios_exec(&init); |
Ben Skeggs | 186ecad | 2012-11-09 12:09:48 +1000 | [diff] [blame] | 930 | } |
| 931 | } |
| 932 | |
Ben Skeggs | 46c13c1 | 2013-02-16 13:49:21 +1000 | [diff] [blame] | 933 | return conf; |
Ben Skeggs | 186ecad | 2012-11-09 12:09:48 +1000 | [diff] [blame] | 934 | } |
| 935 | |
| 936 | static void |
| 937 | nv50_disp_intr_unk10(struct nv50_disp_priv *priv, u32 super) |
| 938 | { |
| 939 | int head = ffs((super & 0x00000060) >> 5) - 1; |
| 940 | if (head >= 0) { |
| 941 | head = ffs((super & 0x00000180) >> 7) - 1; |
| 942 | if (head >= 0) |
| 943 | exec_script(priv, head, 1); |
| 944 | } |
| 945 | |
Ben Skeggs | 186ecad | 2012-11-09 12:09:48 +1000 | [diff] [blame] | 946 | nv_wr32(priv, 0x610030, 0x80000000); |
| 947 | } |
| 948 | |
| 949 | static void |
| 950 | nv50_disp_intr_unk20_dp(struct nv50_disp_priv *priv, |
| 951 | struct dcb_output *outp, u32 pclk) |
| 952 | { |
| 953 | const int link = !(outp->sorconf.link & 1); |
| 954 | const int or = ffs(outp->or) - 1; |
| 955 | const u32 soff = ( or * 0x800); |
| 956 | const u32 loff = (link * 0x080) + soff; |
| 957 | const u32 ctrl = nv_rd32(priv, 0x610794 + (or * 8)); |
Ben Skeggs | 186ecad | 2012-11-09 12:09:48 +1000 | [diff] [blame] | 958 | const u32 symbol = 100000; |
| 959 | u32 dpctrl = nv_rd32(priv, 0x61c10c + loff) & 0x0000f0000; |
| 960 | u32 clksor = nv_rd32(priv, 0x614300 + soff); |
| 961 | int bestTU = 0, bestVTUi = 0, bestVTUf = 0, bestVTUa = 0; |
| 962 | int TU, VTUi, VTUf, VTUa; |
| 963 | u64 link_data_rate, link_ratio, unk; |
| 964 | u32 best_diff = 64 * symbol; |
Ben Skeggs | bf2c886 | 2012-11-21 14:49:54 +1000 | [diff] [blame] | 965 | u32 link_nr, link_bw, bits, r; |
Ben Skeggs | 186ecad | 2012-11-09 12:09:48 +1000 | [diff] [blame] | 966 | |
| 967 | /* calculate packed data rate for each lane */ |
| 968 | if (dpctrl > 0x00030000) link_nr = 4; |
| 969 | else if (dpctrl > 0x00010000) link_nr = 2; |
| 970 | else link_nr = 1; |
| 971 | |
| 972 | if (clksor & 0x000c0000) |
| 973 | link_bw = 270000; |
| 974 | else |
| 975 | link_bw = 162000; |
| 976 | |
Ben Skeggs | bf2c886 | 2012-11-21 14:49:54 +1000 | [diff] [blame] | 977 | if ((ctrl & 0xf0000) == 0x60000) bits = 30; |
| 978 | else if ((ctrl & 0xf0000) == 0x50000) bits = 24; |
| 979 | else bits = 18; |
| 980 | |
Ben Skeggs | 186ecad | 2012-11-09 12:09:48 +1000 | [diff] [blame] | 981 | link_data_rate = (pclk * bits / 8) / link_nr; |
| 982 | |
| 983 | /* calculate ratio of packed data rate to link symbol rate */ |
| 984 | link_ratio = link_data_rate * symbol; |
| 985 | r = do_div(link_ratio, link_bw); |
| 986 | |
| 987 | for (TU = 64; TU >= 32; TU--) { |
| 988 | /* calculate average number of valid symbols in each TU */ |
| 989 | u32 tu_valid = link_ratio * TU; |
| 990 | u32 calc, diff; |
| 991 | |
| 992 | /* find a hw representation for the fraction.. */ |
| 993 | VTUi = tu_valid / symbol; |
| 994 | calc = VTUi * symbol; |
| 995 | diff = tu_valid - calc; |
| 996 | if (diff) { |
| 997 | if (diff >= (symbol / 2)) { |
| 998 | VTUf = symbol / (symbol - diff); |
| 999 | if (symbol - (VTUf * diff)) |
| 1000 | VTUf++; |
| 1001 | |
| 1002 | if (VTUf <= 15) { |
| 1003 | VTUa = 1; |
| 1004 | calc += symbol - (symbol / VTUf); |
| 1005 | } else { |
| 1006 | VTUa = 0; |
| 1007 | VTUf = 1; |
| 1008 | calc += symbol; |
| 1009 | } |
| 1010 | } else { |
| 1011 | VTUa = 0; |
| 1012 | VTUf = min((int)(symbol / diff), 15); |
| 1013 | calc += symbol / VTUf; |
| 1014 | } |
| 1015 | |
| 1016 | diff = calc - tu_valid; |
| 1017 | } else { |
| 1018 | /* no remainder, but the hw doesn't like the fractional |
| 1019 | * part to be zero. decrement the integer part and |
| 1020 | * have the fraction add a whole symbol back |
| 1021 | */ |
| 1022 | VTUa = 0; |
| 1023 | VTUf = 1; |
| 1024 | VTUi--; |
| 1025 | } |
| 1026 | |
| 1027 | if (diff < best_diff) { |
| 1028 | best_diff = diff; |
| 1029 | bestTU = TU; |
| 1030 | bestVTUa = VTUa; |
| 1031 | bestVTUf = VTUf; |
| 1032 | bestVTUi = VTUi; |
| 1033 | if (diff == 0) |
| 1034 | break; |
| 1035 | } |
| 1036 | } |
| 1037 | |
| 1038 | if (!bestTU) { |
| 1039 | nv_error(priv, "unable to find suitable dp config\n"); |
| 1040 | return; |
| 1041 | } |
| 1042 | |
| 1043 | /* XXX close to vbios numbers, but not right */ |
| 1044 | unk = (symbol - link_ratio) * bestTU; |
| 1045 | unk *= link_ratio; |
| 1046 | r = do_div(unk, symbol); |
| 1047 | r = do_div(unk, symbol); |
| 1048 | unk += 6; |
| 1049 | |
| 1050 | nv_mask(priv, 0x61c10c + loff, 0x000001fc, bestTU << 2); |
| 1051 | nv_mask(priv, 0x61c128 + loff, 0x010f7f3f, bestVTUa << 24 | |
| 1052 | bestVTUf << 16 | |
| 1053 | bestVTUi << 8 | unk); |
| 1054 | } |
| 1055 | |
| 1056 | static void |
| 1057 | nv50_disp_intr_unk20(struct nv50_disp_priv *priv, u32 super) |
| 1058 | { |
| 1059 | struct dcb_output outp; |
| 1060 | u32 addr, mask, data; |
| 1061 | int head; |
| 1062 | |
| 1063 | /* finish detaching encoder? */ |
| 1064 | head = ffs((super & 0x00000180) >> 7) - 1; |
| 1065 | if (head >= 0) |
| 1066 | exec_script(priv, head, 2); |
| 1067 | |
| 1068 | /* check whether a vpll change is required */ |
| 1069 | head = ffs((super & 0x00000600) >> 9) - 1; |
| 1070 | if (head >= 0) { |
| 1071 | u32 pclk = nv_rd32(priv, 0x610ad0 + (head * 0x540)) & 0x3fffff; |
| 1072 | if (pclk) { |
| 1073 | struct nouveau_clock *clk = nouveau_clock(priv); |
| 1074 | clk->pll_set(clk, PLL_VPLL0 + head, pclk); |
| 1075 | } |
| 1076 | |
| 1077 | nv_mask(priv, 0x614200 + head * 0x800, 0x0000000f, 0x00000000); |
| 1078 | } |
| 1079 | |
| 1080 | /* (re)attach the relevant OR to the head */ |
| 1081 | head = ffs((super & 0x00000180) >> 7) - 1; |
| 1082 | if (head >= 0) { |
| 1083 | u32 pclk = nv_rd32(priv, 0x610ad0 + (head * 0x540)) & 0x3fffff; |
Ben Skeggs | 0a0afd2 | 2013-02-18 23:17:53 -0500 | [diff] [blame] | 1084 | u32 conf = exec_clkcmp(priv, head, 0xff, pclk, &outp); |
Ben Skeggs | 46c13c1 | 2013-02-16 13:49:21 +1000 | [diff] [blame] | 1085 | if (conf != ~0) { |
Ben Skeggs | 0a0afd2 | 2013-02-18 23:17:53 -0500 | [diff] [blame] | 1086 | if (outp.location == 0 && outp.type == DCB_OUTPUT_DP) { |
| 1087 | u32 soff = (ffs(outp.or) - 1) * 0x08; |
| 1088 | u32 ctrl = nv_rd32(priv, 0x610798 + soff); |
| 1089 | u32 datarate; |
| 1090 | |
| 1091 | switch ((ctrl & 0x000f0000) >> 16) { |
| 1092 | case 6: datarate = pclk * 30 / 8; break; |
| 1093 | case 5: datarate = pclk * 24 / 8; break; |
| 1094 | case 2: |
| 1095 | default: |
| 1096 | datarate = pclk * 18 / 8; |
| 1097 | break; |
| 1098 | } |
| 1099 | |
| 1100 | nouveau_dp_train(&priv->base, priv->sor.dp, |
| 1101 | &outp, head, datarate); |
| 1102 | } |
| 1103 | |
| 1104 | exec_clkcmp(priv, head, 0, pclk, &outp); |
| 1105 | |
Ben Skeggs | 186ecad | 2012-11-09 12:09:48 +1000 | [diff] [blame] | 1106 | if (outp.type == DCB_OUTPUT_ANALOG) { |
| 1107 | addr = 0x614280 + (ffs(outp.or) - 1) * 0x800; |
| 1108 | mask = 0xffffffff; |
| 1109 | data = 0x00000000; |
| 1110 | } else { |
| 1111 | if (outp.type == DCB_OUTPUT_DP) |
| 1112 | nv50_disp_intr_unk20_dp(priv, &outp, pclk); |
| 1113 | addr = 0x614300 + (ffs(outp.or) - 1) * 0x800; |
| 1114 | mask = 0x00000707; |
| 1115 | data = (conf & 0x0100) ? 0x0101 : 0x0000; |
| 1116 | } |
| 1117 | |
| 1118 | nv_mask(priv, addr, mask, data); |
| 1119 | } |
| 1120 | } |
| 1121 | |
Ben Skeggs | 186ecad | 2012-11-09 12:09:48 +1000 | [diff] [blame] | 1122 | nv_wr32(priv, 0x610030, 0x80000000); |
| 1123 | } |
| 1124 | |
| 1125 | /* If programming a TMDS output on a SOR that can also be configured for |
| 1126 | * DisplayPort, make sure NV50_SOR_DP_CTRL_ENABLE is forced off. |
| 1127 | * |
| 1128 | * It looks like the VBIOS TMDS scripts make an attempt at this, however, |
| 1129 | * the VBIOS scripts on at least one board I have only switch it off on |
| 1130 | * link 0, causing a blank display if the output has previously been |
| 1131 | * programmed for DisplayPort. |
| 1132 | */ |
| 1133 | static void |
| 1134 | nv50_disp_intr_unk40_tmds(struct nv50_disp_priv *priv, struct dcb_output *outp) |
| 1135 | { |
| 1136 | struct nouveau_bios *bios = nouveau_bios(priv); |
| 1137 | const int link = !(outp->sorconf.link & 1); |
| 1138 | const int or = ffs(outp->or) - 1; |
| 1139 | const u32 loff = (or * 0x800) + (link * 0x80); |
| 1140 | const u16 mask = (outp->sorconf.link << 6) | outp->or; |
| 1141 | u8 ver, hdr; |
| 1142 | |
| 1143 | if (dcb_outp_match(bios, DCB_OUTPUT_DP, mask, &ver, &hdr, outp)) |
| 1144 | nv_mask(priv, 0x61c10c + loff, 0x00000001, 0x00000000); |
| 1145 | } |
| 1146 | |
| 1147 | static void |
| 1148 | nv50_disp_intr_unk40(struct nv50_disp_priv *priv, u32 super) |
| 1149 | { |
| 1150 | int head = ffs((super & 0x00000180) >> 7) - 1; |
| 1151 | if (head >= 0) { |
| 1152 | struct dcb_output outp; |
| 1153 | u32 pclk = nv_rd32(priv, 0x610ad0 + (head * 0x540)) & 0x3fffff; |
Ben Skeggs | 0a0afd2 | 2013-02-18 23:17:53 -0500 | [diff] [blame] | 1154 | if (exec_clkcmp(priv, head, 1, pclk, &outp) != ~0) |
| 1155 | if (outp.location == 0 && outp.type == DCB_OUTPUT_TMDS) |
Ben Skeggs | 186ecad | 2012-11-09 12:09:48 +1000 | [diff] [blame] | 1156 | nv50_disp_intr_unk40_tmds(priv, &outp); |
Ben Skeggs | 186ecad | 2012-11-09 12:09:48 +1000 | [diff] [blame] | 1157 | } |
| 1158 | |
Ben Skeggs | 186ecad | 2012-11-09 12:09:48 +1000 | [diff] [blame] | 1159 | nv_wr32(priv, 0x610030, 0x80000000); |
| 1160 | } |
| 1161 | |
Ben Skeggs | 5cc027f | 2013-02-18 17:50:51 -0500 | [diff] [blame] | 1162 | void |
| 1163 | nv50_disp_intr_supervisor(struct work_struct *work) |
Ben Skeggs | 186ecad | 2012-11-09 12:09:48 +1000 | [diff] [blame] | 1164 | { |
Ben Skeggs | 5cc027f | 2013-02-18 17:50:51 -0500 | [diff] [blame] | 1165 | struct nv50_disp_priv *priv = |
| 1166 | container_of(work, struct nv50_disp_priv, supervisor); |
Ben Skeggs | 186ecad | 2012-11-09 12:09:48 +1000 | [diff] [blame] | 1167 | u32 super = nv_rd32(priv, 0x610030); |
| 1168 | |
Ben Skeggs | 5cc027f | 2013-02-18 17:50:51 -0500 | [diff] [blame] | 1169 | nv_debug(priv, "supervisor 0x%08x 0x%08x\n", priv->super, super); |
Ben Skeggs | 186ecad | 2012-11-09 12:09:48 +1000 | [diff] [blame] | 1170 | |
Ben Skeggs | 5cc027f | 2013-02-18 17:50:51 -0500 | [diff] [blame] | 1171 | if (priv->super & 0x00000010) |
Ben Skeggs | 186ecad | 2012-11-09 12:09:48 +1000 | [diff] [blame] | 1172 | nv50_disp_intr_unk10(priv, super); |
Ben Skeggs | 5cc027f | 2013-02-18 17:50:51 -0500 | [diff] [blame] | 1173 | if (priv->super & 0x00000020) |
Ben Skeggs | 186ecad | 2012-11-09 12:09:48 +1000 | [diff] [blame] | 1174 | nv50_disp_intr_unk20(priv, super); |
Ben Skeggs | 5cc027f | 2013-02-18 17:50:51 -0500 | [diff] [blame] | 1175 | if (priv->super & 0x00000040) |
Ben Skeggs | 186ecad | 2012-11-09 12:09:48 +1000 | [diff] [blame] | 1176 | nv50_disp_intr_unk40(priv, super); |
| 1177 | } |
| 1178 | |
Ben Skeggs | 70cabe4 | 2012-08-14 10:04:04 +1000 | [diff] [blame] | 1179 | void |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 1180 | nv50_disp_intr(struct nouveau_subdev *subdev) |
| 1181 | { |
| 1182 | struct nv50_disp_priv *priv = (void *)subdev; |
Ben Skeggs | 186ecad | 2012-11-09 12:09:48 +1000 | [diff] [blame] | 1183 | u32 intr0 = nv_rd32(priv, 0x610020); |
| 1184 | u32 intr1 = nv_rd32(priv, 0x610024); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 1185 | |
Ben Skeggs | 186ecad | 2012-11-09 12:09:48 +1000 | [diff] [blame] | 1186 | if (intr0 & 0x001f0000) { |
| 1187 | nv50_disp_intr_error(priv); |
| 1188 | intr0 &= ~0x001f0000; |
| 1189 | } |
| 1190 | |
| 1191 | if (intr1 & 0x00000004) { |
Ben Skeggs | 1d7c71a | 2013-01-31 09:23:34 +1000 | [diff] [blame] | 1192 | nouveau_event_trigger(priv->base.vblank, 0); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 1193 | nv_wr32(priv, 0x610024, 0x00000004); |
Ben Skeggs | 186ecad | 2012-11-09 12:09:48 +1000 | [diff] [blame] | 1194 | intr1 &= ~0x00000004; |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 1195 | } |
| 1196 | |
Ben Skeggs | 186ecad | 2012-11-09 12:09:48 +1000 | [diff] [blame] | 1197 | if (intr1 & 0x00000008) { |
Ben Skeggs | 1d7c71a | 2013-01-31 09:23:34 +1000 | [diff] [blame] | 1198 | nouveau_event_trigger(priv->base.vblank, 1); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 1199 | nv_wr32(priv, 0x610024, 0x00000008); |
Ben Skeggs | 186ecad | 2012-11-09 12:09:48 +1000 | [diff] [blame] | 1200 | intr1 &= ~0x00000008; |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 1201 | } |
| 1202 | |
Ben Skeggs | 186ecad | 2012-11-09 12:09:48 +1000 | [diff] [blame] | 1203 | if (intr1 & 0x00000070) { |
Ben Skeggs | 5cc027f | 2013-02-18 17:50:51 -0500 | [diff] [blame] | 1204 | priv->super = (intr1 & 0x00000070); |
| 1205 | schedule_work(&priv->supervisor); |
| 1206 | nv_wr32(priv, 0x610024, priv->super); |
Ben Skeggs | 186ecad | 2012-11-09 12:09:48 +1000 | [diff] [blame] | 1207 | intr1 &= ~0x00000070; |
| 1208 | } |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 1209 | } |
| 1210 | |
| 1211 | static int |
| 1212 | nv50_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, |
Ben Skeggs | 370c00f | 2012-08-14 14:11:49 +1000 | [diff] [blame] | 1213 | struct nouveau_oclass *oclass, void *data, u32 size, |
| 1214 | struct nouveau_object **pobject) |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 1215 | { |
| 1216 | struct nv50_disp_priv *priv; |
| 1217 | int ret; |
| 1218 | |
Ben Skeggs | 1d7c71a | 2013-01-31 09:23:34 +1000 | [diff] [blame] | 1219 | ret = nouveau_disp_create(parent, engine, oclass, 2, "PDISP", |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 1220 | "display", &priv); |
| 1221 | *pobject = nv_object(priv); |
| 1222 | if (ret) |
| 1223 | return ret; |
| 1224 | |
Ben Skeggs | 70cabe4 | 2012-08-14 10:04:04 +1000 | [diff] [blame] | 1225 | nv_engine(priv)->sclass = nv50_disp_base_oclass; |
| 1226 | nv_engine(priv)->cclass = &nv50_disp_cclass; |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 1227 | nv_subdev(priv)->intr = nv50_disp_intr; |
Ben Skeggs | 5cc027f | 2013-02-18 17:50:51 -0500 | [diff] [blame] | 1228 | INIT_WORK(&priv->supervisor, nv50_disp_intr_supervisor); |
Ben Skeggs | 70cabe4 | 2012-08-14 10:04:04 +1000 | [diff] [blame] | 1229 | priv->sclass = nv50_disp_sclass; |
| 1230 | priv->head.nr = 2; |
| 1231 | priv->dac.nr = 3; |
| 1232 | priv->sor.nr = 2; |
Ben Skeggs | a2bc283 | 2013-02-11 09:11:08 +1000 | [diff] [blame^] | 1233 | priv->pior.nr = 3; |
Ben Skeggs | ef22c8b | 2012-11-09 09:32:56 +1000 | [diff] [blame] | 1234 | priv->dac.power = nv50_dac_power; |
Ben Skeggs | 7ebb38b | 2012-11-09 09:38:06 +1000 | [diff] [blame] | 1235 | priv->dac.sense = nv50_dac_sense; |
Ben Skeggs | ef22c8b | 2012-11-09 09:32:56 +1000 | [diff] [blame] | 1236 | priv->sor.power = nv50_sor_power; |
Ben Skeggs | a2bc283 | 2013-02-11 09:11:08 +1000 | [diff] [blame^] | 1237 | priv->pior.power = nv50_pior_power; |
| 1238 | priv->pior.dp = &nv50_pior_dp_func; |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 1239 | return 0; |
| 1240 | } |
| 1241 | |
| 1242 | struct nouveau_oclass |
| 1243 | nv50_disp_oclass = { |
| 1244 | .handle = NV_ENGINE(DISP, 0x50), |
| 1245 | .ofuncs = &(struct nouveau_ofuncs) { |
| 1246 | .ctor = nv50_disp_ctor, |
| 1247 | .dtor = _nouveau_disp_dtor, |
| 1248 | .init = _nouveau_disp_init, |
| 1249 | .fini = _nouveau_disp_fini, |
| 1250 | }, |
| 1251 | }; |