blob: aa537ed13f0a578ade79e74c62a56302f1d65437 [file] [log] [blame]
Simon Arlottec9653b2012-05-26 01:04:43 -06001/include/ "skeleton.dtsi"
2
3/ {
4 compatible = "brcm,bcm2835";
5 model = "BCM2835";
Simon Arlott89214f02012-09-12 19:57:26 -06006 interrupt-parent = <&intc>;
Simon Arlottec9653b2012-05-26 01:04:43 -06007
8 chosen {
Simon Arlott407f9be2012-09-10 23:29:17 -06009 bootargs = "earlyprintk console=ttyAMA0";
Simon Arlottec9653b2012-05-26 01:04:43 -060010 };
11
12 soc {
13 compatible = "simple-bus";
14 #address-cells = <1>;
15 #size-cells = <1>;
16 ranges = <0x7e000000 0x20000000 0x02000000>;
Simon Arlott89214f02012-09-12 19:57:26 -060017
Simon Arlottee4af562012-09-10 22:38:35 -060018 timer {
19 compatible = "brcm,bcm2835-system-timer";
20 reg = <0x7e003000 0x1000>;
21 interrupts = <1 0>, <1 1>, <1 2>, <1 3>;
22 clock-frequency = <1000000>;
23 };
24
Simon Arlott89214f02012-09-12 19:57:26 -060025 intc: interrupt-controller {
26 compatible = "brcm,bcm2835-armctrl-ic";
27 reg = <0x7e00b200 0x200>;
28 interrupt-controller;
29 #interrupt-cells = <2>;
30 };
Simon Arlott407f9be2012-09-10 23:29:17 -060031
Stephen Warrend0f1c7f2012-09-15 22:18:10 -060032 watchdog {
33 compatible = "brcm,bcm2835-pm-wdt";
34 reg = <0x7e100000 0x28>;
35 };
36
Lubomir Rintela1bf7082013-03-28 07:12:04 +010037 rng {
38 compatible = "brcm,bcm2835-rng";
39 reg = <0x7e104000 0x10>;
40 };
41
Simon Arlott407f9be2012-09-10 23:29:17 -060042 uart@20201000 {
43 compatible = "brcm,bcm2835-pl011", "arm,pl011", "arm,primecell";
44 reg = <0x7e201000 0x1000>;
45 interrupts = <2 25>;
46 clock-frequency = <3000000>;
Jongsung Kim13731d82013-05-29 22:07:39 -060047 arm,primecell-periphid = <0x00241011>;
Simon Arlott407f9be2012-09-10 23:29:17 -060048 };
Stephen Warren805504a2012-09-27 21:54:21 -060049
50 gpio: gpio {
51 compatible = "brcm,bcm2835-gpio";
52 reg = <0x7e200000 0xb4>;
53 /*
54 * The GPIO IP block is designed for 3 banks of GPIOs.
55 * Each bank has a GPIO interrupt for itself.
56 * There is an overall "any bank" interrupt.
57 * In order, these are GIC interrupts 17, 18, 19, 20.
58 * Since the BCM2835 only has 2 banks, the 2nd bank
59 * interrupt output appears to be mirrored onto the
60 * 3rd bank's interrupt signal.
61 * So, a bank0 interrupt shows up on 17, 20, and
62 * a bank1 interrupt shows up on 18, 19, 20!
63 */
64 interrupts = <2 17>, <2 18>, <2 19>, <2 20>;
65
66 gpio-controller;
67 #gpio-cells = <2>;
68
69 interrupt-controller;
70 #interrupt-cells = <2>;
71 };
Stephen Warren5186bf22012-12-24 21:58:56 -070072
Stephen Warren6ce5f022013-02-19 21:39:58 -070073 spi: spi@20204000 {
74 compatible = "brcm,bcm2835-spi";
75 reg = <0x7e204000 0x1000>;
76 interrupts = <2 22>;
77 clocks = <&clk_spi>;
78 #address-cells = <1>;
79 #size-cells = <0>;
80 status = "disabled";
81 };
82
Stephen Warren232fed42012-12-31 23:26:45 -070083 i2c0: i2c@20205000 {
84 compatible = "brcm,bcm2835-i2c";
85 reg = <0x7e205000 0x1000>;
86 interrupts = <2 21>;
87 clocks = <&clk_i2c>;
Stephen Warrena31ab442013-11-25 20:35:42 -070088 #address-cells = <1>;
89 #size-cells = <0>;
Stephen Warren232fed42012-12-31 23:26:45 -070090 status = "disabled";
91 };
92
93 i2c1: i2c@20804000 {
94 compatible = "brcm,bcm2835-i2c";
95 reg = <0x7e804000 0x1000>;
96 interrupts = <2 21>;
97 clocks = <&clk_i2c>;
Stephen Warrena31ab442013-11-25 20:35:42 -070098 #address-cells = <1>;
99 #size-cells = <0>;
Stephen Warren232fed42012-12-31 23:26:45 -0700100 status = "disabled";
101 };
102
Stephen Warren5186bf22012-12-24 21:58:56 -0700103 sdhci: sdhci {
104 compatible = "brcm,bcm2835-sdhci";
105 reg = <0x7e300000 0x100>;
106 interrupts = <2 30>;
107 clocks = <&clk_mmc>;
108 status = "disabled";
109 };
110 };
111
Stephen Warren9692c192013-01-14 21:07:20 -0700112 clocks {
113 compatible = "simple-bus";
114 #address-cells = <1>;
115 #size-cells = <0>;
Stephen Warren232fed42012-12-31 23:26:45 -0700116
Stephen Warren9692c192013-01-14 21:07:20 -0700117 clk_mmc: mmc {
118 compatible = "fixed-clock";
119 reg = <0>;
120 #clock-cells = <0>;
121 clock-frequency = <100000000>;
122 };
123
124 clk_i2c: i2c {
125 compatible = "fixed-clock";
126 reg = <1>;
127 #clock-cells = <0>;
Stephen Warren2837a1d2013-02-21 22:42:38 -0700128 clock-frequency = <250000000>;
Stephen Warren9692c192013-01-14 21:07:20 -0700129 };
Stephen Warren6ce5f022013-02-19 21:39:58 -0700130
131 clk_spi: spi {
132 compatible = "fixed-clock";
133 reg = <2>;
134 #clock-cells = <0>;
135 clock-frequency = <250000000>;
136 };
Simon Arlottec9653b2012-05-26 01:04:43 -0600137 };
138};