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Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001/* bnx2x_reg.h: Broadcom Everest network driver.
2 *
Dmitry Kravkov5de92402011-05-04 23:51:13 +00003 * Copyright (c) 2007-2011 Broadcom Corporation
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
Eilon Greenstein33471622008-08-13 15:59:08 -07009 * The registers description starts with the register Access type followed
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020010 * by size in bits. For example [RW 32]. The access types are:
11 * R - Read only
12 * RC - Clear on read
13 * RW - Read/Write
14 * ST - Statistics register (clear on read)
15 * W - Write only
16 * WB - Wide bus register - the size is over 32 bits and it should be
17 * read/write in consecutive 32 bits accesses
18 * WR - Write Clear (write 1 to clear the bit)
19 *
20 */
Vladislav Zolotarov4a33bc02011-01-09 02:20:04 +000021#ifndef BNX2X_REG_H
22#define BNX2X_REG_H
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020023
Dmitry Kravkovf2e08992010-10-06 03:28:26 +000024#define ATC_ATC_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
25#define ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS (0x1<<2)
26#define ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU (0x1<<5)
27#define ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT (0x1<<3)
28#define ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR (0x1<<4)
29#define ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND (0x1<<1)
30/* [RW 1] Initiate the ATC array - reset all the valid bits */
31#define ATC_REG_ATC_INIT_ARRAY 0x1100b8
32/* [R 1] ATC initalization done */
33#define ATC_REG_ATC_INIT_DONE 0x1100bc
34/* [RC 6] Interrupt register #0 read clear */
35#define ATC_REG_ATC_INT_STS_CLR 0x1101c0
36/* [RW 19] Interrupt mask register #0 read/write */
37#define BRB1_REG_BRB1_INT_MASK 0x60128
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020038/* [R 19] Interrupt register #0 read */
39#define BRB1_REG_BRB1_INT_STS 0x6011c
40/* [RW 4] Parity mask register #0 read/write */
41#define BRB1_REG_BRB1_PRTY_MASK 0x60138
Eliezer Tamirf1410642008-02-28 11:51:50 -080042/* [R 4] Parity register #0 read */
43#define BRB1_REG_BRB1_PRTY_STS 0x6012c
Vladislav Zolotarov4a33bc02011-01-09 02:20:04 +000044/* [RC 4] Parity register #0 read clear */
45#define BRB1_REG_BRB1_PRTY_STS_CLR 0x60130
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020046/* [RW 10] At address BRB1_IND_FREE_LIST_PRS_CRDT initialize free head. At
Dmitry Kravkovf2e08992010-10-06 03:28:26 +000047 * address BRB1_IND_FREE_LIST_PRS_CRDT+1 initialize free tail. At address
48 * BRB1_IND_FREE_LIST_PRS_CRDT+2 initialize parser initial credit. Warning -
49 * following reset the first rbc access to this reg must be write; there can
50 * be no more rbc writes after the first one; there can be any number of rbc
51 * read following the first write; rbc access not following these rules will
52 * result in hang condition. */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020053#define BRB1_REG_FREE_LIST_PRS_CRDT 0x60200
Dmitry Kravkovf2e08992010-10-06 03:28:26 +000054/* [RW 10] The number of free blocks below which the full signal to class 0
55 * is asserted */
56#define BRB1_REG_FULL_0_XOFF_THRESHOLD_0 0x601d0
Yaniv Rosner9380bb92011-06-14 01:34:07 +000057#define BRB1_REG_FULL_0_XOFF_THRESHOLD_1 0x60230
58/* [RW 11] The number of free blocks above which the full signal to class 0
Dmitry Kravkovf2e08992010-10-06 03:28:26 +000059 * is de-asserted */
60#define BRB1_REG_FULL_0_XON_THRESHOLD_0 0x601d4
Yaniv Rosner9380bb92011-06-14 01:34:07 +000061#define BRB1_REG_FULL_0_XON_THRESHOLD_1 0x60234
62/* [RW 11] The number of free blocks below which the full signal to class 1
Dmitry Kravkovf2e08992010-10-06 03:28:26 +000063 * is asserted */
64#define BRB1_REG_FULL_1_XOFF_THRESHOLD_0 0x601d8
Yaniv Rosner9380bb92011-06-14 01:34:07 +000065#define BRB1_REG_FULL_1_XOFF_THRESHOLD_1 0x60238
66/* [RW 11] The number of free blocks above which the full signal to class 1
Dmitry Kravkovf2e08992010-10-06 03:28:26 +000067 * is de-asserted */
68#define BRB1_REG_FULL_1_XON_THRESHOLD_0 0x601dc
Yaniv Rosner9380bb92011-06-14 01:34:07 +000069#define BRB1_REG_FULL_1_XON_THRESHOLD_1 0x6023c
70/* [RW 11] The number of free blocks below which the full signal to the LB
Dmitry Kravkovf2e08992010-10-06 03:28:26 +000071 * port is asserted */
72#define BRB1_REG_FULL_LB_XOFF_THRESHOLD 0x601e0
73/* [RW 10] The number of free blocks above which the full signal to the LB
74 * port is de-asserted */
75#define BRB1_REG_FULL_LB_XON_THRESHOLD 0x601e4
Eilon Greenstein1c063282009-02-12 08:36:43 +000076/* [RW 10] The number of free blocks above which the High_llfc signal to
77 interface #n is de-asserted. */
78#define BRB1_REG_HIGH_LLFC_HIGH_THRESHOLD_0 0x6014c
79/* [RW 10] The number of free blocks below which the High_llfc signal to
80 interface #n is asserted. */
81#define BRB1_REG_HIGH_LLFC_LOW_THRESHOLD_0 0x6013c
Yaniv Rosner9380bb92011-06-14 01:34:07 +000082/* [RW 11] The number of blocks guarantied for the LB port */
83#define BRB1_REG_LB_GUARANTIED 0x601ec
84/* [RW 11] The hysteresis on the guarantied buffer space for the Lb port
85 * before signaling XON. */
86#define BRB1_REG_LB_GUARANTIED_HYST 0x60264
87/* [RW 24] LL RAM data. */
88#define BRB1_REG_LL_RAM 0x61000
Eilon Greenstein1c063282009-02-12 08:36:43 +000089/* [RW 10] The number of free blocks above which the Low_llfc signal to
90 interface #n is de-asserted. */
91#define BRB1_REG_LOW_LLFC_HIGH_THRESHOLD_0 0x6016c
92/* [RW 10] The number of free blocks below which the Low_llfc signal to
93 interface #n is asserted. */
94#define BRB1_REG_LOW_LLFC_LOW_THRESHOLD_0 0x6015c
Yaniv Rosner9380bb92011-06-14 01:34:07 +000095/* [RW 11] The number of blocks guarantied for class 0 in MAC 0. The
96 * register is applicable only when per_class_guaranty_mode is set. */
97#define BRB1_REG_MAC_0_CLASS_0_GUARANTIED 0x60244
98/* [RW 11] The hysteresis on the guarantied buffer space for class 0 in MAC
99 * 1 before signaling XON. The register is applicable only when
100 * per_class_guaranty_mode is set. */
101#define BRB1_REG_MAC_0_CLASS_0_GUARANTIED_HYST 0x60254
102/* [RW 11] The number of blocks guarantied for class 1 in MAC 0. The
103 * register is applicable only when per_class_guaranty_mode is set. */
104#define BRB1_REG_MAC_0_CLASS_1_GUARANTIED 0x60248
105/* [RW 11] The hysteresis on the guarantied buffer space for class 1in MAC 0
106 * before signaling XON. The register is applicable only when
107 * per_class_guaranty_mode is set. */
108#define BRB1_REG_MAC_0_CLASS_1_GUARANTIED_HYST 0x60258
109/* [RW 11] The number of blocks guarantied for class 0in MAC1.The register
110 * is applicable only when per_class_guaranty_mode is set. */
111#define BRB1_REG_MAC_1_CLASS_0_GUARANTIED 0x6024c
112/* [RW 11] The hysteresis on the guarantied buffer space for class 0 in MAC
113 * 1 before signaling XON. The register is applicable only when
114 * per_class_guaranty_mode is set. */
115#define BRB1_REG_MAC_1_CLASS_0_GUARANTIED_HYST 0x6025c
116/* [RW 11] The number of blocks guarantied for class 1 in MAC 1. The
117 * register is applicable only when per_class_guaranty_mode is set. */
118#define BRB1_REG_MAC_1_CLASS_1_GUARANTIED 0x60250
119/* [RW 11] The hysteresis on the guarantied buffer space for class 1 in MAC
120 * 1 before signaling XON. The register is applicable only when
121 * per_class_guaranty_mode is set. */
122#define BRB1_REG_MAC_1_CLASS_1_GUARANTIED_HYST 0x60260
123/* [RW 11] The number of blocks guarantied for the MAC port. The register is
124 * applicable only when per_class_guaranty_mode is reset. */
Dmitry Kravkovf2e08992010-10-06 03:28:26 +0000125#define BRB1_REG_MAC_GUARANTIED_0 0x601e8
126#define BRB1_REG_MAC_GUARANTIED_1 0x60240
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200127/* [R 24] The number of full blocks. */
128#define BRB1_REG_NUM_OF_FULL_BLOCKS 0x60090
129/* [ST 32] The number of cycles that the write_full signal towards MAC #0
130 was asserted. */
131#define BRB1_REG_NUM_OF_FULL_CYCLES_0 0x600c8
132#define BRB1_REG_NUM_OF_FULL_CYCLES_1 0x600cc
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200133#define BRB1_REG_NUM_OF_FULL_CYCLES_4 0x600d8
134/* [ST 32] The number of cycles that the pause signal towards MAC #0 was
135 asserted. */
136#define BRB1_REG_NUM_OF_PAUSE_CYCLES_0 0x600b8
137#define BRB1_REG_NUM_OF_PAUSE_CYCLES_1 0x600bc
Dmitry Kravkovf2e08992010-10-06 03:28:26 +0000138/* [RW 10] The number of free blocks below which the pause signal to class 0
139 * is asserted */
140#define BRB1_REG_PAUSE_0_XOFF_THRESHOLD_0 0x601c0
Yaniv Rosner9380bb92011-06-14 01:34:07 +0000141#define BRB1_REG_PAUSE_0_XOFF_THRESHOLD_1 0x60220
142/* [RW 11] The number of free blocks above which the pause signal to class 0
Dmitry Kravkovf2e08992010-10-06 03:28:26 +0000143 * is de-asserted */
144#define BRB1_REG_PAUSE_0_XON_THRESHOLD_0 0x601c4
Yaniv Rosner9380bb92011-06-14 01:34:07 +0000145#define BRB1_REG_PAUSE_0_XON_THRESHOLD_1 0x60224
146/* [RW 11] The number of free blocks below which the pause signal to class 1
Dmitry Kravkovf2e08992010-10-06 03:28:26 +0000147 * is asserted */
148#define BRB1_REG_PAUSE_1_XOFF_THRESHOLD_0 0x601c8
Yaniv Rosner9380bb92011-06-14 01:34:07 +0000149#define BRB1_REG_PAUSE_1_XOFF_THRESHOLD_1 0x60228
150/* [RW 11] The number of free blocks above which the pause signal to class 1
Dmitry Kravkovf2e08992010-10-06 03:28:26 +0000151 * is de-asserted */
152#define BRB1_REG_PAUSE_1_XON_THRESHOLD_0 0x601cc
Yaniv Rosner9380bb92011-06-14 01:34:07 +0000153#define BRB1_REG_PAUSE_1_XON_THRESHOLD_1 0x6022c
Dmitry Kravkovf2e08992010-10-06 03:28:26 +0000154/* [RW 10] Write client 0: De-assert pause threshold. Not Functional */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200155#define BRB1_REG_PAUSE_HIGH_THRESHOLD_0 0x60078
156#define BRB1_REG_PAUSE_HIGH_THRESHOLD_1 0x6007c
157/* [RW 10] Write client 0: Assert pause threshold. */
158#define BRB1_REG_PAUSE_LOW_THRESHOLD_0 0x60068
159#define BRB1_REG_PAUSE_LOW_THRESHOLD_1 0x6006c
Eilon Greenstein33471622008-08-13 15:59:08 -0700160/* [R 24] The number of full blocks occupied by port. */
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700161#define BRB1_REG_PORT_NUM_OCC_BLOCKS_0 0x60094
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200162/* [RW 1] Reset the design by software. */
163#define BRB1_REG_SOFT_RESET 0x600dc
164/* [R 5] Used to read the value of the XX protection CAM occupancy counter. */
165#define CCM_REG_CAM_OCCUP 0xd0188
166/* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded;
167 acknowledge output is deasserted; all other signals are treated as usual;
168 if 1 - normal activity. */
169#define CCM_REG_CCM_CFC_IFEN 0xd003c
170/* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is
171 disregarded; valid is deasserted; all other signals are treated as usual;
172 if 1 - normal activity. */
173#define CCM_REG_CCM_CQM_IFEN 0xd000c
174/* [RW 1] If set the Q index; received from the QM is inserted to event ID.
175 Otherwise 0 is inserted. */
176#define CCM_REG_CCM_CQM_USE_Q 0xd00c0
177/* [RW 11] Interrupt mask register #0 read/write */
178#define CCM_REG_CCM_INT_MASK 0xd01e4
179/* [R 11] Interrupt register #0 read */
180#define CCM_REG_CCM_INT_STS 0xd01d8
Vladislav Zolotarov4a33bc02011-01-09 02:20:04 +0000181/* [RW 27] Parity mask register #0 read/write */
182#define CCM_REG_CCM_PRTY_MASK 0xd01f4
Yaniv Rosnerc18487e2008-06-23 20:27:52 -0700183/* [R 27] Parity register #0 read */
184#define CCM_REG_CCM_PRTY_STS 0xd01e8
Vladislav Zolotarov4a33bc02011-01-09 02:20:04 +0000185/* [RC 27] Parity register #0 read clear */
186#define CCM_REG_CCM_PRTY_STS_CLR 0xd01ec
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200187/* [RW 3] The size of AG context region 0 in REG-pairs. Designates the MS
188 REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5).
189 Is used to determine the number of the AG context REG-pairs written back;
190 when the input message Reg1WbFlg isn't set. */
191#define CCM_REG_CCM_REG0_SZ 0xd00c4
192/* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is
193 disregarded; valid is deasserted; all other signals are treated as usual;
194 if 1 - normal activity. */
195#define CCM_REG_CCM_STORM0_IFEN 0xd0004
196/* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is
197 disregarded; valid is deasserted; all other signals are treated as usual;
198 if 1 - normal activity. */
199#define CCM_REG_CCM_STORM1_IFEN 0xd0008
200/* [RW 1] CDU AG read Interface enable. If 0 - the request input is
201 disregarded; valid output is deasserted; all other signals are treated as
202 usual; if 1 - normal activity. */
203#define CCM_REG_CDU_AG_RD_IFEN 0xd0030
204/* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input
205 are disregarded; all other signals are treated as usual; if 1 - normal
206 activity. */
207#define CCM_REG_CDU_AG_WR_IFEN 0xd002c
208/* [RW 1] CDU STORM read Interface enable. If 0 - the request input is
209 disregarded; valid output is deasserted; all other signals are treated as
210 usual; if 1 - normal activity. */
211#define CCM_REG_CDU_SM_RD_IFEN 0xd0038
212/* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid
213 input is disregarded; all other signals are treated as usual; if 1 -
214 normal activity. */
215#define CCM_REG_CDU_SM_WR_IFEN 0xd0034
216/* [RW 4] CFC output initial credit. Max credit available - 15.Write writes
217 the initial credit value; read returns the current value of the credit
218 counter. Must be initialized to 1 at start-up. */
219#define CCM_REG_CFC_INIT_CRD 0xd0204
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300220/* [RW 2] Auxiliary counter flag Q number 1. */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200221#define CCM_REG_CNT_AUX1_Q 0xd00c8
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300222/* [RW 2] Auxiliary counter flag Q number 2. */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200223#define CCM_REG_CNT_AUX2_Q 0xd00cc
224/* [RW 28] The CM header value for QM request (primary). */
225#define CCM_REG_CQM_CCM_HDR_P 0xd008c
226/* [RW 28] The CM header value for QM request (secondary). */
227#define CCM_REG_CQM_CCM_HDR_S 0xd0090
228/* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded;
229 acknowledge output is deasserted; all other signals are treated as usual;
230 if 1 - normal activity. */
231#define CCM_REG_CQM_CCM_IFEN 0xd0014
232/* [RW 6] QM output initial credit. Max credit available - 32. Write writes
233 the initial credit value; read returns the current value of the credit
234 counter. Must be initialized to 32 at start-up. */
235#define CCM_REG_CQM_INIT_CRD 0xd020c
236/* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0
237 stands for weight 8 (the most prioritised); 1 stands for weight 1(least
238 prioritised); 2 stands for weight 2; tc. */
239#define CCM_REG_CQM_P_WEIGHT 0xd00b8
Eilon Greenstein8d9c5f32009-02-15 23:24:08 -0800240/* [RW 3] The weight of the QM (secondary) input in the WRR mechanism. 0
241 stands for weight 8 (the most prioritised); 1 stands for weight 1(least
242 prioritised); 2 stands for weight 2; tc. */
243#define CCM_REG_CQM_S_WEIGHT 0xd00bc
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200244/* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded;
245 acknowledge output is deasserted; all other signals are treated as usual;
246 if 1 - normal activity. */
247#define CCM_REG_CSDM_IFEN 0xd0018
248/* [RC 1] Set when the message length mismatch (relative to last indication)
249 at the SDM interface is detected. */
250#define CCM_REG_CSDM_LENGTH_MIS 0xd0170
Eilon Greenstein8d9c5f32009-02-15 23:24:08 -0800251/* [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands for
252 weight 8 (the most prioritised); 1 stands for weight 1(least
253 prioritised); 2 stands for weight 2; tc. */
254#define CCM_REG_CSDM_WEIGHT 0xd00b4
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200255/* [RW 28] The CM header for QM formatting in case of an error in the QM
256 inputs. */
257#define CCM_REG_ERR_CCM_HDR 0xd0094
258/* [RW 8] The Event ID in case the input message ErrorFlg is set. */
259#define CCM_REG_ERR_EVNT_ID 0xd0098
260/* [RW 8] FIC0 output initial credit. Max credit available - 255. Write
261 writes the initial credit value; read returns the current value of the
262 credit counter. Must be initialized to 64 at start-up. */
263#define CCM_REG_FIC0_INIT_CRD 0xd0210
264/* [RW 8] FIC1 output initial credit. Max credit available - 255.Write
265 writes the initial credit value; read returns the current value of the
266 credit counter. Must be initialized to 64 at start-up. */
267#define CCM_REG_FIC1_INIT_CRD 0xd0214
268/* [RW 1] Arbitration between Input Arbiter groups: 0 - fair Round-Robin; 1
269 - strict priority defined by ~ccm_registers_gr_ag_pr.gr_ag_pr;
270 ~ccm_registers_gr_ld0_pr.gr_ld0_pr and
271 ~ccm_registers_gr_ld1_pr.gr_ld1_pr. Groups are according to channels and
272 outputs to STORM: aggregation; load FIC0; load FIC1 and store. */
273#define CCM_REG_GR_ARB_TYPE 0xd015c
274/* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the
275 highest priority is 3. It is supposed; that the Store channel priority is
276 the compliment to 4 of the rest priorities - Aggregation channel; Load
277 (FIC0) channel and Load (FIC1). */
278#define CCM_REG_GR_LD0_PR 0xd0164
279/* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the
280 highest priority is 3. It is supposed; that the Store channel priority is
281 the compliment to 4 of the rest priorities - Aggregation channel; Load
282 (FIC0) channel and Load (FIC1). */
283#define CCM_REG_GR_LD1_PR 0xd0168
284/* [RW 2] General flags index. */
285#define CCM_REG_INV_DONE_Q 0xd0108
286/* [RW 4] The number of double REG-pairs(128 bits); loaded from the STORM
287 context and sent to STORM; for a specific connection type. The double
288 REG-pairs are used in order to align to STORM context row size of 128
289 bits. The offset of these data in the STORM context is always 0. Index
290 _(0..15) stands for the connection type (one of 16). */
291#define CCM_REG_N_SM_CTX_LD_0 0xd004c
292#define CCM_REG_N_SM_CTX_LD_1 0xd0050
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200293#define CCM_REG_N_SM_CTX_LD_2 0xd0054
294#define CCM_REG_N_SM_CTX_LD_3 0xd0058
295#define CCM_REG_N_SM_CTX_LD_4 0xd005c
296/* [RW 1] Input pbf Interface enable. If 0 - the valid input is disregarded;
297 acknowledge output is deasserted; all other signals are treated as usual;
298 if 1 - normal activity. */
299#define CCM_REG_PBF_IFEN 0xd0028
300/* [RC 1] Set when the message length mismatch (relative to last indication)
301 at the pbf interface is detected. */
302#define CCM_REG_PBF_LENGTH_MIS 0xd0180
303/* [RW 3] The weight of the input pbf in the WRR mechanism. 0 stands for
304 weight 8 (the most prioritised); 1 stands for weight 1(least
305 prioritised); 2 stands for weight 2; tc. */
306#define CCM_REG_PBF_WEIGHT 0xd00ac
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200307#define CCM_REG_PHYS_QNUM1_0 0xd0134
308#define CCM_REG_PHYS_QNUM1_1 0xd0138
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200309#define CCM_REG_PHYS_QNUM2_0 0xd013c
310#define CCM_REG_PHYS_QNUM2_1 0xd0140
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200311#define CCM_REG_PHYS_QNUM3_0 0xd0144
Yaniv Rosnerc18487e2008-06-23 20:27:52 -0700312#define CCM_REG_PHYS_QNUM3_1 0xd0148
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200313#define CCM_REG_QOS_PHYS_QNUM0_0 0xd0114
314#define CCM_REG_QOS_PHYS_QNUM0_1 0xd0118
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200315#define CCM_REG_QOS_PHYS_QNUM1_0 0xd011c
316#define CCM_REG_QOS_PHYS_QNUM1_1 0xd0120
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200317#define CCM_REG_QOS_PHYS_QNUM2_0 0xd0124
Yaniv Rosnerc18487e2008-06-23 20:27:52 -0700318#define CCM_REG_QOS_PHYS_QNUM2_1 0xd0128
319#define CCM_REG_QOS_PHYS_QNUM3_0 0xd012c
320#define CCM_REG_QOS_PHYS_QNUM3_1 0xd0130
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200321/* [RW 1] STORM - CM Interface enable. If 0 - the valid input is
322 disregarded; acknowledge output is deasserted; all other signals are
323 treated as usual; if 1 - normal activity. */
324#define CCM_REG_STORM_CCM_IFEN 0xd0010
325/* [RC 1] Set when the message length mismatch (relative to last indication)
326 at the STORM interface is detected. */
327#define CCM_REG_STORM_LENGTH_MIS 0xd016c
Eilon Greenstein8d9c5f32009-02-15 23:24:08 -0800328/* [RW 3] The weight of the STORM input in the WRR (Weighted Round robin)
329 mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for
330 weight 1(least prioritised); 2 stands for weight 2 (more prioritised);
331 tc. */
332#define CCM_REG_STORM_WEIGHT 0xd009c
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200333/* [RW 1] Input tsem Interface enable. If 0 - the valid input is
334 disregarded; acknowledge output is deasserted; all other signals are
335 treated as usual; if 1 - normal activity. */
336#define CCM_REG_TSEM_IFEN 0xd001c
337/* [RC 1] Set when the message length mismatch (relative to last indication)
338 at the tsem interface is detected. */
339#define CCM_REG_TSEM_LENGTH_MIS 0xd0174
340/* [RW 3] The weight of the input tsem in the WRR mechanism. 0 stands for
341 weight 8 (the most prioritised); 1 stands for weight 1(least
342 prioritised); 2 stands for weight 2; tc. */
343#define CCM_REG_TSEM_WEIGHT 0xd00a0
344/* [RW 1] Input usem Interface enable. If 0 - the valid input is
345 disregarded; acknowledge output is deasserted; all other signals are
346 treated as usual; if 1 - normal activity. */
347#define CCM_REG_USEM_IFEN 0xd0024
348/* [RC 1] Set when message length mismatch (relative to last indication) at
349 the usem interface is detected. */
350#define CCM_REG_USEM_LENGTH_MIS 0xd017c
351/* [RW 3] The weight of the input usem in the WRR mechanism. 0 stands for
352 weight 8 (the most prioritised); 1 stands for weight 1(least
353 prioritised); 2 stands for weight 2; tc. */
354#define CCM_REG_USEM_WEIGHT 0xd00a8
355/* [RW 1] Input xsem Interface enable. If 0 - the valid input is
356 disregarded; acknowledge output is deasserted; all other signals are
357 treated as usual; if 1 - normal activity. */
358#define CCM_REG_XSEM_IFEN 0xd0020
359/* [RC 1] Set when the message length mismatch (relative to last indication)
360 at the xsem interface is detected. */
361#define CCM_REG_XSEM_LENGTH_MIS 0xd0178
362/* [RW 3] The weight of the input xsem in the WRR mechanism. 0 stands for
363 weight 8 (the most prioritised); 1 stands for weight 1(least
364 prioritised); 2 stands for weight 2; tc. */
365#define CCM_REG_XSEM_WEIGHT 0xd00a4
366/* [RW 19] Indirect access to the descriptor table of the XX protection
367 mechanism. The fields are: [5:0] - message length; [12:6] - message
368 pointer; 18:13] - next pointer. */
369#define CCM_REG_XX_DESCR_TABLE 0xd0300
Yaniv Rosnerc18487e2008-06-23 20:27:52 -0700370#define CCM_REG_XX_DESCR_TABLE_SIZE 36
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200371/* [R 7] Used to read the value of XX protection Free counter. */
372#define CCM_REG_XX_FREE 0xd0184
373/* [RW 6] Initial value for the credit counter; responsible for fulfilling
374 of the Input Stage XX protection buffer by the XX protection pending
375 messages. Max credit available - 127. Write writes the initial credit
376 value; read returns the current value of the credit counter. Must be
377 initialized to maximum XX protected message size - 2 at start-up. */
378#define CCM_REG_XX_INIT_CRD 0xd0220
379/* [RW 7] The maximum number of pending messages; which may be stored in XX
380 protection. At read the ~ccm_registers_xx_free.xx_free counter is read.
381 At write comprises the start value of the ~ccm_registers_xx_free.xx_free
382 counter. */
383#define CCM_REG_XX_MSG_NUM 0xd0224
384/* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */
385#define CCM_REG_XX_OVFL_EVNT_ID 0xd0044
386/* [RW 18] Indirect access to the XX table of the XX protection mechanism.
387 The fields are: [5:0] - tail pointer; 11:6] - Link List size; 17:12] -
388 header pointer. */
389#define CCM_REG_XX_TABLE 0xd0280
390#define CDU_REG_CDU_CHK_MASK0 0x101000
391#define CDU_REG_CDU_CHK_MASK1 0x101004
392#define CDU_REG_CDU_CONTROL0 0x101008
393#define CDU_REG_CDU_DEBUG 0x101010
394#define CDU_REG_CDU_GLOBAL_PARAMS 0x101020
395/* [RW 7] Interrupt mask register #0 read/write */
396#define CDU_REG_CDU_INT_MASK 0x10103c
397/* [R 7] Interrupt register #0 read */
398#define CDU_REG_CDU_INT_STS 0x101030
399/* [RW 5] Parity mask register #0 read/write */
400#define CDU_REG_CDU_PRTY_MASK 0x10104c
Eliezer Tamirf1410642008-02-28 11:51:50 -0800401/* [R 5] Parity register #0 read */
402#define CDU_REG_CDU_PRTY_STS 0x101040
Vladislav Zolotarov4a33bc02011-01-09 02:20:04 +0000403/* [RC 5] Parity register #0 read clear */
404#define CDU_REG_CDU_PRTY_STS_CLR 0x101044
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200405/* [RC 32] logging of error data in case of a CDU load error:
406 {expected_cid[15:0]; xpected_type[2:0]; xpected_region[2:0]; ctive_error;
407 ype_error; ctual_active; ctual_compressed_context}; */
408#define CDU_REG_ERROR_DATA 0x101014
409/* [WB 216] L1TT ram access. each entry has the following format :
410 {mrege_regions[7:0]; ffset12[5:0]...offset0[5:0];
411 ength12[5:0]...length0[5:0]; d12[3:0]...id0[3:0]} */
412#define CDU_REG_L1TT 0x101800
413/* [WB 24] MATT ram access. each entry has the following
414 format:{RegionLength[11:0]; egionOffset[11:0]} */
415#define CDU_REG_MATT 0x101100
Yaniv Rosnerc18487e2008-06-23 20:27:52 -0700416/* [RW 1] when this bit is set the CDU operates in e1hmf mode */
417#define CDU_REG_MF_MODE 0x101050
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200418/* [R 1] indication the initializing the activity counter by the hardware
419 was done. */
420#define CFC_REG_AC_INIT_DONE 0x104078
421/* [RW 13] activity counter ram access */
422#define CFC_REG_ACTIVITY_COUNTER 0x104400
423#define CFC_REG_ACTIVITY_COUNTER_SIZE 256
424/* [R 1] indication the initializing the cams by the hardware was done. */
425#define CFC_REG_CAM_INIT_DONE 0x10407c
426/* [RW 2] Interrupt mask register #0 read/write */
427#define CFC_REG_CFC_INT_MASK 0x104108
428/* [R 2] Interrupt register #0 read */
429#define CFC_REG_CFC_INT_STS 0x1040fc
430/* [RC 2] Interrupt register #0 read clear */
431#define CFC_REG_CFC_INT_STS_CLR 0x104100
432/* [RW 4] Parity mask register #0 read/write */
433#define CFC_REG_CFC_PRTY_MASK 0x104118
Eliezer Tamirf1410642008-02-28 11:51:50 -0800434/* [R 4] Parity register #0 read */
435#define CFC_REG_CFC_PRTY_STS 0x10410c
Vladislav Zolotarov4a33bc02011-01-09 02:20:04 +0000436/* [RC 4] Parity register #0 read clear */
437#define CFC_REG_CFC_PRTY_STS_CLR 0x104110
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200438/* [RW 21] CID cam access (21:1 - Data; alid - 0) */
439#define CFC_REG_CID_CAM 0x104800
440#define CFC_REG_CONTROL0 0x104028
441#define CFC_REG_DEBUG0 0x104050
442/* [RW 14] indicates per error (in #cfc_registers_cfc_error_vector.cfc_error
443 vector) whether the cfc should be disabled upon it */
444#define CFC_REG_DISABLE_ON_ERROR 0x104044
445/* [RC 14] CFC error vector. when the CFC detects an internal error it will
446 set one of these bits. the bit description can be found in CFC
447 specifications */
448#define CFC_REG_ERROR_VECTOR 0x10403c
Eilon Greenstein8d9c5f32009-02-15 23:24:08 -0800449/* [WB 93] LCID info ram access */
450#define CFC_REG_INFO_RAM 0x105000
451#define CFC_REG_INFO_RAM_SIZE 1024
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200452#define CFC_REG_INIT_REG 0x10404c
Eilon Greenstein8d9c5f32009-02-15 23:24:08 -0800453#define CFC_REG_INTERFACES 0x104058
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200454/* [RW 24] {weight_load_client7[2:0] to weight_load_client0[2:0]}. this
455 field allows changing the priorities of the weighted-round-robin arbiter
456 which selects which CFC load client should be served next */
457#define CFC_REG_LCREQ_WEIGHTS 0x104084
Yaniv Rosnerc18487e2008-06-23 20:27:52 -0700458/* [RW 16] Link List ram access; data = {prev_lcid; ext_lcid} */
459#define CFC_REG_LINK_LIST 0x104c00
460#define CFC_REG_LINK_LIST_SIZE 256
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200461/* [R 1] indication the initializing the link list by the hardware was done. */
462#define CFC_REG_LL_INIT_DONE 0x104074
463/* [R 9] Number of allocated LCIDs which are at empty state */
464#define CFC_REG_NUM_LCIDS_ALLOC 0x104020
465/* [R 9] Number of Arriving LCIDs in Link List Block */
466#define CFC_REG_NUM_LCIDS_ARRIVING 0x104004
Vlad Zolotarov619c5cb2011-06-14 14:33:44 +0300467#define CFC_REG_NUM_LCIDS_INSIDE_PF 0x104120
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200468/* [R 9] Number of Leaving LCIDs in Link List Block */
469#define CFC_REG_NUM_LCIDS_LEAVING 0x104018
Dmitry Kravkovf2e08992010-10-06 03:28:26 +0000470#define CFC_REG_WEAK_ENABLE_PF 0x104124
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200471/* [RW 8] The event id for aggregated interrupt 0 */
472#define CSDM_REG_AGG_INT_EVENT_0 0xc2038
Yaniv Rosnerc18487e2008-06-23 20:27:52 -0700473#define CSDM_REG_AGG_INT_EVENT_10 0xc2060
474#define CSDM_REG_AGG_INT_EVENT_11 0xc2064
475#define CSDM_REG_AGG_INT_EVENT_12 0xc2068
476#define CSDM_REG_AGG_INT_EVENT_13 0xc206c
477#define CSDM_REG_AGG_INT_EVENT_14 0xc2070
478#define CSDM_REG_AGG_INT_EVENT_15 0xc2074
479#define CSDM_REG_AGG_INT_EVENT_16 0xc2078
Yaniv Rosnerc18487e2008-06-23 20:27:52 -0700480#define CSDM_REG_AGG_INT_EVENT_2 0xc2040
Yaniv Rosnerc18487e2008-06-23 20:27:52 -0700481#define CSDM_REG_AGG_INT_EVENT_3 0xc2044
Yaniv Rosnerc18487e2008-06-23 20:27:52 -0700482#define CSDM_REG_AGG_INT_EVENT_4 0xc2048
Eilon Greensteinca003922009-08-12 22:53:28 -0700483#define CSDM_REG_AGG_INT_EVENT_5 0xc204c
484#define CSDM_REG_AGG_INT_EVENT_6 0xc2050
485#define CSDM_REG_AGG_INT_EVENT_7 0xc2054
486#define CSDM_REG_AGG_INT_EVENT_8 0xc2058
487#define CSDM_REG_AGG_INT_EVENT_9 0xc205c
488/* [RW 1] For each aggregated interrupt index whether the mode is normal (0)
489 or auto-mask-mode (1) */
490#define CSDM_REG_AGG_INT_MODE_10 0xc21e0
491#define CSDM_REG_AGG_INT_MODE_11 0xc21e4
492#define CSDM_REG_AGG_INT_MODE_12 0xc21e8
493#define CSDM_REG_AGG_INT_MODE_13 0xc21ec
494#define CSDM_REG_AGG_INT_MODE_14 0xc21f0
495#define CSDM_REG_AGG_INT_MODE_15 0xc21f4
496#define CSDM_REG_AGG_INT_MODE_16 0xc21f8
497#define CSDM_REG_AGG_INT_MODE_6 0xc21d0
498#define CSDM_REG_AGG_INT_MODE_7 0xc21d4
499#define CSDM_REG_AGG_INT_MODE_8 0xc21d8
500#define CSDM_REG_AGG_INT_MODE_9 0xc21dc
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200501/* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */
502#define CSDM_REG_CFC_RSP_START_ADDR 0xc2008
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300503/* [RW 16] The maximum value of the completion counter #0 */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200504#define CSDM_REG_CMP_COUNTER_MAX0 0xc201c
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300505/* [RW 16] The maximum value of the completion counter #1 */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200506#define CSDM_REG_CMP_COUNTER_MAX1 0xc2020
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300507/* [RW 16] The maximum value of the completion counter #2 */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200508#define CSDM_REG_CMP_COUNTER_MAX2 0xc2024
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300509/* [RW 16] The maximum value of the completion counter #3 */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200510#define CSDM_REG_CMP_COUNTER_MAX3 0xc2028
511/* [RW 13] The start address in the internal RAM for the completion
512 counters. */
513#define CSDM_REG_CMP_COUNTER_START_ADDR 0xc200c
514/* [RW 32] Interrupt mask register #0 read/write */
515#define CSDM_REG_CSDM_INT_MASK_0 0xc229c
516#define CSDM_REG_CSDM_INT_MASK_1 0xc22ac
Yaniv Rosnerc18487e2008-06-23 20:27:52 -0700517/* [R 32] Interrupt register #0 read */
518#define CSDM_REG_CSDM_INT_STS_0 0xc2290
519#define CSDM_REG_CSDM_INT_STS_1 0xc22a0
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200520/* [RW 11] Parity mask register #0 read/write */
521#define CSDM_REG_CSDM_PRTY_MASK 0xc22bc
Eliezer Tamirf1410642008-02-28 11:51:50 -0800522/* [R 11] Parity register #0 read */
523#define CSDM_REG_CSDM_PRTY_STS 0xc22b0
Vladislav Zolotarov4a33bc02011-01-09 02:20:04 +0000524/* [RC 11] Parity register #0 read clear */
525#define CSDM_REG_CSDM_PRTY_STS_CLR 0xc22b4
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200526#define CSDM_REG_ENABLE_IN1 0xc2238
527#define CSDM_REG_ENABLE_IN2 0xc223c
528#define CSDM_REG_ENABLE_OUT1 0xc2240
529#define CSDM_REG_ENABLE_OUT2 0xc2244
530/* [RW 4] The initial number of messages that can be sent to the pxp control
531 interface without receiving any ACK. */
532#define CSDM_REG_INIT_CREDIT_PXP_CTRL 0xc24bc
533/* [ST 32] The number of ACK after placement messages received */
534#define CSDM_REG_NUM_OF_ACK_AFTER_PLACE 0xc227c
535/* [ST 32] The number of packet end messages received from the parser */
536#define CSDM_REG_NUM_OF_PKT_END_MSG 0xc2274
537/* [ST 32] The number of requests received from the pxp async if */
538#define CSDM_REG_NUM_OF_PXP_ASYNC_REQ 0xc2278
539/* [ST 32] The number of commands received in queue 0 */
540#define CSDM_REG_NUM_OF_Q0_CMD 0xc2248
541/* [ST 32] The number of commands received in queue 10 */
542#define CSDM_REG_NUM_OF_Q10_CMD 0xc226c
543/* [ST 32] The number of commands received in queue 11 */
544#define CSDM_REG_NUM_OF_Q11_CMD 0xc2270
545/* [ST 32] The number of commands received in queue 1 */
546#define CSDM_REG_NUM_OF_Q1_CMD 0xc224c
547/* [ST 32] The number of commands received in queue 3 */
548#define CSDM_REG_NUM_OF_Q3_CMD 0xc2250
549/* [ST 32] The number of commands received in queue 4 */
550#define CSDM_REG_NUM_OF_Q4_CMD 0xc2254
551/* [ST 32] The number of commands received in queue 5 */
552#define CSDM_REG_NUM_OF_Q5_CMD 0xc2258
553/* [ST 32] The number of commands received in queue 6 */
554#define CSDM_REG_NUM_OF_Q6_CMD 0xc225c
555/* [ST 32] The number of commands received in queue 7 */
556#define CSDM_REG_NUM_OF_Q7_CMD 0xc2260
557/* [ST 32] The number of commands received in queue 8 */
558#define CSDM_REG_NUM_OF_Q8_CMD 0xc2264
559/* [ST 32] The number of commands received in queue 9 */
560#define CSDM_REG_NUM_OF_Q9_CMD 0xc2268
561/* [RW 13] The start address in the internal RAM for queue counters */
562#define CSDM_REG_Q_COUNTER_START_ADDR 0xc2010
563/* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */
564#define CSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0xc2548
565/* [R 1] parser fifo empty in sdm_sync block */
566#define CSDM_REG_SYNC_PARSER_EMPTY 0xc2550
567/* [R 1] parser serial fifo empty in sdm_sync block */
568#define CSDM_REG_SYNC_SYNC_EMPTY 0xc2558
569/* [RW 32] Tick for timer counter. Applicable only when
570 ~csdm_registers_timer_tick_enable.timer_tick_enable =1 */
571#define CSDM_REG_TIMER_TICK 0xc2000
572/* [RW 5] The number of time_slots in the arbitration cycle */
573#define CSEM_REG_ARB_CYCLE_SIZE 0x200034
574/* [RW 3] The source that is associated with arbitration element 0. Source
575 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
576 sleeping thread with priority 1; 4- sleeping thread with priority 2 */
577#define CSEM_REG_ARB_ELEMENT0 0x200020
578/* [RW 3] The source that is associated with arbitration element 1. Source
579 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
580 sleeping thread with priority 1; 4- sleeping thread with priority 2.
581 Could not be equal to register ~csem_registers_arb_element0.arb_element0 */
582#define CSEM_REG_ARB_ELEMENT1 0x200024
583/* [RW 3] The source that is associated with arbitration element 2. Source
584 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
585 sleeping thread with priority 1; 4- sleeping thread with priority 2.
586 Could not be equal to register ~csem_registers_arb_element0.arb_element0
587 and ~csem_registers_arb_element1.arb_element1 */
588#define CSEM_REG_ARB_ELEMENT2 0x200028
589/* [RW 3] The source that is associated with arbitration element 3. Source
590 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
591 sleeping thread with priority 1; 4- sleeping thread with priority 2.Could
592 not be equal to register ~csem_registers_arb_element0.arb_element0 and
593 ~csem_registers_arb_element1.arb_element1 and
594 ~csem_registers_arb_element2.arb_element2 */
595#define CSEM_REG_ARB_ELEMENT3 0x20002c
596/* [RW 3] The source that is associated with arbitration element 4. Source
597 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
598 sleeping thread with priority 1; 4- sleeping thread with priority 2.
599 Could not be equal to register ~csem_registers_arb_element0.arb_element0
600 and ~csem_registers_arb_element1.arb_element1 and
601 ~csem_registers_arb_element2.arb_element2 and
602 ~csem_registers_arb_element3.arb_element3 */
603#define CSEM_REG_ARB_ELEMENT4 0x200030
604/* [RW 32] Interrupt mask register #0 read/write */
605#define CSEM_REG_CSEM_INT_MASK_0 0x200110
606#define CSEM_REG_CSEM_INT_MASK_1 0x200120
Yaniv Rosnerc18487e2008-06-23 20:27:52 -0700607/* [R 32] Interrupt register #0 read */
608#define CSEM_REG_CSEM_INT_STS_0 0x200104
609#define CSEM_REG_CSEM_INT_STS_1 0x200114
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200610/* [RW 32] Parity mask register #0 read/write */
611#define CSEM_REG_CSEM_PRTY_MASK_0 0x200130
612#define CSEM_REG_CSEM_PRTY_MASK_1 0x200140
Eliezer Tamirf1410642008-02-28 11:51:50 -0800613/* [R 32] Parity register #0 read */
614#define CSEM_REG_CSEM_PRTY_STS_0 0x200124
615#define CSEM_REG_CSEM_PRTY_STS_1 0x200134
Vladislav Zolotarov4a33bc02011-01-09 02:20:04 +0000616/* [RC 32] Parity register #0 read clear */
617#define CSEM_REG_CSEM_PRTY_STS_CLR_0 0x200128
618#define CSEM_REG_CSEM_PRTY_STS_CLR_1 0x200138
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200619#define CSEM_REG_ENABLE_IN 0x2000a4
620#define CSEM_REG_ENABLE_OUT 0x2000a8
621/* [RW 32] This address space contains all registers and memories that are
622 placed in SEM_FAST block. The SEM_FAST registers are described in
Yaniv Rosnerc18487e2008-06-23 20:27:52 -0700623 appendix B. In order to access the sem_fast registers the base address
624 ~fast_memory.fast_memory should be added to eachsem_fast register offset. */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200625#define CSEM_REG_FAST_MEMORY 0x220000
626/* [RW 1] Disables input messages from FIC0 May be updated during run_time
627 by the microcode */
628#define CSEM_REG_FIC0_DISABLE 0x200224
629/* [RW 1] Disables input messages from FIC1 May be updated during run_time
630 by the microcode */
631#define CSEM_REG_FIC1_DISABLE 0x200234
632/* [RW 15] Interrupt table Read and write access to it is not possible in
633 the middle of the work */
634#define CSEM_REG_INT_TABLE 0x200400
635/* [ST 24] Statistics register. The number of messages that entered through
636 FIC0 */
637#define CSEM_REG_MSG_NUM_FIC0 0x200000
638/* [ST 24] Statistics register. The number of messages that entered through
639 FIC1 */
640#define CSEM_REG_MSG_NUM_FIC1 0x200004
641/* [ST 24] Statistics register. The number of messages that were sent to
642 FOC0 */
643#define CSEM_REG_MSG_NUM_FOC0 0x200008
644/* [ST 24] Statistics register. The number of messages that were sent to
645 FOC1 */
646#define CSEM_REG_MSG_NUM_FOC1 0x20000c
647/* [ST 24] Statistics register. The number of messages that were sent to
648 FOC2 */
649#define CSEM_REG_MSG_NUM_FOC2 0x200010
650/* [ST 24] Statistics register. The number of messages that were sent to
651 FOC3 */
652#define CSEM_REG_MSG_NUM_FOC3 0x200014
653/* [RW 1] Disables input messages from the passive buffer May be updated
654 during run_time by the microcode */
655#define CSEM_REG_PAS_DISABLE 0x20024c
656/* [WB 128] Debug only. Passive buffer memory */
657#define CSEM_REG_PASSIVE_BUFFER 0x202000
658/* [WB 46] pram memory. B45 is parity; b[44:0] - data. */
659#define CSEM_REG_PRAM 0x240000
660/* [R 16] Valid sleeping threads indication have bit per thread */
661#define CSEM_REG_SLEEP_THREADS_VALID 0x20026c
662/* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */
663#define CSEM_REG_SLOW_EXT_STORE_EMPTY 0x2002a0
664/* [RW 16] List of free threads . There is a bit per thread. */
665#define CSEM_REG_THREADS_LIST 0x2002e4
666/* [RW 3] The arbitration scheme of time_slot 0 */
667#define CSEM_REG_TS_0_AS 0x200038
668/* [RW 3] The arbitration scheme of time_slot 10 */
669#define CSEM_REG_TS_10_AS 0x200060
670/* [RW 3] The arbitration scheme of time_slot 11 */
671#define CSEM_REG_TS_11_AS 0x200064
672/* [RW 3] The arbitration scheme of time_slot 12 */
673#define CSEM_REG_TS_12_AS 0x200068
674/* [RW 3] The arbitration scheme of time_slot 13 */
675#define CSEM_REG_TS_13_AS 0x20006c
676/* [RW 3] The arbitration scheme of time_slot 14 */
677#define CSEM_REG_TS_14_AS 0x200070
678/* [RW 3] The arbitration scheme of time_slot 15 */
679#define CSEM_REG_TS_15_AS 0x200074
680/* [RW 3] The arbitration scheme of time_slot 16 */
681#define CSEM_REG_TS_16_AS 0x200078
682/* [RW 3] The arbitration scheme of time_slot 17 */
683#define CSEM_REG_TS_17_AS 0x20007c
684/* [RW 3] The arbitration scheme of time_slot 18 */
685#define CSEM_REG_TS_18_AS 0x200080
686/* [RW 3] The arbitration scheme of time_slot 1 */
687#define CSEM_REG_TS_1_AS 0x20003c
688/* [RW 3] The arbitration scheme of time_slot 2 */
689#define CSEM_REG_TS_2_AS 0x200040
690/* [RW 3] The arbitration scheme of time_slot 3 */
691#define CSEM_REG_TS_3_AS 0x200044
692/* [RW 3] The arbitration scheme of time_slot 4 */
693#define CSEM_REG_TS_4_AS 0x200048
694/* [RW 3] The arbitration scheme of time_slot 5 */
695#define CSEM_REG_TS_5_AS 0x20004c
696/* [RW 3] The arbitration scheme of time_slot 6 */
697#define CSEM_REG_TS_6_AS 0x200050
698/* [RW 3] The arbitration scheme of time_slot 7 */
699#define CSEM_REG_TS_7_AS 0x200054
700/* [RW 3] The arbitration scheme of time_slot 8 */
701#define CSEM_REG_TS_8_AS 0x200058
702/* [RW 3] The arbitration scheme of time_slot 9 */
703#define CSEM_REG_TS_9_AS 0x20005c
Dmitry Kravkovf2e08992010-10-06 03:28:26 +0000704/* [W 7] VF or PF ID for reset error bit. Values 0-63 reset error bit for 64
705 * VF; values 64-67 reset error for 4 PF; values 68-127 are not valid. */
706#define CSEM_REG_VFPF_ERR_NUM 0x200380
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200707/* [RW 1] Parity mask register #0 read/write */
708#define DBG_REG_DBG_PRTY_MASK 0xc0a8
Eliezer Tamirf1410642008-02-28 11:51:50 -0800709/* [R 1] Parity register #0 read */
710#define DBG_REG_DBG_PRTY_STS 0xc09c
Vladislav Zolotarov4a33bc02011-01-09 02:20:04 +0000711/* [RC 1] Parity register #0 read clear */
712#define DBG_REG_DBG_PRTY_STS_CLR 0xc0a0
Dmitry Kravkovf2e08992010-10-06 03:28:26 +0000713/* [RW 1] When set the DMAE will process the commands as in E1.5. 1.The
714 * function that is used is always SRC-PCI; 2.VF_Valid = 0; 3.VFID=0;
715 * 4.Completion function=0; 5.Error handling=0 */
716#define DMAE_REG_BACKWARD_COMP_EN 0x10207c
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200717/* [RW 32] Commands memory. The address to command X; row Y is to calculated
718 as 14*X+Y. */
719#define DMAE_REG_CMD_MEM 0x102400
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700720#define DMAE_REG_CMD_MEM_SIZE 224
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200721/* [RW 1] If 0 - the CRC-16c initial value is all zeroes; if 1 - the CRC-16c
722 initial value is all ones. */
723#define DMAE_REG_CRC16C_INIT 0x10201c
724/* [RW 1] If 0 - the CRC-16 T10 initial value is all zeroes; if 1 - the
725 CRC-16 T10 initial value is all ones. */
726#define DMAE_REG_CRC16T10_INIT 0x102020
727/* [RW 2] Interrupt mask register #0 read/write */
728#define DMAE_REG_DMAE_INT_MASK 0x102054
729/* [RW 4] Parity mask register #0 read/write */
730#define DMAE_REG_DMAE_PRTY_MASK 0x102064
Eliezer Tamirf1410642008-02-28 11:51:50 -0800731/* [R 4] Parity register #0 read */
732#define DMAE_REG_DMAE_PRTY_STS 0x102058
Vladislav Zolotarov4a33bc02011-01-09 02:20:04 +0000733/* [RC 4] Parity register #0 read clear */
734#define DMAE_REG_DMAE_PRTY_STS_CLR 0x10205c
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200735/* [RW 1] Command 0 go. */
736#define DMAE_REG_GO_C0 0x102080
737/* [RW 1] Command 1 go. */
738#define DMAE_REG_GO_C1 0x102084
739/* [RW 1] Command 10 go. */
740#define DMAE_REG_GO_C10 0x102088
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200741/* [RW 1] Command 11 go. */
742#define DMAE_REG_GO_C11 0x10208c
743/* [RW 1] Command 12 go. */
744#define DMAE_REG_GO_C12 0x102090
745/* [RW 1] Command 13 go. */
746#define DMAE_REG_GO_C13 0x102094
747/* [RW 1] Command 14 go. */
748#define DMAE_REG_GO_C14 0x102098
749/* [RW 1] Command 15 go. */
750#define DMAE_REG_GO_C15 0x10209c
751/* [RW 1] Command 2 go. */
752#define DMAE_REG_GO_C2 0x1020a0
753/* [RW 1] Command 3 go. */
754#define DMAE_REG_GO_C3 0x1020a4
755/* [RW 1] Command 4 go. */
756#define DMAE_REG_GO_C4 0x1020a8
757/* [RW 1] Command 5 go. */
758#define DMAE_REG_GO_C5 0x1020ac
759/* [RW 1] Command 6 go. */
760#define DMAE_REG_GO_C6 0x1020b0
761/* [RW 1] Command 7 go. */
762#define DMAE_REG_GO_C7 0x1020b4
763/* [RW 1] Command 8 go. */
764#define DMAE_REG_GO_C8 0x1020b8
765/* [RW 1] Command 9 go. */
766#define DMAE_REG_GO_C9 0x1020bc
767/* [RW 1] DMAE GRC Interface (Target; aster) enable. If 0 - the acknowledge
768 input is disregarded; valid is deasserted; all other signals are treated
769 as usual; if 1 - normal activity. */
770#define DMAE_REG_GRC_IFEN 0x102008
771/* [RW 1] DMAE PCI Interface (Request; ead; rite) enable. If 0 - the
772 acknowledge input is disregarded; valid is deasserted; full is asserted;
773 all other signals are treated as usual; if 1 - normal activity. */
774#define DMAE_REG_PCI_IFEN 0x102004
775/* [RW 4] DMAE- PCI Request Interface initial credit. Write writes the
776 initial value to the credit counter; related to the address. Read returns
777 the current value of the counter. */
778#define DMAE_REG_PXP_REQ_INIT_CRD 0x1020c0
779/* [RW 8] Aggregation command. */
780#define DORQ_REG_AGG_CMD0 0x170060
781/* [RW 8] Aggregation command. */
782#define DORQ_REG_AGG_CMD1 0x170064
783/* [RW 8] Aggregation command. */
784#define DORQ_REG_AGG_CMD2 0x170068
785/* [RW 8] Aggregation command. */
786#define DORQ_REG_AGG_CMD3 0x17006c
787/* [RW 28] UCM Header. */
788#define DORQ_REG_CMHEAD_RX 0x170050
Yaniv Rosnerc18487e2008-06-23 20:27:52 -0700789/* [RW 32] Doorbell address for RBC doorbells (function 0). */
790#define DORQ_REG_DB_ADDR0 0x17008c
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200791/* [RW 5] Interrupt mask register #0 read/write */
792#define DORQ_REG_DORQ_INT_MASK 0x170180
793/* [R 5] Interrupt register #0 read */
794#define DORQ_REG_DORQ_INT_STS 0x170174
795/* [RC 5] Interrupt register #0 read clear */
796#define DORQ_REG_DORQ_INT_STS_CLR 0x170178
797/* [RW 2] Parity mask register #0 read/write */
798#define DORQ_REG_DORQ_PRTY_MASK 0x170190
Eliezer Tamirf1410642008-02-28 11:51:50 -0800799/* [R 2] Parity register #0 read */
800#define DORQ_REG_DORQ_PRTY_STS 0x170184
Vladislav Zolotarov4a33bc02011-01-09 02:20:04 +0000801/* [RC 2] Parity register #0 read clear */
802#define DORQ_REG_DORQ_PRTY_STS_CLR 0x170188
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200803/* [RW 8] The address to write the DPM CID to STORM. */
804#define DORQ_REG_DPM_CID_ADDR 0x170044
805/* [RW 5] The DPM mode CID extraction offset. */
806#define DORQ_REG_DPM_CID_OFST 0x170030
807/* [RW 12] The threshold of the DQ FIFO to send the almost full interrupt. */
808#define DORQ_REG_DQ_FIFO_AFULL_TH 0x17007c
809/* [RW 12] The threshold of the DQ FIFO to send the full interrupt. */
810#define DORQ_REG_DQ_FIFO_FULL_TH 0x170078
811/* [R 13] Current value of the DQ FIFO fill level according to following
812 pointer. The range is 0 - 256 FIFO rows; where each row stands for the
813 doorbell. */
814#define DORQ_REG_DQ_FILL_LVLF 0x1700a4
815/* [R 1] DQ FIFO full status. Is set; when FIFO filling level is more or
816 equal to full threshold; reset on full clear. */
817#define DORQ_REG_DQ_FULL_ST 0x1700c0
818/* [RW 28] The value sent to CM header in the case of CFC load error. */
819#define DORQ_REG_ERR_CMHEAD 0x170058
820#define DORQ_REG_IF_EN 0x170004
821#define DORQ_REG_MODE_ACT 0x170008
822/* [RW 5] The normal mode CID extraction offset. */
823#define DORQ_REG_NORM_CID_OFST 0x17002c
824/* [RW 28] TCM Header when only TCP context is loaded. */
825#define DORQ_REG_NORM_CMHEAD_TX 0x17004c
826/* [RW 3] The number of simultaneous outstanding requests to Context Fetch
827 Interface. */
828#define DORQ_REG_OUTST_REQ 0x17003c
Vlad Zolotarov619c5cb2011-06-14 14:33:44 +0300829#define DORQ_REG_PF_USAGE_CNT 0x1701d0
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200830#define DORQ_REG_REGN 0x170038
831/* [R 4] Current value of response A counter credit. Initial credit is
832 configured through write to ~dorq_registers_rsp_init_crd.rsp_init_crd
833 register. */
834#define DORQ_REG_RSPA_CRD_CNT 0x1700ac
835/* [R 4] Current value of response B counter credit. Initial credit is
836 configured through write to ~dorq_registers_rsp_init_crd.rsp_init_crd
837 register. */
838#define DORQ_REG_RSPB_CRD_CNT 0x1700b0
839/* [RW 4] The initial credit at the Doorbell Response Interface. The write
840 writes the same initial credit to the rspa_crd_cnt and rspb_crd_cnt. The
841 read reads this written value. */
842#define DORQ_REG_RSP_INIT_CRD 0x170048
843/* [RW 4] Initial activity counter value on the load request; when the
844 shortcut is done. */
845#define DORQ_REG_SHRT_ACT_CNT 0x170070
846/* [RW 28] TCM Header when both ULP and TCP context is loaded. */
847#define DORQ_REG_SHRT_CMHEAD 0x170054
848#define HC_CONFIG_0_REG_ATTN_BIT_EN_0 (0x1<<4)
Vladislav Zolotarovc9ee9202011-06-14 01:33:51 +0000849#define HC_CONFIG_0_REG_BLOCK_DISABLE_0 (0x1<<0)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200850#define HC_CONFIG_0_REG_INT_LINE_EN_0 (0x1<<3)
Eilon Greenstein8badd272009-02-12 08:36:15 +0000851#define HC_CONFIG_0_REG_MSI_ATTN_EN_0 (0x1<<7)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200852#define HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 (0x1<<2)
Vladislav Zolotarovc9ee9202011-06-14 01:33:51 +0000853#define HC_CONFIG_0_REG_SINGLE_ISR_EN_0 (0x1<<1)
854#define HC_CONFIG_1_REG_BLOCK_DISABLE_1 (0x1<<0)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200855#define HC_REG_AGG_INT_0 0x108050
856#define HC_REG_AGG_INT_1 0x108054
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200857#define HC_REG_ATTN_BIT 0x108120
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200858#define HC_REG_ATTN_IDX 0x108100
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200859#define HC_REG_ATTN_MSG0_ADDR_L 0x108018
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200860#define HC_REG_ATTN_MSG1_ADDR_L 0x108020
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200861#define HC_REG_ATTN_NUM_P0 0x108038
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200862#define HC_REG_ATTN_NUM_P1 0x10803c
Eilon Greenstein5c862842008-08-13 15:51:48 -0700863#define HC_REG_COMMAND_REG 0x108180
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200864#define HC_REG_CONFIG_0 0x108000
865#define HC_REG_CONFIG_1 0x108004
Yaniv Rosnerc18487e2008-06-23 20:27:52 -0700866#define HC_REG_FUNC_NUM_P0 0x1080ac
867#define HC_REG_FUNC_NUM_P1 0x1080b0
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200868/* [RW 3] Parity mask register #0 read/write */
869#define HC_REG_HC_PRTY_MASK 0x1080a0
Eliezer Tamirf1410642008-02-28 11:51:50 -0800870/* [R 3] Parity register #0 read */
871#define HC_REG_HC_PRTY_STS 0x108094
Vladislav Zolotarovf4a66892010-10-19 05:13:09 +0000872/* [RC 3] Parity register #0 read clear */
873#define HC_REG_HC_PRTY_STS_CLR 0x108098
874#define HC_REG_INT_MASK 0x108108
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200875#define HC_REG_LEADING_EDGE_0 0x108040
876#define HC_REG_LEADING_EDGE_1 0x108048
Vladislav Zolotarovf4a66892010-10-19 05:13:09 +0000877#define HC_REG_MAIN_MEMORY 0x108800
878#define HC_REG_MAIN_MEMORY_SIZE 152
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200879#define HC_REG_P0_PROD_CONS 0x108200
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200880#define HC_REG_P1_PROD_CONS 0x108400
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200881#define HC_REG_PBA_COMMAND 0x108140
882#define HC_REG_PCI_CONFIG_0 0x108010
883#define HC_REG_PCI_CONFIG_1 0x108014
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200884#define HC_REG_STATISTIC_COUNTERS 0x109000
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200885#define HC_REG_TRAILING_EDGE_0 0x108044
886#define HC_REG_TRAILING_EDGE_1 0x10804c
887#define HC_REG_UC_RAM_ADDR_0 0x108028
888#define HC_REG_UC_RAM_ADDR_1 0x108030
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200889#define HC_REG_USTORM_ADDR_FOR_COALESCE 0x108068
890#define HC_REG_VQID_0 0x108008
891#define HC_REG_VQID_1 0x10800c
Dmitry Kravkovf2e08992010-10-06 03:28:26 +0000892#define IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN (0x1<<1)
Vladislav Zolotarovc9ee9202011-06-14 01:33:51 +0000893#define IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE (0x1<<0)
Dmitry Kravkovf2e08992010-10-06 03:28:26 +0000894#define IGU_REG_ATTENTION_ACK_BITS 0x130108
895/* [R 4] Debug: attn_fsm */
896#define IGU_REG_ATTN_FSM 0x130054
897#define IGU_REG_ATTN_MSG_ADDR_H 0x13011c
898#define IGU_REG_ATTN_MSG_ADDR_L 0x130120
899/* [R 4] Debug: [3] - attention write done message is pending (0-no pending;
900 * 1-pending). [2:0] = PFID. Pending means attention message was sent; but
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300901 * write done didn't receive. */
Dmitry Kravkovf2e08992010-10-06 03:28:26 +0000902#define IGU_REG_ATTN_WRITE_DONE_PENDING 0x130030
903#define IGU_REG_BLOCK_CONFIGURATION 0x130000
904#define IGU_REG_COMMAND_REG_32LSB_DATA 0x130124
905#define IGU_REG_COMMAND_REG_CTRL 0x13012c
906/* [WB_R 32] Cleanup bit status per SB. 1 = cleanup is set. 0 = cleanup bit
907 * is clear. The bits in this registers are set and clear via the producer
908 * command. Data valid only in addresses 0-4. all the rest are zero. */
909#define IGU_REG_CSTORM_TYPE_0_SB_CLEANUP 0x130200
910/* [R 5] Debug: ctrl_fsm */
911#define IGU_REG_CTRL_FSM 0x130064
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300912/* [R 1] data available for error memory. If this bit is clear do not red
Dmitry Kravkovf2e08992010-10-06 03:28:26 +0000913 * from error_handling_memory. */
914#define IGU_REG_ERROR_HANDLING_DATA_VALID 0x130130
Vladislav Zolotarov4a33bc02011-01-09 02:20:04 +0000915/* [RW 11] Parity mask register #0 read/write */
916#define IGU_REG_IGU_PRTY_MASK 0x1300a8
Dmitry Kravkovf2e08992010-10-06 03:28:26 +0000917/* [R 11] Parity register #0 read */
918#define IGU_REG_IGU_PRTY_STS 0x13009c
Vladislav Zolotarov4a33bc02011-01-09 02:20:04 +0000919/* [RC 11] Parity register #0 read clear */
920#define IGU_REG_IGU_PRTY_STS_CLR 0x1300a0
Dmitry Kravkovf2e08992010-10-06 03:28:26 +0000921/* [R 4] Debug: int_handle_fsm */
922#define IGU_REG_INT_HANDLE_FSM 0x130050
923#define IGU_REG_LEADING_EDGE_LATCH 0x130134
924/* [RW 14] mapping CAM; relevant for E2 operating mode only. [0] - valid.
925 * [6:1] - vector number; [13:7] - FID (if VF - [13] = 0; [12:7] = VF
926 * number; if PF - [13] = 1; [12:10] = 0; [9:7] = PF number); */
927#define IGU_REG_MAPPING_MEMORY 0x131000
928#define IGU_REG_MAPPING_MEMORY_SIZE 136
929#define IGU_REG_PBA_STATUS_LSB 0x130138
930#define IGU_REG_PBA_STATUS_MSB 0x13013c
931#define IGU_REG_PCI_PF_MSI_EN 0x130140
932#define IGU_REG_PCI_PF_MSIX_EN 0x130144
933#define IGU_REG_PCI_PF_MSIX_FUNC_MASK 0x130148
934/* [WB_R 32] Each bit represent the pending bits status for that SB. 0 = no
935 * pending; 1 = pending. Pendings means interrupt was asserted; and write
936 * done was not received. Data valid only in addresses 0-4. all the rest are
937 * zero. */
938#define IGU_REG_PENDING_BITS_STATUS 0x130300
939#define IGU_REG_PF_CONFIGURATION 0x130154
940/* [RW 20] producers only. E2 mode: address 0-135 match to the mapping
941 * memory; 136 - PF0 default prod; 137 PF1 default prod; 138 - PF2 default
942 * prod; 139 PF3 default prod; 140 - PF0 - ATTN prod; 141 - PF1 - ATTN prod;
943 * 142 - PF2 - ATTN prod; 143 - PF3 - ATTN prod; 144-147 reserved. E1.5 mode
944 * - In backward compatible mode; for non default SB; each even line in the
945 * memory holds the U producer and each odd line hold the C producer. The
946 * first 128 producer are for NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The
947 * last 20 producers are for the DSB for each PF. each PF has five segments
948 * (the order inside each segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
949 * 132-135 C prods; 136-139 X prods; 140-143 T prods; 144-147 ATTN prods; */
950#define IGU_REG_PROD_CONS_MEMORY 0x132000
951/* [R 3] Debug: pxp_arb_fsm */
952#define IGU_REG_PXP_ARB_FSM 0x130068
953/* [RW 6] Write one for each bit will reset the appropriate memory. When the
954 * memory reset finished the appropriate bit will be clear. Bit 0 - mapping
955 * memory; Bit 1 - SB memory; Bit 2 - SB interrupt and mask register; Bit 3
956 * - MSIX memory; Bit 4 - PBA memory; Bit 5 - statistics; */
957#define IGU_REG_RESET_MEMORIES 0x130158
958/* [R 4] Debug: sb_ctrl_fsm */
959#define IGU_REG_SB_CTRL_FSM 0x13004c
960#define IGU_REG_SB_INT_BEFORE_MASK_LSB 0x13015c
961#define IGU_REG_SB_INT_BEFORE_MASK_MSB 0x130160
962#define IGU_REG_SB_MASK_LSB 0x130164
963#define IGU_REG_SB_MASK_MSB 0x130168
964/* [RW 16] Number of command that were dropped without causing an interrupt
965 * due to: read access for WO BAR address; or write access for RO BAR
966 * address or any access for reserved address or PCI function error is set
967 * and address is not MSIX; PBA or cleanup */
968#define IGU_REG_SILENT_DROP 0x13016c
969/* [RW 10] Number of MSI/MSIX/ATTN messages sent for the function: 0-63 -
970 * number of MSIX messages per VF; 64-67 - number of MSI/MSIX messages per
971 * PF; 68-71 number of ATTN messages per PF */
972#define IGU_REG_STATISTIC_NUM_MESSAGE_SENT 0x130800
973/* [RW 32] Number of cycles the timer mask masking the IGU interrupt when a
974 * timer mask command arrives. Value must be bigger than 100. */
975#define IGU_REG_TIMER_MASKING_VALUE 0x13003c
976#define IGU_REG_TRAILING_EDGE_LATCH 0x130104
977#define IGU_REG_VF_CONFIGURATION 0x130170
978/* [WB_R 32] Each bit represent write done pending bits status for that SB
979 * (MSI/MSIX message was sent and write done was not received yet). 0 =
980 * clear; 1 = set. Data valid only in addresses 0-4. all the rest are zero. */
981#define IGU_REG_WRITE_DONE_PENDING 0x130480
982#define MCP_A_REG_MCPR_SCRATCH 0x3a0000
Dmitry Kravkov7a25cc72011-06-14 01:33:25 +0000983#define MCP_REG_MCPR_CPU_PROGRAM_COUNTER 0x8501c
Yaniv Rosner3c9ada22011-06-14 01:34:12 +0000984#define MCP_REG_MCPR_GP_INPUTS 0x800c0
985#define MCP_REG_MCPR_GP_OENABLE 0x800c8
986#define MCP_REG_MCPR_GP_OUTPUTS 0x800c4
987#define MCP_REG_MCPR_IMC_COMMAND 0x85900
988#define MCP_REG_MCPR_IMC_DATAREG0 0x85920
989#define MCP_REG_MCPR_IMC_SLAVE_CONTROL 0x85904
990#define MCP_REG_MCPR_CPU_PROGRAM_COUNTER 0x8501c
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200991#define MCP_REG_MCPR_NVM_ACCESS_ENABLE 0x86424
992#define MCP_REG_MCPR_NVM_ADDR 0x8640c
993#define MCP_REG_MCPR_NVM_CFG4 0x8642c
994#define MCP_REG_MCPR_NVM_COMMAND 0x86400
995#define MCP_REG_MCPR_NVM_READ 0x86410
996#define MCP_REG_MCPR_NVM_SW_ARB 0x86420
997#define MCP_REG_MCPR_NVM_WRITE 0x86408
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200998#define MCP_REG_MCPR_SCRATCH 0xa0000
Vladislav Zolotarov72fd0712010-04-19 01:13:12 +0000999#define MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK (0x1<<1)
1000#define MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK (0x1<<0)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001001/* [R 32] read first 32 bit after inversion of function 0. mapped as
1002 follows: [0] NIG attention for function0; [1] NIG attention for
1003 function1; [2] GPIO1 mcp; [3] GPIO2 mcp; [4] GPIO3 mcp; [5] GPIO4 mcp;
1004 [6] GPIO1 function 1; [7] GPIO2 function 1; [8] GPIO3 function 1; [9]
1005 GPIO4 function 1; [10] PCIE glue/PXP VPD event function0; [11] PCIE
1006 glue/PXP VPD event function1; [12] PCIE glue/PXP Expansion ROM event0;
1007 [13] PCIE glue/PXP Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16]
1008 MSI/X indication for mcp; [17] MSI/X indication for function 1; [18] BRB
1009 Parity error; [19] BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw
1010 interrupt; [22] SRC Parity error; [23] SRC Hw interrupt; [24] TSDM Parity
1011 error; [25] TSDM Hw interrupt; [26] TCM Parity error; [27] TCM Hw
1012 interrupt; [28] TSEMI Parity error; [29] TSEMI Hw interrupt; [30] PBF
1013 Parity error; [31] PBF Hw interrupt; */
1014#define MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 0xa42c
1015#define MISC_REG_AEU_AFTER_INVERT_1_FUNC_1 0xa430
1016/* [R 32] read first 32 bit after inversion of mcp. mapped as follows: [0]
1017 NIG attention for function0; [1] NIG attention for function1; [2] GPIO1
1018 mcp; [3] GPIO2 mcp; [4] GPIO3 mcp; [5] GPIO4 mcp; [6] GPIO1 function 1;
1019 [7] GPIO2 function 1; [8] GPIO3 function 1; [9] GPIO4 function 1; [10]
1020 PCIE glue/PXP VPD event function0; [11] PCIE glue/PXP VPD event
1021 function1; [12] PCIE glue/PXP Expansion ROM event0; [13] PCIE glue/PXP
1022 Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16] MSI/X indication for
1023 mcp; [17] MSI/X indication for function 1; [18] BRB Parity error; [19]
1024 BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC
1025 Parity error; [23] SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw
1026 interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI
1027 Parity error; [29] TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw
1028 interrupt; */
1029#define MISC_REG_AEU_AFTER_INVERT_1_MCP 0xa434
1030/* [R 32] read second 32 bit after inversion of function 0. mapped as
1031 follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM
1032 Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw
1033 interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity
1034 error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw
1035 interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14]
1036 NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error;
1037 [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw
1038 interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM
1039 Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI
1040 Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM
1041 Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw
1042 interrupt; */
1043#define MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 0xa438
1044#define MISC_REG_AEU_AFTER_INVERT_2_FUNC_1 0xa43c
1045/* [R 32] read second 32 bit after inversion of mcp. mapped as follows: [0]
1046 PBClient Parity error; [1] PBClient Hw interrupt; [2] QM Parity error;
1047 [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw interrupt;
1048 [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity error; [9]
1049 XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw interrupt; [12]
1050 DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] NIG Parity
1051 error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; [17] Vaux
1052 PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw interrupt;
1053 [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM Parity error;
1054 [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI Hw interrupt;
1055 [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM Parity error;
1056 [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw interrupt; */
1057#define MISC_REG_AEU_AFTER_INVERT_2_MCP 0xa440
1058/* [R 32] read third 32 bit after inversion of function 0. mapped as
1059 follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP Parity
1060 error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error; [5]
1061 PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw
1062 interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity
1063 error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC)
1064 Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16]
1065 pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20]
1066 MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23]
1067 SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW
1068 timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3
1069 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General
1070 attn1; */
1071#define MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 0xa444
1072#define MISC_REG_AEU_AFTER_INVERT_3_FUNC_1 0xa448
1073/* [R 32] read third 32 bit after inversion of mcp. mapped as follows: [0]
1074 CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP Parity error; [3] PXP
1075 Hw interrupt; [4] PXPpciClockClient Parity error; [5] PXPpciClockClient
1076 Hw interrupt; [6] CFC Parity error; [7] CFC Hw interrupt; [8] CDU Parity
1077 error; [9] CDU Hw interrupt; [10] DMAE Parity error; [11] DMAE Hw
1078 interrupt; [12] IGU (HC) Parity error; [13] IGU (HC) Hw interrupt; [14]
1079 MISC Parity error; [15] MISC Hw interrupt; [16] pxp_misc_mps_attn; [17]
1080 Flash event; [18] SMB event; [19] MCP attn0; [20] MCP attn1; [21] SW
1081 timers attn_1 func0; [22] SW timers attn_2 func0; [23] SW timers attn_3
1082 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW timers attn_1
1083 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3 func1; [29] SW
1084 timers attn_4 func1; [30] General attn0; [31] General attn1; */
1085#define MISC_REG_AEU_AFTER_INVERT_3_MCP 0xa44c
1086/* [R 32] read fourth 32 bit after inversion of function 0. mapped as
1087 follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
1088 General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
1089 [7] General attn9; [8] General attn10; [9] General attn11; [10] General
1090 attn12; [11] General attn13; [12] General attn14; [13] General attn15;
1091 [14] General attn16; [15] General attn17; [16] General attn18; [17]
1092 General attn19; [18] General attn20; [19] General attn21; [20] Main power
1093 interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
1094 Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
1095 Latched timeout attention; [27] GRC Latched reserved access attention;
1096 [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
1097 Latched ump_tx_parity; [31] MCP Latched scpad_parity; */
1098#define MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 0xa450
1099#define MISC_REG_AEU_AFTER_INVERT_4_FUNC_1 0xa454
1100/* [R 32] read fourth 32 bit after inversion of mcp. mapped as follows: [0]
1101 General attn2; [1] General attn3; [2] General attn4; [3] General attn5;
1102 [4] General attn6; [5] General attn7; [6] General attn8; [7] General
1103 attn9; [8] General attn10; [9] General attn11; [10] General attn12; [11]
1104 General attn13; [12] General attn14; [13] General attn15; [14] General
1105 attn16; [15] General attn17; [16] General attn18; [17] General attn19;
1106 [18] General attn20; [19] General attn21; [20] Main power interrupt; [21]
1107 RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN Latched attn; [24]
1108 RBCU Latched attn; [25] RBCP Latched attn; [26] GRC Latched timeout
1109 attention; [27] GRC Latched reserved access attention; [28] MCP Latched
1110 rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP Latched
1111 ump_tx_parity; [31] MCP Latched scpad_parity; */
1112#define MISC_REG_AEU_AFTER_INVERT_4_MCP 0xa458
Dmitry Kravkovf2e08992010-10-06 03:28:26 +00001113/* [R 32] Read fifth 32 bit after inversion of function 0. Mapped as
1114 * follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC
1115 * attention [3] PGLUE B RBC parity; [4] ATC attention; [5] ATC parity; [6]
1116 * CNIG attention (reserved); [7] CNIG parity (reserved); [31-8] Reserved; */
1117#define MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 0xa700
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07001118/* [W 14] write to this register results with the clear of the latched
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001119 signals; one in d0 clears RBCR latch; one in d1 clears RBCT latch; one in
1120 d2 clears RBCN latch; one in d3 clears RBCU latch; one in d4 clears RBCP
1121 latch; one in d5 clears GRC Latched timeout attention; one in d6 clears
1122 GRC Latched reserved access attention; one in d7 clears Latched
1123 rom_parity; one in d8 clears Latched ump_rx_parity; one in d9 clears
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07001124 Latched ump_tx_parity; one in d10 clears Latched scpad_parity (both
1125 ports); one in d11 clears pxpv_misc_mps_attn; one in d12 clears
1126 pxp_misc_exp_rom_attn0; one in d13 clears pxp_misc_exp_rom_attn1; read
1127 from this register return zero */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001128#define MISC_REG_AEU_CLR_LATCH_SIGNAL 0xa45c
1129/* [RW 32] first 32b for enabling the output for function 0 output0. mapped
1130 as follows: [0] NIG attention for function0; [1] NIG attention for
1131 function1; [2] GPIO1 function 0; [3] GPIO2 function 0; [4] GPIO3 function
1132 0; [5] GPIO4 function 0; [6] GPIO1 function 1; [7] GPIO2 function 1; [8]
1133 GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event
1134 function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP
1135 Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]
1136 SPIO4; [15] SPIO5; [16] MSI/X indication for function 0; [17] MSI/X
1137 indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt;
1138 [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23]
1139 SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26]
1140 TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29]
1141 TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */
1142#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0 0xa06c
1143#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1 0xa07c
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07001144#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2 0xa08c
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001145#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_3 0xa09c
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07001146#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_5 0xa0bc
1147#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_6 0xa0cc
1148#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_7 0xa0dc
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001149/* [RW 32] first 32b for enabling the output for function 1 output0. mapped
1150 as follows: [0] NIG attention for function0; [1] NIG attention for
1151 function1; [2] GPIO1 function 1; [3] GPIO2 function 1; [4] GPIO3 function
1152 1; [5] GPIO4 function 1; [6] GPIO1 function 1; [7] GPIO2 function 1; [8]
1153 GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event
1154 function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP
1155 Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]
1156 SPIO4; [15] SPIO5; [16] MSI/X indication for function 1; [17] MSI/X
1157 indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt;
1158 [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23]
1159 SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26]
1160 TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29]
1161 TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */
1162#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 0xa10c
1163#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 0xa11c
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07001164#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 0xa12c
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001165#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_3 0xa13c
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07001166#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_5 0xa15c
1167#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_6 0xa16c
1168#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_7 0xa17c
1169/* [RW 32] first 32b for enabling the output for close the gate nig. mapped
1170 as follows: [0] NIG attention for function0; [1] NIG attention for
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001171 function1; [2] GPIO1 function 0; [3] GPIO2 function 0; [4] GPIO3 function
1172 0; [5] GPIO4 function 0; [6] GPIO1 function 1; [7] GPIO2 function 1; [8]
1173 GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event
1174 function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP
1175 Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]
1176 SPIO4; [15] SPIO5; [16] MSI/X indication for function 0; [17] MSI/X
1177 indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt;
1178 [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23]
1179 SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26]
1180 TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29]
1181 TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */
1182#define MISC_REG_AEU_ENABLE1_NIG_0 0xa0ec
1183#define MISC_REG_AEU_ENABLE1_NIG_1 0xa18c
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07001184/* [RW 32] first 32b for enabling the output for close the gate pxp. mapped
1185 as follows: [0] NIG attention for function0; [1] NIG attention for
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001186 function1; [2] GPIO1 function 0; [3] GPIO2 function 0; [4] GPIO3 function
1187 0; [5] GPIO4 function 0; [6] GPIO1 function 1; [7] GPIO2 function 1; [8]
1188 GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event
1189 function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP
1190 Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]
1191 SPIO4; [15] SPIO5; [16] MSI/X indication for function 0; [17] MSI/X
1192 indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt;
1193 [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23]
1194 SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26]
1195 TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29]
1196 TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */
1197#define MISC_REG_AEU_ENABLE1_PXP_0 0xa0fc
1198#define MISC_REG_AEU_ENABLE1_PXP_1 0xa19c
1199/* [RW 32] second 32b for enabling the output for function 0 output0. mapped
1200 as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM
1201 Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw
1202 interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity
1203 error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw
1204 interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14]
1205 NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error;
1206 [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw
1207 interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM
1208 Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI
1209 Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM
1210 Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw
1211 interrupt; */
1212#define MISC_REG_AEU_ENABLE2_FUNC_0_OUT_0 0xa070
1213#define MISC_REG_AEU_ENABLE2_FUNC_0_OUT_1 0xa080
1214/* [RW 32] second 32b for enabling the output for function 1 output0. mapped
1215 as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM
1216 Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw
1217 interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity
1218 error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw
1219 interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14]
1220 NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error;
1221 [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw
1222 interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM
1223 Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI
1224 Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM
1225 Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw
1226 interrupt; */
1227#define MISC_REG_AEU_ENABLE2_FUNC_1_OUT_0 0xa110
1228#define MISC_REG_AEU_ENABLE2_FUNC_1_OUT_1 0xa120
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07001229/* [RW 32] second 32b for enabling the output for close the gate nig. mapped
1230 as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM
1231 Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw
1232 interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity
1233 error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw
1234 interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14]
1235 NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error;
1236 [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw
1237 interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM
1238 Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI
1239 Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM
1240 Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw
1241 interrupt; */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001242#define MISC_REG_AEU_ENABLE2_NIG_0 0xa0f0
1243#define MISC_REG_AEU_ENABLE2_NIG_1 0xa190
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07001244/* [RW 32] second 32b for enabling the output for close the gate pxp. mapped
1245 as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM
1246 Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw
1247 interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity
1248 error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw
1249 interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14]
1250 NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error;
1251 [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw
1252 interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM
1253 Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI
1254 Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM
1255 Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw
1256 interrupt; */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001257#define MISC_REG_AEU_ENABLE2_PXP_0 0xa100
1258#define MISC_REG_AEU_ENABLE2_PXP_1 0xa1a0
1259/* [RW 32] third 32b for enabling the output for function 0 output0. mapped
1260 as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP
1261 Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error;
1262 [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw
1263 interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity
1264 error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC)
1265 Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16]
1266 pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20]
1267 MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23]
1268 SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW
1269 timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3
1270 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General
1271 attn1; */
1272#define MISC_REG_AEU_ENABLE3_FUNC_0_OUT_0 0xa074
1273#define MISC_REG_AEU_ENABLE3_FUNC_0_OUT_1 0xa084
1274/* [RW 32] third 32b for enabling the output for function 1 output0. mapped
1275 as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP
1276 Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error;
1277 [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw
1278 interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity
1279 error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC)
1280 Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16]
1281 pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20]
1282 MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23]
1283 SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW
1284 timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3
1285 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General
1286 attn1; */
1287#define MISC_REG_AEU_ENABLE3_FUNC_1_OUT_0 0xa114
1288#define MISC_REG_AEU_ENABLE3_FUNC_1_OUT_1 0xa124
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07001289/* [RW 32] third 32b for enabling the output for close the gate nig. mapped
1290 as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP
1291 Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error;
1292 [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw
1293 interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity
1294 error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC)
1295 Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16]
1296 pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20]
1297 MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23]
1298 SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW
1299 timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3
1300 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General
1301 attn1; */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001302#define MISC_REG_AEU_ENABLE3_NIG_0 0xa0f4
1303#define MISC_REG_AEU_ENABLE3_NIG_1 0xa194
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07001304/* [RW 32] third 32b for enabling the output for close the gate pxp. mapped
1305 as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP
1306 Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error;
1307 [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw
1308 interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity
1309 error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC)
1310 Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16]
1311 pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20]
1312 MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23]
1313 SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW
1314 timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3
1315 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General
1316 attn1; */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001317#define MISC_REG_AEU_ENABLE3_PXP_0 0xa104
1318#define MISC_REG_AEU_ENABLE3_PXP_1 0xa1a4
1319/* [RW 32] fourth 32b for enabling the output for function 0 output0.mapped
1320 as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
1321 General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
1322 [7] General attn9; [8] General attn10; [9] General attn11; [10] General
1323 attn12; [11] General attn13; [12] General attn14; [13] General attn15;
1324 [14] General attn16; [15] General attn17; [16] General attn18; [17]
1325 General attn19; [18] General attn20; [19] General attn21; [20] Main power
1326 interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
1327 Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
1328 Latched timeout attention; [27] GRC Latched reserved access attention;
1329 [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
1330 Latched ump_tx_parity; [31] MCP Latched scpad_parity; */
1331#define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0 0xa078
1332#define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_2 0xa098
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07001333#define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_4 0xa0b8
1334#define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_5 0xa0c8
1335#define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_6 0xa0d8
1336#define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_7 0xa0e8
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001337/* [RW 32] fourth 32b for enabling the output for function 1 output0.mapped
1338 as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
1339 General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
1340 [7] General attn9; [8] General attn10; [9] General attn11; [10] General
1341 attn12; [11] General attn13; [12] General attn14; [13] General attn15;
1342 [14] General attn16; [15] General attn17; [16] General attn18; [17]
1343 General attn19; [18] General attn20; [19] General attn21; [20] Main power
1344 interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
1345 Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
1346 Latched timeout attention; [27] GRC Latched reserved access attention;
1347 [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
1348 Latched ump_tx_parity; [31] MCP Latched scpad_parity; */
1349#define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0 0xa118
1350#define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_2 0xa138
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07001351#define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_4 0xa158
1352#define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_5 0xa168
1353#define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_6 0xa178
1354#define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_7 0xa188
1355/* [RW 32] fourth 32b for enabling the output for close the gate nig.mapped
1356 as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
1357 General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
1358 [7] General attn9; [8] General attn10; [9] General attn11; [10] General
1359 attn12; [11] General attn13; [12] General attn14; [13] General attn15;
1360 [14] General attn16; [15] General attn17; [16] General attn18; [17]
1361 General attn19; [18] General attn20; [19] General attn21; [20] Main power
1362 interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
1363 Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
1364 Latched timeout attention; [27] GRC Latched reserved access attention;
1365 [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
1366 Latched ump_tx_parity; [31] MCP Latched scpad_parity; */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001367#define MISC_REG_AEU_ENABLE4_NIG_0 0xa0f8
1368#define MISC_REG_AEU_ENABLE4_NIG_1 0xa198
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07001369/* [RW 32] fourth 32b for enabling the output for close the gate pxp.mapped
1370 as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
1371 General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
1372 [7] General attn9; [8] General attn10; [9] General attn11; [10] General
1373 attn12; [11] General attn13; [12] General attn14; [13] General attn15;
1374 [14] General attn16; [15] General attn17; [16] General attn18; [17]
1375 General attn19; [18] General attn20; [19] General attn21; [20] Main power
1376 interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
1377 Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
1378 Latched timeout attention; [27] GRC Latched reserved access attention;
1379 [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
1380 Latched ump_tx_parity; [31] MCP Latched scpad_parity; */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001381#define MISC_REG_AEU_ENABLE4_PXP_0 0xa108
1382#define MISC_REG_AEU_ENABLE4_PXP_1 0xa1a8
1383/* [RW 1] set/clr general attention 0; this will set/clr bit 94 in the aeu
1384 128 bit vector */
1385#define MISC_REG_AEU_GENERAL_ATTN_0 0xa000
1386#define MISC_REG_AEU_GENERAL_ATTN_1 0xa004
1387#define MISC_REG_AEU_GENERAL_ATTN_10 0xa028
1388#define MISC_REG_AEU_GENERAL_ATTN_11 0xa02c
1389#define MISC_REG_AEU_GENERAL_ATTN_12 0xa030
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001390#define MISC_REG_AEU_GENERAL_ATTN_2 0xa008
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001391#define MISC_REG_AEU_GENERAL_ATTN_3 0xa00c
1392#define MISC_REG_AEU_GENERAL_ATTN_4 0xa010
1393#define MISC_REG_AEU_GENERAL_ATTN_5 0xa014
1394#define MISC_REG_AEU_GENERAL_ATTN_6 0xa018
Eliezer Tamirf1410642008-02-28 11:51:50 -08001395#define MISC_REG_AEU_GENERAL_ATTN_7 0xa01c
1396#define MISC_REG_AEU_GENERAL_ATTN_8 0xa020
1397#define MISC_REG_AEU_GENERAL_ATTN_9 0xa024
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07001398#define MISC_REG_AEU_GENERAL_MASK 0xa61c
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001399/* [RW 32] first 32b for inverting the input for function 0; for each bit:
1400 0= do not invert; 1= invert; mapped as follows: [0] NIG attention for
1401 function0; [1] NIG attention for function1; [2] GPIO1 mcp; [3] GPIO2 mcp;
1402 [4] GPIO3 mcp; [5] GPIO4 mcp; [6] GPIO1 function 1; [7] GPIO2 function 1;
1403 [8] GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event
1404 function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP
1405 Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]
1406 SPIO4; [15] SPIO5; [16] MSI/X indication for mcp; [17] MSI/X indication
1407 for function 1; [18] BRB Parity error; [19] BRB Hw interrupt; [20] PRS
1408 Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23] SRC Hw
1409 interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26] TCM
1410 Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29] TSEMI
1411 Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */
1412#define MISC_REG_AEU_INVERTER_1_FUNC_0 0xa22c
1413#define MISC_REG_AEU_INVERTER_1_FUNC_1 0xa23c
1414/* [RW 32] second 32b for inverting the input for function 0; for each bit:
1415 0= do not invert; 1= invert. mapped as follows: [0] PBClient Parity
1416 error; [1] PBClient Hw interrupt; [2] QM Parity error; [3] QM Hw
1417 interrupt; [4] Timers Parity error; [5] Timers Hw interrupt; [6] XSDM
1418 Parity error; [7] XSDM Hw interrupt; [8] XCM Parity error; [9] XCM Hw
1419 interrupt; [10] XSEMI Parity error; [11] XSEMI Hw interrupt; [12]
1420 DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] NIG Parity
1421 error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; [17] Vaux
1422 PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw interrupt;
1423 [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM Parity error;
1424 [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI Hw interrupt;
1425 [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM Parity error;
1426 [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw interrupt; */
1427#define MISC_REG_AEU_INVERTER_2_FUNC_0 0xa230
1428#define MISC_REG_AEU_INVERTER_2_FUNC_1 0xa240
1429/* [RW 10] [7:0] = mask 8 attention output signals toward IGU function0;
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07001430 [9:8] = raserved. Zero = mask; one = unmask */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001431#define MISC_REG_AEU_MASK_ATTN_FUNC_0 0xa060
1432#define MISC_REG_AEU_MASK_ATTN_FUNC_1 0xa064
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07001433/* [RW 1] If set a system kill occurred */
1434#define MISC_REG_AEU_SYS_KILL_OCCURRED 0xa610
1435/* [RW 32] Represent the status of the input vector to the AEU when a system
1436 kill occurred. The register is reset in por reset. Mapped as follows: [0]
1437 NIG attention for function0; [1] NIG attention for function1; [2] GPIO1
1438 mcp; [3] GPIO2 mcp; [4] GPIO3 mcp; [5] GPIO4 mcp; [6] GPIO1 function 1;
1439 [7] GPIO2 function 1; [8] GPIO3 function 1; [9] GPIO4 function 1; [10]
1440 PCIE glue/PXP VPD event function0; [11] PCIE glue/PXP VPD event
1441 function1; [12] PCIE glue/PXP Expansion ROM event0; [13] PCIE glue/PXP
1442 Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16] MSI/X indication for
1443 mcp; [17] MSI/X indication for function 1; [18] BRB Parity error; [19]
1444 BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC
1445 Parity error; [23] SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw
1446 interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI
1447 Parity error; [29] TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw
1448 interrupt; */
1449#define MISC_REG_AEU_SYS_KILL_STATUS_0 0xa600
1450#define MISC_REG_AEU_SYS_KILL_STATUS_1 0xa604
1451#define MISC_REG_AEU_SYS_KILL_STATUS_2 0xa608
1452#define MISC_REG_AEU_SYS_KILL_STATUS_3 0xa60c
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001453/* [R 4] This field indicates the type of the device. '0' - 2 Ports; '1' - 1
1454 Port. */
1455#define MISC_REG_BOND_ID 0xa400
1456/* [R 8] These bits indicate the metal revision of the chip. This value
1457 starts at 0x00 for each all-layer tape-out and increments by one for each
1458 tape-out. */
1459#define MISC_REG_CHIP_METAL 0xa404
1460/* [R 16] These bits indicate the part number for the chip. */
1461#define MISC_REG_CHIP_NUM 0xa408
1462/* [R 4] These bits indicate the base revision of the chip. This value
1463 starts at 0x0 for the A0 tape-out and increments by one for each
1464 all-layer tape-out. */
1465#define MISC_REG_CHIP_REV 0xa40c
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07001466/* [RW 32] The following driver registers(1...16) represent 16 drivers and
1467 32 clients. Each client can be controlled by one driver only. One in each
1468 bit represent that this driver control the appropriate client (Ex: bit 5
1469 is set means this driver control client number 5). addr1 = set; addr0 =
1470 clear; read from both addresses will give the same result = status. write
1471 to address 1 will set a request to control all the clients that their
1472 appropriate bit (in the write command) is set. if the client is free (the
1473 appropriate bit in all the other drivers is clear) one will be written to
1474 that driver register; if the client isn't free the bit will remain zero.
1475 if the appropriate bit is set (the driver request to gain control on a
1476 client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW
1477 interrupt will be asserted). write to address 0 will set a request to
1478 free all the clients that their appropriate bit (in the write command) is
1479 set. if the appropriate bit is clear (the driver request to free a client
1480 it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will
1481 be asserted). */
Eliezer Tamirf1410642008-02-28 11:51:50 -08001482#define MISC_REG_DRIVER_CONTROL_1 0xa510
Yitchak Gertner4a37fb62008-08-13 15:50:23 -07001483#define MISC_REG_DRIVER_CONTROL_7 0xa3c8
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07001484/* [RW 1] e1hmf for WOL. If clr WOL signal o the PXP will be send on bit 0
1485 only. */
1486#define MISC_REG_E1HMF_MODE 0xa5f8
Yaniv Rosner3c9ada22011-06-14 01:34:12 +00001487/* [R 1] Status of four port mode path swap input pin. */
1488#define MISC_REG_FOUR_PORT_PATH_SWAP 0xa75c
1489/* [RW 2] 4 port path swap overwrite.[0] - Overwrite control; if it is 0 -
1490 the path_swap output is equal to 4 port mode path swap input pin; if it
1491 is 1 - the path_swap output is equal to bit[1] of this register; [1] -
1492 Overwrite value. If bit[0] of this register is 1 this is the value that
1493 receives the path_swap output. Reset on Hard reset. */
1494#define MISC_REG_FOUR_PORT_PATH_SWAP_OVWR 0xa738
1495/* [R 1] Status of 4 port mode port swap input pin. */
1496#define MISC_REG_FOUR_PORT_PORT_SWAP 0xa754
1497/* [RW 2] 4 port port swap overwrite.[0] - Overwrite control; if it is 0 -
1498 the port_swap output is equal to 4 port mode port swap input pin; if it
1499 is 1 - the port_swap output is equal to bit[1] of this register; [1] -
1500 Overwrite value. If bit[0] of this register is 1 this is the value that
1501 receives the port_swap output. Reset on Hard reset. */
1502#define MISC_REG_FOUR_PORT_PORT_SWAP_OVWR 0xa734
Eilon Greensteinca003922009-08-12 22:53:28 -07001503/* [RW 32] Debug only: spare RW register reset by core reset */
1504#define MISC_REG_GENERIC_CR_0 0xa460
Dmitry Kravkovf2e08992010-10-06 03:28:26 +00001505#define MISC_REG_GENERIC_CR_1 0xa464
Vladislav Zolotarov72fd0712010-04-19 01:13:12 +00001506/* [RW 32] Debug only: spare RW register reset by por reset */
1507#define MISC_REG_GENERIC_POR_1 0xa474
Yaniv Rosner3c9ada22011-06-14 01:34:12 +00001508/* [RW 32] Bit[0]: EPIO MODE SEL: Setting this bit to 1 will allow SW/FW to
1509 use all of the 32 Extended GPIO pins. Without setting this bit; an EPIO
1510 can not be configured as an output. Each output has its output enable in
1511 the MCP register space; but this bit needs to be set to make use of that.
1512 Bit[3:1] spare. Bit[4]: WCVTMON_PWRDN: Powerdown for Warpcore VTMON. When
1513 set to 1 - Powerdown. Bit[5]: WCVTMON_RESETB: Reset for Warpcore VTMON.
1514 When set to 0 - vTMON is in reset. Bit[6]: setting this bit will change
1515 the i/o to an output and will drive the TimeSync output. Bit[31:7]:
1516 spare. Global register. Reset by hard reset. */
1517#define MISC_REG_GEN_PURP_HWG 0xa9a0
Eliezer Tamirf1410642008-02-28 11:51:50 -08001518/* [RW 32] GPIO. [31-28] FLOAT port 0; [27-24] FLOAT port 0; When any of
1519 these bits is written as a '1'; the corresponding SPIO bit will turn off
1520 it's drivers and become an input. This is the reset state of all GPIO
1521 pins. The read value of these bits will be a '1' if that last command
1522 (#SET; #CLR; or #FLOAT) for this bit was a #FLOAT. (reset value 0xff).
1523 [23-20] CLR port 1; 19-16] CLR port 0; When any of these bits is written
1524 as a '1'; the corresponding GPIO bit will drive low. The read value of
1525 these bits will be a '1' if that last command (#SET; #CLR; or #FLOAT) for
1526 this bit was a #CLR. (reset value 0). [15-12] SET port 1; 11-8] port 0;
1527 SET When any of these bits is written as a '1'; the corresponding GPIO
1528 bit will drive high (if it has that capability). The read value of these
1529 bits will be a '1' if that last command (#SET; #CLR; or #FLOAT) for this
1530 bit was a #SET. (reset value 0). [7-4] VALUE port 1; [3-0] VALUE port 0;
1531 RO; These bits indicate the read value of each of the eight GPIO pins.
1532 This is the result value of the pin; not the drive value. Writing these
1533 bits will have not effect. */
1534#define MISC_REG_GPIO 0xa490
Eilon Greenstein4acac6a2009-02-12 08:36:52 +00001535/* [RW 8] These bits enable the GPIO_INTs to signals event to the
1536 IGU/MCP.according to the following map: [0] p0_gpio_0; [1] p0_gpio_1; [2]
1537 p0_gpio_2; [3] p0_gpio_3; [4] p1_gpio_0; [5] p1_gpio_1; [6] p1_gpio_2;
1538 [7] p1_gpio_3; */
1539#define MISC_REG_GPIO_EVENT_EN 0xa2bc
1540/* [RW 32] GPIO INT. [31-28] OLD_CLR port1; [27-24] OLD_CLR port0; Writing a
1541 '1' to these bit clears the corresponding bit in the #OLD_VALUE register.
1542 This will acknowledge an interrupt on the falling edge of corresponding
1543 GPIO input (reset value 0). [23-16] OLD_SET [23-16] port1; OLD_SET port0;
1544 Writing a '1' to these bit sets the corresponding bit in the #OLD_VALUE
1545 register. This will acknowledge an interrupt on the rising edge of
1546 corresponding SPIO input (reset value 0). [15-12] OLD_VALUE [11-8] port1;
1547 OLD_VALUE port0; RO; These bits indicate the old value of the GPIO input
1548 value. When the ~INT_STATE bit is set; this bit indicates the OLD value
1549 of the pin such that if ~INT_STATE is set and this bit is '0'; then the
1550 interrupt is due to a low to high edge. If ~INT_STATE is set and this bit
1551 is '1'; then the interrupt is due to a high to low edge (reset value 0).
1552 [7-4] INT_STATE port1; [3-0] INT_STATE RO port0; These bits indicate the
1553 current GPIO interrupt state for each GPIO pin. This bit is cleared when
1554 the appropriate #OLD_SET or #OLD_CLR command bit is written. This bit is
1555 set when the GPIO input does not match the current value in #OLD_VALUE
1556 (reset value 0). */
1557#define MISC_REG_GPIO_INT 0xa494
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07001558/* [R 28] this field hold the last information that caused reserved
1559 attention. bits [19:0] - address; [22:20] function; [23] reserved;
Eilon Greenstein33471622008-08-13 15:59:08 -07001560 [27:24] the master that caused the attention - according to the following
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07001561 encodeing:1 = pxp; 2 = mcp; 3 = usdm; 4 = tsdm; 5 = xsdm; 6 = csdm; 7 =
1562 dbu; 8 = dmae */
1563#define MISC_REG_GRC_RSV_ATTN 0xa3c0
1564/* [R 28] this field hold the last information that caused timeout
1565 attention. bits [19:0] - address; [22:20] function; [23] reserved;
Eilon Greenstein33471622008-08-13 15:59:08 -07001566 [27:24] the master that caused the attention - according to the following
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07001567 encodeing:1 = pxp; 2 = mcp; 3 = usdm; 4 = tsdm; 5 = xsdm; 6 = csdm; 7 =
1568 dbu; 8 = dmae */
1569#define MISC_REG_GRC_TIMEOUT_ATTN 0xa3c4
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001570/* [RW 1] Setting this bit enables a timer in the GRC block to timeout any
1571 access that does not finish within
1572 ~misc_registers_grc_timout_val.grc_timeout_val cycles. When this bit is
1573 cleared; this timeout is disabled. If this timeout occurs; the GRC shall
1574 assert it attention output. */
1575#define MISC_REG_GRC_TIMEOUT_EN 0xa280
1576/* [RW 28] 28 LSB of LCPLL first register; reset val = 521. inside order of
1577 the bits is: [2:0] OAC reset value 001) CML output buffer bias control;
1578 111 for +40%; 011 for +20%; 001 for 0%; 000 for -20%. [5:3] Icp_ctrl
1579 (reset value 001) Charge pump current control; 111 for 720u; 011 for
1580 600u; 001 for 480u and 000 for 360u. [7:6] Bias_ctrl (reset value 00)
1581 Global bias control; When bit 7 is high bias current will be 10 0gh; When
1582 bit 6 is high bias will be 100w; Valid values are 00; 10; 01. [10:8]
1583 Pll_observe (reset value 010) Bits to control observability. bit 10 is
1584 for test bias; bit 9 is for test CK; bit 8 is test Vc. [12:11] Vth_ctrl
1585 (reset value 00) Comparator threshold control. 00 for 0.6V; 01 for 0.54V
1586 and 10 for 0.66V. [13] pllSeqStart (reset value 0) Enables VCO tuning
1587 sequencer: 1= sequencer disabled; 0= sequencer enabled (inverted
1588 internally). [14] reserved (reset value 0) Reset for VCO sequencer is
1589 connected to RESET input directly. [15] capRetry_en (reset value 0)
1590 enable retry on cap search failure (inverted). [16] freqMonitor_e (reset
1591 value 0) bit to continuously monitor vco freq (inverted). [17]
1592 freqDetRestart_en (reset value 0) bit to enable restart when not freq
1593 locked (inverted). [18] freqDetRetry_en (reset value 0) bit to enable
1594 retry on freq det failure(inverted). [19] pllForceFdone_en (reset value
1595 0) bit to enable pllForceFdone & pllForceFpass into pllSeq. [20]
1596 pllForceFdone (reset value 0) bit to force freqDone. [21] pllForceFpass
1597 (reset value 0) bit to force freqPass. [22] pllForceDone_en (reset value
1598 0) bit to enable pllForceCapDone. [23] pllForceCapDone (reset value 0)
1599 bit to force capDone. [24] pllForceCapPass_en (reset value 0) bit to
1600 enable pllForceCapPass. [25] pllForceCapPass (reset value 0) bit to force
1601 capPass. [26] capRestart (reset value 0) bit to force cap sequencer to
1602 restart. [27] capSelectM_en (reset value 0) bit to enable cap select
1603 register bits. */
1604#define MISC_REG_LCPLL_CTRL_1 0xa2a4
1605#define MISC_REG_LCPLL_CTRL_REG_2 0xa2a8
1606/* [RW 4] Interrupt mask register #0 read/write */
1607#define MISC_REG_MISC_INT_MASK 0xa388
1608/* [RW 1] Parity mask register #0 read/write */
1609#define MISC_REG_MISC_PRTY_MASK 0xa398
Eliezer Tamirf1410642008-02-28 11:51:50 -08001610/* [R 1] Parity register #0 read */
1611#define MISC_REG_MISC_PRTY_STS 0xa38c
Vladislav Zolotarov4a33bc02011-01-09 02:20:04 +00001612/* [RC 1] Parity register #0 read clear */
1613#define MISC_REG_MISC_PRTY_STS_CLR 0xa390
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07001614#define MISC_REG_NIG_WOL_P0 0xa270
1615#define MISC_REG_NIG_WOL_P1 0xa274
1616/* [R 1] If set indicate that the pcie_rst_b was asserted without perst
1617 assertion */
1618#define MISC_REG_PCIE_HOT_RESET 0xa618
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001619/* [RW 32] 32 LSB of storm PLL first register; reset val = 0x 071d2911.
1620 inside order of the bits is: [0] P1 divider[0] (reset value 1); [1] P1
1621 divider[1] (reset value 0); [2] P1 divider[2] (reset value 0); [3] P1
1622 divider[3] (reset value 0); [4] P2 divider[0] (reset value 1); [5] P2
1623 divider[1] (reset value 0); [6] P2 divider[2] (reset value 0); [7] P2
1624 divider[3] (reset value 0); [8] ph_det_dis (reset value 1); [9]
1625 freq_det_dis (reset value 0); [10] Icpx[0] (reset value 0); [11] Icpx[1]
1626 (reset value 1); [12] Icpx[2] (reset value 0); [13] Icpx[3] (reset value
1627 1); [14] Icpx[4] (reset value 0); [15] Icpx[5] (reset value 0); [16]
1628 Rx[0] (reset value 1); [17] Rx[1] (reset value 0); [18] vc_en (reset
1629 value 1); [19] vco_rng[0] (reset value 1); [20] vco_rng[1] (reset value
1630 1); [21] Kvco_xf[0] (reset value 0); [22] Kvco_xf[1] (reset value 0);
1631 [23] Kvco_xf[2] (reset value 0); [24] Kvco_xs[0] (reset value 1); [25]
1632 Kvco_xs[1] (reset value 1); [26] Kvco_xs[2] (reset value 1); [27]
1633 testd_en (reset value 0); [28] testd_sel[0] (reset value 0); [29]
1634 testd_sel[1] (reset value 0); [30] testd_sel[2] (reset value 0); [31]
1635 testa_en (reset value 0); */
1636#define MISC_REG_PLL_STORM_CTRL_1 0xa294
1637#define MISC_REG_PLL_STORM_CTRL_2 0xa298
1638#define MISC_REG_PLL_STORM_CTRL_3 0xa29c
1639#define MISC_REG_PLL_STORM_CTRL_4 0xa2a0
Dmitry Kravkovf2e08992010-10-06 03:28:26 +00001640/* [R 1] Status of 4 port mode enable input pin. */
1641#define MISC_REG_PORT4MODE_EN 0xa750
1642/* [RW 2] 4 port mode enable overwrite.[0] - Overwrite control; if it is 0 -
1643 * the port4mode_en output is equal to 4 port mode input pin; if it is 1 -
1644 * the port4mode_en output is equal to bit[1] of this register; [1] -
1645 * Overwrite value. If bit[0] of this register is 1 this is the value that
1646 * receives the port4mode_en output . */
1647#define MISC_REG_PORT4MODE_EN_OVWR 0xa720
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07001648/* [RW 32] reset reg#2; rite/read one = the specific block is out of reset;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001649 write/read zero = the specific block is in reset; addr 0-wr- the write
1650 value will be written to the register; addr 1-set - one will be written
1651 to all the bits that have the value of one in the data written (bits that
1652 have the value of zero will not be change) ; addr 2-clear - zero will be
1653 written to all the bits that have the value of one in the data written
1654 (bits that have the value of zero will not be change); addr 3-ignore;
1655 read ignore from all addr except addr 00; inside order of the bits is:
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07001656 [0] rst_bmac0; [1] rst_bmac1; [2] rst_emac0; [3] rst_emac1; [4] rst_grc;
1657 [5] rst_mcp_n_reset_reg_hard_core; [6] rst_ mcp_n_hard_core_rst_b; [7]
1658 rst_ mcp_n_reset_cmn_cpu; [8] rst_ mcp_n_reset_cmn_core; [9] rst_rbcn;
1659 [10] rst_dbg; [11] rst_misc_core; [12] rst_dbue (UART); [13]
1660 Pci_resetmdio_n; [14] rst_emac0_hard_core; [15] rst_emac1_hard_core; 16]
1661 rst_pxp_rq_rd_wr; 31:17] reserved */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001662#define MISC_REG_RESET_REG_2 0xa590
1663/* [RW 20] 20 bit GRC address where the scratch-pad of the MCP that is
1664 shared with the driver resides */
1665#define MISC_REG_SHARED_MEM_ADDR 0xa2b4
Eliezer Tamirf1410642008-02-28 11:51:50 -08001666/* [RW 32] SPIO. [31-24] FLOAT When any of these bits is written as a '1';
1667 the corresponding SPIO bit will turn off it's drivers and become an
1668 input. This is the reset state of all SPIO pins. The read value of these
1669 bits will be a '1' if that last command (#SET; #CL; or #FLOAT) for this
1670 bit was a #FLOAT. (reset value 0xff). [23-16] CLR When any of these bits
1671 is written as a '1'; the corresponding SPIO bit will drive low. The read
1672 value of these bits will be a '1' if that last command (#SET; #CLR; or
1673#FLOAT) for this bit was a #CLR. (reset value 0). [15-8] SET When any of
1674 these bits is written as a '1'; the corresponding SPIO bit will drive
1675 high (if it has that capability). The read value of these bits will be a
1676 '1' if that last command (#SET; #CLR; or #FLOAT) for this bit was a #SET.
1677 (reset value 0). [7-0] VALUE RO; These bits indicate the read value of
1678 each of the eight SPIO pins. This is the result value of the pin; not the
1679 drive value. Writing these bits will have not effect. Each 8 bits field
1680 is divided as follows: [0] VAUX Enable; when pulsed low; enables supply
1681 from VAUX. (This is an output pin only; the FLOAT field is not applicable
1682 for this pin); [1] VAUX Disable; when pulsed low; disables supply form
1683 VAUX. (This is an output pin only; FLOAT field is not applicable for this
1684 pin); [2] SEL_VAUX_B - Control to power switching logic. Drive low to
1685 select VAUX supply. (This is an output pin only; it is not controlled by
1686 the SET and CLR fields; it is controlled by the Main Power SM; the FLOAT
1687 field is not applicable for this pin; only the VALUE fields is relevant -
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07001688 it reflects the output value); [3] port swap [4] spio_4; [5] spio_5; [6]
Eliezer Tamirf1410642008-02-28 11:51:50 -08001689 Bit 0 of UMP device ID select; read by UMP firmware; [7] Bit 1 of UMP
1690 device ID select; read by UMP firmware. */
1691#define MISC_REG_SPIO 0xa4fc
1692/* [RW 8] These bits enable the SPIO_INTs to signals event to the IGU/MC.
1693 according to the following map: [3:0] reserved; [4] spio_4 [5] spio_5;
1694 [7:0] reserved */
1695#define MISC_REG_SPIO_EVENT_EN 0xa2b8
1696/* [RW 32] SPIO INT. [31-24] OLD_CLR Writing a '1' to these bit clears the
1697 corresponding bit in the #OLD_VALUE register. This will acknowledge an
1698 interrupt on the falling edge of corresponding SPIO input (reset value
1699 0). [23-16] OLD_SET Writing a '1' to these bit sets the corresponding bit
1700 in the #OLD_VALUE register. This will acknowledge an interrupt on the
1701 rising edge of corresponding SPIO input (reset value 0). [15-8] OLD_VALUE
1702 RO; These bits indicate the old value of the SPIO input value. When the
1703 ~INT_STATE bit is set; this bit indicates the OLD value of the pin such
1704 that if ~INT_STATE is set and this bit is '0'; then the interrupt is due
1705 to a low to high edge. If ~INT_STATE is set and this bit is '1'; then the
1706 interrupt is due to a high to low edge (reset value 0). [7-0] INT_STATE
1707 RO; These bits indicate the current SPIO interrupt state for each SPIO
1708 pin. This bit is cleared when the appropriate #OLD_SET or #OLD_CLR
1709 command bit is written. This bit is set when the SPIO input does not
1710 match the current value in #OLD_VALUE (reset value 0). */
1711#define MISC_REG_SPIO_INT 0xa500
Eilon Greenstein8d9c5f32009-02-15 23:24:08 -08001712/* [RW 32] reload value for counter 4 if reload; the value will be reload if
1713 the counter reached zero and the reload bit
1714 (~misc_registers_sw_timer_cfg_4.sw_timer_cfg_4[1] ) is set */
1715#define MISC_REG_SW_TIMER_RELOAD_VAL_4 0xa2fc
1716/* [RW 32] the value of the counter for sw timers1-8. there are 8 addresses
Uwe Kleine-Königb5950762010-11-01 15:38:34 -04001717 in this register. address 0 - timer 1; address 1 - timer 2, ... address 7 -
Eilon Greenstein8d9c5f32009-02-15 23:24:08 -08001718 timer 8 */
1719#define MISC_REG_SW_TIMER_VAL 0xa5c0
Yaniv Rosner3c9ada22011-06-14 01:34:12 +00001720/* [R 1] Status of two port mode path swap input pin. */
1721#define MISC_REG_TWO_PORT_PATH_SWAP 0xa758
1722/* [RW 2] 2 port swap overwrite.[0] - Overwrite control; if it is 0 - the
1723 path_swap output is equal to 2 port mode path swap input pin; if it is 1
1724 - the path_swap output is equal to bit[1] of this register; [1] -
1725 Overwrite value. If bit[0] of this register is 1 this is the value that
1726 receives the path_swap output. Reset on Hard reset. */
1727#define MISC_REG_TWO_PORT_PATH_SWAP_OVWR 0xa72c
Eliezer Tamirf1410642008-02-28 11:51:50 -08001728/* [RW 1] Set by the MCP to remember if one or more of the drivers is/are
1729 loaded; 0-prepare; -unprepare */
1730#define MISC_REG_UNPREPARED 0xa424
Eilon Greenstein581ce432009-07-29 00:20:04 +00001731#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_BRCST (0x1<<0)
1732#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_MLCST (0x1<<1)
1733#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_NO_VLAN (0x1<<4)
1734#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_UNCST (0x1<<2)
1735#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_VLAN (0x1<<3)
Vlad Zolotarov619c5cb2011-06-14 14:33:44 +03001736/* [RW 5] MDIO PHY Address. The WC uses this address to determine whether or
1737 * not it is the recipient of the message on the MDIO interface. The value
1738 * is compared to the value on ctrl_md_devad. Drives output
1739 * misc_xgxs0_phy_addr. Global register. */
1740#define MISC_REG_WC0_CTRL_PHY_ADDR 0xa9cc
Yaniv Rosner9380bb92011-06-14 01:34:07 +00001741/* [RW 2] XMAC Core port mode. Indicates the number of ports on the system
1742 side. This should be less than or equal to phy_port_mode; if some of the
1743 ports are not used. This enables reduction of frequency on the core side.
1744 This is a strap input for the XMAC_MP core. 00 - Single Port Mode; 01 -
1745 Dual Port Mode; 10 - Tri Port Mode; 11 - Quad Port Mode. This is a strap
1746 input for the XMAC_MP core; and should be changed only while reset is
1747 held low. Reset on Hard reset. */
1748#define MISC_REG_XMAC_CORE_PORT_MODE 0xa964
1749/* [RW 2] XMAC PHY port mode. Indicates the number of ports on the Warp
1750 Core. This is a strap input for the XMAC_MP core. 00 - Single Port Mode;
1751 01 - Dual Port Mode; 1x - Quad Port Mode; This is a strap input for the
1752 XMAC_MP core; and should be changed only while reset is held low. Reset
1753 on Hard reset. */
1754#define MISC_REG_XMAC_PHY_PORT_MODE 0xa960
Vlad Zolotarov619c5cb2011-06-14 14:33:44 +03001755/* [RW 32] 1 [47] Packet Size = 64 Write to this register write bits 31:0.
1756 * Reads from this register will clear bits 31:0. */
1757#define MSTAT_REG_RX_STAT_GR64_LO 0x200
1758/* [RW 32] 1 [00] Tx Good Packet Count Write to this register write bits
1759 * 31:0. Reads from this register will clear bits 31:0. */
1760#define MSTAT_REG_TX_STAT_GTXPOK_LO 0
Yaniv Rosner9380bb92011-06-14 01:34:07 +00001761#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_BRCST (0x1<<0)
1762#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_MLCST (0x1<<1)
1763#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_NO_VLAN (0x1<<4)
1764#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_UNCST (0x1<<2)
1765#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_VLAN (0x1<<3)
Vladislav Zolotarovbcab15c2010-12-13 05:44:25 +00001766#define NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN (0x1<<0)
1767#define NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN (0x1<<0)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001768#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT (0x1<<0)
1769#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS (0x1<<9)
1770#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G (0x1<<15)
1771#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS (0xf<<18)
1772/* [RW 1] Input enable for RX_BMAC0 IF */
1773#define NIG_REG_BMAC0_IN_EN 0x100ac
1774/* [RW 1] output enable for TX_BMAC0 IF */
1775#define NIG_REG_BMAC0_OUT_EN 0x100e0
1776/* [RW 1] output enable for TX BMAC pause port 0 IF */
1777#define NIG_REG_BMAC0_PAUSE_OUT_EN 0x10110
1778/* [RW 1] output enable for RX_BMAC0_REGS IF */
1779#define NIG_REG_BMAC0_REGS_OUT_EN 0x100e8
1780/* [RW 1] output enable for RX BRB1 port0 IF */
1781#define NIG_REG_BRB0_OUT_EN 0x100f8
1782/* [RW 1] Input enable for TX BRB1 pause port 0 IF */
1783#define NIG_REG_BRB0_PAUSE_IN_EN 0x100c4
1784/* [RW 1] output enable for RX BRB1 port1 IF */
1785#define NIG_REG_BRB1_OUT_EN 0x100fc
1786/* [RW 1] Input enable for TX BRB1 pause port 1 IF */
1787#define NIG_REG_BRB1_PAUSE_IN_EN 0x100c8
1788/* [RW 1] output enable for RX BRB1 LP IF */
1789#define NIG_REG_BRB_LB_OUT_EN 0x10100
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07001790/* [WB_W 82] Debug packet to LP from RBC; Data spelling:[63:0] data; 64]
1791 error; [67:65]eop_bvalid; [68]eop; [69]sop; [70]port_id; 71]flush;
1792 72:73]-vnic_num; 81:74]-sideband_info */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001793#define NIG_REG_DEBUG_PACKET_LB 0x10800
1794/* [RW 1] Input enable for TX Debug packet */
1795#define NIG_REG_EGRESS_DEBUG_IN_EN 0x100dc
1796/* [RW 1] If 1 - egress drain mode for port0 is active. In this mode all
1797 packets from PBFare not forwarded to the MAC and just deleted from FIFO.
1798 First packet may be deleted from the middle. And last packet will be
1799 always deleted till the end. */
1800#define NIG_REG_EGRESS_DRAIN0_MODE 0x10060
1801/* [RW 1] Output enable to EMAC0 */
1802#define NIG_REG_EGRESS_EMAC0_OUT_EN 0x10120
1803/* [RW 1] MAC configuration for packets of port0. If 1 - all packet outputs
1804 to emac for port0; other way to bmac for port0 */
1805#define NIG_REG_EGRESS_EMAC0_PORT 0x10058
1806/* [RW 1] Input enable for TX PBF user packet port0 IF */
1807#define NIG_REG_EGRESS_PBF0_IN_EN 0x100cc
1808/* [RW 1] Input enable for TX PBF user packet port1 IF */
1809#define NIG_REG_EGRESS_PBF1_IN_EN 0x100d0
Eilon Greenstein279abdf2009-07-21 05:47:22 +00001810/* [RW 1] Input enable for TX UMP management packet port0 IF */
1811#define NIG_REG_EGRESS_UMP0_IN_EN 0x100d4
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001812/* [RW 1] Input enable for RX_EMAC0 IF */
1813#define NIG_REG_EMAC0_IN_EN 0x100a4
1814/* [RW 1] output enable for TX EMAC pause port 0 IF */
1815#define NIG_REG_EMAC0_PAUSE_OUT_EN 0x10118
1816/* [R 1] status from emac0. This bit is set when MDINT from either the
1817 EXT_MDINT pin or from the Copper PHY is driven low. This condition must
1818 be cleared in the attached PHY device that is driving the MINT pin. */
1819#define NIG_REG_EMAC0_STATUS_MISC_MI_INT 0x10494
1820/* [WB 48] This address space contains BMAC0 registers. The BMAC registers
1821 are described in appendix A. In order to access the BMAC0 registers; the
1822 base address; NIG_REGISTERS_INGRESS_BMAC0_MEM; Offset: 0x10c00; should be
1823 added to each BMAC register offset */
1824#define NIG_REG_INGRESS_BMAC0_MEM 0x10c00
1825/* [WB 48] This address space contains BMAC1 registers. The BMAC registers
1826 are described in appendix A. In order to access the BMAC0 registers; the
1827 base address; NIG_REGISTERS_INGRESS_BMAC1_MEM; Offset: 0x11000; should be
1828 added to each BMAC register offset */
1829#define NIG_REG_INGRESS_BMAC1_MEM 0x11000
1830/* [R 1] FIFO empty in EOP descriptor FIFO of LP in NIG_RX_EOP */
1831#define NIG_REG_INGRESS_EOP_LB_EMPTY 0x104e0
1832/* [RW 17] Debug only. RX_EOP_DSCR_lb_FIFO in NIG_RX_EOP. Data
1833 packet_length[13:0]; mac_error[14]; trunc_error[15]; parity[16] */
1834#define NIG_REG_INGRESS_EOP_LB_FIFO 0x104e4
Eilon Greenstein2f904462009-08-12 08:22:16 +00001835/* [RW 27] 0 - must be active for Everest A0; 1- for Everest B0 when latch
1836 logic for interrupts must be used. Enable per bit of interrupt of
1837 ~latch_status.latch_status */
1838#define NIG_REG_LATCH_BC_0 0x16210
1839/* [RW 27] Latch for each interrupt from Unicore.b[0]
1840 status_emac0_misc_mi_int; b[1] status_emac0_misc_mi_complete;
1841 b[2]status_emac0_misc_cfg_change; b[3]status_emac0_misc_link_status;
1842 b[4]status_emac0_misc_link_change; b[5]status_emac0_misc_attn;
1843 b[6]status_serdes0_mac_crs; b[7]status_serdes0_autoneg_complete;
1844 b[8]status_serdes0_fiber_rxact; b[9]status_serdes0_link_status;
1845 b[10]status_serdes0_mr_page_rx; b[11]status_serdes0_cl73_an_complete;
1846 b[12]status_serdes0_cl73_mr_page_rx; b[13]status_serdes0_rx_sigdet;
1847 b[14]status_xgxs0_remotemdioreq; b[15]status_xgxs0_link10g;
1848 b[16]status_xgxs0_autoneg_complete; b[17]status_xgxs0_fiber_rxact;
1849 b[21:18]status_xgxs0_link_status; b[22]status_xgxs0_mr_page_rx;
1850 b[23]status_xgxs0_cl73_an_complete; b[24]status_xgxs0_cl73_mr_page_rx;
1851 b[25]status_xgxs0_rx_sigdet; b[26]status_xgxs0_mac_crs */
1852#define NIG_REG_LATCH_STATUS_0 0x18000
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001853/* [RW 1] led 10g for port 0 */
1854#define NIG_REG_LED_10G_P0 0x10320
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07001855/* [RW 1] led 10g for port 1 */
1856#define NIG_REG_LED_10G_P1 0x10324
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001857/* [RW 1] Port0: This bit is set to enable the use of the
1858 ~nig_registers_led_control_blink_rate_p0.led_control_blink_rate_p0 field
1859 defined below. If this bit is cleared; then the blink rate will be about
1860 8Hz. */
1861#define NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 0x10318
1862/* [RW 12] Port0: Specifies the period of each blink cycle (on + off) for
1863 Traffic LED in milliseconds. Must be a non-zero value. This 12-bit field
1864 is reset to 0x080; giving a default blink period of approximately 8Hz. */
1865#define NIG_REG_LED_CONTROL_BLINK_RATE_P0 0x10310
1866/* [RW 1] Port0: If set along with the
Eilon Greenstein34f80b02008-06-23 20:33:01 -07001867 ~nig_registers_led_control_override_traffic_p0.led_control_override_traffic_p0
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001868 bit and ~nig_registers_led_control_traffic_p0.led_control_traffic_p0 LED
1869 bit; the Traffic LED will blink with the blink rate specified in
1870 ~nig_registers_led_control_blink_rate_p0.led_control_blink_rate_p0 and
1871 ~nig_registers_led_control_blink_rate_ena_p0.led_control_blink_rate_ena_p0
1872 fields. */
1873#define NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 0x10308
1874/* [RW 1] Port0: If set overrides hardware control of the Traffic LED. The
1875 Traffic LED will then be controlled via bit ~nig_registers_
1876 led_control_traffic_p0.led_control_traffic_p0 and bit
1877 ~nig_registers_led_control_blink_traffic_p0.led_control_blink_traffic_p0 */
1878#define NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 0x102f8
1879/* [RW 1] Port0: If set along with the led_control_override_trafic_p0 bit;
1880 turns on the Traffic LED. If the led_control_blink_traffic_p0 bit is also
1881 set; the LED will blink with blink rate specified in
1882 ~nig_registers_led_control_blink_rate_p0.led_control_blink_rate_p0 and
1883 ~nig_regsters_led_control_blink_rate_ena_p0.led_control_blink_rate_ena_p0
1884 fields. */
1885#define NIG_REG_LED_CONTROL_TRAFFIC_P0 0x10300
1886/* [RW 4] led mode for port0: 0 MAC; 1-3 PHY1; 4 MAC2; 5-7 PHY4; 8-MAC3;
1887 9-11PHY7; 12 MAC4; 13-15 PHY10; */
1888#define NIG_REG_LED_MODE_P0 0x102f0
Eilon Greenstein1c063282009-02-12 08:36:43 +00001889/* [RW 3] for port0 enable for llfc ppp and pause. b0 - brb1 enable; b1-
1890 tsdm enable; b2- usdm enable */
1891#define NIG_REG_LLFC_EGRESS_SRC_ENABLE_0 0x16070
Eilon Greensteinca003922009-08-12 22:53:28 -07001892#define NIG_REG_LLFC_EGRESS_SRC_ENABLE_1 0x16074
Eilon Greenstein1c063282009-02-12 08:36:43 +00001893/* [RW 1] SAFC enable for port0. This register may get 1 only when
1894 ~ppp_enable.ppp_enable = 0 and pause_enable.pause_enable =0 for the same
1895 port */
1896#define NIG_REG_LLFC_ENABLE_0 0x16208
Vladislav Zolotarovbcab15c2010-12-13 05:44:25 +00001897#define NIG_REG_LLFC_ENABLE_1 0x1620c
Eilon Greenstein1c063282009-02-12 08:36:43 +00001898/* [RW 16] classes are high-priority for port0 */
1899#define NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0 0x16058
Vladislav Zolotarovbcab15c2010-12-13 05:44:25 +00001900#define NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1 0x1605c
Eilon Greenstein1c063282009-02-12 08:36:43 +00001901/* [RW 16] classes are low-priority for port0 */
1902#define NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0 0x16060
Vladislav Zolotarovbcab15c2010-12-13 05:44:25 +00001903#define NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1 0x16064
Eilon Greenstein1c063282009-02-12 08:36:43 +00001904/* [RW 1] Output enable of message to LLFC BMAC IF for port0 */
1905#define NIG_REG_LLFC_OUT_EN_0 0x160c8
Vladislav Zolotarovbcab15c2010-12-13 05:44:25 +00001906#define NIG_REG_LLFC_OUT_EN_1 0x160cc
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07001907#define NIG_REG_LLH0_ACPI_PAT_0_CRC 0x1015c
1908#define NIG_REG_LLH0_ACPI_PAT_6_LEN 0x10154
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001909#define NIG_REG_LLH0_BRB1_DRV_MASK 0x10244
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07001910#define NIG_REG_LLH0_BRB1_DRV_MASK_MF 0x16048
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001911/* [RW 1] send to BRB1 if no match on any of RMP rules. */
1912#define NIG_REG_LLH0_BRB1_NOT_MCP 0x1025c
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07001913/* [RW 2] Determine the classification participants. 0: no classification.1:
1914 classification upon VLAN id. 2: classification upon MAC address. 3:
1915 classification upon both VLAN id & MAC addr. */
1916#define NIG_REG_LLH0_CLS_TYPE 0x16080
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001917/* [RW 32] cm header for llh0 */
1918#define NIG_REG_LLH0_CM_HEADER 0x1007c
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07001919#define NIG_REG_LLH0_DEST_IP_0_1 0x101dc
1920#define NIG_REG_LLH0_DEST_MAC_0_0 0x101c0
1921/* [RW 16] destination TCP address 1. The LLH will look for this address in
1922 all incoming packets. */
1923#define NIG_REG_LLH0_DEST_TCP_0 0x10220
1924/* [RW 16] destination UDP address 1 The LLH will look for this address in
1925 all incoming packets. */
1926#define NIG_REG_LLH0_DEST_UDP_0 0x10214
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001927#define NIG_REG_LLH0_ERROR_MASK 0x1008c
1928/* [RW 8] event id for llh0 */
1929#define NIG_REG_LLH0_EVENT_ID 0x10084
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07001930#define NIG_REG_LLH0_FUNC_EN 0x160fc
Dmitry Kravkov0793f83f2010-12-01 12:39:28 -08001931#define NIG_REG_LLH0_FUNC_MEM 0x16180
1932#define NIG_REG_LLH0_FUNC_MEM_ENABLE 0x16140
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07001933#define NIG_REG_LLH0_FUNC_VLAN_ID 0x16100
1934/* [RW 1] Determine the IP version to look for in
1935 ~nig_registers_llh0_dest_ip_0.llh0_dest_ip_0. 0 - IPv6; 1-IPv4 */
1936#define NIG_REG_LLH0_IPV4_IPV6_0 0x10208
1937/* [RW 1] t bit for llh0 */
1938#define NIG_REG_LLH0_T_BIT 0x10074
1939/* [RW 12] VLAN ID 1. In case of VLAN packet the LLH will look for this ID. */
1940#define NIG_REG_LLH0_VLAN_ID_0 0x1022c
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001941/* [RW 8] init credit counter for port0 in LLH */
1942#define NIG_REG_LLH0_XCM_INIT_CREDIT 0x10554
1943#define NIG_REG_LLH0_XCM_MASK 0x10130
Vladislav Zolotarovda5a6622008-08-13 15:50:00 -07001944#define NIG_REG_LLH1_BRB1_DRV_MASK 0x10248
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001945/* [RW 1] send to BRB1 if no match on any of RMP rules. */
1946#define NIG_REG_LLH1_BRB1_NOT_MCP 0x102dc
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07001947/* [RW 2] Determine the classification participants. 0: no classification.1:
1948 classification upon VLAN id. 2: classification upon MAC address. 3:
1949 classification upon both VLAN id & MAC addr. */
1950#define NIG_REG_LLH1_CLS_TYPE 0x16084
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001951/* [RW 32] cm header for llh1 */
1952#define NIG_REG_LLH1_CM_HEADER 0x10080
1953#define NIG_REG_LLH1_ERROR_MASK 0x10090
1954/* [RW 8] event id for llh1 */
1955#define NIG_REG_LLH1_EVENT_ID 0x10088
Dmitry Kravkov0793f83f2010-12-01 12:39:28 -08001956#define NIG_REG_LLH1_FUNC_MEM 0x161c0
1957#define NIG_REG_LLH1_FUNC_MEM_ENABLE 0x16160
1958#define NIG_REG_LLH1_FUNC_MEM_SIZE 16
Vlad Zolotarov619c5cb2011-06-14 14:33:44 +03001959/* [RW 1] When this bit is set; the LLH will classify the packet before
1960 * sending it to the BRB or calculating WoL on it. This bit controls port 1
1961 * only. The legacy llh_multi_function_mode bit controls port 0. */
1962#define NIG_REG_LLH1_MF_MODE 0x18614
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001963/* [RW 8] init credit counter for port1 in LLH */
1964#define NIG_REG_LLH1_XCM_INIT_CREDIT 0x10564
1965#define NIG_REG_LLH1_XCM_MASK 0x10134
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07001966/* [RW 1] When this bit is set; the LLH will expect all packets to be with
1967 e1hov */
1968#define NIG_REG_LLH_E1HOV_MODE 0x160d8
1969/* [RW 1] When this bit is set; the LLH will classify the packet before
1970 sending it to the BRB or calculating WoL on it. */
1971#define NIG_REG_LLH_MF_MODE 0x16024
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001972#define NIG_REG_MASK_INTERRUPT_PORT0 0x10330
1973#define NIG_REG_MASK_INTERRUPT_PORT1 0x10334
1974/* [RW 1] Output signal from NIG to EMAC0. When set enables the EMAC0 block. */
1975#define NIG_REG_NIG_EMAC0_EN 0x1003c
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07001976/* [RW 1] Output signal from NIG to EMAC1. When set enables the EMAC1 block. */
1977#define NIG_REG_NIG_EMAC1_EN 0x10040
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001978/* [RW 1] Output signal from NIG to TX_EMAC0. When set indicates to the
1979 EMAC0 to strip the CRC from the ingress packets. */
1980#define NIG_REG_NIG_INGRESS_EMAC0_NO_CRC 0x10044
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07001981/* [R 32] Interrupt register #0 read */
1982#define NIG_REG_NIG_INT_STS_0 0x103b0
1983#define NIG_REG_NIG_INT_STS_1 0x103c0
Vladislav Zolotarovc9ee9202011-06-14 01:33:51 +00001984/* [R 32] Legacy E1 and E1H location for parity error mask register. */
1985#define NIG_REG_NIG_PRTY_MASK 0x103dc
1986/* [RW 32] Parity mask register #0 read/write */
1987#define NIG_REG_NIG_PRTY_MASK_0 0x183c8
1988#define NIG_REG_NIG_PRTY_MASK_1 0x183d8
Dmitry Kravkovf2e08992010-10-06 03:28:26 +00001989/* [R 32] Legacy E1 and E1H location for parity error status register. */
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07001990#define NIG_REG_NIG_PRTY_STS 0x103d0
Dmitry Kravkovf2e08992010-10-06 03:28:26 +00001991/* [R 32] Parity register #0 read */
1992#define NIG_REG_NIG_PRTY_STS_0 0x183bc
1993#define NIG_REG_NIG_PRTY_STS_1 0x183cc
Vladislav Zolotarovc9ee9202011-06-14 01:33:51 +00001994/* [R 32] Legacy E1 and E1H location for parity error status clear register. */
1995#define NIG_REG_NIG_PRTY_STS_CLR 0x103d4
1996/* [RC 32] Parity register #0 read clear */
1997#define NIG_REG_NIG_PRTY_STS_CLR_0 0x183c0
1998#define NIG_REG_NIG_PRTY_STS_CLR_1 0x183d0
Yaniv Rosner3c9ada22011-06-14 01:34:12 +00001999#define MCPR_IMC_COMMAND_ENABLE (1L<<31)
2000#define MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT 16
2001#define MCPR_IMC_COMMAND_OPERATION_BITSHIFT 28
2002#define MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT 8
Dmitry Kravkovf2e08992010-10-06 03:28:26 +00002003/* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic
2004 * Ethernet header. */
2005#define NIG_REG_P0_HDRS_AFTER_BASIC 0x18038
2006/* [RW 1] HW PFC enable bit. Set this bit to enable the PFC functionality in
2007 * the NIG. Other flow control modes such as PAUSE and SAFC/LLFC should be
2008 * disabled when this bit is set. */
2009#define NIG_REG_P0_HWPFC_ENABLE 0x18078
2010#define NIG_REG_P0_LLH_FUNC_MEM2 0x18480
2011#define NIG_REG_P0_LLH_FUNC_MEM2_ENABLE 0x18440
Yaniv Rosner9380bb92011-06-14 01:34:07 +00002012/* [RW 1] Input enable for RX MAC interface. */
2013#define NIG_REG_P0_MAC_IN_EN 0x185ac
2014/* [RW 1] Output enable for TX MAC interface */
2015#define NIG_REG_P0_MAC_OUT_EN 0x185b0
2016/* [RW 1] Output enable for TX PAUSE signal to the MAC. */
2017#define NIG_REG_P0_MAC_PAUSE_OUT_EN 0x185b4
Dmitry Kravkovf2e08992010-10-06 03:28:26 +00002018/* [RW 32] Eight 4-bit configurations for specifying which COS (0-15 for
2019 * future expansion) each priorty is to be mapped to. Bits 3:0 specify the
2020 * COS for priority 0. Bits 31:28 specify the COS for priority 7. The 3-bit
2021 * priority field is extracted from the outer-most VLAN in receive packet.
2022 * Only COS 0 and COS 1 are supported in E2. */
2023#define NIG_REG_P0_PKT_PRIORITY_TO_COS 0x18054
2024/* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 0. A
2025 * priority is mapped to COS 0 when the corresponding mask bit is 1. More
2026 * than one bit may be set; allowing multiple priorities to be mapped to one
2027 * COS. */
2028#define NIG_REG_P0_RX_COS0_PRIORITY_MASK 0x18058
2029/* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 1. A
2030 * priority is mapped to COS 1 when the corresponding mask bit is 1. More
2031 * than one bit may be set; allowing multiple priorities to be mapped to one
2032 * COS. */
2033#define NIG_REG_P0_RX_COS1_PRIORITY_MASK 0x1805c
Vlad Zolotarov619c5cb2011-06-14 14:33:44 +03002034/* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 2. A
2035 * priority is mapped to COS 2 when the corresponding mask bit is 1. More
2036 * than one bit may be set; allowing multiple priorities to be mapped to one
2037 * COS. */
2038#define NIG_REG_P0_RX_COS2_PRIORITY_MASK 0x186b0
2039/* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 3. A
2040 * priority is mapped to COS 3 when the corresponding mask bit is 1. More
2041 * than one bit may be set; allowing multiple priorities to be mapped to one
2042 * COS. */
2043#define NIG_REG_P0_RX_COS3_PRIORITY_MASK 0x186b4
2044/* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 4. A
2045 * priority is mapped to COS 4 when the corresponding mask bit is 1. More
2046 * than one bit may be set; allowing multiple priorities to be mapped to one
2047 * COS. */
2048#define NIG_REG_P0_RX_COS4_PRIORITY_MASK 0x186b8
2049/* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 5. A
2050 * priority is mapped to COS 5 when the corresponding mask bit is 1. More
2051 * than one bit may be set; allowing multiple priorities to be mapped to one
2052 * COS. */
2053#define NIG_REG_P0_RX_COS5_PRIORITY_MASK 0x186bc
Yaniv Rosner9380bb92011-06-14 01:34:07 +00002054/* [R 1] RX FIFO for receiving data from MAC is empty. */
Dmitry Kravkovf2e08992010-10-06 03:28:26 +00002055/* [RW 15] Specify which of the credit registers the client is to be mapped
2056 * to. Bits[2:0] are for client 0; bits [14:12] are for client 4. For
2057 * clients that are not subject to WFQ credit blocking - their
2058 * specifications here are not used. */
2059#define NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP 0x180f0
Yaniv Rosner6c3218c2011-06-14 01:34:23 +00002060/* [RW 32] Specify which of the credit registers the client is to be mapped
2061 * to. This register specifies bits 31:0 of the 36-bit value. Bits[3:0] are
2062 * for client 0; bits [35:32] are for client 8. For clients that are not
2063 * subject to WFQ credit blocking - their specifications here are not used.
2064 * This is a new register (with 2_) added in E3 B0 to accommodate the 9
2065 * input clients to ETS arbiter. The reset default is set for management and
2066 * debug to use credit registers 6, 7, and 8, respectively, and COSes 0-5 to
2067 * use credit registers 0-5 respectively (0x543210876). Note that credit
2068 * registers can not be shared between clients. */
2069#define NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_LSB 0x18688
2070/* [RW 4] Specify which of the credit registers the client is to be mapped
2071 * to. This register specifies bits 35:32 of the 36-bit value. Bits[3:0] are
2072 * for client 0; bits [35:32] are for client 8. For clients that are not
2073 * subject to WFQ credit blocking - their specifications here are not used.
2074 * This is a new register (with 2_) added in E3 B0 to accommodate the 9
2075 * input clients to ETS arbiter. The reset default is set for management and
2076 * debug to use credit registers 6, 7, and 8, respectively, and COSes 0-5 to
2077 * use credit registers 0-5 respectively (0x543210876). Note that credit
2078 * registers can not be shared between clients. */
2079#define NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_MSB 0x1868c
Dmitry Kravkovf2e08992010-10-06 03:28:26 +00002080/* [RW 5] Specify whether the client competes directly in the strict
2081 * priority arbiter. The bits are mapped according to client ID (client IDs
2082 * are defined in tx_arb_priority_client). Default value is set to enable
2083 * strict priorities for clients 0-2 -- management and debug traffic. */
2084#define NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT 0x180e8
2085/* [RW 5] Specify whether the client is subject to WFQ credit blocking. The
2086 * bits are mapped according to client ID (client IDs are defined in
2087 * tx_arb_priority_client). Default value is 0 for not using WFQ credit
2088 * blocking. */
2089#define NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ 0x180ec
2090/* [RW 32] Specify the upper bound that credit register 0 is allowed to
2091 * reach. */
2092#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0 0x1810c
2093#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1 0x18110
Yaniv Rosner6c3218c2011-06-14 01:34:23 +00002094#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_2 0x18114
2095#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_3 0x18118
2096#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_4 0x1811c
2097#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_5 0x186a0
2098#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_6 0x186a4
2099#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_7 0x186a8
2100#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_8 0x186ac
Dmitry Kravkovf2e08992010-10-06 03:28:26 +00002101/* [RW 32] Specify the weight (in bytes) to be added to credit register 0
2102 * when it is time to increment. */
2103#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0 0x180f8
2104#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1 0x180fc
Yaniv Rosner6c3218c2011-06-14 01:34:23 +00002105#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2 0x18100
2106#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3 0x18104
2107#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4 0x18108
2108#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5 0x18690
2109#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_6 0x18694
2110#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_7 0x18698
2111#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_8 0x1869c
Dmitry Kravkovf2e08992010-10-06 03:28:26 +00002112/* [RW 12] Specify the number of strict priority arbitration slots between
2113 * two round-robin arbitration slots to avoid starvation. A value of 0 means
2114 * no strict priority cycles - the strict priority with anti-starvation
2115 * arbiter becomes a round-robin arbiter. */
2116#define NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS 0x180f4
2117/* [RW 15] Specify the client number to be assigned to each priority of the
2118 * strict priority arbiter. Priority 0 is the highest priority. Bits [2:0]
2119 * are for priority 0 client; bits [14:12] are for priority 4 client. The
2120 * clients are assigned the following IDs: 0-management; 1-debug traffic
2121 * from this port; 2-debug traffic from other port; 3-COS0 traffic; 4-COS1
2122 * traffic. The reset value[14:0] is set to 0x4688 (15'b100_011_010_001_000)
2123 * for management at priority 0; debug traffic at priorities 1 and 2; COS0
2124 * traffic at priority 3; and COS1 traffic at priority 4. */
2125#define NIG_REG_P0_TX_ARB_PRIORITY_CLIENT 0x180e4
Vlad Zolotarov619c5cb2011-06-14 14:33:44 +03002126/* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic
2127 * Ethernet header. */
2128#define NIG_REG_P1_HDRS_AFTER_BASIC 0x1818c
Dmitry Kravkovf2e08992010-10-06 03:28:26 +00002129#define NIG_REG_P1_LLH_FUNC_MEM2 0x184c0
2130#define NIG_REG_P1_LLH_FUNC_MEM2_ENABLE 0x18460
Yaniv Rosner6c3218c2011-06-14 01:34:23 +00002131/* [RW 32] Specify the client number to be assigned to each priority of the
2132 * strict priority arbiter. This register specifies bits 31:0 of the 36-bit
2133 * value. Priority 0 is the highest priority. Bits [3:0] are for priority 0
2134 * client; bits [35-32] are for priority 8 client. The clients are assigned
2135 * the following IDs: 0-management; 1-debug traffic from this port; 2-debug
2136 * traffic from other port; 3-COS0 traffic; 4-COS1 traffic; 5-COS2 traffic;
2137 * 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. The reset value[35:0] is
2138 * set to 0x345678021. This is a new register (with 2_) added in E3 B0 to
2139 * accommodate the 9 input clients to ETS arbiter. */
2140#define NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB 0x18680
2141/* [RW 4] Specify the client number to be assigned to each priority of the
2142 * strict priority arbiter. This register specifies bits 35:32 of the 36-bit
2143 * value. Priority 0 is the highest priority. Bits [3:0] are for priority 0
2144 * client; bits [35-32] are for priority 8 client. The clients are assigned
2145 * the following IDs: 0-management; 1-debug traffic from this port; 2-debug
2146 * traffic from other port; 3-COS0 traffic; 4-COS1 traffic; 5-COS2 traffic;
2147 * 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. The reset value[35:0] is
2148 * set to 0x345678021. This is a new register (with 2_) added in E3 B0 to
2149 * accommodate the 9 input clients to ETS arbiter. */
2150#define NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB 0x18684
Yaniv Rosner9380bb92011-06-14 01:34:07 +00002151#define NIG_REG_P1_MAC_IN_EN 0x185c0
2152/* [RW 1] Output enable for TX MAC interface */
2153#define NIG_REG_P1_MAC_OUT_EN 0x185c4
2154/* [RW 1] Output enable for TX PAUSE signal to the MAC. */
2155#define NIG_REG_P1_MAC_PAUSE_OUT_EN 0x185c8
Dmitry Kravkovf2e08992010-10-06 03:28:26 +00002156/* [RW 32] Eight 4-bit configurations for specifying which COS (0-15 for
2157 * future expansion) each priorty is to be mapped to. Bits 3:0 specify the
2158 * COS for priority 0. Bits 31:28 specify the COS for priority 7. The 3-bit
2159 * priority field is extracted from the outer-most VLAN in receive packet.
2160 * Only COS 0 and COS 1 are supported in E2. */
2161#define NIG_REG_P1_PKT_PRIORITY_TO_COS 0x181a8
2162/* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 0. A
2163 * priority is mapped to COS 0 when the corresponding mask bit is 1. More
2164 * than one bit may be set; allowing multiple priorities to be mapped to one
2165 * COS. */
2166#define NIG_REG_P1_RX_COS0_PRIORITY_MASK 0x181ac
2167/* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 1. A
2168 * priority is mapped to COS 1 when the corresponding mask bit is 1. More
2169 * than one bit may be set; allowing multiple priorities to be mapped to one
2170 * COS. */
2171#define NIG_REG_P1_RX_COS1_PRIORITY_MASK 0x181b0
Vlad Zolotarov619c5cb2011-06-14 14:33:44 +03002172/* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 2. A
2173 * priority is mapped to COS 2 when the corresponding mask bit is 1. More
2174 * than one bit may be set; allowing multiple priorities to be mapped to one
2175 * COS. */
2176#define NIG_REG_P1_RX_COS2_PRIORITY_MASK 0x186f8
Yaniv Rosner9380bb92011-06-14 01:34:07 +00002177/* [R 1] RX FIFO for receiving data from MAC is empty. */
2178#define NIG_REG_P1_RX_MACFIFO_EMPTY 0x1858c
2179/* [R 1] TLLH FIFO is empty. */
2180#define NIG_REG_P1_TLLH_FIFO_EMPTY 0x18338
2181/* [RW 32] Specify which of the credit registers the client is to be mapped
2182 * to. This register specifies bits 31:0 of the 36-bit value. Bits[3:0] are
2183 * for client 0; bits [35:32] are for client 8. For clients that are not
2184 * subject to WFQ credit blocking - their specifications here are not used.
2185 * This is a new register (with 2_) added in E3 B0 to accommodate the 9
2186 * input clients to ETS arbiter. The reset default is set for management and
2187 * debug to use credit registers 6, 7, and 8, respectively, and COSes 0-5 to
2188 * use credit registers 0-5 respectively (0x543210876). Note that credit
2189 * registers can not be shared between clients. Note also that there are
2190 * only COS0-2 in port 1- there is a total of 6 clients in port 1. Only
2191 * credit registers 0-5 are valid. This register should be configured
2192 * appropriately before enabling WFQ. */
2193#define NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_LSB 0x186e8
2194/* [RW 4] Specify which of the credit registers the client is to be mapped
2195 * to. This register specifies bits 35:32 of the 36-bit value. Bits[3:0] are
2196 * for client 0; bits [35:32] are for client 8. For clients that are not
2197 * subject to WFQ credit blocking - their specifications here are not used.
2198 * This is a new register (with 2_) added in E3 B0 to accommodate the 9
2199 * input clients to ETS arbiter. The reset default is set for management and
2200 * debug to use credit registers 6, 7, and 8, respectively, and COSes 0-5 to
2201 * use credit registers 0-5 respectively (0x543210876). Note that credit
2202 * registers can not be shared between clients. Note also that there are
2203 * only COS0-2 in port 1- there is a total of 6 clients in port 1. Only
2204 * credit registers 0-5 are valid. This register should be configured
2205 * appropriately before enabling WFQ. */
2206#define NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_MSB 0x186ec
2207/* [RW 9] Specify whether the client competes directly in the strict
2208 * priority arbiter. The bits are mapped according to client ID (client IDs
2209 * are defined in tx_arb_priority_client2): 0-management; 1-debug traffic
2210 * from this port; 2-debug traffic from other port; 3-COS0 traffic; 4-COS1
2211 * traffic; 5-COS2 traffic; 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic.
2212 * Default value is set to enable strict priorities for all clients. */
2213#define NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT 0x18234
2214/* [RW 9] Specify whether the client is subject to WFQ credit blocking. The
2215 * bits are mapped according to client ID (client IDs are defined in
2216 * tx_arb_priority_client2): 0-management; 1-debug traffic from this port;
2217 * 2-debug traffic from other port; 3-COS0 traffic; 4-COS1 traffic; 5-COS2
2218 * traffic; 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. Default value is
2219 * 0 for not using WFQ credit blocking. */
2220#define NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ 0x18238
Yaniv Rosner6c3218c2011-06-14 01:34:23 +00002221#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_0 0x18258
2222#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_1 0x1825c
2223#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_2 0x18260
2224#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_3 0x18264
2225#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_4 0x18268
2226#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_5 0x186f4
2227/* [RW 32] Specify the weight (in bytes) to be added to credit register 0
2228 * when it is time to increment. */
2229#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 0x18244
2230#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 0x18248
2231#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 0x1824c
2232#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_3 0x18250
2233#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_4 0x18254
2234#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_5 0x186f0
2235/* [RW 12] Specify the number of strict priority arbitration slots between
2236 two round-robin arbitration slots to avoid starvation. A value of 0 means
2237 no strict priority cycles - the strict priority with anti-starvation
2238 arbiter becomes a round-robin arbiter. */
2239#define NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS 0x18240
2240/* [RW 32] Specify the client number to be assigned to each priority of the
2241 strict priority arbiter. This register specifies bits 31:0 of the 36-bit
2242 value. Priority 0 is the highest priority. Bits [3:0] are for priority 0
2243 client; bits [35-32] are for priority 8 client. The clients are assigned
2244 the following IDs: 0-management; 1-debug traffic from this port; 2-debug
2245 traffic from other port; 3-COS0 traffic; 4-COS1 traffic; 5-COS2 traffic;
2246 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. The reset value[35:0] is
2247 set to 0x345678021. This is a new register (with 2_) added in E3 B0 to
2248 accommodate the 9 input clients to ETS arbiter. Note that this register
2249 is the same as the one for port 0, except that port 1 only has COS 0-2
2250 traffic. There is no traffic for COS 3-5 of port 1. */
2251#define NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB 0x186e0
2252/* [RW 4] Specify the client number to be assigned to each priority of the
2253 strict priority arbiter. This register specifies bits 35:32 of the 36-bit
2254 value. Priority 0 is the highest priority. Bits [3:0] are for priority 0
2255 client; bits [35-32] are for priority 8 client. The clients are assigned
2256 the following IDs: 0-management; 1-debug traffic from this port; 2-debug
2257 traffic from other port; 3-COS0 traffic; 4-COS1 traffic; 5-COS2 traffic;
2258 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. The reset value[35:0] is
2259 set to 0x345678021. This is a new register (with 2_) added in E3 B0 to
2260 accommodate the 9 input clients to ETS arbiter. Note that this register
2261 is the same as the one for port 0, except that port 1 only has COS 0-2
2262 traffic. There is no traffic for COS 3-5 of port 1. */
2263#define NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_MSB 0x186e4
2264/* [R 1] TX FIFO for transmitting data to MAC is empty. */
2265#define NIG_REG_P1_TX_MACFIFO_EMPTY 0x18594
2266/* [R 1] FIFO empty status of the MCP TX FIFO used for storing MCP packets
2267 forwarded to the host. */
2268#define NIG_REG_P1_TX_MNG_HOST_FIFO_EMPTY 0x182b8
Yaniv Rosner9380bb92011-06-14 01:34:07 +00002269/* [RW 32] Specify the upper bound that credit register 0 is allowed to
2270 * reach. */
Eilon Greenstein1c063282009-02-12 08:36:43 +00002271/* [RW 1] Pause enable for port0. This register may get 1 only when
2272 ~safc_enable.safc_enable = 0 and ppp_enable.ppp_enable =0 for the same
2273 port */
2274#define NIG_REG_PAUSE_ENABLE_0 0x160c0
Vladislav Zolotarovbcab15c2010-12-13 05:44:25 +00002275#define NIG_REG_PAUSE_ENABLE_1 0x160c4
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002276/* [RW 1] Input enable for RX PBF LP IF */
2277#define NIG_REG_PBF_LB_IN_EN 0x100b4
Eliezer Tamirf1410642008-02-28 11:51:50 -08002278/* [RW 1] Value of this register will be transmitted to port swap when
2279 ~nig_registers_strap_override.strap_override =1 */
2280#define NIG_REG_PORT_SWAP 0x10394
Vladislav Zolotarovbcab15c2010-12-13 05:44:25 +00002281/* [RW 1] PPP enable for port0. This register may get 1 only when
2282 * ~safc_enable.safc_enable = 0 and pause_enable.pause_enable =0 for the
2283 * same port */
2284#define NIG_REG_PPP_ENABLE_0 0x160b0
2285#define NIG_REG_PPP_ENABLE_1 0x160b4
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002286/* [RW 1] output enable for RX parser descriptor IF */
2287#define NIG_REG_PRS_EOP_OUT_EN 0x10104
2288/* [RW 1] Input enable for RX parser request IF */
2289#define NIG_REG_PRS_REQ_IN_EN 0x100b8
Eilon Greensteinc1b73992009-02-12 08:37:07 +00002290/* [RW 5] control to serdes - CL45 DEVAD */
2291#define NIG_REG_SERDES0_CTRL_MD_DEVAD 0x10370
2292/* [RW 1] control to serdes; 0 - clause 45; 1 - clause 22 */
2293#define NIG_REG_SERDES0_CTRL_MD_ST 0x1036c
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002294/* [RW 5] control to serdes - CL22 PHY_ADD and CL45 PRTAD */
2295#define NIG_REG_SERDES0_CTRL_PHY_ADDR 0x10374
2296/* [R 1] status from serdes0 that inputs to interrupt logic of link status */
2297#define NIG_REG_SERDES0_STATUS_LINK_STATUS 0x10578
2298/* [R 32] Rx statistics : In user packets discarded due to BRB backpressure
2299 for port0 */
2300#define NIG_REG_STAT0_BRB_DISCARD 0x105f0
Yitchak Gertner66e855f2008-08-13 15:49:05 -07002301/* [R 32] Rx statistics : In user packets truncated due to BRB backpressure
2302 for port0 */
2303#define NIG_REG_STAT0_BRB_TRUNCATE 0x105f8
Eilon Greenstein34f80b02008-06-23 20:33:01 -07002304/* [WB_R 36] Tx statistics : Number of packets from emac0 or bmac0 that
2305 between 1024 and 1522 bytes for port0 */
2306#define NIG_REG_STAT0_EGRESS_MAC_PKT0 0x10750
2307/* [WB_R 36] Tx statistics : Number of packets from emac0 or bmac0 that
2308 between 1523 bytes and above for port0 */
2309#define NIG_REG_STAT0_EGRESS_MAC_PKT1 0x10760
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002310/* [R 32] Rx statistics : In user packets discarded due to BRB backpressure
2311 for port1 */
2312#define NIG_REG_STAT1_BRB_DISCARD 0x10628
Eilon Greenstein34f80b02008-06-23 20:33:01 -07002313/* [WB_R 36] Tx statistics : Number of packets from emac1 or bmac1 that
2314 between 1024 and 1522 bytes for port1 */
2315#define NIG_REG_STAT1_EGRESS_MAC_PKT0 0x107a0
2316/* [WB_R 36] Tx statistics : Number of packets from emac1 or bmac1 that
2317 between 1523 bytes and above for port1 */
2318#define NIG_REG_STAT1_EGRESS_MAC_PKT1 0x107b0
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002319/* [WB_R 64] Rx statistics : User octets received for LP */
2320#define NIG_REG_STAT2_BRB_OCTET 0x107e0
2321#define NIG_REG_STATUS_INTERRUPT_PORT0 0x10328
2322#define NIG_REG_STATUS_INTERRUPT_PORT1 0x1032c
Eliezer Tamirf1410642008-02-28 11:51:50 -08002323/* [RW 1] port swap mux selection. If this register equal to 0 then port
2324 swap is equal to SPIO pin that inputs from ifmux_serdes_swap. If 1 then
2325 ort swap is equal to ~nig_registers_port_swap.port_swap */
2326#define NIG_REG_STRAP_OVERRIDE 0x10398
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002327/* [RW 1] output enable for RX_XCM0 IF */
2328#define NIG_REG_XCM0_OUT_EN 0x100f0
2329/* [RW 1] output enable for RX_XCM1 IF */
2330#define NIG_REG_XCM1_OUT_EN 0x100f4
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07002331/* [RW 1] control to xgxs - remote PHY in-band MDIO */
2332#define NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST 0x10348
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002333/* [RW 5] control to xgxs - CL45 DEVAD */
2334#define NIG_REG_XGXS0_CTRL_MD_DEVAD 0x1033c
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07002335/* [RW 1] control to xgxs; 0 - clause 45; 1 - clause 22 */
2336#define NIG_REG_XGXS0_CTRL_MD_ST 0x10338
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002337/* [RW 5] control to xgxs - CL22 PHY_ADD and CL45 PRTAD */
2338#define NIG_REG_XGXS0_CTRL_PHY_ADDR 0x10340
2339/* [R 1] status from xgxs0 that inputs to interrupt logic of link10g. */
2340#define NIG_REG_XGXS0_STATUS_LINK10G 0x10680
2341/* [R 4] status from xgxs0 that inputs to interrupt logic of link status */
2342#define NIG_REG_XGXS0_STATUS_LINK_STATUS 0x10684
2343/* [RW 2] selection for XGXS lane of port 0 in NIG_MUX block */
2344#define NIG_REG_XGXS_LANE_SEL_P0 0x102e8
2345/* [RW 1] selection for port0 for NIG_MUX block : 0 = SerDes; 1 = XGXS */
2346#define NIG_REG_XGXS_SERDES0_MODE_SEL 0x102e0
Eilon Greenstein2f904462009-08-12 08:22:16 +00002347#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT (0x1<<0)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002348#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS (0x1<<9)
2349#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G (0x1<<15)
2350#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS (0xf<<18)
2351#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE 18
Vladislav Zolotarovbcab15c2010-12-13 05:44:25 +00002352/* [RW 31] The upper bound of the weight of COS0 in the ETS command arbiter. */
2353#define PBF_REG_COS0_UPPER_BOUND 0x15c05c
Yaniv Rosner6c3218c2011-06-14 01:34:23 +00002354/* [RW 31] The upper bound of the weight of COS0 in the ETS command arbiter
2355 * of port 0. */
2356#define PBF_REG_COS0_UPPER_BOUND_P0 0x15c2cc
2357/* [RW 31] The upper bound of the weight of COS0 in the ETS command arbiter
2358 * of port 1. */
2359#define PBF_REG_COS0_UPPER_BOUND_P1 0x15c2e4
Vladislav Zolotarovbcab15c2010-12-13 05:44:25 +00002360/* [RW 31] The weight of COS0 in the ETS command arbiter. */
2361#define PBF_REG_COS0_WEIGHT 0x15c054
Yaniv Rosner6c3218c2011-06-14 01:34:23 +00002362/* [RW 31] The weight of COS0 in port 0 ETS command arbiter. */
2363#define PBF_REG_COS0_WEIGHT_P0 0x15c2a8
2364/* [RW 31] The weight of COS0 in port 1 ETS command arbiter. */
2365#define PBF_REG_COS0_WEIGHT_P1 0x15c2c0
Vladislav Zolotarovbcab15c2010-12-13 05:44:25 +00002366/* [RW 31] The upper bound of the weight of COS1 in the ETS command arbiter. */
2367#define PBF_REG_COS1_UPPER_BOUND 0x15c060
2368/* [RW 31] The weight of COS1 in the ETS command arbiter. */
2369#define PBF_REG_COS1_WEIGHT 0x15c058
Yaniv Rosner6c3218c2011-06-14 01:34:23 +00002370/* [RW 31] The weight of COS1 in port 0 ETS command arbiter. */
2371#define PBF_REG_COS1_WEIGHT_P0 0x15c2ac
2372/* [RW 31] The weight of COS1 in port 1 ETS command arbiter. */
2373#define PBF_REG_COS1_WEIGHT_P1 0x15c2c4
2374/* [RW 31] The weight of COS2 in port 0 ETS command arbiter. */
2375#define PBF_REG_COS2_WEIGHT_P0 0x15c2b0
2376/* [RW 31] The weight of COS2 in port 1 ETS command arbiter. */
2377#define PBF_REG_COS2_WEIGHT_P1 0x15c2c8
2378/* [RW 31] The weight of COS3 in port 0 ETS command arbiter. */
2379#define PBF_REG_COS3_WEIGHT_P0 0x15c2b4
2380/* [RW 31] The weight of COS4 in port 0 ETS command arbiter. */
2381#define PBF_REG_COS4_WEIGHT_P0 0x15c2b8
2382/* [RW 31] The weight of COS5 in port 0 ETS command arbiter. */
2383#define PBF_REG_COS5_WEIGHT_P0 0x15c2bc
Vlad Zolotarov619c5cb2011-06-14 14:33:44 +03002384/* [R 11] Current credit for the LB queue in the tx port buffers in 16 byte
2385 * lines. */
2386#define PBF_REG_CREDIT_LB_Q 0x140338
2387/* [R 11] Current credit for queue 0 in the tx port buffers in 16 byte
2388 * lines. */
2389#define PBF_REG_CREDIT_Q0 0x14033c
2390/* [R 11] Current credit for queue 1 in the tx port buffers in 16 byte
2391 * lines. */
2392#define PBF_REG_CREDIT_Q1 0x140340
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002393/* [RW 1] Disable processing further tasks from port 0 (after ending the
2394 current task in process). */
2395#define PBF_REG_DISABLE_NEW_TASK_PROC_P0 0x14005c
2396/* [RW 1] Disable processing further tasks from port 1 (after ending the
2397 current task in process). */
2398#define PBF_REG_DISABLE_NEW_TASK_PROC_P1 0x140060
2399/* [RW 1] Disable processing further tasks from port 4 (after ending the
2400 current task in process). */
2401#define PBF_REG_DISABLE_NEW_TASK_PROC_P4 0x14006c
Dmitry Kravkovf2e08992010-10-06 03:28:26 +00002402#define PBF_REG_DISABLE_PF 0x1402e8
Yaniv Rosner6c3218c2011-06-14 01:34:23 +00002403/* [RW 18] For port 0: For each client that is subject to WFQ (the
2404 * corresponding bit is 1); indicates to which of the credit registers this
2405 * client is mapped. For clients which are not credit blocked; their mapping
2406 * is dont care. */
2407#define PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P0 0x15c288
2408/* [RW 9] For port 1: For each client that is subject to WFQ (the
2409 * corresponding bit is 1); indicates to which of the credit registers this
2410 * client is mapped. For clients which are not credit blocked; their mapping
2411 * is dont care. */
2412#define PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P1 0x15c28c
2413/* [RW 6] For port 0: Bit per client to indicate if the client competes in
2414 * the strict priority arbiter directly (corresponding bit = 1); or first
2415 * goes to the RR arbiter (corresponding bit = 0); and then competes in the
2416 * lowest priority in the strict-priority arbiter. */
2417#define PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 0x15c278
2418/* [RW 3] For port 1: Bit per client to indicate if the client competes in
2419 * the strict priority arbiter directly (corresponding bit = 1); or first
2420 * goes to the RR arbiter (corresponding bit = 0); and then competes in the
2421 * lowest priority in the strict-priority arbiter. */
2422#define PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 0x15c27c
2423/* [RW 6] For port 0: Bit per client to indicate if the client is subject to
2424 * WFQ credit blocking (corresponding bit = 1). */
2425#define PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0 0x15c280
2426/* [RW 3] For port 0: Bit per client to indicate if the client is subject to
2427 * WFQ credit blocking (corresponding bit = 1). */
2428#define PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 0x15c284
2429/* [RW 16] For port 0: The number of strict priority arbitration slots
2430 * between 2 RR arbitration slots. A value of 0 means no strict priority
2431 * cycles; i.e. the strict-priority w/ anti-starvation arbiter is a RR
2432 * arbiter. */
2433#define PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P0 0x15c2a0
2434/* [RW 16] For port 1: The number of strict priority arbitration slots
2435 * between 2 RR arbitration slots. A value of 0 means no strict priority
2436 * cycles; i.e. the strict-priority w/ anti-starvation arbiter is a RR
2437 * arbiter. */
2438#define PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P1 0x15c2a4
2439/* [RW 18] For port 0: Indicates which client is connected to each priority
2440 * in the strict-priority arbiter. Priority 0 is the highest priority, and
2441 * priority 5 is the lowest; to which the RR output is connected to (this is
2442 * not configurable). */
2443#define PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 0x15c270
2444/* [RW 9] For port 1: Indicates which client is connected to each priority
2445 * in the strict-priority arbiter. Priority 0 is the highest priority, and
2446 * priority 5 is the lowest; to which the RR output is connected to (this is
2447 * not configurable). */
2448#define PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 0x15c274
Vladislav Zolotarovbcab15c2010-12-13 05:44:25 +00002449/* [RW 1] Indicates that ETS is performed between the COSes in the command
2450 * arbiter. If reset strict priority w/ anti-starvation will be performed
2451 * w/o WFQ. */
2452#define PBF_REG_ETS_ENABLED 0x15c050
Dmitry Kravkovf2e08992010-10-06 03:28:26 +00002453/* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic
2454 * Ethernet header. */
2455#define PBF_REG_HDRS_AFTER_BASIC 0x15c0a8
Vlad Zolotarov619c5cb2011-06-14 14:33:44 +03002456/* [RW 6] Bit-map indicating which L2 hdrs may appear after L2 tag 0 */
2457#define PBF_REG_HDRS_AFTER_TAG_0 0x15c0b8
2458/* [R 1] Removed for E3 B0 - Indicates which COS is conncted to the highest
2459 * priority in the command arbiter. */
Vladislav Zolotarovbcab15c2010-12-13 05:44:25 +00002460#define PBF_REG_HIGH_PRIORITY_COS_NUM 0x15c04c
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002461#define PBF_REG_IF_ENABLE_REG 0x140044
2462/* [RW 1] Init bit. When set the initial credits are copied to the credit
2463 registers (except the port credits). Should be set and then reset after
2464 the configuration of the block has ended. */
2465#define PBF_REG_INIT 0x140000
Vlad Zolotarov619c5cb2011-06-14 14:33:44 +03002466/* [RW 11] Initial credit for the LB queue in the tx port buffers in 16 byte
2467 * lines. */
2468#define PBF_REG_INIT_CRD_LB_Q 0x15c248
2469/* [RW 11] Initial credit for queue 0 in the tx port buffers in 16 byte
2470 * lines. */
2471#define PBF_REG_INIT_CRD_Q0 0x15c230
2472/* [RW 11] Initial credit for queue 1 in the tx port buffers in 16 byte
2473 * lines. */
2474#define PBF_REG_INIT_CRD_Q1 0x15c234
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002475/* [RW 1] Init bit for port 0. When set the initial credit of port 0 is
2476 copied to the credit register. Should be set and then reset after the
2477 configuration of the port has ended. */
2478#define PBF_REG_INIT_P0 0x140004
2479/* [RW 1] Init bit for port 1. When set the initial credit of port 1 is
2480 copied to the credit register. Should be set and then reset after the
2481 configuration of the port has ended. */
2482#define PBF_REG_INIT_P1 0x140008
2483/* [RW 1] Init bit for port 4. When set the initial credit of port 4 is
2484 copied to the credit register. Should be set and then reset after the
2485 configuration of the port has ended. */
2486#define PBF_REG_INIT_P4 0x14000c
Vlad Zolotarov619c5cb2011-06-14 14:33:44 +03002487/* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for
2488 * the LB queue. Reset upon init. */
2489#define PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q 0x140354
2490/* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for
2491 * queue 0. Reset upon init. */
2492#define PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 0x140358
2493/* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for
2494 * queue 1. Reset upon init. */
2495#define PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 0x14035c
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002496/* [RW 1] Enable for mac interface 0. */
2497#define PBF_REG_MAC_IF0_ENABLE 0x140030
2498/* [RW 1] Enable for mac interface 1. */
2499#define PBF_REG_MAC_IF1_ENABLE 0x140034
2500/* [RW 1] Enable for the loopback interface. */
2501#define PBF_REG_MAC_LB_ENABLE 0x140040
Dmitry Kravkovf2e08992010-10-06 03:28:26 +00002502/* [RW 6] Bit-map indicating which headers must appear in the packet */
2503#define PBF_REG_MUST_HAVE_HDRS 0x15c0c4
Vladislav Zolotarovbcab15c2010-12-13 05:44:25 +00002504/* [RW 16] The number of strict priority arbitration slots between 2 RR
2505 * arbitration slots. A value of 0 means no strict priority cycles; i.e. the
2506 * strict-priority w/ anti-starvation arbiter is a RR arbiter. */
2507#define PBF_REG_NUM_STRICT_ARB_SLOTS 0x15c064
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002508/* [RW 10] Port 0 threshold used by arbiter in 16 byte lines used when pause
2509 not suppoterd. */
2510#define PBF_REG_P0_ARB_THRSH 0x1400e4
2511/* [R 11] Current credit for port 0 in the tx port buffers in 16 byte lines. */
2512#define PBF_REG_P0_CREDIT 0x140200
2513/* [RW 11] Initial credit for port 0 in the tx port buffers in 16 byte
2514 lines. */
2515#define PBF_REG_P0_INIT_CRD 0x1400d0
Vlad Zolotarov619c5cb2011-06-14 14:33:44 +03002516/* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for
2517 * port 0. Reset upon init. */
2518#define PBF_REG_P0_INTERNAL_CRD_FREED_CNT 0x140308
2519/* [R 1] Removed for E3 B0 - Indication that pause is enabled for port 0. */
2520#define PBF_REG_P0_PAUSE_ENABLE 0x140014
2521/* [R 8] Removed for E3 B0 - Number of tasks in port 0 task queue. */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002522#define PBF_REG_P0_TASK_CNT 0x140204
Vlad Zolotarov619c5cb2011-06-14 14:33:44 +03002523/* [R 32] Removed for E3 B0 - Cyclic counter for number of 8 byte lines
2524 * freed from the task queue of port 0. Reset upon init. */
2525#define PBF_REG_P0_TQ_LINES_FREED_CNT 0x1402f0
2526/* [R 12] Number of 8 bytes lines occupied in the task queue of port 0. */
2527#define PBF_REG_P0_TQ_OCCUPANCY 0x1402fc
2528/* [R 11] Removed for E3 B0 - Current credit for port 1 in the tx port
2529 * buffers in 16 byte lines. */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002530#define PBF_REG_P1_CREDIT 0x140208
Vlad Zolotarov619c5cb2011-06-14 14:33:44 +03002531/* [R 11] Removed for E3 B0 - Initial credit for port 0 in the tx port
2532 * buffers in 16 byte lines. */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002533#define PBF_REG_P1_INIT_CRD 0x1400d4
Vlad Zolotarov619c5cb2011-06-14 14:33:44 +03002534/* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for
2535 * port 1. Reset upon init. */
2536#define PBF_REG_P1_INTERNAL_CRD_FREED_CNT 0x14030c
2537/* [R 8] Removed for E3 B0 - Number of tasks in port 1 task queue. */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002538#define PBF_REG_P1_TASK_CNT 0x14020c
Vlad Zolotarov619c5cb2011-06-14 14:33:44 +03002539/* [R 32] Removed for E3 B0 - Cyclic counter for number of 8 byte lines
2540 * freed from the task queue of port 1. Reset upon init. */
2541#define PBF_REG_P1_TQ_LINES_FREED_CNT 0x1402f4
2542/* [R 12] Number of 8 bytes lines occupied in the task queue of port 1. */
2543#define PBF_REG_P1_TQ_OCCUPANCY 0x140300
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002544/* [R 11] Current credit for port 4 in the tx port buffers in 16 byte lines. */
2545#define PBF_REG_P4_CREDIT 0x140210
2546/* [RW 11] Initial credit for port 4 in the tx port buffers in 16 byte
2547 lines. */
2548#define PBF_REG_P4_INIT_CRD 0x1400e0
Vlad Zolotarov619c5cb2011-06-14 14:33:44 +03002549/* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for
2550 * port 4. Reset upon init. */
2551#define PBF_REG_P4_INTERNAL_CRD_FREED_CNT 0x140310
2552/* [R 8] Removed for E3 B0 - Number of tasks in port 4 task queue. */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002553#define PBF_REG_P4_TASK_CNT 0x140214
Vlad Zolotarov619c5cb2011-06-14 14:33:44 +03002554/* [R 32] Removed for E3 B0 - Cyclic counter for number of 8 byte lines
2555 * freed from the task queue of port 4. Reset upon init. */
2556#define PBF_REG_P4_TQ_LINES_FREED_CNT 0x1402f8
2557/* [R 12] Number of 8 bytes lines occupied in the task queue of port 4. */
2558#define PBF_REG_P4_TQ_OCCUPANCY 0x140304
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002559/* [RW 5] Interrupt mask register #0 read/write */
2560#define PBF_REG_PBF_INT_MASK 0x1401d4
2561/* [R 5] Interrupt register #0 read */
2562#define PBF_REG_PBF_INT_STS 0x1401c8
Vladislav Zolotarov4a33bc02011-01-09 02:20:04 +00002563/* [RW 20] Parity mask register #0 read/write */
2564#define PBF_REG_PBF_PRTY_MASK 0x1401e4
2565/* [RC 20] Parity register #0 read clear */
2566#define PBF_REG_PBF_PRTY_STS_CLR 0x1401dc
Vlad Zolotarov619c5cb2011-06-14 14:33:44 +03002567/* [RW 16] The Ethernet type value for L2 tag 0 */
2568#define PBF_REG_TAG_ETHERTYPE_0 0x15c090
2569/* [RW 4] The length of the info field for L2 tag 0. The length is between
2570 * 2B and 14B; in 2B granularity */
2571#define PBF_REG_TAG_LEN_0 0x15c09c
2572/* [R 32] Cyclic counter for number of 8 byte lines freed from the LB task
2573 * queue. Reset upon init. */
2574#define PBF_REG_TQ_LINES_FREED_CNT_LB_Q 0x14038c
2575/* [R 32] Cyclic counter for number of 8 byte lines freed from the task
2576 * queue 0. Reset upon init. */
2577#define PBF_REG_TQ_LINES_FREED_CNT_Q0 0x140390
2578/* [R 32] Cyclic counter for number of 8 byte lines freed from task queue 1.
2579 * Reset upon init. */
2580#define PBF_REG_TQ_LINES_FREED_CNT_Q1 0x140394
2581/* [R 13] Number of 8 bytes lines occupied in the task queue of the LB
2582 * queue. */
2583#define PBF_REG_TQ_OCCUPANCY_LB_Q 0x1403a8
2584/* [R 13] Number of 8 bytes lines occupied in the task queue of queue 0. */
2585#define PBF_REG_TQ_OCCUPANCY_Q0 0x1403ac
2586/* [R 13] Number of 8 bytes lines occupied in the task queue of queue 1. */
2587#define PBF_REG_TQ_OCCUPANCY_Q1 0x1403b0
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002588#define PB_REG_CONTROL 0
2589/* [RW 2] Interrupt mask register #0 read/write */
2590#define PB_REG_PB_INT_MASK 0x28
2591/* [R 2] Interrupt register #0 read */
2592#define PB_REG_PB_INT_STS 0x1c
2593/* [RW 4] Parity mask register #0 read/write */
2594#define PB_REG_PB_PRTY_MASK 0x38
Eliezer Tamirf1410642008-02-28 11:51:50 -08002595/* [R 4] Parity register #0 read */
2596#define PB_REG_PB_PRTY_STS 0x2c
Vladislav Zolotarov4a33bc02011-01-09 02:20:04 +00002597/* [RC 4] Parity register #0 read clear */
2598#define PB_REG_PB_PRTY_STS_CLR 0x30
Dmitry Kravkovf2e08992010-10-06 03:28:26 +00002599#define PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
2600#define PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW (0x1<<8)
2601#define PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR (0x1<<1)
2602#define PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN (0x1<<6)
2603#define PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN (0x1<<7)
2604#define PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN (0x1<<4)
2605#define PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN (0x1<<3)
2606#define PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN (0x1<<5)
2607#define PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN (0x1<<2)
2608/* [R 8] Config space A attention dirty bits. Each bit indicates that the
2609 * corresponding PF generates config space A attention. Set by PXP. Reset by
2610 * MCP writing 1 to icfg_space_a_request_clr. Note: register contains bits
2611 * from both paths. */
2612#define PGLUE_B_REG_CFG_SPACE_A_REQUEST 0x9010
2613/* [R 8] Config space B attention dirty bits. Each bit indicates that the
2614 * corresponding PF generates config space B attention. Set by PXP. Reset by
2615 * MCP writing 1 to icfg_space_b_request_clr. Note: register contains bits
2616 * from both paths. */
2617#define PGLUE_B_REG_CFG_SPACE_B_REQUEST 0x9014
2618/* [RW 1] Type A PF enable inbound interrupt table for CSDM. 0 - disable; 1
2619 * - enable. */
2620#define PGLUE_B_REG_CSDM_INB_INT_A_PF_ENABLE 0x9194
2621/* [RW 18] Type B VF inbound interrupt table for CSDM: bits[17:9]-mask;
2622 * its[8:0]-address. Bits [1:0] must be zero (DW resolution address). */
2623#define PGLUE_B_REG_CSDM_INB_INT_B_VF 0x916c
2624/* [RW 1] Type B VF enable inbound interrupt table for CSDM. 0 - disable; 1
2625 * - enable. */
2626#define PGLUE_B_REG_CSDM_INB_INT_B_VF_ENABLE 0x919c
2627/* [RW 16] Start offset of CSDM zone A (queue zone) in the internal RAM */
2628#define PGLUE_B_REG_CSDM_START_OFFSET_A 0x9100
2629/* [RW 16] Start offset of CSDM zone B (legacy zone) in the internal RAM */
2630#define PGLUE_B_REG_CSDM_START_OFFSET_B 0x9108
2631/* [RW 5] VF Shift of CSDM zone B (legacy zone) in the internal RAM */
2632#define PGLUE_B_REG_CSDM_VF_SHIFT_B 0x9110
2633/* [RW 1] 0 - Zone A size is 136x32B; 1 - Zone A size is 152x32B. */
2634#define PGLUE_B_REG_CSDM_ZONE_A_SIZE_PF 0x91ac
2635/* [R 8] FLR request attention dirty bits for PFs 0 to 7. Each bit indicates
2636 * that the FLR register of the corresponding PF was set. Set by PXP. Reset
2637 * by MCP writing 1 to flr_request_pf_7_0_clr. Note: register contains bits
2638 * from both paths. */
2639#define PGLUE_B_REG_FLR_REQUEST_PF_7_0 0x9028
2640/* [W 8] FLR request attention dirty bits clear for PFs 0 to 7. MCP writes 1
2641 * to a bit in this register in order to clear the corresponding bit in
2642 * flr_request_pf_7_0 register. Note: register contains bits from both
2643 * paths. */
2644#define PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR 0x9418
2645/* [R 32] FLR request attention dirty bits for VFs 96 to 127. Each bit
2646 * indicates that the FLR register of the corresponding VF was set. Set by
2647 * PXP. Reset by MCP writing 1 to flr_request_vf_127_96_clr. */
2648#define PGLUE_B_REG_FLR_REQUEST_VF_127_96 0x9024
2649/* [R 32] FLR request attention dirty bits for VFs 0 to 31. Each bit
2650 * indicates that the FLR register of the corresponding VF was set. Set by
2651 * PXP. Reset by MCP writing 1 to flr_request_vf_31_0_clr. */
2652#define PGLUE_B_REG_FLR_REQUEST_VF_31_0 0x9018
2653/* [R 32] FLR request attention dirty bits for VFs 32 to 63. Each bit
2654 * indicates that the FLR register of the corresponding VF was set. Set by
2655 * PXP. Reset by MCP writing 1 to flr_request_vf_63_32_clr. */
2656#define PGLUE_B_REG_FLR_REQUEST_VF_63_32 0x901c
2657/* [R 32] FLR request attention dirty bits for VFs 64 to 95. Each bit
2658 * indicates that the FLR register of the corresponding VF was set. Set by
2659 * PXP. Reset by MCP writing 1 to flr_request_vf_95_64_clr. */
2660#define PGLUE_B_REG_FLR_REQUEST_VF_95_64 0x9020
2661/* [R 8] Each bit indicates an incorrect behavior in user RX interface. Bit
2662 * 0 - Target memory read arrived with a correctable error. Bit 1 - Target
2663 * memory read arrived with an uncorrectable error. Bit 2 - Configuration RW
2664 * arrived with a correctable error. Bit 3 - Configuration RW arrived with
2665 * an uncorrectable error. Bit 4 - Completion with Configuration Request
2666 * Retry Status. Bit 5 - Expansion ROM access received with a write request.
2667 * Bit 6 - Completion with pcie_rx_err of 0000; CMPL_STATUS of non-zero; and
2668 * pcie_rx_last not asserted. Bit 7 - Completion with pcie_rx_err of 1010;
2669 * and pcie_rx_last not asserted. */
2670#define PGLUE_B_REG_INCORRECT_RCV_DETAILS 0x9068
2671#define PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER 0x942c
2672#define PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ 0x9430
2673#define PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_WRITE 0x9434
2674#define PGLUE_B_REG_INTERNAL_VFID_ENABLE 0x9438
2675/* [R 9] Interrupt register #0 read */
2676#define PGLUE_B_REG_PGLUE_B_INT_STS 0x9298
2677/* [RC 9] Interrupt register #0 read clear */
2678#define PGLUE_B_REG_PGLUE_B_INT_STS_CLR 0x929c
2679/* [R 2] Parity register #0 read */
2680#define PGLUE_B_REG_PGLUE_B_PRTY_STS 0x92a8
2681/* [R 13] Details of first request received with error. [2:0] - PFID. [3] -
2682 * VF_VALID. [9:4] - VFID. [11:10] - Error Code - 0 - Indicates Completion
2683 * Timeout of a User Tx non-posted request. 1 - unsupported request. 2 -
2684 * completer abort. 3 - Illegal value for this field. [12] valid - indicates
2685 * if there was a completion error since the last time this register was
2686 * cleared. */
2687#define PGLUE_B_REG_RX_ERR_DETAILS 0x9080
2688/* [R 18] Details of first ATS Translation Completion request received with
2689 * error. [2:0] - PFID. [3] - VF_VALID. [9:4] - VFID. [11:10] - Error Code -
2690 * 0 - Indicates Completion Timeout of a User Tx non-posted request. 1 -
2691 * unsupported request. 2 - completer abort. 3 - Illegal value for this
2692 * field. [16:12] - ATC OTB EntryID. [17] valid - indicates if there was a
2693 * completion error since the last time this register was cleared. */
2694#define PGLUE_B_REG_RX_TCPL_ERR_DETAILS 0x9084
2695/* [W 8] Debug only - Shadow BME bits clear for PFs 0 to 7. MCP writes 1 to
2696 * a bit in this register in order to clear the corresponding bit in
2697 * shadow_bme_pf_7_0 register. MCP should never use this unless a
2698 * work-around is needed. Note: register contains bits from both paths. */
2699#define PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR 0x9458
2700/* [R 8] SR IOV disabled attention dirty bits. Each bit indicates that the
2701 * VF enable register of the corresponding PF is written to 0 and was
2702 * previously 1. Set by PXP. Reset by MCP writing 1 to
2703 * sr_iov_disabled_request_clr. Note: register contains bits from both
2704 * paths. */
2705#define PGLUE_B_REG_SR_IOV_DISABLED_REQUEST 0x9030
2706/* [R 32] Indicates the status of tags 32-63. 0 - tags is used - read
2707 * completion did not return yet. 1 - tag is unused. Same functionality as
2708 * pxp2_registers_pgl_exp_rom_data2 for tags 0-31. */
2709#define PGLUE_B_REG_TAGS_63_32 0x9244
2710/* [RW 1] Type A PF enable inbound interrupt table for TSDM. 0 - disable; 1
2711 * - enable. */
2712#define PGLUE_B_REG_TSDM_INB_INT_A_PF_ENABLE 0x9170
2713/* [RW 16] Start offset of TSDM zone A (queue zone) in the internal RAM */
2714#define PGLUE_B_REG_TSDM_START_OFFSET_A 0x90c4
2715/* [RW 16] Start offset of TSDM zone B (legacy zone) in the internal RAM */
2716#define PGLUE_B_REG_TSDM_START_OFFSET_B 0x90cc
2717/* [RW 5] VF Shift of TSDM zone B (legacy zone) in the internal RAM */
2718#define PGLUE_B_REG_TSDM_VF_SHIFT_B 0x90d4
2719/* [RW 1] 0 - Zone A size is 136x32B; 1 - Zone A size is 152x32B. */
2720#define PGLUE_B_REG_TSDM_ZONE_A_SIZE_PF 0x91a0
2721/* [R 32] Address [31:0] of first read request not submitted due to error */
2722#define PGLUE_B_REG_TX_ERR_RD_ADD_31_0 0x9098
2723/* [R 32] Address [63:32] of first read request not submitted due to error */
2724#define PGLUE_B_REG_TX_ERR_RD_ADD_63_32 0x909c
2725/* [R 31] Details of first read request not submitted due to error. [4:0]
2726 * VQID. [5] TREQ. 1 - Indicates the request is a Translation Request.
2727 * [20:8] - Length in bytes. [23:21] - PFID. [24] - VF_VALID. [30:25] -
2728 * VFID. */
2729#define PGLUE_B_REG_TX_ERR_RD_DETAILS 0x90a0
2730/* [R 26] Details of first read request not submitted due to error. [15:0]
2731 * Request ID. [19:16] client ID. [20] - last SR. [24:21] - Error type -
2732 * [21] - Indicates was_error was set; [22] - Indicates BME was cleared;
2733 * [23] - Indicates FID_enable was cleared; [24] - Indicates VF with parent
2734 * PF FLR_request or IOV_disable_request dirty bit is set. [25] valid -
2735 * indicates if there was a request not submitted due to error since the
2736 * last time this register was cleared. */
2737#define PGLUE_B_REG_TX_ERR_RD_DETAILS2 0x90a4
2738/* [R 32] Address [31:0] of first write request not submitted due to error */
2739#define PGLUE_B_REG_TX_ERR_WR_ADD_31_0 0x9088
2740/* [R 32] Address [63:32] of first write request not submitted due to error */
2741#define PGLUE_B_REG_TX_ERR_WR_ADD_63_32 0x908c
2742/* [R 31] Details of first write request not submitted due to error. [4:0]
2743 * VQID. [20:8] - Length in bytes. [23:21] - PFID. [24] - VF_VALID. [30:25]
2744 * - VFID. */
2745#define PGLUE_B_REG_TX_ERR_WR_DETAILS 0x9090
2746/* [R 26] Details of first write request not submitted due to error. [15:0]
2747 * Request ID. [19:16] client ID. [20] - last SR. [24:21] - Error type -
2748 * [21] - Indicates was_error was set; [22] - Indicates BME was cleared;
2749 * [23] - Indicates FID_enable was cleared; [24] - Indicates VF with parent
2750 * PF FLR_request or IOV_disable_request dirty bit is set. [25] valid -
2751 * indicates if there was a request not submitted due to error since the
2752 * last time this register was cleared. */
2753#define PGLUE_B_REG_TX_ERR_WR_DETAILS2 0x9094
2754/* [RW 10] Type A PF/VF inbound interrupt table for USDM: bits[9:5]-mask;
2755 * its[4:0]-address relative to start_offset_a. Bits [1:0] can have any
2756 * value (Byte resolution address). */
2757#define PGLUE_B_REG_USDM_INB_INT_A_0 0x9128
2758#define PGLUE_B_REG_USDM_INB_INT_A_1 0x912c
2759#define PGLUE_B_REG_USDM_INB_INT_A_2 0x9130
2760#define PGLUE_B_REG_USDM_INB_INT_A_3 0x9134
2761#define PGLUE_B_REG_USDM_INB_INT_A_4 0x9138
2762#define PGLUE_B_REG_USDM_INB_INT_A_5 0x913c
2763#define PGLUE_B_REG_USDM_INB_INT_A_6 0x9140
2764/* [RW 1] Type A PF enable inbound interrupt table for USDM. 0 - disable; 1
2765 * - enable. */
2766#define PGLUE_B_REG_USDM_INB_INT_A_PF_ENABLE 0x917c
2767/* [RW 1] Type A VF enable inbound interrupt table for USDM. 0 - disable; 1
2768 * - enable. */
2769#define PGLUE_B_REG_USDM_INB_INT_A_VF_ENABLE 0x9180
2770/* [RW 1] Type B VF enable inbound interrupt table for USDM. 0 - disable; 1
2771 * - enable. */
2772#define PGLUE_B_REG_USDM_INB_INT_B_VF_ENABLE 0x9184
2773/* [RW 16] Start offset of USDM zone A (queue zone) in the internal RAM */
2774#define PGLUE_B_REG_USDM_START_OFFSET_A 0x90d8
2775/* [RW 16] Start offset of USDM zone B (legacy zone) in the internal RAM */
2776#define PGLUE_B_REG_USDM_START_OFFSET_B 0x90e0
2777/* [RW 5] VF Shift of USDM zone B (legacy zone) in the internal RAM */
2778#define PGLUE_B_REG_USDM_VF_SHIFT_B 0x90e8
2779/* [RW 1] 0 - Zone A size is 136x32B; 1 - Zone A size is 152x32B. */
2780#define PGLUE_B_REG_USDM_ZONE_A_SIZE_PF 0x91a4
2781/* [R 26] Details of first target VF request accessing VF GRC space that
2782 * failed permission check. [14:0] Address. [15] w_nr: 0 - Read; 1 - Write.
2783 * [21:16] VFID. [24:22] - PFID. [25] valid - indicates if there was a
2784 * request accessing VF GRC space that failed permission check since the
2785 * last time this register was cleared. Permission checks are: function
2786 * permission; R/W permission; address range permission. */
2787#define PGLUE_B_REG_VF_GRC_SPACE_VIOLATION_DETAILS 0x9234
2788/* [R 31] Details of first target VF request with length violation (too many
2789 * DWs) accessing BAR0. [12:0] Address in DWs (bits [14:2] of byte address).
2790 * [14:13] BAR. [20:15] VFID. [23:21] - PFID. [29:24] - Length in DWs. [30]
2791 * valid - indicates if there was a request with length violation since the
2792 * last time this register was cleared. Length violations: length of more
2793 * than 2DWs; length of 2DWs and address not QW aligned; window is GRC and
2794 * length is more than 1 DW. */
2795#define PGLUE_B_REG_VF_LENGTH_VIOLATION_DETAILS 0x9230
2796/* [R 8] Was_error indication dirty bits for PFs 0 to 7. Each bit indicates
2797 * that there was a completion with uncorrectable error for the
2798 * corresponding PF. Set by PXP. Reset by MCP writing 1 to
2799 * was_error_pf_7_0_clr. */
2800#define PGLUE_B_REG_WAS_ERROR_PF_7_0 0x907c
2801/* [W 8] Was_error indication dirty bits clear for PFs 0 to 7. MCP writes 1
2802 * to a bit in this register in order to clear the corresponding bit in
2803 * flr_request_pf_7_0 register. */
2804#define PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR 0x9470
2805/* [R 32] Was_error indication dirty bits for VFs 96 to 127. Each bit
2806 * indicates that there was a completion with uncorrectable error for the
2807 * corresponding VF. Set by PXP. Reset by MCP writing 1 to
2808 * was_error_vf_127_96_clr. */
2809#define PGLUE_B_REG_WAS_ERROR_VF_127_96 0x9078
2810/* [W 32] Was_error indication dirty bits clear for VFs 96 to 127. MCP
2811 * writes 1 to a bit in this register in order to clear the corresponding
2812 * bit in was_error_vf_127_96 register. */
2813#define PGLUE_B_REG_WAS_ERROR_VF_127_96_CLR 0x9474
2814/* [R 32] Was_error indication dirty bits for VFs 0 to 31. Each bit
2815 * indicates that there was a completion with uncorrectable error for the
2816 * corresponding VF. Set by PXP. Reset by MCP writing 1 to
2817 * was_error_vf_31_0_clr. */
2818#define PGLUE_B_REG_WAS_ERROR_VF_31_0 0x906c
2819/* [W 32] Was_error indication dirty bits clear for VFs 0 to 31. MCP writes
2820 * 1 to a bit in this register in order to clear the corresponding bit in
2821 * was_error_vf_31_0 register. */
2822#define PGLUE_B_REG_WAS_ERROR_VF_31_0_CLR 0x9478
2823/* [R 32] Was_error indication dirty bits for VFs 32 to 63. Each bit
2824 * indicates that there was a completion with uncorrectable error for the
2825 * corresponding VF. Set by PXP. Reset by MCP writing 1 to
2826 * was_error_vf_63_32_clr. */
2827#define PGLUE_B_REG_WAS_ERROR_VF_63_32 0x9070
2828/* [W 32] Was_error indication dirty bits clear for VFs 32 to 63. MCP writes
2829 * 1 to a bit in this register in order to clear the corresponding bit in
2830 * was_error_vf_63_32 register. */
2831#define PGLUE_B_REG_WAS_ERROR_VF_63_32_CLR 0x947c
2832/* [R 32] Was_error indication dirty bits for VFs 64 to 95. Each bit
2833 * indicates that there was a completion with uncorrectable error for the
2834 * corresponding VF. Set by PXP. Reset by MCP writing 1 to
2835 * was_error_vf_95_64_clr. */
2836#define PGLUE_B_REG_WAS_ERROR_VF_95_64 0x9074
2837/* [W 32] Was_error indication dirty bits clear for VFs 64 to 95. MCP writes
2838 * 1 to a bit in this register in order to clear the corresponding bit in
2839 * was_error_vf_95_64 register. */
2840#define PGLUE_B_REG_WAS_ERROR_VF_95_64_CLR 0x9480
2841/* [RW 1] Type A PF enable inbound interrupt table for XSDM. 0 - disable; 1
2842 * - enable. */
2843#define PGLUE_B_REG_XSDM_INB_INT_A_PF_ENABLE 0x9188
2844/* [RW 16] Start offset of XSDM zone A (queue zone) in the internal RAM */
2845#define PGLUE_B_REG_XSDM_START_OFFSET_A 0x90ec
2846/* [RW 16] Start offset of XSDM zone B (legacy zone) in the internal RAM */
2847#define PGLUE_B_REG_XSDM_START_OFFSET_B 0x90f4
2848/* [RW 5] VF Shift of XSDM zone B (legacy zone) in the internal RAM */
2849#define PGLUE_B_REG_XSDM_VF_SHIFT_B 0x90fc
2850/* [RW 1] 0 - Zone A size is 136x32B; 1 - Zone A size is 152x32B. */
2851#define PGLUE_B_REG_XSDM_ZONE_A_SIZE_PF 0x91a8
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002852#define PRS_REG_A_PRSU_20 0x40134
2853/* [R 8] debug only: CFC load request current credit. Transaction based. */
2854#define PRS_REG_CFC_LD_CURRENT_CREDIT 0x40164
2855/* [R 8] debug only: CFC search request current credit. Transaction based. */
2856#define PRS_REG_CFC_SEARCH_CURRENT_CREDIT 0x40168
2857/* [RW 6] The initial credit for the search message to the CFC interface.
2858 Credit is transaction based. */
2859#define PRS_REG_CFC_SEARCH_INITIAL_CREDIT 0x4011c
2860/* [RW 24] CID for port 0 if no match */
2861#define PRS_REG_CID_PORT_0 0x400fc
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002862/* [RW 32] The CM header for flush message where 'load existed' bit in CFC
2863 load response is reset and packet type is 0. Used in packet start message
2864 to TCM. */
2865#define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_0 0x400dc
2866#define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_1 0x400e0
2867#define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_2 0x400e4
2868#define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_3 0x400e8
2869#define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_4 0x400ec
Eilon Greenstein8d9c5f32009-02-15 23:24:08 -08002870#define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_5 0x400f0
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002871/* [RW 32] The CM header for flush message where 'load existed' bit in CFC
2872 load response is set and packet type is 0. Used in packet start message
2873 to TCM. */
2874#define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_0 0x400bc
2875#define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_1 0x400c0
2876#define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_2 0x400c4
2877#define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_3 0x400c8
2878#define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_4 0x400cc
Eilon Greenstein8d9c5f32009-02-15 23:24:08 -08002879#define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_5 0x400d0
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002880/* [RW 32] The CM header for a match and packet type 1 for loopback port.
2881 Used in packet start message to TCM. */
2882#define PRS_REG_CM_HDR_LOOPBACK_TYPE_1 0x4009c
2883#define PRS_REG_CM_HDR_LOOPBACK_TYPE_2 0x400a0
2884#define PRS_REG_CM_HDR_LOOPBACK_TYPE_3 0x400a4
2885#define PRS_REG_CM_HDR_LOOPBACK_TYPE_4 0x400a8
2886/* [RW 32] The CM header for a match and packet type 0. Used in packet start
2887 message to TCM. */
2888#define PRS_REG_CM_HDR_TYPE_0 0x40078
2889#define PRS_REG_CM_HDR_TYPE_1 0x4007c
2890#define PRS_REG_CM_HDR_TYPE_2 0x40080
2891#define PRS_REG_CM_HDR_TYPE_3 0x40084
2892#define PRS_REG_CM_HDR_TYPE_4 0x40088
2893/* [RW 32] The CM header in case there was not a match on the connection */
2894#define PRS_REG_CM_NO_MATCH_HDR 0x400b8
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07002895/* [RW 1] Indicates if in e1hov mode. 0=non-e1hov mode; 1=e1hov mode. */
2896#define PRS_REG_E1HOV_MODE 0x401c8
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002897/* [RW 8] The 8-bit event ID for a match and packet type 1. Used in packet
2898 start message to TCM. */
2899#define PRS_REG_EVENT_ID_1 0x40054
2900#define PRS_REG_EVENT_ID_2 0x40058
2901#define PRS_REG_EVENT_ID_3 0x4005c
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07002902/* [RW 16] The Ethernet type value for FCoE */
2903#define PRS_REG_FCOE_TYPE 0x401d0
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002904/* [RW 8] Context region for flush packet with packet type 0. Used in CFC
2905 load request message. */
2906#define PRS_REG_FLUSH_REGIONS_TYPE_0 0x40004
2907#define PRS_REG_FLUSH_REGIONS_TYPE_1 0x40008
2908#define PRS_REG_FLUSH_REGIONS_TYPE_2 0x4000c
2909#define PRS_REG_FLUSH_REGIONS_TYPE_3 0x40010
2910#define PRS_REG_FLUSH_REGIONS_TYPE_4 0x40014
2911#define PRS_REG_FLUSH_REGIONS_TYPE_5 0x40018
2912#define PRS_REG_FLUSH_REGIONS_TYPE_6 0x4001c
2913#define PRS_REG_FLUSH_REGIONS_TYPE_7 0x40020
Dmitry Kravkovf2e08992010-10-06 03:28:26 +00002914/* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic
2915 * Ethernet header. */
2916#define PRS_REG_HDRS_AFTER_BASIC 0x40238
Vlad Zolotarov619c5cb2011-06-14 14:33:44 +03002917/* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic
2918 * Ethernet header for port 0 packets. */
2919#define PRS_REG_HDRS_AFTER_BASIC_PORT_0 0x40270
2920#define PRS_REG_HDRS_AFTER_BASIC_PORT_1 0x40290
2921/* [R 6] Bit-map indicating which L2 hdrs may appear after L2 tag 0 */
2922#define PRS_REG_HDRS_AFTER_TAG_0 0x40248
2923/* [RW 6] Bit-map indicating which L2 hdrs may appear after L2 tag 0 for
2924 * port 0 packets */
2925#define PRS_REG_HDRS_AFTER_TAG_0_PORT_0 0x40280
2926#define PRS_REG_HDRS_AFTER_TAG_0_PORT_1 0x402a0
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002927/* [RW 4] The increment value to send in the CFC load request message */
2928#define PRS_REG_INC_VALUE 0x40048
Dmitry Kravkovf2e08992010-10-06 03:28:26 +00002929/* [RW 6] Bit-map indicating which headers must appear in the packet */
2930#define PRS_REG_MUST_HAVE_HDRS 0x40254
Vlad Zolotarov619c5cb2011-06-14 14:33:44 +03002931/* [RW 6] Bit-map indicating which headers must appear in the packet for
2932 * port 0 packets */
2933#define PRS_REG_MUST_HAVE_HDRS_PORT_0 0x4028c
2934#define PRS_REG_MUST_HAVE_HDRS_PORT_1 0x402ac
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002935#define PRS_REG_NIC_MODE 0x40138
2936/* [RW 8] The 8-bit event ID for cases where there is no match on the
2937 connection. Used in packet start message to TCM. */
2938#define PRS_REG_NO_MATCH_EVENT_ID 0x40070
2939/* [ST 24] The number of input CFC flush packets */
2940#define PRS_REG_NUM_OF_CFC_FLUSH_MESSAGES 0x40128
2941/* [ST 32] The number of cycles the Parser halted its operation since it
2942 could not allocate the next serial number */
2943#define PRS_REG_NUM_OF_DEAD_CYCLES 0x40130
2944/* [ST 24] The number of input packets */
2945#define PRS_REG_NUM_OF_PACKETS 0x40124
2946/* [ST 24] The number of input transparent flush packets */
2947#define PRS_REG_NUM_OF_TRANSPARENT_FLUSH_MESSAGES 0x4012c
2948/* [RW 8] Context region for received Ethernet packet with a match and
2949 packet type 0. Used in CFC load request message */
2950#define PRS_REG_PACKET_REGIONS_TYPE_0 0x40028
2951#define PRS_REG_PACKET_REGIONS_TYPE_1 0x4002c
2952#define PRS_REG_PACKET_REGIONS_TYPE_2 0x40030
2953#define PRS_REG_PACKET_REGIONS_TYPE_3 0x40034
2954#define PRS_REG_PACKET_REGIONS_TYPE_4 0x40038
2955#define PRS_REG_PACKET_REGIONS_TYPE_5 0x4003c
2956#define PRS_REG_PACKET_REGIONS_TYPE_6 0x40040
2957#define PRS_REG_PACKET_REGIONS_TYPE_7 0x40044
2958/* [R 2] debug only: Number of pending requests for CAC on port 0. */
2959#define PRS_REG_PENDING_BRB_CAC0_RQ 0x40174
2960/* [R 2] debug only: Number of pending requests for header parsing. */
2961#define PRS_REG_PENDING_BRB_PRS_RQ 0x40170
2962/* [R 1] Interrupt register #0 read */
2963#define PRS_REG_PRS_INT_STS 0x40188
2964/* [RW 8] Parity mask register #0 read/write */
2965#define PRS_REG_PRS_PRTY_MASK 0x401a4
Eliezer Tamirf1410642008-02-28 11:51:50 -08002966/* [R 8] Parity register #0 read */
2967#define PRS_REG_PRS_PRTY_STS 0x40198
Vladislav Zolotarov4a33bc02011-01-09 02:20:04 +00002968/* [RC 8] Parity register #0 read clear */
2969#define PRS_REG_PRS_PRTY_STS_CLR 0x4019c
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002970/* [RW 8] Context region for pure acknowledge packets. Used in CFC load
2971 request message */
2972#define PRS_REG_PURE_REGIONS 0x40024
2973/* [R 32] debug only: Serial number status lsb 32 bits. '1' indicates this
2974 serail number was released by SDM but cannot be used because a previous
2975 serial number was not released. */
2976#define PRS_REG_SERIAL_NUM_STATUS_LSB 0x40154
2977/* [R 32] debug only: Serial number status msb 32 bits. '1' indicates this
2978 serail number was released by SDM but cannot be used because a previous
2979 serial number was not released. */
2980#define PRS_REG_SERIAL_NUM_STATUS_MSB 0x40158
2981/* [R 4] debug only: SRC current credit. Transaction based. */
2982#define PRS_REG_SRC_CURRENT_CREDIT 0x4016c
Vlad Zolotarov619c5cb2011-06-14 14:33:44 +03002983/* [RW 16] The Ethernet type value for L2 tag 0 */
2984#define PRS_REG_TAG_ETHERTYPE_0 0x401d4
2985/* [RW 4] The length of the info field for L2 tag 0. The length is between
2986 * 2B and 14B; in 2B granularity */
2987#define PRS_REG_TAG_LEN_0 0x4022c
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002988/* [R 8] debug only: TCM current credit. Cycle based. */
2989#define PRS_REG_TCM_CURRENT_CREDIT 0x40160
2990/* [R 8] debug only: TSDM current credit. Transaction based. */
2991#define PRS_REG_TSDM_CURRENT_CREDIT 0x4015c
Dmitry Kravkovf2e08992010-10-06 03:28:26 +00002992#define PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT (0x1<<19)
2993#define PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF (0x1<<20)
2994#define PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN (0x1<<22)
2995#define PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED (0x1<<23)
2996#define PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED (0x1<<24)
2997#define PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR (0x1<<7)
2998#define PXP2_PXP2_INT_STS_CLR_0_REG_WR_PGLUE_EOP_ERROR (0x1<<7)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002999/* [R 6] Debug only: Number of used entries in the data FIFO */
3000#define PXP2_REG_HST_DATA_FIFO_STATUS 0x12047c
3001/* [R 7] Debug only: Number of used entries in the header FIFO */
3002#define PXP2_REG_HST_HEADER_FIFO_STATUS 0x120478
Eilon Greenstein34f80b02008-06-23 20:33:01 -07003003#define PXP2_REG_PGL_ADDR_88_F0 0x120534
3004#define PXP2_REG_PGL_ADDR_8C_F0 0x120538
3005#define PXP2_REG_PGL_ADDR_90_F0 0x12053c
3006#define PXP2_REG_PGL_ADDR_94_F0 0x120540
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003007#define PXP2_REG_PGL_CONTROL0 0x120490
3008#define PXP2_REG_PGL_CONTROL1 0x120514
Eilon Greensteinca003922009-08-12 22:53:28 -07003009#define PXP2_REG_PGL_DEBUG 0x120520
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003010/* [RW 32] third dword data of expansion rom request. this register is
3011 special. reading from it provides a vector outstanding read requests. if
3012 a bit is zero it means that a read request on the corresponding tag did
3013 not finish yet (not all completions have arrived for it) */
3014#define PXP2_REG_PGL_EXP_ROM2 0x120808
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003015/* [RW 32] Inbound interrupt table for CSDM: bits[31:16]-mask;
3016 its[15:0]-address */
3017#define PXP2_REG_PGL_INT_CSDM_0 0x1204f4
3018#define PXP2_REG_PGL_INT_CSDM_1 0x1204f8
3019#define PXP2_REG_PGL_INT_CSDM_2 0x1204fc
3020#define PXP2_REG_PGL_INT_CSDM_3 0x120500
3021#define PXP2_REG_PGL_INT_CSDM_4 0x120504
3022#define PXP2_REG_PGL_INT_CSDM_5 0x120508
3023#define PXP2_REG_PGL_INT_CSDM_6 0x12050c
3024#define PXP2_REG_PGL_INT_CSDM_7 0x120510
3025/* [RW 32] Inbound interrupt table for TSDM: bits[31:16]-mask;
3026 its[15:0]-address */
3027#define PXP2_REG_PGL_INT_TSDM_0 0x120494
3028#define PXP2_REG_PGL_INT_TSDM_1 0x120498
3029#define PXP2_REG_PGL_INT_TSDM_2 0x12049c
3030#define PXP2_REG_PGL_INT_TSDM_3 0x1204a0
3031#define PXP2_REG_PGL_INT_TSDM_4 0x1204a4
3032#define PXP2_REG_PGL_INT_TSDM_5 0x1204a8
3033#define PXP2_REG_PGL_INT_TSDM_6 0x1204ac
3034#define PXP2_REG_PGL_INT_TSDM_7 0x1204b0
3035/* [RW 32] Inbound interrupt table for USDM: bits[31:16]-mask;
3036 its[15:0]-address */
3037#define PXP2_REG_PGL_INT_USDM_0 0x1204b4
3038#define PXP2_REG_PGL_INT_USDM_1 0x1204b8
3039#define PXP2_REG_PGL_INT_USDM_2 0x1204bc
3040#define PXP2_REG_PGL_INT_USDM_3 0x1204c0
3041#define PXP2_REG_PGL_INT_USDM_4 0x1204c4
3042#define PXP2_REG_PGL_INT_USDM_5 0x1204c8
3043#define PXP2_REG_PGL_INT_USDM_6 0x1204cc
3044#define PXP2_REG_PGL_INT_USDM_7 0x1204d0
3045/* [RW 32] Inbound interrupt table for XSDM: bits[31:16]-mask;
3046 its[15:0]-address */
3047#define PXP2_REG_PGL_INT_XSDM_0 0x1204d4
3048#define PXP2_REG_PGL_INT_XSDM_1 0x1204d8
3049#define PXP2_REG_PGL_INT_XSDM_2 0x1204dc
3050#define PXP2_REG_PGL_INT_XSDM_3 0x1204e0
3051#define PXP2_REG_PGL_INT_XSDM_4 0x1204e4
3052#define PXP2_REG_PGL_INT_XSDM_5 0x1204e8
3053#define PXP2_REG_PGL_INT_XSDM_6 0x1204ec
3054#define PXP2_REG_PGL_INT_XSDM_7 0x1204f0
Eilon Greensteinf1ef27e2009-02-12 08:36:23 +00003055/* [RW 3] this field allows one function to pretend being another function
3056 when accessing any BAR mapped resource within the device. the value of
3057 the field is the number of the function that will be accessed
3058 effectively. after software write to this bit it must read it in order to
3059 know that the new value is updated */
3060#define PXP2_REG_PGL_PRETEND_FUNC_F0 0x120674
3061#define PXP2_REG_PGL_PRETEND_FUNC_F1 0x120678
3062#define PXP2_REG_PGL_PRETEND_FUNC_F2 0x12067c
3063#define PXP2_REG_PGL_PRETEND_FUNC_F3 0x120680
3064#define PXP2_REG_PGL_PRETEND_FUNC_F4 0x120684
3065#define PXP2_REG_PGL_PRETEND_FUNC_F5 0x120688
3066#define PXP2_REG_PGL_PRETEND_FUNC_F6 0x12068c
3067#define PXP2_REG_PGL_PRETEND_FUNC_F7 0x120690
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003068/* [R 1] this bit indicates that a read request was blocked because of
3069 bus_master_en was deasserted */
3070#define PXP2_REG_PGL_READ_BLOCKED 0x120568
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003071#define PXP2_REG_PGL_TAGS_LIMIT 0x1205a8
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003072/* [R 18] debug only */
3073#define PXP2_REG_PGL_TXW_CDTS 0x12052c
3074/* [R 1] this bit indicates that a write request was blocked because of
3075 bus_master_en was deasserted */
3076#define PXP2_REG_PGL_WRITE_BLOCKED 0x120564
3077#define PXP2_REG_PSWRQ_BW_ADD1 0x1201c0
3078#define PXP2_REG_PSWRQ_BW_ADD10 0x1201e4
3079#define PXP2_REG_PSWRQ_BW_ADD11 0x1201e8
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003080#define PXP2_REG_PSWRQ_BW_ADD2 0x1201c4
3081#define PXP2_REG_PSWRQ_BW_ADD28 0x120228
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003082#define PXP2_REG_PSWRQ_BW_ADD3 0x1201c8
3083#define PXP2_REG_PSWRQ_BW_ADD6 0x1201d4
3084#define PXP2_REG_PSWRQ_BW_ADD7 0x1201d8
3085#define PXP2_REG_PSWRQ_BW_ADD8 0x1201dc
3086#define PXP2_REG_PSWRQ_BW_ADD9 0x1201e0
3087#define PXP2_REG_PSWRQ_BW_CREDIT 0x12032c
3088#define PXP2_REG_PSWRQ_BW_L1 0x1202b0
3089#define PXP2_REG_PSWRQ_BW_L10 0x1202d4
3090#define PXP2_REG_PSWRQ_BW_L11 0x1202d8
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003091#define PXP2_REG_PSWRQ_BW_L2 0x1202b4
3092#define PXP2_REG_PSWRQ_BW_L28 0x120318
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003093#define PXP2_REG_PSWRQ_BW_L3 0x1202b8
3094#define PXP2_REG_PSWRQ_BW_L6 0x1202c4
3095#define PXP2_REG_PSWRQ_BW_L7 0x1202c8
3096#define PXP2_REG_PSWRQ_BW_L8 0x1202cc
3097#define PXP2_REG_PSWRQ_BW_L9 0x1202d0
3098#define PXP2_REG_PSWRQ_BW_RD 0x120324
3099#define PXP2_REG_PSWRQ_BW_UB1 0x120238
3100#define PXP2_REG_PSWRQ_BW_UB10 0x12025c
3101#define PXP2_REG_PSWRQ_BW_UB11 0x120260
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003102#define PXP2_REG_PSWRQ_BW_UB2 0x12023c
3103#define PXP2_REG_PSWRQ_BW_UB28 0x1202a0
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003104#define PXP2_REG_PSWRQ_BW_UB3 0x120240
3105#define PXP2_REG_PSWRQ_BW_UB6 0x12024c
3106#define PXP2_REG_PSWRQ_BW_UB7 0x120250
3107#define PXP2_REG_PSWRQ_BW_UB8 0x120254
3108#define PXP2_REG_PSWRQ_BW_UB9 0x120258
3109#define PXP2_REG_PSWRQ_BW_WR 0x120328
3110#define PXP2_REG_PSWRQ_CDU0_L2P 0x120000
3111#define PXP2_REG_PSWRQ_QM0_L2P 0x120038
3112#define PXP2_REG_PSWRQ_SRC0_L2P 0x120054
3113#define PXP2_REG_PSWRQ_TM0_L2P 0x12001c
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003114#define PXP2_REG_PSWRQ_TSDM0_L2P 0x1200e0
Eilon Greenstein34f80b02008-06-23 20:33:01 -07003115/* [RW 32] Interrupt mask register #0 read/write */
3116#define PXP2_REG_PXP2_INT_MASK_0 0x120578
3117/* [R 32] Interrupt register #0 read */
3118#define PXP2_REG_PXP2_INT_STS_0 0x12056c
3119#define PXP2_REG_PXP2_INT_STS_1 0x120608
3120/* [RC 32] Interrupt register #0 read clear */
3121#define PXP2_REG_PXP2_INT_STS_CLR_0 0x120570
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003122/* [RW 32] Parity mask register #0 read/write */
3123#define PXP2_REG_PXP2_PRTY_MASK_0 0x120588
3124#define PXP2_REG_PXP2_PRTY_MASK_1 0x120598
Eliezer Tamirf1410642008-02-28 11:51:50 -08003125/* [R 32] Parity register #0 read */
3126#define PXP2_REG_PXP2_PRTY_STS_0 0x12057c
3127#define PXP2_REG_PXP2_PRTY_STS_1 0x12058c
Vladislav Zolotarov4a33bc02011-01-09 02:20:04 +00003128/* [RC 32] Parity register #0 read clear */
3129#define PXP2_REG_PXP2_PRTY_STS_CLR_0 0x120580
3130#define PXP2_REG_PXP2_PRTY_STS_CLR_1 0x120590
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003131/* [R 1] Debug only: The 'almost full' indication from each fifo (gives
3132 indication about backpressure) */
3133#define PXP2_REG_RD_ALMOST_FULL_0 0x120424
3134/* [R 8] Debug only: The blocks counter - number of unused block ids */
3135#define PXP2_REG_RD_BLK_CNT 0x120418
3136/* [RW 8] Debug only: Total number of available blocks in Tetris Buffer.
3137 Must be bigger than 6. Normally should not be changed. */
3138#define PXP2_REG_RD_BLK_NUM_CFG 0x12040c
3139/* [RW 2] CDU byte swapping mode configuration for master read requests */
3140#define PXP2_REG_RD_CDURD_SWAP_MODE 0x120404
3141/* [RW 1] When '1'; inputs to the PSWRD block are ignored */
3142#define PXP2_REG_RD_DISABLE_INPUTS 0x120374
3143/* [R 1] PSWRD internal memories initialization is done */
3144#define PXP2_REG_RD_INIT_DONE 0x120370
3145/* [RW 8] The maximum number of blocks in Tetris Buffer that can be
3146 allocated for vq10 */
3147#define PXP2_REG_RD_MAX_BLKS_VQ10 0x1203a0
3148/* [RW 8] The maximum number of blocks in Tetris Buffer that can be
3149 allocated for vq11 */
3150#define PXP2_REG_RD_MAX_BLKS_VQ11 0x1203a4
3151/* [RW 8] The maximum number of blocks in Tetris Buffer that can be
3152 allocated for vq17 */
3153#define PXP2_REG_RD_MAX_BLKS_VQ17 0x1203bc
3154/* [RW 8] The maximum number of blocks in Tetris Buffer that can be
3155 allocated for vq18 */
3156#define PXP2_REG_RD_MAX_BLKS_VQ18 0x1203c0
3157/* [RW 8] The maximum number of blocks in Tetris Buffer that can be
3158 allocated for vq19 */
3159#define PXP2_REG_RD_MAX_BLKS_VQ19 0x1203c4
3160/* [RW 8] The maximum number of blocks in Tetris Buffer that can be
3161 allocated for vq22 */
3162#define PXP2_REG_RD_MAX_BLKS_VQ22 0x1203d0
3163/* [RW 8] The maximum number of blocks in Tetris Buffer that can be
Eilon Greensteinca003922009-08-12 22:53:28 -07003164 allocated for vq25 */
3165#define PXP2_REG_RD_MAX_BLKS_VQ25 0x1203dc
3166/* [RW 8] The maximum number of blocks in Tetris Buffer that can be
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003167 allocated for vq6 */
3168#define PXP2_REG_RD_MAX_BLKS_VQ6 0x120390
3169/* [RW 8] The maximum number of blocks in Tetris Buffer that can be
3170 allocated for vq9 */
3171#define PXP2_REG_RD_MAX_BLKS_VQ9 0x12039c
3172/* [RW 2] PBF byte swapping mode configuration for master read requests */
3173#define PXP2_REG_RD_PBF_SWAP_MODE 0x1203f4
3174/* [R 1] Debug only: Indication if delivery ports are idle */
3175#define PXP2_REG_RD_PORT_IS_IDLE_0 0x12041c
3176#define PXP2_REG_RD_PORT_IS_IDLE_1 0x120420
3177/* [RW 2] QM byte swapping mode configuration for master read requests */
3178#define PXP2_REG_RD_QM_SWAP_MODE 0x1203f8
3179/* [R 7] Debug only: The SR counter - number of unused sub request ids */
3180#define PXP2_REG_RD_SR_CNT 0x120414
3181/* [RW 2] SRC byte swapping mode configuration for master read requests */
3182#define PXP2_REG_RD_SRC_SWAP_MODE 0x120400
3183/* [RW 7] Debug only: Total number of available PCI read sub-requests. Must
3184 be bigger than 1. Normally should not be changed. */
3185#define PXP2_REG_RD_SR_NUM_CFG 0x120408
3186/* [RW 1] Signals the PSWRD block to start initializing internal memories */
3187#define PXP2_REG_RD_START_INIT 0x12036c
3188/* [RW 2] TM byte swapping mode configuration for master read requests */
3189#define PXP2_REG_RD_TM_SWAP_MODE 0x1203fc
3190/* [RW 10] Bandwidth addition to VQ0 write requests */
3191#define PXP2_REG_RQ_BW_RD_ADD0 0x1201bc
3192/* [RW 10] Bandwidth addition to VQ12 read requests */
3193#define PXP2_REG_RQ_BW_RD_ADD12 0x1201ec
3194/* [RW 10] Bandwidth addition to VQ13 read requests */
3195#define PXP2_REG_RQ_BW_RD_ADD13 0x1201f0
3196/* [RW 10] Bandwidth addition to VQ14 read requests */
3197#define PXP2_REG_RQ_BW_RD_ADD14 0x1201f4
3198/* [RW 10] Bandwidth addition to VQ15 read requests */
3199#define PXP2_REG_RQ_BW_RD_ADD15 0x1201f8
3200/* [RW 10] Bandwidth addition to VQ16 read requests */
3201#define PXP2_REG_RQ_BW_RD_ADD16 0x1201fc
3202/* [RW 10] Bandwidth addition to VQ17 read requests */
3203#define PXP2_REG_RQ_BW_RD_ADD17 0x120200
3204/* [RW 10] Bandwidth addition to VQ18 read requests */
3205#define PXP2_REG_RQ_BW_RD_ADD18 0x120204
3206/* [RW 10] Bandwidth addition to VQ19 read requests */
3207#define PXP2_REG_RQ_BW_RD_ADD19 0x120208
3208/* [RW 10] Bandwidth addition to VQ20 read requests */
3209#define PXP2_REG_RQ_BW_RD_ADD20 0x12020c
3210/* [RW 10] Bandwidth addition to VQ22 read requests */
3211#define PXP2_REG_RQ_BW_RD_ADD22 0x120210
3212/* [RW 10] Bandwidth addition to VQ23 read requests */
3213#define PXP2_REG_RQ_BW_RD_ADD23 0x120214
3214/* [RW 10] Bandwidth addition to VQ24 read requests */
3215#define PXP2_REG_RQ_BW_RD_ADD24 0x120218
3216/* [RW 10] Bandwidth addition to VQ25 read requests */
3217#define PXP2_REG_RQ_BW_RD_ADD25 0x12021c
3218/* [RW 10] Bandwidth addition to VQ26 read requests */
3219#define PXP2_REG_RQ_BW_RD_ADD26 0x120220
3220/* [RW 10] Bandwidth addition to VQ27 read requests */
3221#define PXP2_REG_RQ_BW_RD_ADD27 0x120224
3222/* [RW 10] Bandwidth addition to VQ4 read requests */
3223#define PXP2_REG_RQ_BW_RD_ADD4 0x1201cc
3224/* [RW 10] Bandwidth addition to VQ5 read requests */
3225#define PXP2_REG_RQ_BW_RD_ADD5 0x1201d0
3226/* [RW 10] Bandwidth Typical L for VQ0 Read requests */
3227#define PXP2_REG_RQ_BW_RD_L0 0x1202ac
3228/* [RW 10] Bandwidth Typical L for VQ12 Read requests */
3229#define PXP2_REG_RQ_BW_RD_L12 0x1202dc
3230/* [RW 10] Bandwidth Typical L for VQ13 Read requests */
3231#define PXP2_REG_RQ_BW_RD_L13 0x1202e0
3232/* [RW 10] Bandwidth Typical L for VQ14 Read requests */
3233#define PXP2_REG_RQ_BW_RD_L14 0x1202e4
3234/* [RW 10] Bandwidth Typical L for VQ15 Read requests */
3235#define PXP2_REG_RQ_BW_RD_L15 0x1202e8
3236/* [RW 10] Bandwidth Typical L for VQ16 Read requests */
3237#define PXP2_REG_RQ_BW_RD_L16 0x1202ec
3238/* [RW 10] Bandwidth Typical L for VQ17 Read requests */
3239#define PXP2_REG_RQ_BW_RD_L17 0x1202f0
3240/* [RW 10] Bandwidth Typical L for VQ18 Read requests */
3241#define PXP2_REG_RQ_BW_RD_L18 0x1202f4
3242/* [RW 10] Bandwidth Typical L for VQ19 Read requests */
3243#define PXP2_REG_RQ_BW_RD_L19 0x1202f8
3244/* [RW 10] Bandwidth Typical L for VQ20 Read requests */
3245#define PXP2_REG_RQ_BW_RD_L20 0x1202fc
3246/* [RW 10] Bandwidth Typical L for VQ22 Read requests */
3247#define PXP2_REG_RQ_BW_RD_L22 0x120300
3248/* [RW 10] Bandwidth Typical L for VQ23 Read requests */
3249#define PXP2_REG_RQ_BW_RD_L23 0x120304
3250/* [RW 10] Bandwidth Typical L for VQ24 Read requests */
3251#define PXP2_REG_RQ_BW_RD_L24 0x120308
3252/* [RW 10] Bandwidth Typical L for VQ25 Read requests */
3253#define PXP2_REG_RQ_BW_RD_L25 0x12030c
3254/* [RW 10] Bandwidth Typical L for VQ26 Read requests */
3255#define PXP2_REG_RQ_BW_RD_L26 0x120310
3256/* [RW 10] Bandwidth Typical L for VQ27 Read requests */
3257#define PXP2_REG_RQ_BW_RD_L27 0x120314
3258/* [RW 10] Bandwidth Typical L for VQ4 Read requests */
3259#define PXP2_REG_RQ_BW_RD_L4 0x1202bc
3260/* [RW 10] Bandwidth Typical L for VQ5 Read- currently not used */
3261#define PXP2_REG_RQ_BW_RD_L5 0x1202c0
3262/* [RW 7] Bandwidth upper bound for VQ0 read requests */
3263#define PXP2_REG_RQ_BW_RD_UBOUND0 0x120234
3264/* [RW 7] Bandwidth upper bound for VQ12 read requests */
3265#define PXP2_REG_RQ_BW_RD_UBOUND12 0x120264
3266/* [RW 7] Bandwidth upper bound for VQ13 read requests */
3267#define PXP2_REG_RQ_BW_RD_UBOUND13 0x120268
3268/* [RW 7] Bandwidth upper bound for VQ14 read requests */
3269#define PXP2_REG_RQ_BW_RD_UBOUND14 0x12026c
3270/* [RW 7] Bandwidth upper bound for VQ15 read requests */
3271#define PXP2_REG_RQ_BW_RD_UBOUND15 0x120270
3272/* [RW 7] Bandwidth upper bound for VQ16 read requests */
3273#define PXP2_REG_RQ_BW_RD_UBOUND16 0x120274
3274/* [RW 7] Bandwidth upper bound for VQ17 read requests */
3275#define PXP2_REG_RQ_BW_RD_UBOUND17 0x120278
3276/* [RW 7] Bandwidth upper bound for VQ18 read requests */
3277#define PXP2_REG_RQ_BW_RD_UBOUND18 0x12027c
3278/* [RW 7] Bandwidth upper bound for VQ19 read requests */
3279#define PXP2_REG_RQ_BW_RD_UBOUND19 0x120280
3280/* [RW 7] Bandwidth upper bound for VQ20 read requests */
3281#define PXP2_REG_RQ_BW_RD_UBOUND20 0x120284
3282/* [RW 7] Bandwidth upper bound for VQ22 read requests */
3283#define PXP2_REG_RQ_BW_RD_UBOUND22 0x120288
3284/* [RW 7] Bandwidth upper bound for VQ23 read requests */
3285#define PXP2_REG_RQ_BW_RD_UBOUND23 0x12028c
3286/* [RW 7] Bandwidth upper bound for VQ24 read requests */
3287#define PXP2_REG_RQ_BW_RD_UBOUND24 0x120290
3288/* [RW 7] Bandwidth upper bound for VQ25 read requests */
3289#define PXP2_REG_RQ_BW_RD_UBOUND25 0x120294
3290/* [RW 7] Bandwidth upper bound for VQ26 read requests */
3291#define PXP2_REG_RQ_BW_RD_UBOUND26 0x120298
3292/* [RW 7] Bandwidth upper bound for VQ27 read requests */
3293#define PXP2_REG_RQ_BW_RD_UBOUND27 0x12029c
3294/* [RW 7] Bandwidth upper bound for VQ4 read requests */
3295#define PXP2_REG_RQ_BW_RD_UBOUND4 0x120244
3296/* [RW 7] Bandwidth upper bound for VQ5 read requests */
3297#define PXP2_REG_RQ_BW_RD_UBOUND5 0x120248
3298/* [RW 10] Bandwidth addition to VQ29 write requests */
3299#define PXP2_REG_RQ_BW_WR_ADD29 0x12022c
3300/* [RW 10] Bandwidth addition to VQ30 write requests */
3301#define PXP2_REG_RQ_BW_WR_ADD30 0x120230
3302/* [RW 10] Bandwidth Typical L for VQ29 Write requests */
3303#define PXP2_REG_RQ_BW_WR_L29 0x12031c
3304/* [RW 10] Bandwidth Typical L for VQ30 Write requests */
3305#define PXP2_REG_RQ_BW_WR_L30 0x120320
3306/* [RW 7] Bandwidth upper bound for VQ29 */
3307#define PXP2_REG_RQ_BW_WR_UBOUND29 0x1202a4
3308/* [RW 7] Bandwidth upper bound for VQ30 */
3309#define PXP2_REG_RQ_BW_WR_UBOUND30 0x1202a8
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003310/* [RW 18] external first_mem_addr field in L2P table for CDU module port 0 */
3311#define PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR 0x120008
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003312/* [RW 2] Endian mode for cdu */
3313#define PXP2_REG_RQ_CDU_ENDIAN_M 0x1201a0
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003314#define PXP2_REG_RQ_CDU_FIRST_ILT 0x12061c
3315#define PXP2_REG_RQ_CDU_LAST_ILT 0x120620
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003316/* [RW 3] page size in L2P table for CDU module; -4k; -8k; -16k; -32k; -64k;
3317 -128k */
3318#define PXP2_REG_RQ_CDU_P_SIZE 0x120018
3319/* [R 1] 1' indicates that the requester has finished its internal
3320 configuration */
3321#define PXP2_REG_RQ_CFG_DONE 0x1201b4
3322/* [RW 2] Endian mode for debug */
3323#define PXP2_REG_RQ_DBG_ENDIAN_M 0x1201a4
3324/* [RW 1] When '1'; requests will enter input buffers but wont get out
3325 towards the glue */
3326#define PXP2_REG_RQ_DISABLE_INPUTS 0x120330
Dmitry Kravkovf2e08992010-10-06 03:28:26 +00003327/* [RW 4] Determines alignment of write SRs when a request is split into
3328 * several SRs. 0 - 8B aligned. 1 - 64B aligned. 2 - 128B aligned. 3 - 256B
3329 * aligned. 4 - 512B aligned. */
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003330#define PXP2_REG_RQ_DRAM_ALIGN 0x1205b0
Dmitry Kravkovf2e08992010-10-06 03:28:26 +00003331/* [RW 4] Determines alignment of read SRs when a request is split into
3332 * several SRs. 0 - 8B aligned. 1 - 64B aligned. 2 - 128B aligned. 3 - 256B
3333 * aligned. 4 - 512B aligned. */
3334#define PXP2_REG_RQ_DRAM_ALIGN_RD 0x12092c
3335/* [RW 1] when set the new alignment method (E2) will be applied; when reset
3336 * the original alignment method (E1 E1H) will be applied */
3337#define PXP2_REG_RQ_DRAM_ALIGN_SEL 0x120930
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003338/* [RW 1] If 1 ILT failiue will not result in ELT access; An interrupt will
3339 be asserted */
3340#define PXP2_REG_RQ_ELT_DISABLE 0x12066c
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003341/* [RW 2] Endian mode for hc */
3342#define PXP2_REG_RQ_HC_ENDIAN_M 0x1201a8
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003343/* [RW 1] when '0' ILT logic will work as in A0; otherwise B0; for back
3344 compatibility needs; Note that different registers are used per mode */
3345#define PXP2_REG_RQ_ILT_MODE 0x1205b4
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003346/* [WB 53] Onchip address table */
3347#define PXP2_REG_RQ_ONCHIP_AT 0x122000
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003348/* [WB 53] Onchip address table - B0 */
3349#define PXP2_REG_RQ_ONCHIP_AT_B0 0x128000
Eliezer Tamirf1410642008-02-28 11:51:50 -08003350/* [RW 13] Pending read limiter threshold; in Dwords */
3351#define PXP2_REG_RQ_PDR_LIMIT 0x12033c
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003352/* [RW 2] Endian mode for qm */
3353#define PXP2_REG_RQ_QM_ENDIAN_M 0x120194
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003354#define PXP2_REG_RQ_QM_FIRST_ILT 0x120634
3355#define PXP2_REG_RQ_QM_LAST_ILT 0x120638
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003356/* [RW 3] page size in L2P table for QM module; -4k; -8k; -16k; -32k; -64k;
3357 -128k */
3358#define PXP2_REG_RQ_QM_P_SIZE 0x120050
Eilon Greenstein33471622008-08-13 15:59:08 -07003359/* [RW 1] 1' indicates that the RBC has finished configuring the PSWRQ */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003360#define PXP2_REG_RQ_RBC_DONE 0x1201b0
3361/* [RW 3] Max burst size filed for read requests port 0; 000 - 128B;
3362 001:256B; 010: 512B; 11:1K:100:2K; 01:4K */
3363#define PXP2_REG_RQ_RD_MBS0 0x120160
Eliezer Tamirf1410642008-02-28 11:51:50 -08003364/* [RW 3] Max burst size filed for read requests port 1; 000 - 128B;
3365 001:256B; 010: 512B; 11:1K:100:2K; 01:4K */
3366#define PXP2_REG_RQ_RD_MBS1 0x120168
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003367/* [RW 2] Endian mode for src */
3368#define PXP2_REG_RQ_SRC_ENDIAN_M 0x12019c
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003369#define PXP2_REG_RQ_SRC_FIRST_ILT 0x12063c
3370#define PXP2_REG_RQ_SRC_LAST_ILT 0x120640
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003371/* [RW 3] page size in L2P table for SRC module; -4k; -8k; -16k; -32k; -64k;
3372 -128k */
3373#define PXP2_REG_RQ_SRC_P_SIZE 0x12006c
3374/* [RW 2] Endian mode for tm */
3375#define PXP2_REG_RQ_TM_ENDIAN_M 0x120198
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003376#define PXP2_REG_RQ_TM_FIRST_ILT 0x120644
3377#define PXP2_REG_RQ_TM_LAST_ILT 0x120648
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003378/* [RW 3] page size in L2P table for TM module; -4k; -8k; -16k; -32k; -64k;
3379 -128k */
3380#define PXP2_REG_RQ_TM_P_SIZE 0x120034
3381/* [R 5] Number of entries in the ufifo; his fifo has l2p completions */
3382#define PXP2_REG_RQ_UFIFO_NUM_OF_ENTRY 0x12080c
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003383/* [RW 18] external first_mem_addr field in L2P table for USDM module port 0 */
3384#define PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR 0x120094
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003385/* [R 8] Number of entries occupied by vq 0 in pswrq memory */
3386#define PXP2_REG_RQ_VQ0_ENTRY_CNT 0x120810
3387/* [R 8] Number of entries occupied by vq 10 in pswrq memory */
3388#define PXP2_REG_RQ_VQ10_ENTRY_CNT 0x120818
3389/* [R 8] Number of entries occupied by vq 11 in pswrq memory */
3390#define PXP2_REG_RQ_VQ11_ENTRY_CNT 0x120820
3391/* [R 8] Number of entries occupied by vq 12 in pswrq memory */
3392#define PXP2_REG_RQ_VQ12_ENTRY_CNT 0x120828
3393/* [R 8] Number of entries occupied by vq 13 in pswrq memory */
3394#define PXP2_REG_RQ_VQ13_ENTRY_CNT 0x120830
3395/* [R 8] Number of entries occupied by vq 14 in pswrq memory */
3396#define PXP2_REG_RQ_VQ14_ENTRY_CNT 0x120838
3397/* [R 8] Number of entries occupied by vq 15 in pswrq memory */
3398#define PXP2_REG_RQ_VQ15_ENTRY_CNT 0x120840
3399/* [R 8] Number of entries occupied by vq 16 in pswrq memory */
3400#define PXP2_REG_RQ_VQ16_ENTRY_CNT 0x120848
3401/* [R 8] Number of entries occupied by vq 17 in pswrq memory */
3402#define PXP2_REG_RQ_VQ17_ENTRY_CNT 0x120850
3403/* [R 8] Number of entries occupied by vq 18 in pswrq memory */
3404#define PXP2_REG_RQ_VQ18_ENTRY_CNT 0x120858
3405/* [R 8] Number of entries occupied by vq 19 in pswrq memory */
3406#define PXP2_REG_RQ_VQ19_ENTRY_CNT 0x120860
3407/* [R 8] Number of entries occupied by vq 1 in pswrq memory */
3408#define PXP2_REG_RQ_VQ1_ENTRY_CNT 0x120868
3409/* [R 8] Number of entries occupied by vq 20 in pswrq memory */
3410#define PXP2_REG_RQ_VQ20_ENTRY_CNT 0x120870
3411/* [R 8] Number of entries occupied by vq 21 in pswrq memory */
3412#define PXP2_REG_RQ_VQ21_ENTRY_CNT 0x120878
3413/* [R 8] Number of entries occupied by vq 22 in pswrq memory */
3414#define PXP2_REG_RQ_VQ22_ENTRY_CNT 0x120880
3415/* [R 8] Number of entries occupied by vq 23 in pswrq memory */
3416#define PXP2_REG_RQ_VQ23_ENTRY_CNT 0x120888
3417/* [R 8] Number of entries occupied by vq 24 in pswrq memory */
3418#define PXP2_REG_RQ_VQ24_ENTRY_CNT 0x120890
3419/* [R 8] Number of entries occupied by vq 25 in pswrq memory */
3420#define PXP2_REG_RQ_VQ25_ENTRY_CNT 0x120898
3421/* [R 8] Number of entries occupied by vq 26 in pswrq memory */
3422#define PXP2_REG_RQ_VQ26_ENTRY_CNT 0x1208a0
3423/* [R 8] Number of entries occupied by vq 27 in pswrq memory */
3424#define PXP2_REG_RQ_VQ27_ENTRY_CNT 0x1208a8
3425/* [R 8] Number of entries occupied by vq 28 in pswrq memory */
3426#define PXP2_REG_RQ_VQ28_ENTRY_CNT 0x1208b0
3427/* [R 8] Number of entries occupied by vq 29 in pswrq memory */
3428#define PXP2_REG_RQ_VQ29_ENTRY_CNT 0x1208b8
3429/* [R 8] Number of entries occupied by vq 2 in pswrq memory */
3430#define PXP2_REG_RQ_VQ2_ENTRY_CNT 0x1208c0
3431/* [R 8] Number of entries occupied by vq 30 in pswrq memory */
3432#define PXP2_REG_RQ_VQ30_ENTRY_CNT 0x1208c8
3433/* [R 8] Number of entries occupied by vq 31 in pswrq memory */
3434#define PXP2_REG_RQ_VQ31_ENTRY_CNT 0x1208d0
3435/* [R 8] Number of entries occupied by vq 3 in pswrq memory */
3436#define PXP2_REG_RQ_VQ3_ENTRY_CNT 0x1208d8
3437/* [R 8] Number of entries occupied by vq 4 in pswrq memory */
3438#define PXP2_REG_RQ_VQ4_ENTRY_CNT 0x1208e0
3439/* [R 8] Number of entries occupied by vq 5 in pswrq memory */
3440#define PXP2_REG_RQ_VQ5_ENTRY_CNT 0x1208e8
3441/* [R 8] Number of entries occupied by vq 6 in pswrq memory */
3442#define PXP2_REG_RQ_VQ6_ENTRY_CNT 0x1208f0
3443/* [R 8] Number of entries occupied by vq 7 in pswrq memory */
3444#define PXP2_REG_RQ_VQ7_ENTRY_CNT 0x1208f8
3445/* [R 8] Number of entries occupied by vq 8 in pswrq memory */
3446#define PXP2_REG_RQ_VQ8_ENTRY_CNT 0x120900
3447/* [R 8] Number of entries occupied by vq 9 in pswrq memory */
3448#define PXP2_REG_RQ_VQ9_ENTRY_CNT 0x120908
3449/* [RW 3] Max burst size filed for write requests port 0; 000 - 128B;
3450 001:256B; 010: 512B; */
3451#define PXP2_REG_RQ_WR_MBS0 0x12015c
Eliezer Tamirf1410642008-02-28 11:51:50 -08003452/* [RW 3] Max burst size filed for write requests port 1; 000 - 128B;
3453 001:256B; 010: 512B; */
3454#define PXP2_REG_RQ_WR_MBS1 0x120164
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003455/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
3456 buffer reaches this number has_payload will be asserted */
3457#define PXP2_REG_WR_CDU_MPS 0x1205f0
3458/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
3459 buffer reaches this number has_payload will be asserted */
3460#define PXP2_REG_WR_CSDM_MPS 0x1205d0
3461/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
3462 buffer reaches this number has_payload will be asserted */
3463#define PXP2_REG_WR_DBG_MPS 0x1205e8
3464/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
3465 buffer reaches this number has_payload will be asserted */
3466#define PXP2_REG_WR_DMAE_MPS 0x1205ec
Eilon Greenstein33471622008-08-13 15:59:08 -07003467/* [RW 10] if Number of entries in dmae fifo will be higher than this
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003468 threshold then has_payload indication will be asserted; the default value
3469 should be equal to &gt; write MBS size! */
3470#define PXP2_REG_WR_DMAE_TH 0x120368
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003471/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
3472 buffer reaches this number has_payload will be asserted */
3473#define PXP2_REG_WR_HC_MPS 0x1205c8
3474/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
3475 buffer reaches this number has_payload will be asserted */
3476#define PXP2_REG_WR_QM_MPS 0x1205dc
3477/* [RW 1] 0 - working in A0 mode; - working in B0 mode */
3478#define PXP2_REG_WR_REV_MODE 0x120670
3479/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
3480 buffer reaches this number has_payload will be asserted */
3481#define PXP2_REG_WR_SRC_MPS 0x1205e4
3482/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
3483 buffer reaches this number has_payload will be asserted */
3484#define PXP2_REG_WR_TM_MPS 0x1205e0
3485/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
3486 buffer reaches this number has_payload will be asserted */
3487#define PXP2_REG_WR_TSDM_MPS 0x1205d4
Eilon Greenstein33471622008-08-13 15:59:08 -07003488/* [RW 10] if Number of entries in usdmdp fifo will be higher than this
Eliezer Tamirf1410642008-02-28 11:51:50 -08003489 threshold then has_payload indication will be asserted; the default value
3490 should be equal to &gt; write MBS size! */
3491#define PXP2_REG_WR_USDMDP_TH 0x120348
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003492/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
3493 buffer reaches this number has_payload will be asserted */
3494#define PXP2_REG_WR_USDM_MPS 0x1205cc
3495/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
3496 buffer reaches this number has_payload will be asserted */
3497#define PXP2_REG_WR_XSDM_MPS 0x1205d8
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003498/* [R 1] debug only: Indication if PSWHST arbiter is idle */
3499#define PXP_REG_HST_ARB_IS_IDLE 0x103004
3500/* [R 8] debug only: A bit mask for all PSWHST arbiter clients. '1' means
3501 this client is waiting for the arbiter. */
3502#define PXP_REG_HST_CLIENTS_WAITING_TO_ARB 0x103008
Vladislav Zolotarov72fd0712010-04-19 01:13:12 +00003503/* [RW 1] When 1; doorbells are discarded and not passed to doorbell queue
3504 block. Should be used for close the gates. */
3505#define PXP_REG_HST_DISCARD_DOORBELLS 0x1030a4
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003506/* [R 1] debug only: '1' means this PSWHST is discarding doorbells. This bit
Lucas De Marchi25985ed2011-03-30 22:57:33 -03003507 should update according to 'hst_discard_doorbells' register when the state
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003508 machine is idle */
3509#define PXP_REG_HST_DISCARD_DOORBELLS_STATUS 0x1030a0
Vladislav Zolotarov72fd0712010-04-19 01:13:12 +00003510/* [RW 1] When 1; new internal writes arriving to the block are discarded.
3511 Should be used for close the gates. */
3512#define PXP_REG_HST_DISCARD_INTERNAL_WRITES 0x1030a8
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003513/* [R 6] debug only: A bit mask for all PSWHST internal write clients. '1'
3514 means this PSWHST is discarding inputs from this client. Each bit should
Lucas De Marchi25985ed2011-03-30 22:57:33 -03003515 update according to 'hst_discard_internal_writes' register when the state
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003516 machine is idle. */
3517#define PXP_REG_HST_DISCARD_INTERNAL_WRITES_STATUS 0x10309c
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003518/* [WB 160] Used for initialization of the inbound interrupts memory */
3519#define PXP_REG_HST_INBOUND_INT 0x103800
3520/* [RW 32] Interrupt mask register #0 read/write */
3521#define PXP_REG_PXP_INT_MASK_0 0x103074
3522#define PXP_REG_PXP_INT_MASK_1 0x103084
3523/* [R 32] Interrupt register #0 read */
3524#define PXP_REG_PXP_INT_STS_0 0x103068
3525#define PXP_REG_PXP_INT_STS_1 0x103078
3526/* [RC 32] Interrupt register #0 read clear */
3527#define PXP_REG_PXP_INT_STS_CLR_0 0x10306c
Dmitry Kravkovf2e08992010-10-06 03:28:26 +00003528#define PXP_REG_PXP_INT_STS_CLR_1 0x10307c
3529/* [RW 27] Parity mask register #0 read/write */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003530#define PXP_REG_PXP_PRTY_MASK 0x103094
Eliezer Tamirf1410642008-02-28 11:51:50 -08003531/* [R 26] Parity register #0 read */
3532#define PXP_REG_PXP_PRTY_STS 0x103088
Vladislav Zolotarov4a33bc02011-01-09 02:20:04 +00003533/* [RC 27] Parity register #0 read clear */
3534#define PXP_REG_PXP_PRTY_STS_CLR 0x10308c
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003535/* [RW 4] The activity counter initial increment value sent in the load
3536 request */
3537#define QM_REG_ACTCTRINITVAL_0 0x168040
3538#define QM_REG_ACTCTRINITVAL_1 0x168044
3539#define QM_REG_ACTCTRINITVAL_2 0x168048
3540#define QM_REG_ACTCTRINITVAL_3 0x16804c
3541/* [RW 32] The base logical address (in bytes) of each physical queue. The
3542 index I represents the physical queue number. The 12 lsbs are ignore and
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003543 considered zero so practically there are only 20 bits in this register;
3544 queues 63-0 */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003545#define QM_REG_BASEADDR 0x168900
Eilon Greenstein8d9c5f32009-02-15 23:24:08 -08003546/* [RW 32] The base logical address (in bytes) of each physical queue. The
3547 index I represents the physical queue number. The 12 lsbs are ignore and
3548 considered zero so practically there are only 20 bits in this register;
3549 queues 127-64 */
3550#define QM_REG_BASEADDR_EXT_A 0x16e100
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003551/* [RW 16] The byte credit cost for each task. This value is for both ports */
3552#define QM_REG_BYTECRDCOST 0x168234
3553/* [RW 16] The initial byte credit value for both ports. */
3554#define QM_REG_BYTECRDINITVAL 0x168238
3555/* [RW 32] A bit per physical queue. If the bit is cleared then the physical
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003556 queue uses port 0 else it uses port 1; queues 31-0 */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003557#define QM_REG_BYTECRDPORT_LSB 0x168228
3558/* [RW 32] A bit per physical queue. If the bit is cleared then the physical
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003559 queue uses port 0 else it uses port 1; queues 95-64 */
3560#define QM_REG_BYTECRDPORT_LSB_EXT_A 0x16e520
3561/* [RW 32] A bit per physical queue. If the bit is cleared then the physical
3562 queue uses port 0 else it uses port 1; queues 63-32 */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003563#define QM_REG_BYTECRDPORT_MSB 0x168224
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003564/* [RW 32] A bit per physical queue. If the bit is cleared then the physical
3565 queue uses port 0 else it uses port 1; queues 127-96 */
3566#define QM_REG_BYTECRDPORT_MSB_EXT_A 0x16e51c
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003567/* [RW 16] The byte credit value that if above the QM is considered almost
3568 full */
3569#define QM_REG_BYTECREDITAFULLTHR 0x168094
3570/* [RW 4] The initial credit for interface */
3571#define QM_REG_CMINITCRD_0 0x1680cc
Vlad Zolotarov619c5cb2011-06-14 14:33:44 +03003572#define QM_REG_BYTECRDCMDQ_0 0x16e6e8
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003573#define QM_REG_CMINITCRD_1 0x1680d0
3574#define QM_REG_CMINITCRD_2 0x1680d4
3575#define QM_REG_CMINITCRD_3 0x1680d8
3576#define QM_REG_CMINITCRD_4 0x1680dc
3577#define QM_REG_CMINITCRD_5 0x1680e0
3578#define QM_REG_CMINITCRD_6 0x1680e4
3579#define QM_REG_CMINITCRD_7 0x1680e8
3580/* [RW 8] A mask bit per CM interface. If this bit is 0 then this interface
3581 is masked */
3582#define QM_REG_CMINTEN 0x1680ec
3583/* [RW 12] A bit vector which indicates which one of the queues are tied to
3584 interface 0 */
3585#define QM_REG_CMINTVOQMASK_0 0x1681f4
3586#define QM_REG_CMINTVOQMASK_1 0x1681f8
3587#define QM_REG_CMINTVOQMASK_2 0x1681fc
3588#define QM_REG_CMINTVOQMASK_3 0x168200
3589#define QM_REG_CMINTVOQMASK_4 0x168204
3590#define QM_REG_CMINTVOQMASK_5 0x168208
3591#define QM_REG_CMINTVOQMASK_6 0x16820c
3592#define QM_REG_CMINTVOQMASK_7 0x168210
3593/* [RW 20] The number of connections divided by 16 which dictates the size
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003594 of each queue which belongs to even function number. */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003595#define QM_REG_CONNNUM_0 0x168020
3596/* [R 6] Keep the fill level of the fifo from write client 4 */
3597#define QM_REG_CQM_WRC_FIFOLVL 0x168018
3598/* [RW 8] The context regions sent in the CFC load request */
3599#define QM_REG_CTXREG_0 0x168030
3600#define QM_REG_CTXREG_1 0x168034
3601#define QM_REG_CTXREG_2 0x168038
3602#define QM_REG_CTXREG_3 0x16803c
3603/* [RW 12] The VOQ mask used to select the VOQs which needs to be full for
3604 bypass enable */
3605#define QM_REG_ENBYPVOQMASK 0x16823c
3606/* [RW 32] A bit mask per each physical queue. If a bit is set then the
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003607 physical queue uses the byte credit; queues 31-0 */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003608#define QM_REG_ENBYTECRD_LSB 0x168220
3609/* [RW 32] A bit mask per each physical queue. If a bit is set then the
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003610 physical queue uses the byte credit; queues 95-64 */
3611#define QM_REG_ENBYTECRD_LSB_EXT_A 0x16e518
3612/* [RW 32] A bit mask per each physical queue. If a bit is set then the
3613 physical queue uses the byte credit; queues 63-32 */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003614#define QM_REG_ENBYTECRD_MSB 0x16821c
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003615/* [RW 32] A bit mask per each physical queue. If a bit is set then the
3616 physical queue uses the byte credit; queues 127-96 */
3617#define QM_REG_ENBYTECRD_MSB_EXT_A 0x16e514
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003618/* [RW 4] If cleared then the secondary interface will not be served by the
3619 RR arbiter */
3620#define QM_REG_ENSEC 0x1680f0
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003621/* [RW 32] NA */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003622#define QM_REG_FUNCNUMSEL_LSB 0x168230
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003623/* [RW 32] NA */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003624#define QM_REG_FUNCNUMSEL_MSB 0x16822c
3625/* [RW 32] A mask register to mask the Almost empty signals which will not
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003626 be use for the almost empty indication to the HW block; queues 31:0 */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003627#define QM_REG_HWAEMPTYMASK_LSB 0x168218
3628/* [RW 32] A mask register to mask the Almost empty signals which will not
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003629 be use for the almost empty indication to the HW block; queues 95-64 */
3630#define QM_REG_HWAEMPTYMASK_LSB_EXT_A 0x16e510
3631/* [RW 32] A mask register to mask the Almost empty signals which will not
3632 be use for the almost empty indication to the HW block; queues 63:32 */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003633#define QM_REG_HWAEMPTYMASK_MSB 0x168214
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003634/* [RW 32] A mask register to mask the Almost empty signals which will not
3635 be use for the almost empty indication to the HW block; queues 127-96 */
3636#define QM_REG_HWAEMPTYMASK_MSB_EXT_A 0x16e50c
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003637/* [RW 4] The number of outstanding request to CFC */
3638#define QM_REG_OUTLDREQ 0x168804
3639/* [RC 1] A flag to indicate that overflow error occurred in one of the
3640 queues. */
3641#define QM_REG_OVFERROR 0x16805c
André Goddard Rosaaf901ca2009-11-14 13:09:05 -02003642/* [RC 7] the Q where the overflow occurs */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003643#define QM_REG_OVFQNUM 0x168058
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003644/* [R 16] Pause state for physical queues 15-0 */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003645#define QM_REG_PAUSESTATE0 0x168410
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003646/* [R 16] Pause state for physical queues 31-16 */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003647#define QM_REG_PAUSESTATE1 0x168414
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003648/* [R 16] Pause state for physical queues 47-32 */
3649#define QM_REG_PAUSESTATE2 0x16e684
3650/* [R 16] Pause state for physical queues 63-48 */
3651#define QM_REG_PAUSESTATE3 0x16e688
3652/* [R 16] Pause state for physical queues 79-64 */
3653#define QM_REG_PAUSESTATE4 0x16e68c
3654/* [R 16] Pause state for physical queues 95-80 */
3655#define QM_REG_PAUSESTATE5 0x16e690
3656/* [R 16] Pause state for physical queues 111-96 */
3657#define QM_REG_PAUSESTATE6 0x16e694
3658/* [R 16] Pause state for physical queues 127-112 */
3659#define QM_REG_PAUSESTATE7 0x16e698
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003660/* [RW 2] The PCI attributes field used in the PCI request. */
3661#define QM_REG_PCIREQAT 0x168054
Dmitry Kravkovf2e08992010-10-06 03:28:26 +00003662#define QM_REG_PF_EN 0x16e70c
Vlad Zolotarov619c5cb2011-06-14 14:33:44 +03003663/* [R 24] The number of tasks stored in the QM for the PF. only even
3664 * functions are valid in E2 (odd I registers will be hard wired to 0) */
3665#define QM_REG_PF_USG_CNT_0 0x16e040
3666/* [R 16] NOT USED */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003667#define QM_REG_PORT0BYTECRD 0x168300
3668/* [R 16] The byte credit of port 1 */
3669#define QM_REG_PORT1BYTECRD 0x168304
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003670/* [RW 3] pci function number of queues 15-0 */
3671#define QM_REG_PQ2PCIFUNC_0 0x16e6bc
3672#define QM_REG_PQ2PCIFUNC_1 0x16e6c0
3673#define QM_REG_PQ2PCIFUNC_2 0x16e6c4
3674#define QM_REG_PQ2PCIFUNC_3 0x16e6c8
3675#define QM_REG_PQ2PCIFUNC_4 0x16e6cc
3676#define QM_REG_PQ2PCIFUNC_5 0x16e6d0
3677#define QM_REG_PQ2PCIFUNC_6 0x16e6d4
3678#define QM_REG_PQ2PCIFUNC_7 0x16e6d8
3679/* [WB 54] Pointer Table Memory for queues 63-0; The mapping is as follow:
3680 ptrtbl[53:30] read pointer; ptrtbl[29:6] write pointer; ptrtbl[5:4] read
3681 bank0; ptrtbl[3:2] read bank 1; ptrtbl[1:0] write bank; */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003682#define QM_REG_PTRTBL 0x168a00
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003683/* [WB 54] Pointer Table Memory for queues 127-64; The mapping is as follow:
3684 ptrtbl[53:30] read pointer; ptrtbl[29:6] write pointer; ptrtbl[5:4] read
3685 bank0; ptrtbl[3:2] read bank 1; ptrtbl[1:0] write bank; */
3686#define QM_REG_PTRTBL_EXT_A 0x16e200
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003687/* [RW 2] Interrupt mask register #0 read/write */
3688#define QM_REG_QM_INT_MASK 0x168444
3689/* [R 2] Interrupt register #0 read */
3690#define QM_REG_QM_INT_STS 0x168438
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003691/* [RW 12] Parity mask register #0 read/write */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003692#define QM_REG_QM_PRTY_MASK 0x168454
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003693/* [R 12] Parity register #0 read */
Eliezer Tamirf1410642008-02-28 11:51:50 -08003694#define QM_REG_QM_PRTY_STS 0x168448
Vladislav Zolotarov4a33bc02011-01-09 02:20:04 +00003695/* [RC 12] Parity register #0 read clear */
3696#define QM_REG_QM_PRTY_STS_CLR 0x16844c
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003697/* [R 32] Current queues in pipeline: Queues from 32 to 63 */
3698#define QM_REG_QSTATUS_HIGH 0x16802c
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003699/* [R 32] Current queues in pipeline: Queues from 96 to 127 */
3700#define QM_REG_QSTATUS_HIGH_EXT_A 0x16e408
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003701/* [R 32] Current queues in pipeline: Queues from 0 to 31 */
3702#define QM_REG_QSTATUS_LOW 0x168028
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003703/* [R 32] Current queues in pipeline: Queues from 64 to 95 */
3704#define QM_REG_QSTATUS_LOW_EXT_A 0x16e404
3705/* [R 24] The number of tasks queued for each queue; queues 63-0 */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003706#define QM_REG_QTASKCTR_0 0x168308
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003707/* [R 24] The number of tasks queued for each queue; queues 127-64 */
3708#define QM_REG_QTASKCTR_EXT_A_0 0x16e584
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003709/* [RW 4] Queue tied to VOQ */
3710#define QM_REG_QVOQIDX_0 0x1680f4
3711#define QM_REG_QVOQIDX_10 0x16811c
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003712#define QM_REG_QVOQIDX_100 0x16e49c
3713#define QM_REG_QVOQIDX_101 0x16e4a0
3714#define QM_REG_QVOQIDX_102 0x16e4a4
3715#define QM_REG_QVOQIDX_103 0x16e4a8
3716#define QM_REG_QVOQIDX_104 0x16e4ac
3717#define QM_REG_QVOQIDX_105 0x16e4b0
3718#define QM_REG_QVOQIDX_106 0x16e4b4
3719#define QM_REG_QVOQIDX_107 0x16e4b8
3720#define QM_REG_QVOQIDX_108 0x16e4bc
3721#define QM_REG_QVOQIDX_109 0x16e4c0
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003722#define QM_REG_QVOQIDX_11 0x168120
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003723#define QM_REG_QVOQIDX_110 0x16e4c4
3724#define QM_REG_QVOQIDX_111 0x16e4c8
3725#define QM_REG_QVOQIDX_112 0x16e4cc
3726#define QM_REG_QVOQIDX_113 0x16e4d0
3727#define QM_REG_QVOQIDX_114 0x16e4d4
3728#define QM_REG_QVOQIDX_115 0x16e4d8
3729#define QM_REG_QVOQIDX_116 0x16e4dc
3730#define QM_REG_QVOQIDX_117 0x16e4e0
3731#define QM_REG_QVOQIDX_118 0x16e4e4
3732#define QM_REG_QVOQIDX_119 0x16e4e8
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003733#define QM_REG_QVOQIDX_12 0x168124
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003734#define QM_REG_QVOQIDX_120 0x16e4ec
3735#define QM_REG_QVOQIDX_121 0x16e4f0
3736#define QM_REG_QVOQIDX_122 0x16e4f4
3737#define QM_REG_QVOQIDX_123 0x16e4f8
3738#define QM_REG_QVOQIDX_124 0x16e4fc
3739#define QM_REG_QVOQIDX_125 0x16e500
3740#define QM_REG_QVOQIDX_126 0x16e504
3741#define QM_REG_QVOQIDX_127 0x16e508
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003742#define QM_REG_QVOQIDX_13 0x168128
3743#define QM_REG_QVOQIDX_14 0x16812c
3744#define QM_REG_QVOQIDX_15 0x168130
3745#define QM_REG_QVOQIDX_16 0x168134
3746#define QM_REG_QVOQIDX_17 0x168138
3747#define QM_REG_QVOQIDX_21 0x168148
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003748#define QM_REG_QVOQIDX_22 0x16814c
3749#define QM_REG_QVOQIDX_23 0x168150
3750#define QM_REG_QVOQIDX_24 0x168154
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003751#define QM_REG_QVOQIDX_25 0x168158
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003752#define QM_REG_QVOQIDX_26 0x16815c
3753#define QM_REG_QVOQIDX_27 0x168160
3754#define QM_REG_QVOQIDX_28 0x168164
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003755#define QM_REG_QVOQIDX_29 0x168168
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003756#define QM_REG_QVOQIDX_30 0x16816c
3757#define QM_REG_QVOQIDX_31 0x168170
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003758#define QM_REG_QVOQIDX_32 0x168174
3759#define QM_REG_QVOQIDX_33 0x168178
3760#define QM_REG_QVOQIDX_34 0x16817c
3761#define QM_REG_QVOQIDX_35 0x168180
3762#define QM_REG_QVOQIDX_36 0x168184
3763#define QM_REG_QVOQIDX_37 0x168188
3764#define QM_REG_QVOQIDX_38 0x16818c
3765#define QM_REG_QVOQIDX_39 0x168190
3766#define QM_REG_QVOQIDX_40 0x168194
3767#define QM_REG_QVOQIDX_41 0x168198
3768#define QM_REG_QVOQIDX_42 0x16819c
3769#define QM_REG_QVOQIDX_43 0x1681a0
3770#define QM_REG_QVOQIDX_44 0x1681a4
3771#define QM_REG_QVOQIDX_45 0x1681a8
3772#define QM_REG_QVOQIDX_46 0x1681ac
3773#define QM_REG_QVOQIDX_47 0x1681b0
3774#define QM_REG_QVOQIDX_48 0x1681b4
3775#define QM_REG_QVOQIDX_49 0x1681b8
3776#define QM_REG_QVOQIDX_5 0x168108
3777#define QM_REG_QVOQIDX_50 0x1681bc
3778#define QM_REG_QVOQIDX_51 0x1681c0
3779#define QM_REG_QVOQIDX_52 0x1681c4
3780#define QM_REG_QVOQIDX_53 0x1681c8
3781#define QM_REG_QVOQIDX_54 0x1681cc
3782#define QM_REG_QVOQIDX_55 0x1681d0
3783#define QM_REG_QVOQIDX_56 0x1681d4
3784#define QM_REG_QVOQIDX_57 0x1681d8
3785#define QM_REG_QVOQIDX_58 0x1681dc
3786#define QM_REG_QVOQIDX_59 0x1681e0
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003787#define QM_REG_QVOQIDX_6 0x16810c
3788#define QM_REG_QVOQIDX_60 0x1681e4
3789#define QM_REG_QVOQIDX_61 0x1681e8
3790#define QM_REG_QVOQIDX_62 0x1681ec
3791#define QM_REG_QVOQIDX_63 0x1681f0
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003792#define QM_REG_QVOQIDX_64 0x16e40c
3793#define QM_REG_QVOQIDX_65 0x16e410
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003794#define QM_REG_QVOQIDX_69 0x16e420
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003795#define QM_REG_QVOQIDX_7 0x168110
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003796#define QM_REG_QVOQIDX_70 0x16e424
3797#define QM_REG_QVOQIDX_71 0x16e428
3798#define QM_REG_QVOQIDX_72 0x16e42c
3799#define QM_REG_QVOQIDX_73 0x16e430
3800#define QM_REG_QVOQIDX_74 0x16e434
3801#define QM_REG_QVOQIDX_75 0x16e438
3802#define QM_REG_QVOQIDX_76 0x16e43c
3803#define QM_REG_QVOQIDX_77 0x16e440
3804#define QM_REG_QVOQIDX_78 0x16e444
3805#define QM_REG_QVOQIDX_79 0x16e448
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003806#define QM_REG_QVOQIDX_8 0x168114
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003807#define QM_REG_QVOQIDX_80 0x16e44c
3808#define QM_REG_QVOQIDX_81 0x16e450
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003809#define QM_REG_QVOQIDX_85 0x16e460
3810#define QM_REG_QVOQIDX_86 0x16e464
3811#define QM_REG_QVOQIDX_87 0x16e468
3812#define QM_REG_QVOQIDX_88 0x16e46c
3813#define QM_REG_QVOQIDX_89 0x16e470
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003814#define QM_REG_QVOQIDX_9 0x168118
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003815#define QM_REG_QVOQIDX_90 0x16e474
3816#define QM_REG_QVOQIDX_91 0x16e478
3817#define QM_REG_QVOQIDX_92 0x16e47c
3818#define QM_REG_QVOQIDX_93 0x16e480
3819#define QM_REG_QVOQIDX_94 0x16e484
3820#define QM_REG_QVOQIDX_95 0x16e488
3821#define QM_REG_QVOQIDX_96 0x16e48c
3822#define QM_REG_QVOQIDX_97 0x16e490
3823#define QM_REG_QVOQIDX_98 0x16e494
3824#define QM_REG_QVOQIDX_99 0x16e498
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003825/* [RW 1] Initialization bit command */
3826#define QM_REG_SOFT_RESET 0x168428
3827/* [RW 8] The credit cost per every task in the QM. A value per each VOQ */
3828#define QM_REG_TASKCRDCOST_0 0x16809c
3829#define QM_REG_TASKCRDCOST_1 0x1680a0
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003830#define QM_REG_TASKCRDCOST_2 0x1680a4
3831#define QM_REG_TASKCRDCOST_4 0x1680ac
3832#define QM_REG_TASKCRDCOST_5 0x1680b0
3833/* [R 6] Keep the fill level of the fifo from write client 3 */
3834#define QM_REG_TQM_WRC_FIFOLVL 0x168010
3835/* [R 6] Keep the fill level of the fifo from write client 2 */
3836#define QM_REG_UQM_WRC_FIFOLVL 0x168008
3837/* [RC 32] Credit update error register */
3838#define QM_REG_VOQCRDERRREG 0x168408
3839/* [R 16] The credit value for each VOQ */
3840#define QM_REG_VOQCREDIT_0 0x1682d0
3841#define QM_REG_VOQCREDIT_1 0x1682d4
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003842#define QM_REG_VOQCREDIT_4 0x1682e0
3843/* [RW 16] The credit value that if above the QM is considered almost full */
3844#define QM_REG_VOQCREDITAFULLTHR 0x168090
3845/* [RW 16] The init and maximum credit for each VoQ */
3846#define QM_REG_VOQINITCREDIT_0 0x168060
3847#define QM_REG_VOQINITCREDIT_1 0x168064
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003848#define QM_REG_VOQINITCREDIT_2 0x168068
3849#define QM_REG_VOQINITCREDIT_4 0x168070
3850#define QM_REG_VOQINITCREDIT_5 0x168074
3851/* [RW 1] The port of which VOQ belongs */
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003852#define QM_REG_VOQPORT_0 0x1682a0
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003853#define QM_REG_VOQPORT_1 0x1682a4
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003854#define QM_REG_VOQPORT_2 0x1682a8
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003855/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003856#define QM_REG_VOQQMASK_0_LSB 0x168240
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003857/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
3858#define QM_REG_VOQQMASK_0_LSB_EXT_A 0x16e524
3859/* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003860#define QM_REG_VOQQMASK_0_MSB 0x168244
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003861/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
3862#define QM_REG_VOQQMASK_0_MSB_EXT_A 0x16e528
3863/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
3864#define QM_REG_VOQQMASK_10_LSB 0x168290
3865/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
3866#define QM_REG_VOQQMASK_10_LSB_EXT_A 0x16e574
3867/* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
3868#define QM_REG_VOQQMASK_10_MSB 0x168294
3869/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
3870#define QM_REG_VOQQMASK_10_MSB_EXT_A 0x16e578
3871/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
3872#define QM_REG_VOQQMASK_11_LSB 0x168298
3873/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
3874#define QM_REG_VOQQMASK_11_LSB_EXT_A 0x16e57c
3875/* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
3876#define QM_REG_VOQQMASK_11_MSB 0x16829c
3877/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
3878#define QM_REG_VOQQMASK_11_MSB_EXT_A 0x16e580
3879/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
3880#define QM_REG_VOQQMASK_1_LSB 0x168248
3881/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
3882#define QM_REG_VOQQMASK_1_LSB_EXT_A 0x16e52c
3883/* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003884#define QM_REG_VOQQMASK_1_MSB 0x16824c
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003885/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
3886#define QM_REG_VOQQMASK_1_MSB_EXT_A 0x16e530
3887/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003888#define QM_REG_VOQQMASK_2_LSB 0x168250
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003889/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
3890#define QM_REG_VOQQMASK_2_LSB_EXT_A 0x16e534
3891/* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003892#define QM_REG_VOQQMASK_2_MSB 0x168254
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003893/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
3894#define QM_REG_VOQQMASK_2_MSB_EXT_A 0x16e538
3895/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003896#define QM_REG_VOQQMASK_3_LSB 0x168258
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003897/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
3898#define QM_REG_VOQQMASK_3_LSB_EXT_A 0x16e53c
3899/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
3900#define QM_REG_VOQQMASK_3_MSB_EXT_A 0x16e540
3901/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003902#define QM_REG_VOQQMASK_4_LSB 0x168260
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003903/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
3904#define QM_REG_VOQQMASK_4_LSB_EXT_A 0x16e544
3905/* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003906#define QM_REG_VOQQMASK_4_MSB 0x168264
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003907/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
3908#define QM_REG_VOQQMASK_4_MSB_EXT_A 0x16e548
3909/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003910#define QM_REG_VOQQMASK_5_LSB 0x168268
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003911/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
3912#define QM_REG_VOQQMASK_5_LSB_EXT_A 0x16e54c
3913/* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003914#define QM_REG_VOQQMASK_5_MSB 0x16826c
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003915/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
3916#define QM_REG_VOQQMASK_5_MSB_EXT_A 0x16e550
3917/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003918#define QM_REG_VOQQMASK_6_LSB 0x168270
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003919/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
3920#define QM_REG_VOQQMASK_6_LSB_EXT_A 0x16e554
3921/* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003922#define QM_REG_VOQQMASK_6_MSB 0x168274
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003923/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
3924#define QM_REG_VOQQMASK_6_MSB_EXT_A 0x16e558
3925/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003926#define QM_REG_VOQQMASK_7_LSB 0x168278
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003927/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
3928#define QM_REG_VOQQMASK_7_LSB_EXT_A 0x16e55c
3929/* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003930#define QM_REG_VOQQMASK_7_MSB 0x16827c
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003931/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
3932#define QM_REG_VOQQMASK_7_MSB_EXT_A 0x16e560
3933/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003934#define QM_REG_VOQQMASK_8_LSB 0x168280
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003935/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
3936#define QM_REG_VOQQMASK_8_LSB_EXT_A 0x16e564
3937/* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003938#define QM_REG_VOQQMASK_8_MSB 0x168284
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003939/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
3940#define QM_REG_VOQQMASK_8_MSB_EXT_A 0x16e568
3941/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003942#define QM_REG_VOQQMASK_9_LSB 0x168288
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003943/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
3944#define QM_REG_VOQQMASK_9_LSB_EXT_A 0x16e56c
3945/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
3946#define QM_REG_VOQQMASK_9_MSB_EXT_A 0x16e570
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003947/* [RW 32] Wrr weights */
3948#define QM_REG_WRRWEIGHTS_0 0x16880c
3949#define QM_REG_WRRWEIGHTS_1 0x168810
3950#define QM_REG_WRRWEIGHTS_10 0x168814
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003951#define QM_REG_WRRWEIGHTS_11 0x168818
3952#define QM_REG_WRRWEIGHTS_12 0x16881c
3953#define QM_REG_WRRWEIGHTS_13 0x168820
3954#define QM_REG_WRRWEIGHTS_14 0x168824
3955#define QM_REG_WRRWEIGHTS_15 0x168828
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003956#define QM_REG_WRRWEIGHTS_16 0x16e000
3957#define QM_REG_WRRWEIGHTS_17 0x16e004
3958#define QM_REG_WRRWEIGHTS_18 0x16e008
3959#define QM_REG_WRRWEIGHTS_19 0x16e00c
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003960#define QM_REG_WRRWEIGHTS_2 0x16882c
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003961#define QM_REG_WRRWEIGHTS_20 0x16e010
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003962#define QM_REG_WRRWEIGHTS_21 0x16e014
3963#define QM_REG_WRRWEIGHTS_22 0x16e018
3964#define QM_REG_WRRWEIGHTS_23 0x16e01c
3965#define QM_REG_WRRWEIGHTS_24 0x16e020
3966#define QM_REG_WRRWEIGHTS_25 0x16e024
3967#define QM_REG_WRRWEIGHTS_26 0x16e028
3968#define QM_REG_WRRWEIGHTS_27 0x16e02c
3969#define QM_REG_WRRWEIGHTS_28 0x16e030
3970#define QM_REG_WRRWEIGHTS_29 0x16e034
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003971#define QM_REG_WRRWEIGHTS_3 0x168830
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003972#define QM_REG_WRRWEIGHTS_30 0x16e038
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003973#define QM_REG_WRRWEIGHTS_31 0x16e03c
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003974#define QM_REG_WRRWEIGHTS_4 0x168834
3975#define QM_REG_WRRWEIGHTS_5 0x168838
3976#define QM_REG_WRRWEIGHTS_6 0x16883c
3977#define QM_REG_WRRWEIGHTS_7 0x168840
3978#define QM_REG_WRRWEIGHTS_8 0x168844
3979#define QM_REG_WRRWEIGHTS_9 0x168848
3980/* [R 6] Keep the fill level of the fifo from write client 1 */
3981#define QM_REG_XQM_WRC_FIFOLVL 0x168000
Vladislav Zolotarov4a33bc02011-01-09 02:20:04 +00003982/* [W 1] reset to parity interrupt */
3983#define SEM_FAST_REG_PARITY_RST 0x18840
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003984#define SRC_REG_COUNTFREE0 0x40500
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003985/* [RW 1] If clr the searcher is compatible to E1 A0 - support only two
3986 ports. If set the searcher support 8 functions. */
3987#define SRC_REG_E1HMF_ENABLE 0x404cc
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003988#define SRC_REG_FIRSTFREE0 0x40510
3989#define SRC_REG_KEYRSS0_0 0x40408
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07003990#define SRC_REG_KEYRSS0_7 0x40424
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02003991#define SRC_REG_KEYRSS1_9 0x40454
Eilon Greenstein8d9c5f32009-02-15 23:24:08 -08003992#define SRC_REG_KEYSEARCH_0 0x40458
3993#define SRC_REG_KEYSEARCH_1 0x4045c
3994#define SRC_REG_KEYSEARCH_2 0x40460
3995#define SRC_REG_KEYSEARCH_3 0x40464
3996#define SRC_REG_KEYSEARCH_4 0x40468
3997#define SRC_REG_KEYSEARCH_5 0x4046c
3998#define SRC_REG_KEYSEARCH_6 0x40470
3999#define SRC_REG_KEYSEARCH_7 0x40474
4000#define SRC_REG_KEYSEARCH_8 0x40478
4001#define SRC_REG_KEYSEARCH_9 0x4047c
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004002#define SRC_REG_LASTFREE0 0x40530
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004003#define SRC_REG_NUMBER_HASH_BITS0 0x40400
4004/* [RW 1] Reset internal state machines. */
4005#define SRC_REG_SOFT_RST 0x4049c
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07004006/* [R 3] Interrupt register #0 read */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004007#define SRC_REG_SRC_INT_STS 0x404ac
4008/* [RW 3] Parity mask register #0 read/write */
4009#define SRC_REG_SRC_PRTY_MASK 0x404c8
Eliezer Tamirf1410642008-02-28 11:51:50 -08004010/* [R 3] Parity register #0 read */
4011#define SRC_REG_SRC_PRTY_STS 0x404bc
Vladislav Zolotarov4a33bc02011-01-09 02:20:04 +00004012/* [RC 3] Parity register #0 read clear */
4013#define SRC_REG_SRC_PRTY_STS_CLR 0x404c0
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004014/* [R 4] Used to read the value of the XX protection CAM occupancy counter. */
4015#define TCM_REG_CAM_OCCUP 0x5017c
4016/* [RW 1] CDU AG read Interface enable. If 0 - the request input is
4017 disregarded; valid output is deasserted; all other signals are treated as
4018 usual; if 1 - normal activity. */
4019#define TCM_REG_CDU_AG_RD_IFEN 0x50034
4020/* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input
4021 are disregarded; all other signals are treated as usual; if 1 - normal
4022 activity. */
4023#define TCM_REG_CDU_AG_WR_IFEN 0x50030
4024/* [RW 1] CDU STORM read Interface enable. If 0 - the request input is
4025 disregarded; valid output is deasserted; all other signals are treated as
4026 usual; if 1 - normal activity. */
4027#define TCM_REG_CDU_SM_RD_IFEN 0x5003c
4028/* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid
4029 input is disregarded; all other signals are treated as usual; if 1 -
4030 normal activity. */
4031#define TCM_REG_CDU_SM_WR_IFEN 0x50038
4032/* [RW 4] CFC output initial credit. Max credit available - 15.Write writes
4033 the initial credit value; read returns the current value of the credit
4034 counter. Must be initialized to 1 at start-up. */
4035#define TCM_REG_CFC_INIT_CRD 0x50204
4036/* [RW 3] The weight of the CP input in the WRR mechanism. 0 stands for
4037 weight 8 (the most prioritised); 1 stands for weight 1(least
4038 prioritised); 2 stands for weight 2; tc. */
4039#define TCM_REG_CP_WEIGHT 0x500c0
4040/* [RW 1] Input csem Interface enable. If 0 - the valid input is
4041 disregarded; acknowledge output is deasserted; all other signals are
4042 treated as usual; if 1 - normal activity. */
4043#define TCM_REG_CSEM_IFEN 0x5002c
4044/* [RC 1] Message length mismatch (relative to last indication) at the In#9
4045 interface. */
4046#define TCM_REG_CSEM_LENGTH_MIS 0x50174
Eilon Greenstein8d9c5f32009-02-15 23:24:08 -08004047/* [RW 3] The weight of the input csem in the WRR mechanism. 0 stands for
4048 weight 8 (the most prioritised); 1 stands for weight 1(least
4049 prioritised); 2 stands for weight 2; tc. */
4050#define TCM_REG_CSEM_WEIGHT 0x500bc
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004051/* [RW 8] The Event ID in case of ErrorFlg is set in the input message. */
4052#define TCM_REG_ERR_EVNT_ID 0x500a0
4053/* [RW 28] The CM erroneous header for QM and Timers formatting. */
4054#define TCM_REG_ERR_TCM_HDR 0x5009c
4055/* [RW 8] The Event ID for Timers expiration. */
4056#define TCM_REG_EXPR_EVNT_ID 0x500a4
4057/* [RW 8] FIC0 output initial credit. Max credit available - 255.Write
4058 writes the initial credit value; read returns the current value of the
4059 credit counter. Must be initialized to 64 at start-up. */
4060#define TCM_REG_FIC0_INIT_CRD 0x5020c
4061/* [RW 8] FIC1 output initial credit. Max credit available - 255.Write
4062 writes the initial credit value; read returns the current value of the
4063 credit counter. Must be initialized to 64 at start-up. */
4064#define TCM_REG_FIC1_INIT_CRD 0x50210
4065/* [RW 1] Arbitration between Input Arbiter groups: 0 - fair Round-Robin; 1
4066 - strict priority defined by ~tcm_registers_gr_ag_pr.gr_ag_pr;
4067 ~tcm_registers_gr_ld0_pr.gr_ld0_pr and
4068 ~tcm_registers_gr_ld1_pr.gr_ld1_pr. */
4069#define TCM_REG_GR_ARB_TYPE 0x50114
4070/* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the
4071 highest priority is 3. It is supposed that the Store channel is the
4072 compliment of the other 3 groups. */
4073#define TCM_REG_GR_LD0_PR 0x5011c
4074/* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the
4075 highest priority is 3. It is supposed that the Store channel is the
4076 compliment of the other 3 groups. */
4077#define TCM_REG_GR_LD1_PR 0x50120
4078/* [RW 4] The number of double REG-pairs; loaded from the STORM context and
4079 sent to STORM; for a specific connection type. The double REG-pairs are
4080 used to align to STORM context row size of 128 bits. The offset of these
4081 data in the STORM context is always 0. Index _i stands for the connection
4082 type (one of 16). */
4083#define TCM_REG_N_SM_CTX_LD_0 0x50050
4084#define TCM_REG_N_SM_CTX_LD_1 0x50054
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004085#define TCM_REG_N_SM_CTX_LD_2 0x50058
4086#define TCM_REG_N_SM_CTX_LD_3 0x5005c
4087#define TCM_REG_N_SM_CTX_LD_4 0x50060
Eilon Greenstein8d9c5f32009-02-15 23:24:08 -08004088#define TCM_REG_N_SM_CTX_LD_5 0x50064
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004089/* [RW 1] Input pbf Interface enable. If 0 - the valid input is disregarded;
4090 acknowledge output is deasserted; all other signals are treated as usual;
4091 if 1 - normal activity. */
4092#define TCM_REG_PBF_IFEN 0x50024
4093/* [RC 1] Message length mismatch (relative to last indication) at the In#7
4094 interface. */
4095#define TCM_REG_PBF_LENGTH_MIS 0x5016c
4096/* [RW 3] The weight of the input pbf in the WRR mechanism. 0 stands for
4097 weight 8 (the most prioritised); 1 stands for weight 1(least
4098 prioritised); 2 stands for weight 2; tc. */
4099#define TCM_REG_PBF_WEIGHT 0x500b4
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004100#define TCM_REG_PHYS_QNUM0_0 0x500e0
4101#define TCM_REG_PHYS_QNUM0_1 0x500e4
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004102#define TCM_REG_PHYS_QNUM1_0 0x500e8
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07004103#define TCM_REG_PHYS_QNUM1_1 0x500ec
4104#define TCM_REG_PHYS_QNUM2_0 0x500f0
4105#define TCM_REG_PHYS_QNUM2_1 0x500f4
4106#define TCM_REG_PHYS_QNUM3_0 0x500f8
4107#define TCM_REG_PHYS_QNUM3_1 0x500fc
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004108/* [RW 1] Input prs Interface enable. If 0 - the valid input is disregarded;
4109 acknowledge output is deasserted; all other signals are treated as usual;
4110 if 1 - normal activity. */
4111#define TCM_REG_PRS_IFEN 0x50020
4112/* [RC 1] Message length mismatch (relative to last indication) at the In#6
4113 interface. */
4114#define TCM_REG_PRS_LENGTH_MIS 0x50168
4115/* [RW 3] The weight of the input prs in the WRR mechanism. 0 stands for
4116 weight 8 (the most prioritised); 1 stands for weight 1(least
4117 prioritised); 2 stands for weight 2; tc. */
4118#define TCM_REG_PRS_WEIGHT 0x500b0
4119/* [RW 8] The Event ID for Timers formatting in case of stop done. */
4120#define TCM_REG_STOP_EVNT_ID 0x500a8
4121/* [RC 1] Message length mismatch (relative to last indication) at the STORM
4122 interface. */
4123#define TCM_REG_STORM_LENGTH_MIS 0x50160
4124/* [RW 1] STORM - CM Interface enable. If 0 - the valid input is
4125 disregarded; acknowledge output is deasserted; all other signals are
4126 treated as usual; if 1 - normal activity. */
4127#define TCM_REG_STORM_TCM_IFEN 0x50010
Eilon Greenstein8d9c5f32009-02-15 23:24:08 -08004128/* [RW 3] The weight of the STORM input in the WRR mechanism. 0 stands for
4129 weight 8 (the most prioritised); 1 stands for weight 1(least
4130 prioritised); 2 stands for weight 2; tc. */
4131#define TCM_REG_STORM_WEIGHT 0x500ac
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004132/* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded;
4133 acknowledge output is deasserted; all other signals are treated as usual;
4134 if 1 - normal activity. */
4135#define TCM_REG_TCM_CFC_IFEN 0x50040
4136/* [RW 11] Interrupt mask register #0 read/write */
4137#define TCM_REG_TCM_INT_MASK 0x501dc
4138/* [R 11] Interrupt register #0 read */
4139#define TCM_REG_TCM_INT_STS 0x501d0
Vladislav Zolotarov4a33bc02011-01-09 02:20:04 +00004140/* [RW 27] Parity mask register #0 read/write */
4141#define TCM_REG_TCM_PRTY_MASK 0x501ec
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07004142/* [R 27] Parity register #0 read */
4143#define TCM_REG_TCM_PRTY_STS 0x501e0
Vladislav Zolotarov4a33bc02011-01-09 02:20:04 +00004144/* [RC 27] Parity register #0 read clear */
4145#define TCM_REG_TCM_PRTY_STS_CLR 0x501e4
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004146/* [RW 3] The size of AG context region 0 in REG-pairs. Designates the MS
4147 REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5).
4148 Is used to determine the number of the AG context REG-pairs written back;
4149 when the input message Reg1WbFlg isn't set. */
4150#define TCM_REG_TCM_REG0_SZ 0x500d8
4151/* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is
4152 disregarded; valid is deasserted; all other signals are treated as usual;
4153 if 1 - normal activity. */
4154#define TCM_REG_TCM_STORM0_IFEN 0x50004
4155/* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is
4156 disregarded; valid is deasserted; all other signals are treated as usual;
4157 if 1 - normal activity. */
4158#define TCM_REG_TCM_STORM1_IFEN 0x50008
4159/* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is
4160 disregarded; valid is deasserted; all other signals are treated as usual;
4161 if 1 - normal activity. */
4162#define TCM_REG_TCM_TQM_IFEN 0x5000c
4163/* [RW 1] If set the Q index; received from the QM is inserted to event ID. */
4164#define TCM_REG_TCM_TQM_USE_Q 0x500d4
4165/* [RW 28] The CM header for Timers expiration command. */
4166#define TCM_REG_TM_TCM_HDR 0x50098
4167/* [RW 1] Timers - CM Interface enable. If 0 - the valid input is
4168 disregarded; acknowledge output is deasserted; all other signals are
4169 treated as usual; if 1 - normal activity. */
4170#define TCM_REG_TM_TCM_IFEN 0x5001c
Eilon Greenstein8d9c5f32009-02-15 23:24:08 -08004171/* [RW 3] The weight of the Timers input in the WRR mechanism. 0 stands for
4172 weight 8 (the most prioritised); 1 stands for weight 1(least
4173 prioritised); 2 stands for weight 2; tc. */
4174#define TCM_REG_TM_WEIGHT 0x500d0
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004175/* [RW 6] QM output initial credit. Max credit available - 32.Write writes
4176 the initial credit value; read returns the current value of the credit
4177 counter. Must be initialized to 32 at start-up. */
4178#define TCM_REG_TQM_INIT_CRD 0x5021c
Eilon Greenstein8d9c5f32009-02-15 23:24:08 -08004179/* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0
4180 stands for weight 8 (the most prioritised); 1 stands for weight 1(least
4181 prioritised); 2 stands for weight 2; tc. */
4182#define TCM_REG_TQM_P_WEIGHT 0x500c8
4183/* [RW 3] The weight of the QM (secondary) input in the WRR mechanism. 0
4184 stands for weight 8 (the most prioritised); 1 stands for weight 1(least
4185 prioritised); 2 stands for weight 2; tc. */
4186#define TCM_REG_TQM_S_WEIGHT 0x500cc
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004187/* [RW 28] The CM header value for QM request (primary). */
4188#define TCM_REG_TQM_TCM_HDR_P 0x50090
4189/* [RW 28] The CM header value for QM request (secondary). */
4190#define TCM_REG_TQM_TCM_HDR_S 0x50094
4191/* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded;
4192 acknowledge output is deasserted; all other signals are treated as usual;
4193 if 1 - normal activity. */
4194#define TCM_REG_TQM_TCM_IFEN 0x50014
4195/* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded;
4196 acknowledge output is deasserted; all other signals are treated as usual;
4197 if 1 - normal activity. */
4198#define TCM_REG_TSDM_IFEN 0x50018
4199/* [RC 1] Message length mismatch (relative to last indication) at the SDM
4200 interface. */
4201#define TCM_REG_TSDM_LENGTH_MIS 0x50164
4202/* [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands for
4203 weight 8 (the most prioritised); 1 stands for weight 1(least
4204 prioritised); 2 stands for weight 2; tc. */
4205#define TCM_REG_TSDM_WEIGHT 0x500c4
4206/* [RW 1] Input usem Interface enable. If 0 - the valid input is
4207 disregarded; acknowledge output is deasserted; all other signals are
4208 treated as usual; if 1 - normal activity. */
4209#define TCM_REG_USEM_IFEN 0x50028
4210/* [RC 1] Message length mismatch (relative to last indication) at the In#8
4211 interface. */
4212#define TCM_REG_USEM_LENGTH_MIS 0x50170
Eilon Greenstein8d9c5f32009-02-15 23:24:08 -08004213/* [RW 3] The weight of the input usem in the WRR mechanism. 0 stands for
4214 weight 8 (the most prioritised); 1 stands for weight 1(least
4215 prioritised); 2 stands for weight 2; tc. */
4216#define TCM_REG_USEM_WEIGHT 0x500b8
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004217/* [RW 21] Indirect access to the descriptor table of the XX protection
4218 mechanism. The fields are: [5:0] - length of the message; 15:6] - message
4219 pointer; 20:16] - next pointer. */
4220#define TCM_REG_XX_DESCR_TABLE 0x50280
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07004221#define TCM_REG_XX_DESCR_TABLE_SIZE 32
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004222/* [R 6] Use to read the value of XX protection Free counter. */
4223#define TCM_REG_XX_FREE 0x50178
4224/* [RW 6] Initial value for the credit counter; responsible for fulfilling
4225 of the Input Stage XX protection buffer by the XX protection pending
4226 messages. Max credit available - 127.Write writes the initial credit
4227 value; read returns the current value of the credit counter. Must be
4228 initialized to 19 at start-up. */
4229#define TCM_REG_XX_INIT_CRD 0x50220
4230/* [RW 6] Maximum link list size (messages locked) per connection in the XX
4231 protection. */
4232#define TCM_REG_XX_MAX_LL_SZ 0x50044
4233/* [RW 6] The maximum number of pending messages; which may be stored in XX
4234 protection. ~tcm_registers_xx_free.xx_free is read on read. */
4235#define TCM_REG_XX_MSG_NUM 0x50224
4236/* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */
4237#define TCM_REG_XX_OVFL_EVNT_ID 0x50048
4238/* [RW 16] Indirect access to the XX table of the XX protection mechanism.
4239 The fields are:[4:0] - tail pointer; [10:5] - Link List size; 15:11] -
4240 header pointer. */
4241#define TCM_REG_XX_TABLE 0x50240
Anand Gadiyar411c9402009-07-07 15:24:23 +05304242/* [RW 4] Load value for cfc ac credit cnt. */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004243#define TM_REG_CFC_AC_CRDCNT_VAL 0x164208
4244/* [RW 4] Load value for cfc cld credit cnt. */
4245#define TM_REG_CFC_CLD_CRDCNT_VAL 0x164210
4246/* [RW 8] Client0 context region. */
4247#define TM_REG_CL0_CONT_REGION 0x164030
4248/* [RW 8] Client1 context region. */
4249#define TM_REG_CL1_CONT_REGION 0x164034
4250/* [RW 8] Client2 context region. */
4251#define TM_REG_CL2_CONT_REGION 0x164038
4252/* [RW 2] Client in High priority client number. */
4253#define TM_REG_CLIN_PRIOR0_CLIENT 0x164024
4254/* [RW 4] Load value for clout0 cred cnt. */
4255#define TM_REG_CLOUT_CRDCNT0_VAL 0x164220
4256/* [RW 4] Load value for clout1 cred cnt. */
4257#define TM_REG_CLOUT_CRDCNT1_VAL 0x164228
4258/* [RW 4] Load value for clout2 cred cnt. */
4259#define TM_REG_CLOUT_CRDCNT2_VAL 0x164230
4260/* [RW 1] Enable client0 input. */
4261#define TM_REG_EN_CL0_INPUT 0x164008
4262/* [RW 1] Enable client1 input. */
4263#define TM_REG_EN_CL1_INPUT 0x16400c
4264/* [RW 1] Enable client2 input. */
4265#define TM_REG_EN_CL2_INPUT 0x164010
Eilon Greenstein8d9c5f32009-02-15 23:24:08 -08004266#define TM_REG_EN_LINEAR0_TIMER 0x164014
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004267/* [RW 1] Enable real time counter. */
4268#define TM_REG_EN_REAL_TIME_CNT 0x1640d8
4269/* [RW 1] Enable for Timers state machines. */
4270#define TM_REG_EN_TIMERS 0x164000
4271/* [RW 4] Load value for expiration credit cnt. CFC max number of
4272 outstanding load requests for timers (expiration) context loading. */
4273#define TM_REG_EXP_CRDCNT_VAL 0x164238
Eilon Greenstein8d9c5f32009-02-15 23:24:08 -08004274/* [RW 32] Linear0 logic address. */
4275#define TM_REG_LIN0_LOGIC_ADDR 0x164240
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07004276/* [RW 18] Linear0 Max active cid (in banks of 32 entries). */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004277#define TM_REG_LIN0_MAX_ACTIVE_CID 0x164048
Vlad Zolotarov619c5cb2011-06-14 14:33:44 +03004278/* [ST 16] Linear0 Number of scans counter. */
4279#define TM_REG_LIN0_NUM_SCANS 0x1640a0
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004280/* [WB 64] Linear0 phy address. */
4281#define TM_REG_LIN0_PHY_ADDR 0x164270
Eilon Greenstein8d9c5f32009-02-15 23:24:08 -08004282/* [RW 1] Linear0 physical address valid. */
4283#define TM_REG_LIN0_PHY_ADDR_VALID 0x164248
Eilon Greensteinca003922009-08-12 22:53:28 -07004284#define TM_REG_LIN0_SCAN_ON 0x1640d0
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004285/* [RW 24] Linear0 array scan timeout. */
4286#define TM_REG_LIN0_SCAN_TIME 0x16403c
Vlad Zolotarov619c5cb2011-06-14 14:33:44 +03004287#define TM_REG_LIN0_VNIC_UC 0x164128
Eilon Greenstein8d9c5f32009-02-15 23:24:08 -08004288/* [RW 32] Linear1 logic address. */
4289#define TM_REG_LIN1_LOGIC_ADDR 0x164250
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004290/* [WB 64] Linear1 phy address. */
4291#define TM_REG_LIN1_PHY_ADDR 0x164280
Eilon Greenstein8d9c5f32009-02-15 23:24:08 -08004292/* [RW 1] Linear1 physical address valid. */
4293#define TM_REG_LIN1_PHY_ADDR_VALID 0x164258
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004294/* [RW 6] Linear timer set_clear fifo threshold. */
4295#define TM_REG_LIN_SETCLR_FIFO_ALFULL_THR 0x164070
4296/* [RW 2] Load value for pci arbiter credit cnt. */
4297#define TM_REG_PCIARB_CRDCNT_VAL 0x164260
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004298/* [RW 20] The amount of hardware cycles for each timer tick. */
4299#define TM_REG_TIMER_TICK_SIZE 0x16401c
4300/* [RW 8] Timers Context region. */
4301#define TM_REG_TM_CONTEXT_REGION 0x164044
4302/* [RW 1] Interrupt mask register #0 read/write */
4303#define TM_REG_TM_INT_MASK 0x1640fc
4304/* [R 1] Interrupt register #0 read */
4305#define TM_REG_TM_INT_STS 0x1640f0
Vladislav Zolotarov4a33bc02011-01-09 02:20:04 +00004306/* [RW 7] Parity mask register #0 read/write */
4307#define TM_REG_TM_PRTY_MASK 0x16410c
4308/* [RC 7] Parity register #0 read clear */
4309#define TM_REG_TM_PRTY_STS_CLR 0x164104
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004310/* [RW 8] The event id for aggregated interrupt 0 */
4311#define TSDM_REG_AGG_INT_EVENT_0 0x42038
Eilon Greenstein8d9c5f32009-02-15 23:24:08 -08004312#define TSDM_REG_AGG_INT_EVENT_1 0x4203c
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07004313#define TSDM_REG_AGG_INT_EVENT_2 0x42040
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07004314#define TSDM_REG_AGG_INT_EVENT_3 0x42044
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07004315#define TSDM_REG_AGG_INT_EVENT_4 0x42048
Eilon Greenstein8d9c5f32009-02-15 23:24:08 -08004316/* [RW 1] The T bit for aggregated interrupt 0 */
4317#define TSDM_REG_AGG_INT_T_0 0x420b8
4318#define TSDM_REG_AGG_INT_T_1 0x420bc
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004319/* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */
4320#define TSDM_REG_CFC_RSP_START_ADDR 0x42008
Lucas De Marchi25985ed2011-03-30 22:57:33 -03004321/* [RW 16] The maximum value of the completion counter #0 */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004322#define TSDM_REG_CMP_COUNTER_MAX0 0x4201c
Lucas De Marchi25985ed2011-03-30 22:57:33 -03004323/* [RW 16] The maximum value of the completion counter #1 */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004324#define TSDM_REG_CMP_COUNTER_MAX1 0x42020
Lucas De Marchi25985ed2011-03-30 22:57:33 -03004325/* [RW 16] The maximum value of the completion counter #2 */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004326#define TSDM_REG_CMP_COUNTER_MAX2 0x42024
Lucas De Marchi25985ed2011-03-30 22:57:33 -03004327/* [RW 16] The maximum value of the completion counter #3 */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004328#define TSDM_REG_CMP_COUNTER_MAX3 0x42028
4329/* [RW 13] The start address in the internal RAM for the completion
4330 counters. */
4331#define TSDM_REG_CMP_COUNTER_START_ADDR 0x4200c
4332#define TSDM_REG_ENABLE_IN1 0x42238
4333#define TSDM_REG_ENABLE_IN2 0x4223c
4334#define TSDM_REG_ENABLE_OUT1 0x42240
4335#define TSDM_REG_ENABLE_OUT2 0x42244
4336/* [RW 4] The initial number of messages that can be sent to the pxp control
4337 interface without receiving any ACK. */
4338#define TSDM_REG_INIT_CREDIT_PXP_CTRL 0x424bc
4339/* [ST 32] The number of ACK after placement messages received */
4340#define TSDM_REG_NUM_OF_ACK_AFTER_PLACE 0x4227c
4341/* [ST 32] The number of packet end messages received from the parser */
4342#define TSDM_REG_NUM_OF_PKT_END_MSG 0x42274
4343/* [ST 32] The number of requests received from the pxp async if */
4344#define TSDM_REG_NUM_OF_PXP_ASYNC_REQ 0x42278
4345/* [ST 32] The number of commands received in queue 0 */
4346#define TSDM_REG_NUM_OF_Q0_CMD 0x42248
4347/* [ST 32] The number of commands received in queue 10 */
4348#define TSDM_REG_NUM_OF_Q10_CMD 0x4226c
4349/* [ST 32] The number of commands received in queue 11 */
4350#define TSDM_REG_NUM_OF_Q11_CMD 0x42270
4351/* [ST 32] The number of commands received in queue 1 */
4352#define TSDM_REG_NUM_OF_Q1_CMD 0x4224c
4353/* [ST 32] The number of commands received in queue 3 */
4354#define TSDM_REG_NUM_OF_Q3_CMD 0x42250
4355/* [ST 32] The number of commands received in queue 4 */
4356#define TSDM_REG_NUM_OF_Q4_CMD 0x42254
4357/* [ST 32] The number of commands received in queue 5 */
4358#define TSDM_REG_NUM_OF_Q5_CMD 0x42258
4359/* [ST 32] The number of commands received in queue 6 */
4360#define TSDM_REG_NUM_OF_Q6_CMD 0x4225c
4361/* [ST 32] The number of commands received in queue 7 */
4362#define TSDM_REG_NUM_OF_Q7_CMD 0x42260
4363/* [ST 32] The number of commands received in queue 8 */
4364#define TSDM_REG_NUM_OF_Q8_CMD 0x42264
4365/* [ST 32] The number of commands received in queue 9 */
4366#define TSDM_REG_NUM_OF_Q9_CMD 0x42268
4367/* [RW 13] The start address in the internal RAM for the packet end message */
4368#define TSDM_REG_PCK_END_MSG_START_ADDR 0x42014
4369/* [RW 13] The start address in the internal RAM for queue counters */
4370#define TSDM_REG_Q_COUNTER_START_ADDR 0x42010
4371/* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */
4372#define TSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0x42548
4373/* [R 1] parser fifo empty in sdm_sync block */
4374#define TSDM_REG_SYNC_PARSER_EMPTY 0x42550
4375/* [R 1] parser serial fifo empty in sdm_sync block */
4376#define TSDM_REG_SYNC_SYNC_EMPTY 0x42558
4377/* [RW 32] Tick for timer counter. Applicable only when
4378 ~tsdm_registers_timer_tick_enable.timer_tick_enable =1 */
4379#define TSDM_REG_TIMER_TICK 0x42000
4380/* [RW 32] Interrupt mask register #0 read/write */
4381#define TSDM_REG_TSDM_INT_MASK_0 0x4229c
4382#define TSDM_REG_TSDM_INT_MASK_1 0x422ac
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07004383/* [R 32] Interrupt register #0 read */
4384#define TSDM_REG_TSDM_INT_STS_0 0x42290
4385#define TSDM_REG_TSDM_INT_STS_1 0x422a0
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004386/* [RW 11] Parity mask register #0 read/write */
4387#define TSDM_REG_TSDM_PRTY_MASK 0x422bc
Eliezer Tamirf1410642008-02-28 11:51:50 -08004388/* [R 11] Parity register #0 read */
4389#define TSDM_REG_TSDM_PRTY_STS 0x422b0
Vladislav Zolotarov4a33bc02011-01-09 02:20:04 +00004390/* [RC 11] Parity register #0 read clear */
4391#define TSDM_REG_TSDM_PRTY_STS_CLR 0x422b4
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004392/* [RW 5] The number of time_slots in the arbitration cycle */
4393#define TSEM_REG_ARB_CYCLE_SIZE 0x180034
4394/* [RW 3] The source that is associated with arbitration element 0. Source
4395 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4396 sleeping thread with priority 1; 4- sleeping thread with priority 2 */
4397#define TSEM_REG_ARB_ELEMENT0 0x180020
4398/* [RW 3] The source that is associated with arbitration element 1. Source
4399 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4400 sleeping thread with priority 1; 4- sleeping thread with priority 2.
4401 Could not be equal to register ~tsem_registers_arb_element0.arb_element0 */
4402#define TSEM_REG_ARB_ELEMENT1 0x180024
4403/* [RW 3] The source that is associated with arbitration element 2. Source
4404 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4405 sleeping thread with priority 1; 4- sleeping thread with priority 2.
4406 Could not be equal to register ~tsem_registers_arb_element0.arb_element0
4407 and ~tsem_registers_arb_element1.arb_element1 */
4408#define TSEM_REG_ARB_ELEMENT2 0x180028
4409/* [RW 3] The source that is associated with arbitration element 3. Source
4410 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4411 sleeping thread with priority 1; 4- sleeping thread with priority 2.Could
4412 not be equal to register ~tsem_registers_arb_element0.arb_element0 and
4413 ~tsem_registers_arb_element1.arb_element1 and
4414 ~tsem_registers_arb_element2.arb_element2 */
4415#define TSEM_REG_ARB_ELEMENT3 0x18002c
4416/* [RW 3] The source that is associated with arbitration element 4. Source
4417 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4418 sleeping thread with priority 1; 4- sleeping thread with priority 2.
4419 Could not be equal to register ~tsem_registers_arb_element0.arb_element0
4420 and ~tsem_registers_arb_element1.arb_element1 and
4421 ~tsem_registers_arb_element2.arb_element2 and
4422 ~tsem_registers_arb_element3.arb_element3 */
4423#define TSEM_REG_ARB_ELEMENT4 0x180030
4424#define TSEM_REG_ENABLE_IN 0x1800a4
4425#define TSEM_REG_ENABLE_OUT 0x1800a8
4426/* [RW 32] This address space contains all registers and memories that are
4427 placed in SEM_FAST block. The SEM_FAST registers are described in
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07004428 appendix B. In order to access the sem_fast registers the base address
4429 ~fast_memory.fast_memory should be added to eachsem_fast register offset. */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004430#define TSEM_REG_FAST_MEMORY 0x1a0000
4431/* [RW 1] Disables input messages from FIC0 May be updated during run_time
4432 by the microcode */
4433#define TSEM_REG_FIC0_DISABLE 0x180224
4434/* [RW 1] Disables input messages from FIC1 May be updated during run_time
4435 by the microcode */
4436#define TSEM_REG_FIC1_DISABLE 0x180234
4437/* [RW 15] Interrupt table Read and write access to it is not possible in
4438 the middle of the work */
4439#define TSEM_REG_INT_TABLE 0x180400
4440/* [ST 24] Statistics register. The number of messages that entered through
4441 FIC0 */
4442#define TSEM_REG_MSG_NUM_FIC0 0x180000
4443/* [ST 24] Statistics register. The number of messages that entered through
4444 FIC1 */
4445#define TSEM_REG_MSG_NUM_FIC1 0x180004
4446/* [ST 24] Statistics register. The number of messages that were sent to
4447 FOC0 */
4448#define TSEM_REG_MSG_NUM_FOC0 0x180008
4449/* [ST 24] Statistics register. The number of messages that were sent to
4450 FOC1 */
4451#define TSEM_REG_MSG_NUM_FOC1 0x18000c
4452/* [ST 24] Statistics register. The number of messages that were sent to
4453 FOC2 */
4454#define TSEM_REG_MSG_NUM_FOC2 0x180010
4455/* [ST 24] Statistics register. The number of messages that were sent to
4456 FOC3 */
4457#define TSEM_REG_MSG_NUM_FOC3 0x180014
4458/* [RW 1] Disables input messages from the passive buffer May be updated
4459 during run_time by the microcode */
4460#define TSEM_REG_PAS_DISABLE 0x18024c
4461/* [WB 128] Debug only. Passive buffer memory */
4462#define TSEM_REG_PASSIVE_BUFFER 0x181000
4463/* [WB 46] pram memory. B45 is parity; b[44:0] - data. */
4464#define TSEM_REG_PRAM 0x1c0000
4465/* [R 8] Valid sleeping threads indication have bit per thread */
4466#define TSEM_REG_SLEEP_THREADS_VALID 0x18026c
4467/* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */
4468#define TSEM_REG_SLOW_EXT_STORE_EMPTY 0x1802a0
4469/* [RW 8] List of free threads . There is a bit per thread. */
4470#define TSEM_REG_THREADS_LIST 0x1802e4
Vladislav Zolotarov4a33bc02011-01-09 02:20:04 +00004471/* [RC 32] Parity register #0 read clear */
4472#define TSEM_REG_TSEM_PRTY_STS_CLR_0 0x180118
4473#define TSEM_REG_TSEM_PRTY_STS_CLR_1 0x180128
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004474/* [RW 3] The arbitration scheme of time_slot 0 */
4475#define TSEM_REG_TS_0_AS 0x180038
4476/* [RW 3] The arbitration scheme of time_slot 10 */
4477#define TSEM_REG_TS_10_AS 0x180060
4478/* [RW 3] The arbitration scheme of time_slot 11 */
4479#define TSEM_REG_TS_11_AS 0x180064
4480/* [RW 3] The arbitration scheme of time_slot 12 */
4481#define TSEM_REG_TS_12_AS 0x180068
4482/* [RW 3] The arbitration scheme of time_slot 13 */
4483#define TSEM_REG_TS_13_AS 0x18006c
4484/* [RW 3] The arbitration scheme of time_slot 14 */
4485#define TSEM_REG_TS_14_AS 0x180070
4486/* [RW 3] The arbitration scheme of time_slot 15 */
4487#define TSEM_REG_TS_15_AS 0x180074
4488/* [RW 3] The arbitration scheme of time_slot 16 */
4489#define TSEM_REG_TS_16_AS 0x180078
4490/* [RW 3] The arbitration scheme of time_slot 17 */
4491#define TSEM_REG_TS_17_AS 0x18007c
4492/* [RW 3] The arbitration scheme of time_slot 18 */
4493#define TSEM_REG_TS_18_AS 0x180080
4494/* [RW 3] The arbitration scheme of time_slot 1 */
4495#define TSEM_REG_TS_1_AS 0x18003c
4496/* [RW 3] The arbitration scheme of time_slot 2 */
4497#define TSEM_REG_TS_2_AS 0x180040
4498/* [RW 3] The arbitration scheme of time_slot 3 */
4499#define TSEM_REG_TS_3_AS 0x180044
4500/* [RW 3] The arbitration scheme of time_slot 4 */
4501#define TSEM_REG_TS_4_AS 0x180048
4502/* [RW 3] The arbitration scheme of time_slot 5 */
4503#define TSEM_REG_TS_5_AS 0x18004c
4504/* [RW 3] The arbitration scheme of time_slot 6 */
4505#define TSEM_REG_TS_6_AS 0x180050
4506/* [RW 3] The arbitration scheme of time_slot 7 */
4507#define TSEM_REG_TS_7_AS 0x180054
4508/* [RW 3] The arbitration scheme of time_slot 8 */
4509#define TSEM_REG_TS_8_AS 0x180058
4510/* [RW 3] The arbitration scheme of time_slot 9 */
4511#define TSEM_REG_TS_9_AS 0x18005c
4512/* [RW 32] Interrupt mask register #0 read/write */
4513#define TSEM_REG_TSEM_INT_MASK_0 0x180100
4514#define TSEM_REG_TSEM_INT_MASK_1 0x180110
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07004515/* [R 32] Interrupt register #0 read */
4516#define TSEM_REG_TSEM_INT_STS_0 0x1800f4
4517#define TSEM_REG_TSEM_INT_STS_1 0x180104
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004518/* [RW 32] Parity mask register #0 read/write */
4519#define TSEM_REG_TSEM_PRTY_MASK_0 0x180120
4520#define TSEM_REG_TSEM_PRTY_MASK_1 0x180130
Eliezer Tamirf1410642008-02-28 11:51:50 -08004521/* [R 32] Parity register #0 read */
4522#define TSEM_REG_TSEM_PRTY_STS_0 0x180114
4523#define TSEM_REG_TSEM_PRTY_STS_1 0x180124
Dmitry Kravkovf2e08992010-10-06 03:28:26 +00004524/* [W 7] VF or PF ID for reset error bit. Values 0-63 reset error bit for 64
4525 * VF; values 64-67 reset error for 4 PF; values 68-127 are not valid. */
4526#define TSEM_REG_VFPF_ERR_NUM 0x180380
4527/* [RW 32] Indirect access to AG context with 32-bits granularity. The bits
4528 * [10:8] of the address should be the offset within the accessed LCID
4529 * context; the bits [7:0] are the accessed LCID.Example: to write to REG10
4530 * LCID100. The RBC address should be 12'ha64. */
4531#define UCM_REG_AG_CTX 0xe2000
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004532/* [R 5] Used to read the XX protection CAM occupancy counter. */
4533#define UCM_REG_CAM_OCCUP 0xe0170
4534/* [RW 1] CDU AG read Interface enable. If 0 - the request input is
4535 disregarded; valid output is deasserted; all other signals are treated as
4536 usual; if 1 - normal activity. */
4537#define UCM_REG_CDU_AG_RD_IFEN 0xe0038
4538/* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input
4539 are disregarded; all other signals are treated as usual; if 1 - normal
4540 activity. */
4541#define UCM_REG_CDU_AG_WR_IFEN 0xe0034
4542/* [RW 1] CDU STORM read Interface enable. If 0 - the request input is
4543 disregarded; valid output is deasserted; all other signals are treated as
4544 usual; if 1 - normal activity. */
4545#define UCM_REG_CDU_SM_RD_IFEN 0xe0040
4546/* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid
4547 input is disregarded; all other signals are treated as usual; if 1 -
4548 normal activity. */
4549#define UCM_REG_CDU_SM_WR_IFEN 0xe003c
4550/* [RW 4] CFC output initial credit. Max credit available - 15.Write writes
4551 the initial credit value; read returns the current value of the credit
4552 counter. Must be initialized to 1 at start-up. */
4553#define UCM_REG_CFC_INIT_CRD 0xe0204
4554/* [RW 3] The weight of the CP input in the WRR mechanism. 0 stands for
4555 weight 8 (the most prioritised); 1 stands for weight 1(least
4556 prioritised); 2 stands for weight 2; tc. */
4557#define UCM_REG_CP_WEIGHT 0xe00c4
4558/* [RW 1] Input csem Interface enable. If 0 - the valid input is
4559 disregarded; acknowledge output is deasserted; all other signals are
4560 treated as usual; if 1 - normal activity. */
4561#define UCM_REG_CSEM_IFEN 0xe0028
4562/* [RC 1] Set when the message length mismatch (relative to last indication)
4563 at the csem interface is detected. */
4564#define UCM_REG_CSEM_LENGTH_MIS 0xe0160
4565/* [RW 3] The weight of the input csem in the WRR mechanism. 0 stands for
4566 weight 8 (the most prioritised); 1 stands for weight 1(least
4567 prioritised); 2 stands for weight 2; tc. */
4568#define UCM_REG_CSEM_WEIGHT 0xe00b8
4569/* [RW 1] Input dorq Interface enable. If 0 - the valid input is
4570 disregarded; acknowledge output is deasserted; all other signals are
4571 treated as usual; if 1 - normal activity. */
4572#define UCM_REG_DORQ_IFEN 0xe0030
4573/* [RC 1] Set when the message length mismatch (relative to last indication)
4574 at the dorq interface is detected. */
4575#define UCM_REG_DORQ_LENGTH_MIS 0xe0168
Eilon Greenstein8d9c5f32009-02-15 23:24:08 -08004576/* [RW 3] The weight of the input dorq in the WRR mechanism. 0 stands for
4577 weight 8 (the most prioritised); 1 stands for weight 1(least
4578 prioritised); 2 stands for weight 2; tc. */
4579#define UCM_REG_DORQ_WEIGHT 0xe00c0
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004580/* [RW 8] The Event ID in case ErrorFlg input message bit is set. */
4581#define UCM_REG_ERR_EVNT_ID 0xe00a4
4582/* [RW 28] The CM erroneous header for QM and Timers formatting. */
4583#define UCM_REG_ERR_UCM_HDR 0xe00a0
4584/* [RW 8] The Event ID for Timers expiration. */
4585#define UCM_REG_EXPR_EVNT_ID 0xe00a8
4586/* [RW 8] FIC0 output initial credit. Max credit available - 255.Write
4587 writes the initial credit value; read returns the current value of the
4588 credit counter. Must be initialized to 64 at start-up. */
4589#define UCM_REG_FIC0_INIT_CRD 0xe020c
4590/* [RW 8] FIC1 output initial credit. Max credit available - 255.Write
4591 writes the initial credit value; read returns the current value of the
4592 credit counter. Must be initialized to 64 at start-up. */
4593#define UCM_REG_FIC1_INIT_CRD 0xe0210
4594/* [RW 1] Arbitration between Input Arbiter groups: 0 - fair Round-Robin; 1
4595 - strict priority defined by ~ucm_registers_gr_ag_pr.gr_ag_pr;
4596 ~ucm_registers_gr_ld0_pr.gr_ld0_pr and
4597 ~ucm_registers_gr_ld1_pr.gr_ld1_pr. */
4598#define UCM_REG_GR_ARB_TYPE 0xe0144
4599/* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the
4600 highest priority is 3. It is supposed that the Store channel group is
4601 compliment to the others. */
4602#define UCM_REG_GR_LD0_PR 0xe014c
4603/* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the
4604 highest priority is 3. It is supposed that the Store channel group is
4605 compliment to the others. */
4606#define UCM_REG_GR_LD1_PR 0xe0150
4607/* [RW 2] The queue index for invalidate counter flag decision. */
4608#define UCM_REG_INV_CFLG_Q 0xe00e4
4609/* [RW 5] The number of double REG-pairs; loaded from the STORM context and
4610 sent to STORM; for a specific connection type. the double REG-pairs are
4611 used in order to align to STORM context row size of 128 bits. The offset
4612 of these data in the STORM context is always 0. Index _i stands for the
4613 connection type (one of 16). */
4614#define UCM_REG_N_SM_CTX_LD_0 0xe0054
4615#define UCM_REG_N_SM_CTX_LD_1 0xe0058
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004616#define UCM_REG_N_SM_CTX_LD_2 0xe005c
4617#define UCM_REG_N_SM_CTX_LD_3 0xe0060
4618#define UCM_REG_N_SM_CTX_LD_4 0xe0064
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07004619#define UCM_REG_N_SM_CTX_LD_5 0xe0068
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004620#define UCM_REG_PHYS_QNUM0_0 0xe0110
4621#define UCM_REG_PHYS_QNUM0_1 0xe0114
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004622#define UCM_REG_PHYS_QNUM1_0 0xe0118
4623#define UCM_REG_PHYS_QNUM1_1 0xe011c
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07004624#define UCM_REG_PHYS_QNUM2_0 0xe0120
4625#define UCM_REG_PHYS_QNUM2_1 0xe0124
4626#define UCM_REG_PHYS_QNUM3_0 0xe0128
4627#define UCM_REG_PHYS_QNUM3_1 0xe012c
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004628/* [RW 8] The Event ID for Timers formatting in case of stop done. */
4629#define UCM_REG_STOP_EVNT_ID 0xe00ac
4630/* [RC 1] Set when the message length mismatch (relative to last indication)
4631 at the STORM interface is detected. */
4632#define UCM_REG_STORM_LENGTH_MIS 0xe0154
4633/* [RW 1] STORM - CM Interface enable. If 0 - the valid input is
4634 disregarded; acknowledge output is deasserted; all other signals are
4635 treated as usual; if 1 - normal activity. */
4636#define UCM_REG_STORM_UCM_IFEN 0xe0010
Eilon Greenstein8d9c5f32009-02-15 23:24:08 -08004637/* [RW 3] The weight of the STORM input in the WRR mechanism. 0 stands for
4638 weight 8 (the most prioritised); 1 stands for weight 1(least
4639 prioritised); 2 stands for weight 2; tc. */
4640#define UCM_REG_STORM_WEIGHT 0xe00b0
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004641/* [RW 4] Timers output initial credit. Max credit available - 15.Write
4642 writes the initial credit value; read returns the current value of the
4643 credit counter. Must be initialized to 4 at start-up. */
4644#define UCM_REG_TM_INIT_CRD 0xe021c
4645/* [RW 28] The CM header for Timers expiration command. */
4646#define UCM_REG_TM_UCM_HDR 0xe009c
4647/* [RW 1] Timers - CM Interface enable. If 0 - the valid input is
4648 disregarded; acknowledge output is deasserted; all other signals are
4649 treated as usual; if 1 - normal activity. */
4650#define UCM_REG_TM_UCM_IFEN 0xe001c
Eilon Greenstein8d9c5f32009-02-15 23:24:08 -08004651/* [RW 3] The weight of the Timers input in the WRR mechanism. 0 stands for
4652 weight 8 (the most prioritised); 1 stands for weight 1(least
4653 prioritised); 2 stands for weight 2; tc. */
4654#define UCM_REG_TM_WEIGHT 0xe00d4
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004655/* [RW 1] Input tsem Interface enable. If 0 - the valid input is
4656 disregarded; acknowledge output is deasserted; all other signals are
4657 treated as usual; if 1 - normal activity. */
4658#define UCM_REG_TSEM_IFEN 0xe0024
4659/* [RC 1] Set when the message length mismatch (relative to last indication)
4660 at the tsem interface is detected. */
4661#define UCM_REG_TSEM_LENGTH_MIS 0xe015c
4662/* [RW 3] The weight of the input tsem in the WRR mechanism. 0 stands for
4663 weight 8 (the most prioritised); 1 stands for weight 1(least
4664 prioritised); 2 stands for weight 2; tc. */
4665#define UCM_REG_TSEM_WEIGHT 0xe00b4
4666/* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded;
4667 acknowledge output is deasserted; all other signals are treated as usual;
4668 if 1 - normal activity. */
4669#define UCM_REG_UCM_CFC_IFEN 0xe0044
4670/* [RW 11] Interrupt mask register #0 read/write */
4671#define UCM_REG_UCM_INT_MASK 0xe01d4
4672/* [R 11] Interrupt register #0 read */
4673#define UCM_REG_UCM_INT_STS 0xe01c8
Vladislav Zolotarovc9ee9202011-06-14 01:33:51 +00004674/* [RW 27] Parity mask register #0 read/write */
4675#define UCM_REG_UCM_PRTY_MASK 0xe01e4
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07004676/* [R 27] Parity register #0 read */
4677#define UCM_REG_UCM_PRTY_STS 0xe01d8
Vladislav Zolotarov4a33bc02011-01-09 02:20:04 +00004678/* [RC 27] Parity register #0 read clear */
4679#define UCM_REG_UCM_PRTY_STS_CLR 0xe01dc
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004680/* [RW 2] The size of AG context region 0 in REG-pairs. Designates the MS
4681 REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5).
4682 Is used to determine the number of the AG context REG-pairs written back;
4683 when the Reg1WbFlg isn't set. */
4684#define UCM_REG_UCM_REG0_SZ 0xe00dc
4685/* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is
4686 disregarded; valid is deasserted; all other signals are treated as usual;
4687 if 1 - normal activity. */
4688#define UCM_REG_UCM_STORM0_IFEN 0xe0004
4689/* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is
4690 disregarded; valid is deasserted; all other signals are treated as usual;
4691 if 1 - normal activity. */
4692#define UCM_REG_UCM_STORM1_IFEN 0xe0008
4693/* [RW 1] CM - Timers Interface enable. If 0 - the valid input is
4694 disregarded; acknowledge output is deasserted; all other signals are
4695 treated as usual; if 1 - normal activity. */
4696#define UCM_REG_UCM_TM_IFEN 0xe0020
4697/* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is
4698 disregarded; valid is deasserted; all other signals are treated as usual;
4699 if 1 - normal activity. */
4700#define UCM_REG_UCM_UQM_IFEN 0xe000c
4701/* [RW 1] If set the Q index; received from the QM is inserted to event ID. */
4702#define UCM_REG_UCM_UQM_USE_Q 0xe00d8
4703/* [RW 6] QM output initial credit. Max credit available - 32.Write writes
4704 the initial credit value; read returns the current value of the credit
4705 counter. Must be initialized to 32 at start-up. */
4706#define UCM_REG_UQM_INIT_CRD 0xe0220
4707/* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0
4708 stands for weight 8 (the most prioritised); 1 stands for weight 1(least
4709 prioritised); 2 stands for weight 2; tc. */
4710#define UCM_REG_UQM_P_WEIGHT 0xe00cc
Eilon Greenstein8d9c5f32009-02-15 23:24:08 -08004711/* [RW 3] The weight of the QM (secondary) input in the WRR mechanism. 0
4712 stands for weight 8 (the most prioritised); 1 stands for weight 1(least
4713 prioritised); 2 stands for weight 2; tc. */
4714#define UCM_REG_UQM_S_WEIGHT 0xe00d0
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004715/* [RW 28] The CM header value for QM request (primary). */
4716#define UCM_REG_UQM_UCM_HDR_P 0xe0094
4717/* [RW 28] The CM header value for QM request (secondary). */
4718#define UCM_REG_UQM_UCM_HDR_S 0xe0098
4719/* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded;
4720 acknowledge output is deasserted; all other signals are treated as usual;
4721 if 1 - normal activity. */
4722#define UCM_REG_UQM_UCM_IFEN 0xe0014
4723/* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded;
4724 acknowledge output is deasserted; all other signals are treated as usual;
4725 if 1 - normal activity. */
4726#define UCM_REG_USDM_IFEN 0xe0018
4727/* [RC 1] Set when the message length mismatch (relative to last indication)
4728 at the SDM interface is detected. */
4729#define UCM_REG_USDM_LENGTH_MIS 0xe0158
Eilon Greenstein8d9c5f32009-02-15 23:24:08 -08004730/* [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands for
4731 weight 8 (the most prioritised); 1 stands for weight 1(least
4732 prioritised); 2 stands for weight 2; tc. */
4733#define UCM_REG_USDM_WEIGHT 0xe00c8
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004734/* [RW 1] Input xsem Interface enable. If 0 - the valid input is
4735 disregarded; acknowledge output is deasserted; all other signals are
4736 treated as usual; if 1 - normal activity. */
4737#define UCM_REG_XSEM_IFEN 0xe002c
4738/* [RC 1] Set when the message length mismatch (relative to last indication)
4739 at the xsem interface isdetected. */
4740#define UCM_REG_XSEM_LENGTH_MIS 0xe0164
Eilon Greenstein8d9c5f32009-02-15 23:24:08 -08004741/* [RW 3] The weight of the input xsem in the WRR mechanism. 0 stands for
4742 weight 8 (the most prioritised); 1 stands for weight 1(least
4743 prioritised); 2 stands for weight 2; tc. */
4744#define UCM_REG_XSEM_WEIGHT 0xe00bc
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004745/* [RW 20] Indirect access to the descriptor table of the XX protection
4746 mechanism. The fields are:[5:0] - message length; 14:6] - message
4747 pointer; 19:15] - next pointer. */
4748#define UCM_REG_XX_DESCR_TABLE 0xe0280
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07004749#define UCM_REG_XX_DESCR_TABLE_SIZE 32
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004750/* [R 6] Use to read the XX protection Free counter. */
4751#define UCM_REG_XX_FREE 0xe016c
4752/* [RW 6] Initial value for the credit counter; responsible for fulfilling
4753 of the Input Stage XX protection buffer by the XX protection pending
4754 messages. Write writes the initial credit value; read returns the current
4755 value of the credit counter. Must be initialized to 12 at start-up. */
4756#define UCM_REG_XX_INIT_CRD 0xe0224
4757/* [RW 6] The maximum number of pending messages; which may be stored in XX
4758 protection. ~ucm_registers_xx_free.xx_free read on read. */
4759#define UCM_REG_XX_MSG_NUM 0xe0228
4760/* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */
4761#define UCM_REG_XX_OVFL_EVNT_ID 0xe004c
4762/* [RW 16] Indirect access to the XX table of the XX protection mechanism.
4763 The fields are: [4:0] - tail pointer; 10:5] - Link List size; 15:11] -
4764 header pointer. */
4765#define UCM_REG_XX_TABLE 0xe0300
Yaniv Rosner9380bb92011-06-14 01:34:07 +00004766#define UMAC_COMMAND_CONFIG_REG_LOOP_ENA (0x1<<15)
4767#define UMAC_COMMAND_CONFIG_REG_NO_LGTH_CHECK (0x1<<24)
4768#define UMAC_COMMAND_CONFIG_REG_PAD_EN (0x1<<5)
4769#define UMAC_COMMAND_CONFIG_REG_PROMIS_EN (0x1<<4)
4770#define UMAC_COMMAND_CONFIG_REG_RX_ENA (0x1<<1)
4771#define UMAC_COMMAND_CONFIG_REG_SW_RESET (0x1<<13)
4772#define UMAC_COMMAND_CONFIG_REG_TX_ENA (0x1<<0)
4773#define UMAC_REG_COMMAND_CONFIG 0x8
Yaniv Rosnerb8d6d082011-07-05 01:06:27 +00004774/* [RW 32] Register Bit 0 refers to Bit 16 of the MAC address; Bit 1 refers
4775 * to bit 17 of the MAC address etc. */
4776#define UMAC_REG_MAC_ADDR0 0xc
4777/* [RW 16] Register Bit 0 refers to Bit 0 of the MAC address; Register Bit 1
4778 * refers to Bit 1 of the MAC address etc. Bits 16 to 31 are reserved. */
4779#define UMAC_REG_MAC_ADDR1 0x10
Yaniv Rosner9380bb92011-06-14 01:34:07 +00004780/* [RW 14] Defines a 14-Bit maximum frame length used by the MAC receive
4781 * logic to check frames. */
4782#define UMAC_REG_MAXFR 0x14
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004783/* [RW 8] The event id for aggregated interrupt 0 */
4784#define USDM_REG_AGG_INT_EVENT_0 0xc4038
4785#define USDM_REG_AGG_INT_EVENT_1 0xc403c
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07004786#define USDM_REG_AGG_INT_EVENT_2 0xc4040
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07004787#define USDM_REG_AGG_INT_EVENT_4 0xc4048
Eilon Greenstein8d9c5f32009-02-15 23:24:08 -08004788#define USDM_REG_AGG_INT_EVENT_5 0xc404c
Eilon Greensteinca003922009-08-12 22:53:28 -07004789#define USDM_REG_AGG_INT_EVENT_6 0xc4050
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004790/* [RW 1] For each aggregated interrupt index whether the mode is normal (0)
4791 or auto-mask-mode (1) */
4792#define USDM_REG_AGG_INT_MODE_0 0xc41b8
4793#define USDM_REG_AGG_INT_MODE_1 0xc41bc
Eilon Greenstein8d9c5f32009-02-15 23:24:08 -08004794#define USDM_REG_AGG_INT_MODE_4 0xc41c8
4795#define USDM_REG_AGG_INT_MODE_5 0xc41cc
Eilon Greensteinca003922009-08-12 22:53:28 -07004796#define USDM_REG_AGG_INT_MODE_6 0xc41d0
4797/* [RW 1] The T bit for aggregated interrupt 5 */
4798#define USDM_REG_AGG_INT_T_5 0xc40cc
4799#define USDM_REG_AGG_INT_T_6 0xc40d0
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004800/* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */
4801#define USDM_REG_CFC_RSP_START_ADDR 0xc4008
Lucas De Marchi25985ed2011-03-30 22:57:33 -03004802/* [RW 16] The maximum value of the completion counter #0 */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004803#define USDM_REG_CMP_COUNTER_MAX0 0xc401c
Lucas De Marchi25985ed2011-03-30 22:57:33 -03004804/* [RW 16] The maximum value of the completion counter #1 */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004805#define USDM_REG_CMP_COUNTER_MAX1 0xc4020
Lucas De Marchi25985ed2011-03-30 22:57:33 -03004806/* [RW 16] The maximum value of the completion counter #2 */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004807#define USDM_REG_CMP_COUNTER_MAX2 0xc4024
Lucas De Marchi25985ed2011-03-30 22:57:33 -03004808/* [RW 16] The maximum value of the completion counter #3 */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004809#define USDM_REG_CMP_COUNTER_MAX3 0xc4028
4810/* [RW 13] The start address in the internal RAM for the completion
4811 counters. */
4812#define USDM_REG_CMP_COUNTER_START_ADDR 0xc400c
4813#define USDM_REG_ENABLE_IN1 0xc4238
4814#define USDM_REG_ENABLE_IN2 0xc423c
4815#define USDM_REG_ENABLE_OUT1 0xc4240
4816#define USDM_REG_ENABLE_OUT2 0xc4244
4817/* [RW 4] The initial number of messages that can be sent to the pxp control
4818 interface without receiving any ACK. */
4819#define USDM_REG_INIT_CREDIT_PXP_CTRL 0xc44c0
4820/* [ST 32] The number of ACK after placement messages received */
4821#define USDM_REG_NUM_OF_ACK_AFTER_PLACE 0xc4280
4822/* [ST 32] The number of packet end messages received from the parser */
4823#define USDM_REG_NUM_OF_PKT_END_MSG 0xc4278
4824/* [ST 32] The number of requests received from the pxp async if */
4825#define USDM_REG_NUM_OF_PXP_ASYNC_REQ 0xc427c
4826/* [ST 32] The number of commands received in queue 0 */
4827#define USDM_REG_NUM_OF_Q0_CMD 0xc4248
4828/* [ST 32] The number of commands received in queue 10 */
4829#define USDM_REG_NUM_OF_Q10_CMD 0xc4270
4830/* [ST 32] The number of commands received in queue 11 */
4831#define USDM_REG_NUM_OF_Q11_CMD 0xc4274
4832/* [ST 32] The number of commands received in queue 1 */
4833#define USDM_REG_NUM_OF_Q1_CMD 0xc424c
4834/* [ST 32] The number of commands received in queue 2 */
4835#define USDM_REG_NUM_OF_Q2_CMD 0xc4250
4836/* [ST 32] The number of commands received in queue 3 */
4837#define USDM_REG_NUM_OF_Q3_CMD 0xc4254
4838/* [ST 32] The number of commands received in queue 4 */
4839#define USDM_REG_NUM_OF_Q4_CMD 0xc4258
4840/* [ST 32] The number of commands received in queue 5 */
4841#define USDM_REG_NUM_OF_Q5_CMD 0xc425c
4842/* [ST 32] The number of commands received in queue 6 */
4843#define USDM_REG_NUM_OF_Q6_CMD 0xc4260
4844/* [ST 32] The number of commands received in queue 7 */
4845#define USDM_REG_NUM_OF_Q7_CMD 0xc4264
4846/* [ST 32] The number of commands received in queue 8 */
4847#define USDM_REG_NUM_OF_Q8_CMD 0xc4268
4848/* [ST 32] The number of commands received in queue 9 */
4849#define USDM_REG_NUM_OF_Q9_CMD 0xc426c
4850/* [RW 13] The start address in the internal RAM for the packet end message */
4851#define USDM_REG_PCK_END_MSG_START_ADDR 0xc4014
4852/* [RW 13] The start address in the internal RAM for queue counters */
4853#define USDM_REG_Q_COUNTER_START_ADDR 0xc4010
4854/* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */
4855#define USDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0xc4550
4856/* [R 1] parser fifo empty in sdm_sync block */
4857#define USDM_REG_SYNC_PARSER_EMPTY 0xc4558
4858/* [R 1] parser serial fifo empty in sdm_sync block */
4859#define USDM_REG_SYNC_SYNC_EMPTY 0xc4560
4860/* [RW 32] Tick for timer counter. Applicable only when
4861 ~usdm_registers_timer_tick_enable.timer_tick_enable =1 */
4862#define USDM_REG_TIMER_TICK 0xc4000
4863/* [RW 32] Interrupt mask register #0 read/write */
4864#define USDM_REG_USDM_INT_MASK_0 0xc42a0
4865#define USDM_REG_USDM_INT_MASK_1 0xc42b0
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07004866/* [R 32] Interrupt register #0 read */
4867#define USDM_REG_USDM_INT_STS_0 0xc4294
4868#define USDM_REG_USDM_INT_STS_1 0xc42a4
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004869/* [RW 11] Parity mask register #0 read/write */
4870#define USDM_REG_USDM_PRTY_MASK 0xc42c0
Eliezer Tamirf1410642008-02-28 11:51:50 -08004871/* [R 11] Parity register #0 read */
4872#define USDM_REG_USDM_PRTY_STS 0xc42b4
Vladislav Zolotarov4a33bc02011-01-09 02:20:04 +00004873/* [RC 11] Parity register #0 read clear */
4874#define USDM_REG_USDM_PRTY_STS_CLR 0xc42b8
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004875/* [RW 5] The number of time_slots in the arbitration cycle */
4876#define USEM_REG_ARB_CYCLE_SIZE 0x300034
4877/* [RW 3] The source that is associated with arbitration element 0. Source
4878 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4879 sleeping thread with priority 1; 4- sleeping thread with priority 2 */
4880#define USEM_REG_ARB_ELEMENT0 0x300020
4881/* [RW 3] The source that is associated with arbitration element 1. Source
4882 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4883 sleeping thread with priority 1; 4- sleeping thread with priority 2.
4884 Could not be equal to register ~usem_registers_arb_element0.arb_element0 */
4885#define USEM_REG_ARB_ELEMENT1 0x300024
4886/* [RW 3] The source that is associated with arbitration element 2. Source
4887 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4888 sleeping thread with priority 1; 4- sleeping thread with priority 2.
4889 Could not be equal to register ~usem_registers_arb_element0.arb_element0
4890 and ~usem_registers_arb_element1.arb_element1 */
4891#define USEM_REG_ARB_ELEMENT2 0x300028
4892/* [RW 3] The source that is associated with arbitration element 3. Source
4893 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4894 sleeping thread with priority 1; 4- sleeping thread with priority 2.Could
4895 not be equal to register ~usem_registers_arb_element0.arb_element0 and
4896 ~usem_registers_arb_element1.arb_element1 and
4897 ~usem_registers_arb_element2.arb_element2 */
4898#define USEM_REG_ARB_ELEMENT3 0x30002c
4899/* [RW 3] The source that is associated with arbitration element 4. Source
4900 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4901 sleeping thread with priority 1; 4- sleeping thread with priority 2.
4902 Could not be equal to register ~usem_registers_arb_element0.arb_element0
4903 and ~usem_registers_arb_element1.arb_element1 and
4904 ~usem_registers_arb_element2.arb_element2 and
4905 ~usem_registers_arb_element3.arb_element3 */
4906#define USEM_REG_ARB_ELEMENT4 0x300030
4907#define USEM_REG_ENABLE_IN 0x3000a4
4908#define USEM_REG_ENABLE_OUT 0x3000a8
4909/* [RW 32] This address space contains all registers and memories that are
4910 placed in SEM_FAST block. The SEM_FAST registers are described in
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07004911 appendix B. In order to access the sem_fast registers the base address
4912 ~fast_memory.fast_memory should be added to eachsem_fast register offset. */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004913#define USEM_REG_FAST_MEMORY 0x320000
4914/* [RW 1] Disables input messages from FIC0 May be updated during run_time
4915 by the microcode */
4916#define USEM_REG_FIC0_DISABLE 0x300224
4917/* [RW 1] Disables input messages from FIC1 May be updated during run_time
4918 by the microcode */
4919#define USEM_REG_FIC1_DISABLE 0x300234
4920/* [RW 15] Interrupt table Read and write access to it is not possible in
4921 the middle of the work */
4922#define USEM_REG_INT_TABLE 0x300400
4923/* [ST 24] Statistics register. The number of messages that entered through
4924 FIC0 */
4925#define USEM_REG_MSG_NUM_FIC0 0x300000
4926/* [ST 24] Statistics register. The number of messages that entered through
4927 FIC1 */
4928#define USEM_REG_MSG_NUM_FIC1 0x300004
4929/* [ST 24] Statistics register. The number of messages that were sent to
4930 FOC0 */
4931#define USEM_REG_MSG_NUM_FOC0 0x300008
4932/* [ST 24] Statistics register. The number of messages that were sent to
4933 FOC1 */
4934#define USEM_REG_MSG_NUM_FOC1 0x30000c
4935/* [ST 24] Statistics register. The number of messages that were sent to
4936 FOC2 */
4937#define USEM_REG_MSG_NUM_FOC2 0x300010
4938/* [ST 24] Statistics register. The number of messages that were sent to
4939 FOC3 */
4940#define USEM_REG_MSG_NUM_FOC3 0x300014
4941/* [RW 1] Disables input messages from the passive buffer May be updated
4942 during run_time by the microcode */
4943#define USEM_REG_PAS_DISABLE 0x30024c
4944/* [WB 128] Debug only. Passive buffer memory */
4945#define USEM_REG_PASSIVE_BUFFER 0x302000
4946/* [WB 46] pram memory. B45 is parity; b[44:0] - data. */
4947#define USEM_REG_PRAM 0x340000
4948/* [R 16] Valid sleeping threads indication have bit per thread */
4949#define USEM_REG_SLEEP_THREADS_VALID 0x30026c
4950/* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */
4951#define USEM_REG_SLOW_EXT_STORE_EMPTY 0x3002a0
4952/* [RW 16] List of free threads . There is a bit per thread. */
4953#define USEM_REG_THREADS_LIST 0x3002e4
4954/* [RW 3] The arbitration scheme of time_slot 0 */
4955#define USEM_REG_TS_0_AS 0x300038
4956/* [RW 3] The arbitration scheme of time_slot 10 */
4957#define USEM_REG_TS_10_AS 0x300060
4958/* [RW 3] The arbitration scheme of time_slot 11 */
4959#define USEM_REG_TS_11_AS 0x300064
4960/* [RW 3] The arbitration scheme of time_slot 12 */
4961#define USEM_REG_TS_12_AS 0x300068
4962/* [RW 3] The arbitration scheme of time_slot 13 */
4963#define USEM_REG_TS_13_AS 0x30006c
4964/* [RW 3] The arbitration scheme of time_slot 14 */
4965#define USEM_REG_TS_14_AS 0x300070
4966/* [RW 3] The arbitration scheme of time_slot 15 */
4967#define USEM_REG_TS_15_AS 0x300074
4968/* [RW 3] The arbitration scheme of time_slot 16 */
4969#define USEM_REG_TS_16_AS 0x300078
4970/* [RW 3] The arbitration scheme of time_slot 17 */
4971#define USEM_REG_TS_17_AS 0x30007c
4972/* [RW 3] The arbitration scheme of time_slot 18 */
4973#define USEM_REG_TS_18_AS 0x300080
4974/* [RW 3] The arbitration scheme of time_slot 1 */
4975#define USEM_REG_TS_1_AS 0x30003c
4976/* [RW 3] The arbitration scheme of time_slot 2 */
4977#define USEM_REG_TS_2_AS 0x300040
4978/* [RW 3] The arbitration scheme of time_slot 3 */
4979#define USEM_REG_TS_3_AS 0x300044
4980/* [RW 3] The arbitration scheme of time_slot 4 */
4981#define USEM_REG_TS_4_AS 0x300048
4982/* [RW 3] The arbitration scheme of time_slot 5 */
4983#define USEM_REG_TS_5_AS 0x30004c
4984/* [RW 3] The arbitration scheme of time_slot 6 */
4985#define USEM_REG_TS_6_AS 0x300050
4986/* [RW 3] The arbitration scheme of time_slot 7 */
4987#define USEM_REG_TS_7_AS 0x300054
4988/* [RW 3] The arbitration scheme of time_slot 8 */
4989#define USEM_REG_TS_8_AS 0x300058
4990/* [RW 3] The arbitration scheme of time_slot 9 */
4991#define USEM_REG_TS_9_AS 0x30005c
4992/* [RW 32] Interrupt mask register #0 read/write */
4993#define USEM_REG_USEM_INT_MASK_0 0x300110
4994#define USEM_REG_USEM_INT_MASK_1 0x300120
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07004995/* [R 32] Interrupt register #0 read */
4996#define USEM_REG_USEM_INT_STS_0 0x300104
4997#define USEM_REG_USEM_INT_STS_1 0x300114
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004998/* [RW 32] Parity mask register #0 read/write */
4999#define USEM_REG_USEM_PRTY_MASK_0 0x300130
5000#define USEM_REG_USEM_PRTY_MASK_1 0x300140
Eliezer Tamirf1410642008-02-28 11:51:50 -08005001/* [R 32] Parity register #0 read */
5002#define USEM_REG_USEM_PRTY_STS_0 0x300124
5003#define USEM_REG_USEM_PRTY_STS_1 0x300134
Vladislav Zolotarov4a33bc02011-01-09 02:20:04 +00005004/* [RC 32] Parity register #0 read clear */
5005#define USEM_REG_USEM_PRTY_STS_CLR_0 0x300128
5006#define USEM_REG_USEM_PRTY_STS_CLR_1 0x300138
Dmitry Kravkovf2e08992010-10-06 03:28:26 +00005007/* [W 7] VF or PF ID for reset error bit. Values 0-63 reset error bit for 64
5008 * VF; values 64-67 reset error for 4 PF; values 68-127 are not valid. */
5009#define USEM_REG_VFPF_ERR_NUM 0x300380
5010#define VFC_MEMORIES_RST_REG_CAM_RST (0x1<<0)
5011#define VFC_MEMORIES_RST_REG_RAM_RST (0x1<<1)
5012#define VFC_REG_MEMORIES_RST 0x1943c
5013/* [RW 32] Indirect access to AG context with 32-bits granularity. The bits
5014 * [12:8] of the address should be the offset within the accessed LCID
5015 * context; the bits [7:0] are the accessed LCID.Example: to write to REG10
5016 * LCID100. The RBC address should be 13'ha64. */
5017#define XCM_REG_AG_CTX 0x28000
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005018/* [RW 2] The queue index for registration on Aux1 counter flag. */
5019#define XCM_REG_AUX1_Q 0x20134
5020/* [RW 2] Per each decision rule the queue index to register to. */
5021#define XCM_REG_AUX_CNT_FLG_Q_19 0x201b0
5022/* [R 5] Used to read the XX protection CAM occupancy counter. */
5023#define XCM_REG_CAM_OCCUP 0x20244
5024/* [RW 1] CDU AG read Interface enable. If 0 - the request input is
5025 disregarded; valid output is deasserted; all other signals are treated as
5026 usual; if 1 - normal activity. */
5027#define XCM_REG_CDU_AG_RD_IFEN 0x20044
5028/* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input
5029 are disregarded; all other signals are treated as usual; if 1 - normal
5030 activity. */
5031#define XCM_REG_CDU_AG_WR_IFEN 0x20040
5032/* [RW 1] CDU STORM read Interface enable. If 0 - the request input is
5033 disregarded; valid output is deasserted; all other signals are treated as
5034 usual; if 1 - normal activity. */
5035#define XCM_REG_CDU_SM_RD_IFEN 0x2004c
5036/* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid
5037 input is disregarded; all other signals are treated as usual; if 1 -
5038 normal activity. */
5039#define XCM_REG_CDU_SM_WR_IFEN 0x20048
5040/* [RW 4] CFC output initial credit. Max credit available - 15.Write writes
5041 the initial credit value; read returns the current value of the credit
5042 counter. Must be initialized to 1 at start-up. */
5043#define XCM_REG_CFC_INIT_CRD 0x20404
5044/* [RW 3] The weight of the CP input in the WRR mechanism. 0 stands for
5045 weight 8 (the most prioritised); 1 stands for weight 1(least
5046 prioritised); 2 stands for weight 2; tc. */
5047#define XCM_REG_CP_WEIGHT 0x200dc
5048/* [RW 1] Input csem Interface enable. If 0 - the valid input is
5049 disregarded; acknowledge output is deasserted; all other signals are
5050 treated as usual; if 1 - normal activity. */
5051#define XCM_REG_CSEM_IFEN 0x20028
5052/* [RC 1] Set at message length mismatch (relative to last indication) at
5053 the csem interface. */
5054#define XCM_REG_CSEM_LENGTH_MIS 0x20228
5055/* [RW 3] The weight of the input csem in the WRR mechanism. 0 stands for
5056 weight 8 (the most prioritised); 1 stands for weight 1(least
5057 prioritised); 2 stands for weight 2; tc. */
5058#define XCM_REG_CSEM_WEIGHT 0x200c4
5059/* [RW 1] Input dorq Interface enable. If 0 - the valid input is
5060 disregarded; acknowledge output is deasserted; all other signals are
5061 treated as usual; if 1 - normal activity. */
5062#define XCM_REG_DORQ_IFEN 0x20030
5063/* [RC 1] Set at message length mismatch (relative to last indication) at
5064 the dorq interface. */
5065#define XCM_REG_DORQ_LENGTH_MIS 0x20230
Eilon Greenstein8d9c5f32009-02-15 23:24:08 -08005066/* [RW 3] The weight of the input dorq in the WRR mechanism. 0 stands for
5067 weight 8 (the most prioritised); 1 stands for weight 1(least
5068 prioritised); 2 stands for weight 2; tc. */
5069#define XCM_REG_DORQ_WEIGHT 0x200cc
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005070/* [RW 8] The Event ID in case the ErrorFlg input message bit is set. */
5071#define XCM_REG_ERR_EVNT_ID 0x200b0
5072/* [RW 28] The CM erroneous header for QM and Timers formatting. */
5073#define XCM_REG_ERR_XCM_HDR 0x200ac
5074/* [RW 8] The Event ID for Timers expiration. */
5075#define XCM_REG_EXPR_EVNT_ID 0x200b4
5076/* [RW 8] FIC0 output initial credit. Max credit available - 255.Write
5077 writes the initial credit value; read returns the current value of the
5078 credit counter. Must be initialized to 64 at start-up. */
5079#define XCM_REG_FIC0_INIT_CRD 0x2040c
5080/* [RW 8] FIC1 output initial credit. Max credit available - 255.Write
5081 writes the initial credit value; read returns the current value of the
5082 credit counter. Must be initialized to 64 at start-up. */
5083#define XCM_REG_FIC1_INIT_CRD 0x20410
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005084#define XCM_REG_GLB_DEL_ACK_MAX_CNT_0 0x20118
5085#define XCM_REG_GLB_DEL_ACK_MAX_CNT_1 0x2011c
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005086#define XCM_REG_GLB_DEL_ACK_TMR_VAL_0 0x20108
5087#define XCM_REG_GLB_DEL_ACK_TMR_VAL_1 0x2010c
5088/* [RW 1] Arbitratiojn between Input Arbiter groups: 0 - fair Round-Robin; 1
5089 - strict priority defined by ~xcm_registers_gr_ag_pr.gr_ag_pr;
5090 ~xcm_registers_gr_ld0_pr.gr_ld0_pr and
5091 ~xcm_registers_gr_ld1_pr.gr_ld1_pr. */
5092#define XCM_REG_GR_ARB_TYPE 0x2020c
5093/* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the
5094 highest priority is 3. It is supposed that the Channel group is the
5095 compliment of the other 3 groups. */
5096#define XCM_REG_GR_LD0_PR 0x20214
5097/* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the
5098 highest priority is 3. It is supposed that the Channel group is the
5099 compliment of the other 3 groups. */
5100#define XCM_REG_GR_LD1_PR 0x20218
5101/* [RW 1] Input nig0 Interface enable. If 0 - the valid input is
5102 disregarded; acknowledge output is deasserted; all other signals are
5103 treated as usual; if 1 - normal activity. */
5104#define XCM_REG_NIG0_IFEN 0x20038
5105/* [RC 1] Set at message length mismatch (relative to last indication) at
5106 the nig0 interface. */
5107#define XCM_REG_NIG0_LENGTH_MIS 0x20238
Eilon Greenstein8d9c5f32009-02-15 23:24:08 -08005108/* [RW 3] The weight of the input nig0 in the WRR mechanism. 0 stands for
5109 weight 8 (the most prioritised); 1 stands for weight 1(least
5110 prioritised); 2 stands for weight 2; tc. */
5111#define XCM_REG_NIG0_WEIGHT 0x200d4
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005112/* [RW 1] Input nig1 Interface enable. If 0 - the valid input is
5113 disregarded; acknowledge output is deasserted; all other signals are
5114 treated as usual; if 1 - normal activity. */
5115#define XCM_REG_NIG1_IFEN 0x2003c
5116/* [RC 1] Set at message length mismatch (relative to last indication) at
5117 the nig1 interface. */
5118#define XCM_REG_NIG1_LENGTH_MIS 0x2023c
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005119/* [RW 5] The number of double REG-pairs; loaded from the STORM context and
5120 sent to STORM; for a specific connection type. The double REG-pairs are
5121 used in order to align to STORM context row size of 128 bits. The offset
5122 of these data in the STORM context is always 0. Index _i stands for the
5123 connection type (one of 16). */
5124#define XCM_REG_N_SM_CTX_LD_0 0x20060
5125#define XCM_REG_N_SM_CTX_LD_1 0x20064
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005126#define XCM_REG_N_SM_CTX_LD_2 0x20068
5127#define XCM_REG_N_SM_CTX_LD_3 0x2006c
5128#define XCM_REG_N_SM_CTX_LD_4 0x20070
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07005129#define XCM_REG_N_SM_CTX_LD_5 0x20074
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005130/* [RW 1] Input pbf Interface enable. If 0 - the valid input is disregarded;
5131 acknowledge output is deasserted; all other signals are treated as usual;
5132 if 1 - normal activity. */
5133#define XCM_REG_PBF_IFEN 0x20034
5134/* [RC 1] Set at message length mismatch (relative to last indication) at
5135 the pbf interface. */
5136#define XCM_REG_PBF_LENGTH_MIS 0x20234
5137/* [RW 3] The weight of the input pbf in the WRR mechanism. 0 stands for
5138 weight 8 (the most prioritised); 1 stands for weight 1(least
5139 prioritised); 2 stands for weight 2; tc. */
5140#define XCM_REG_PBF_WEIGHT 0x200d0
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07005141#define XCM_REG_PHYS_QNUM3_0 0x20100
5142#define XCM_REG_PHYS_QNUM3_1 0x20104
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005143/* [RW 8] The Event ID for Timers formatting in case of stop done. */
5144#define XCM_REG_STOP_EVNT_ID 0x200b8
5145/* [RC 1] Set at message length mismatch (relative to last indication) at
5146 the STORM interface. */
5147#define XCM_REG_STORM_LENGTH_MIS 0x2021c
5148/* [RW 3] The weight of the STORM input in the WRR mechanism. 0 stands for
5149 weight 8 (the most prioritised); 1 stands for weight 1(least
5150 prioritised); 2 stands for weight 2; tc. */
5151#define XCM_REG_STORM_WEIGHT 0x200bc
5152/* [RW 1] STORM - CM Interface enable. If 0 - the valid input is
5153 disregarded; acknowledge output is deasserted; all other signals are
5154 treated as usual; if 1 - normal activity. */
5155#define XCM_REG_STORM_XCM_IFEN 0x20010
5156/* [RW 4] Timers output initial credit. Max credit available - 15.Write
5157 writes the initial credit value; read returns the current value of the
5158 credit counter. Must be initialized to 4 at start-up. */
5159#define XCM_REG_TM_INIT_CRD 0x2041c
Eilon Greenstein8d9c5f32009-02-15 23:24:08 -08005160/* [RW 3] The weight of the Timers input in the WRR mechanism. 0 stands for
5161 weight 8 (the most prioritised); 1 stands for weight 1(least
5162 prioritised); 2 stands for weight 2; tc. */
5163#define XCM_REG_TM_WEIGHT 0x200ec
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005164/* [RW 28] The CM header for Timers expiration command. */
5165#define XCM_REG_TM_XCM_HDR 0x200a8
5166/* [RW 1] Timers - CM Interface enable. If 0 - the valid input is
5167 disregarded; acknowledge output is deasserted; all other signals are
5168 treated as usual; if 1 - normal activity. */
5169#define XCM_REG_TM_XCM_IFEN 0x2001c
5170/* [RW 1] Input tsem Interface enable. If 0 - the valid input is
5171 disregarded; acknowledge output is deasserted; all other signals are
5172 treated as usual; if 1 - normal activity. */
5173#define XCM_REG_TSEM_IFEN 0x20024
5174/* [RC 1] Set at message length mismatch (relative to last indication) at
5175 the tsem interface. */
5176#define XCM_REG_TSEM_LENGTH_MIS 0x20224
5177/* [RW 3] The weight of the input tsem in the WRR mechanism. 0 stands for
5178 weight 8 (the most prioritised); 1 stands for weight 1(least
5179 prioritised); 2 stands for weight 2; tc. */
5180#define XCM_REG_TSEM_WEIGHT 0x200c0
5181/* [RW 2] The queue index for registration on UNA greater NXT decision rule. */
5182#define XCM_REG_UNA_GT_NXT_Q 0x20120
5183/* [RW 1] Input usem Interface enable. If 0 - the valid input is
5184 disregarded; acknowledge output is deasserted; all other signals are
5185 treated as usual; if 1 - normal activity. */
5186#define XCM_REG_USEM_IFEN 0x2002c
5187/* [RC 1] Message length mismatch (relative to last indication) at the usem
5188 interface. */
5189#define XCM_REG_USEM_LENGTH_MIS 0x2022c
5190/* [RW 3] The weight of the input usem in the WRR mechanism. 0 stands for
5191 weight 8 (the most prioritised); 1 stands for weight 1(least
5192 prioritised); 2 stands for weight 2; tc. */
5193#define XCM_REG_USEM_WEIGHT 0x200c8
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005194#define XCM_REG_WU_DA_CNT_CMD00 0x201d4
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005195#define XCM_REG_WU_DA_CNT_CMD01 0x201d8
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005196#define XCM_REG_WU_DA_CNT_CMD10 0x201dc
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005197#define XCM_REG_WU_DA_CNT_CMD11 0x201e0
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005198#define XCM_REG_WU_DA_CNT_UPD_VAL00 0x201e4
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005199#define XCM_REG_WU_DA_CNT_UPD_VAL01 0x201e8
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005200#define XCM_REG_WU_DA_CNT_UPD_VAL10 0x201ec
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005201#define XCM_REG_WU_DA_CNT_UPD_VAL11 0x201f0
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005202#define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00 0x201c4
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005203#define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD01 0x201c8
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005204#define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD10 0x201cc
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005205#define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD11 0x201d0
5206/* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded;
5207 acknowledge output is deasserted; all other signals are treated as usual;
5208 if 1 - normal activity. */
5209#define XCM_REG_XCM_CFC_IFEN 0x20050
5210/* [RW 14] Interrupt mask register #0 read/write */
5211#define XCM_REG_XCM_INT_MASK 0x202b4
5212/* [R 14] Interrupt register #0 read */
5213#define XCM_REG_XCM_INT_STS 0x202a8
Vladislav Zolotarovc9ee9202011-06-14 01:33:51 +00005214/* [RW 30] Parity mask register #0 read/write */
5215#define XCM_REG_XCM_PRTY_MASK 0x202c4
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07005216/* [R 30] Parity register #0 read */
5217#define XCM_REG_XCM_PRTY_STS 0x202b8
Vladislav Zolotarovc9ee9202011-06-14 01:33:51 +00005218/* [RC 30] Parity register #0 read clear */
5219#define XCM_REG_XCM_PRTY_STS_CLR 0x202bc
5220
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005221/* [RW 4] The size of AG context region 0 in REG-pairs. Designates the MS
5222 REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5).
5223 Is used to determine the number of the AG context REG-pairs written back;
5224 when the Reg1WbFlg isn't set. */
5225#define XCM_REG_XCM_REG0_SZ 0x200f4
5226/* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is
5227 disregarded; valid is deasserted; all other signals are treated as usual;
5228 if 1 - normal activity. */
5229#define XCM_REG_XCM_STORM0_IFEN 0x20004
5230/* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is
5231 disregarded; valid is deasserted; all other signals are treated as usual;
5232 if 1 - normal activity. */
5233#define XCM_REG_XCM_STORM1_IFEN 0x20008
5234/* [RW 1] CM - Timers Interface enable. If 0 - the valid input is
5235 disregarded; acknowledge output is deasserted; all other signals are
5236 treated as usual; if 1 - normal activity. */
5237#define XCM_REG_XCM_TM_IFEN 0x20020
5238/* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is
5239 disregarded; valid is deasserted; all other signals are treated as usual;
5240 if 1 - normal activity. */
5241#define XCM_REG_XCM_XQM_IFEN 0x2000c
5242/* [RW 1] If set the Q index; received from the QM is inserted to event ID. */
5243#define XCM_REG_XCM_XQM_USE_Q 0x200f0
5244/* [RW 4] The value by which CFC updates the activity counter at QM bypass. */
5245#define XCM_REG_XQM_BYP_ACT_UPD 0x200fc
5246/* [RW 6] QM output initial credit. Max credit available - 32.Write writes
5247 the initial credit value; read returns the current value of the credit
5248 counter. Must be initialized to 32 at start-up. */
5249#define XCM_REG_XQM_INIT_CRD 0x20420
5250/* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0
5251 stands for weight 8 (the most prioritised); 1 stands for weight 1(least
5252 prioritised); 2 stands for weight 2; tc. */
5253#define XCM_REG_XQM_P_WEIGHT 0x200e4
Eilon Greenstein8d9c5f32009-02-15 23:24:08 -08005254/* [RW 3] The weight of the QM (secondary) input in the WRR mechanism. 0
5255 stands for weight 8 (the most prioritised); 1 stands for weight 1(least
5256 prioritised); 2 stands for weight 2; tc. */
5257#define XCM_REG_XQM_S_WEIGHT 0x200e8
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005258/* [RW 28] The CM header value for QM request (primary). */
5259#define XCM_REG_XQM_XCM_HDR_P 0x200a0
5260/* [RW 28] The CM header value for QM request (secondary). */
5261#define XCM_REG_XQM_XCM_HDR_S 0x200a4
5262/* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded;
5263 acknowledge output is deasserted; all other signals are treated as usual;
5264 if 1 - normal activity. */
5265#define XCM_REG_XQM_XCM_IFEN 0x20014
5266/* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded;
5267 acknowledge output is deasserted; all other signals are treated as usual;
5268 if 1 - normal activity. */
5269#define XCM_REG_XSDM_IFEN 0x20018
5270/* [RC 1] Set at message length mismatch (relative to last indication) at
5271 the SDM interface. */
5272#define XCM_REG_XSDM_LENGTH_MIS 0x20220
5273/* [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands for
5274 weight 8 (the most prioritised); 1 stands for weight 1(least
5275 prioritised); 2 stands for weight 2; tc. */
5276#define XCM_REG_XSDM_WEIGHT 0x200e0
5277/* [RW 17] Indirect access to the descriptor table of the XX protection
5278 mechanism. The fields are: [5:0] - message length; 11:6] - message
5279 pointer; 16:12] - next pointer. */
5280#define XCM_REG_XX_DESCR_TABLE 0x20480
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07005281#define XCM_REG_XX_DESCR_TABLE_SIZE 32
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005282/* [R 6] Used to read the XX protection Free counter. */
5283#define XCM_REG_XX_FREE 0x20240
5284/* [RW 6] Initial value for the credit counter; responsible for fulfilling
5285 of the Input Stage XX protection buffer by the XX protection pending
5286 messages. Max credit available - 3.Write writes the initial credit value;
5287 read returns the current value of the credit counter. Must be initialized
5288 to 2 at start-up. */
5289#define XCM_REG_XX_INIT_CRD 0x20424
5290/* [RW 6] The maximum number of pending messages; which may be stored in XX
5291 protection. ~xcm_registers_xx_free.xx_free read on read. */
5292#define XCM_REG_XX_MSG_NUM 0x20428
5293/* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */
5294#define XCM_REG_XX_OVFL_EVNT_ID 0x20058
Yaniv Rosner9380bb92011-06-14 01:34:07 +00005295#define XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS (0x1<<0)
5296#define XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS (0x1<<1)
5297#define XMAC_CTRL_REG_CORE_LOCAL_LPBK (0x1<<3)
5298#define XMAC_CTRL_REG_RX_EN (0x1<<1)
5299#define XMAC_CTRL_REG_SOFT_RESET (0x1<<6)
5300#define XMAC_CTRL_REG_TX_EN (0x1<<0)
5301#define XMAC_PAUSE_CTRL_REG_RX_PAUSE_EN (0x1<<18)
5302#define XMAC_PAUSE_CTRL_REG_TX_PAUSE_EN (0x1<<17)
5303#define XMAC_PFC_CTRL_HI_REG_PFC_REFRESH_EN (0x1<<0)
5304#define XMAC_PFC_CTRL_HI_REG_PFC_STATS_EN (0x1<<3)
5305#define XMAC_PFC_CTRL_HI_REG_RX_PFC_EN (0x1<<4)
5306#define XMAC_PFC_CTRL_HI_REG_TX_PFC_EN (0x1<<5)
5307#define XMAC_REG_CLEAR_RX_LSS_STATUS 0x60
5308#define XMAC_REG_CTRL 0
Yaniv Rosnerb8d6d082011-07-05 01:06:27 +00005309/* [RW 16] Upper 48 bits of ctrl_sa register. Used as the SA in PAUSE/PFC
5310 * packets transmitted by the MAC */
5311#define XMAC_REG_CTRL_SA_HI 0x2c
5312/* [RW 32] Lower 48 bits of ctrl_sa register. Used as the SA in PAUSE/PFC
5313 * packets transmitted by the MAC */
5314#define XMAC_REG_CTRL_SA_LO 0x28
Yaniv Rosner9380bb92011-06-14 01:34:07 +00005315#define XMAC_REG_PAUSE_CTRL 0x68
5316#define XMAC_REG_PFC_CTRL 0x70
5317#define XMAC_REG_PFC_CTRL_HI 0x74
5318#define XMAC_REG_RX_LSS_STATUS 0x58
5319/* [RW 14] Maximum packet size in receive direction; exclusive of preamble &
5320 * CRC in strip mode */
5321#define XMAC_REG_RX_MAX_SIZE 0x40
5322#define XMAC_REG_TX_CTRL 0x20
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07005323/* [RW 16] Indirect access to the XX table of the XX protection mechanism.
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005324 The fields are:[4:0] - tail pointer; 9:5] - Link List size; 14:10] -
5325 header pointer. */
5326#define XCM_REG_XX_TABLE 0x20500
5327/* [RW 8] The event id for aggregated interrupt 0 */
5328#define XSDM_REG_AGG_INT_EVENT_0 0x166038
5329#define XSDM_REG_AGG_INT_EVENT_1 0x16603c
5330#define XSDM_REG_AGG_INT_EVENT_10 0x166060
5331#define XSDM_REG_AGG_INT_EVENT_11 0x166064
5332#define XSDM_REG_AGG_INT_EVENT_12 0x166068
5333#define XSDM_REG_AGG_INT_EVENT_13 0x16606c
5334#define XSDM_REG_AGG_INT_EVENT_14 0x166070
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005335#define XSDM_REG_AGG_INT_EVENT_2 0x166040
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07005336#define XSDM_REG_AGG_INT_EVENT_3 0x166044
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07005337#define XSDM_REG_AGG_INT_EVENT_4 0x166048
5338#define XSDM_REG_AGG_INT_EVENT_5 0x16604c
5339#define XSDM_REG_AGG_INT_EVENT_6 0x166050
5340#define XSDM_REG_AGG_INT_EVENT_7 0x166054
5341#define XSDM_REG_AGG_INT_EVENT_8 0x166058
5342#define XSDM_REG_AGG_INT_EVENT_9 0x16605c
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005343/* [RW 1] For each aggregated interrupt index whether the mode is normal (0)
5344 or auto-mask-mode (1) */
5345#define XSDM_REG_AGG_INT_MODE_0 0x1661b8
5346#define XSDM_REG_AGG_INT_MODE_1 0x1661bc
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005347/* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */
5348#define XSDM_REG_CFC_RSP_START_ADDR 0x166008
Lucas De Marchi25985ed2011-03-30 22:57:33 -03005349/* [RW 16] The maximum value of the completion counter #0 */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005350#define XSDM_REG_CMP_COUNTER_MAX0 0x16601c
Lucas De Marchi25985ed2011-03-30 22:57:33 -03005351/* [RW 16] The maximum value of the completion counter #1 */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005352#define XSDM_REG_CMP_COUNTER_MAX1 0x166020
Lucas De Marchi25985ed2011-03-30 22:57:33 -03005353/* [RW 16] The maximum value of the completion counter #2 */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005354#define XSDM_REG_CMP_COUNTER_MAX2 0x166024
Lucas De Marchi25985ed2011-03-30 22:57:33 -03005355/* [RW 16] The maximum value of the completion counter #3 */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005356#define XSDM_REG_CMP_COUNTER_MAX3 0x166028
5357/* [RW 13] The start address in the internal RAM for the completion
5358 counters. */
5359#define XSDM_REG_CMP_COUNTER_START_ADDR 0x16600c
5360#define XSDM_REG_ENABLE_IN1 0x166238
5361#define XSDM_REG_ENABLE_IN2 0x16623c
5362#define XSDM_REG_ENABLE_OUT1 0x166240
5363#define XSDM_REG_ENABLE_OUT2 0x166244
5364/* [RW 4] The initial number of messages that can be sent to the pxp control
5365 interface without receiving any ACK. */
5366#define XSDM_REG_INIT_CREDIT_PXP_CTRL 0x1664bc
5367/* [ST 32] The number of ACK after placement messages received */
5368#define XSDM_REG_NUM_OF_ACK_AFTER_PLACE 0x16627c
5369/* [ST 32] The number of packet end messages received from the parser */
5370#define XSDM_REG_NUM_OF_PKT_END_MSG 0x166274
5371/* [ST 32] The number of requests received from the pxp async if */
5372#define XSDM_REG_NUM_OF_PXP_ASYNC_REQ 0x166278
5373/* [ST 32] The number of commands received in queue 0 */
5374#define XSDM_REG_NUM_OF_Q0_CMD 0x166248
5375/* [ST 32] The number of commands received in queue 10 */
5376#define XSDM_REG_NUM_OF_Q10_CMD 0x16626c
5377/* [ST 32] The number of commands received in queue 11 */
5378#define XSDM_REG_NUM_OF_Q11_CMD 0x166270
5379/* [ST 32] The number of commands received in queue 1 */
5380#define XSDM_REG_NUM_OF_Q1_CMD 0x16624c
5381/* [ST 32] The number of commands received in queue 3 */
5382#define XSDM_REG_NUM_OF_Q3_CMD 0x166250
5383/* [ST 32] The number of commands received in queue 4 */
5384#define XSDM_REG_NUM_OF_Q4_CMD 0x166254
5385/* [ST 32] The number of commands received in queue 5 */
5386#define XSDM_REG_NUM_OF_Q5_CMD 0x166258
5387/* [ST 32] The number of commands received in queue 6 */
5388#define XSDM_REG_NUM_OF_Q6_CMD 0x16625c
5389/* [ST 32] The number of commands received in queue 7 */
5390#define XSDM_REG_NUM_OF_Q7_CMD 0x166260
5391/* [ST 32] The number of commands received in queue 8 */
5392#define XSDM_REG_NUM_OF_Q8_CMD 0x166264
5393/* [ST 32] The number of commands received in queue 9 */
5394#define XSDM_REG_NUM_OF_Q9_CMD 0x166268
Yaniv Rosner9380bb92011-06-14 01:34:07 +00005395/* [RW 13] The start address in the internal RAM for queue counters */
5396#define XSDM_REG_Q_COUNTER_START_ADDR 0x166010
Vlad Zolotarov619c5cb2011-06-14 14:33:44 +03005397/* [W 17] Generate an operation after completion; bit-16 is
5398 * AggVectIdx_valid; bits 15:8 are AggVectIdx; bits 7:5 are the TRIG and
5399 * bits 4:0 are the T124Param[4:0] */
5400#define XSDM_REG_OPERATION_GEN 0x1664c4
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005401/* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */
5402#define XSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0x166548
5403/* [R 1] parser fifo empty in sdm_sync block */
5404#define XSDM_REG_SYNC_PARSER_EMPTY 0x166550
5405/* [R 1] parser serial fifo empty in sdm_sync block */
5406#define XSDM_REG_SYNC_SYNC_EMPTY 0x166558
5407/* [RW 32] Tick for timer counter. Applicable only when
5408 ~xsdm_registers_timer_tick_enable.timer_tick_enable =1 */
5409#define XSDM_REG_TIMER_TICK 0x166000
5410/* [RW 32] Interrupt mask register #0 read/write */
5411#define XSDM_REG_XSDM_INT_MASK_0 0x16629c
5412#define XSDM_REG_XSDM_INT_MASK_1 0x1662ac
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07005413/* [R 32] Interrupt register #0 read */
5414#define XSDM_REG_XSDM_INT_STS_0 0x166290
5415#define XSDM_REG_XSDM_INT_STS_1 0x1662a0
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005416/* [RW 11] Parity mask register #0 read/write */
5417#define XSDM_REG_XSDM_PRTY_MASK 0x1662bc
Eliezer Tamirf1410642008-02-28 11:51:50 -08005418/* [R 11] Parity register #0 read */
5419#define XSDM_REG_XSDM_PRTY_STS 0x1662b0
Vladislav Zolotarov4a33bc02011-01-09 02:20:04 +00005420/* [RC 11] Parity register #0 read clear */
5421#define XSDM_REG_XSDM_PRTY_STS_CLR 0x1662b4
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005422/* [RW 5] The number of time_slots in the arbitration cycle */
5423#define XSEM_REG_ARB_CYCLE_SIZE 0x280034
5424/* [RW 3] The source that is associated with arbitration element 0. Source
5425 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
5426 sleeping thread with priority 1; 4- sleeping thread with priority 2 */
5427#define XSEM_REG_ARB_ELEMENT0 0x280020
5428/* [RW 3] The source that is associated with arbitration element 1. Source
5429 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
5430 sleeping thread with priority 1; 4- sleeping thread with priority 2.
5431 Could not be equal to register ~xsem_registers_arb_element0.arb_element0 */
5432#define XSEM_REG_ARB_ELEMENT1 0x280024
5433/* [RW 3] The source that is associated with arbitration element 2. Source
5434 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
5435 sleeping thread with priority 1; 4- sleeping thread with priority 2.
5436 Could not be equal to register ~xsem_registers_arb_element0.arb_element0
5437 and ~xsem_registers_arb_element1.arb_element1 */
5438#define XSEM_REG_ARB_ELEMENT2 0x280028
5439/* [RW 3] The source that is associated with arbitration element 3. Source
5440 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
5441 sleeping thread with priority 1; 4- sleeping thread with priority 2.Could
5442 not be equal to register ~xsem_registers_arb_element0.arb_element0 and
5443 ~xsem_registers_arb_element1.arb_element1 and
5444 ~xsem_registers_arb_element2.arb_element2 */
5445#define XSEM_REG_ARB_ELEMENT3 0x28002c
5446/* [RW 3] The source that is associated with arbitration element 4. Source
5447 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
5448 sleeping thread with priority 1; 4- sleeping thread with priority 2.
5449 Could not be equal to register ~xsem_registers_arb_element0.arb_element0
5450 and ~xsem_registers_arb_element1.arb_element1 and
5451 ~xsem_registers_arb_element2.arb_element2 and
5452 ~xsem_registers_arb_element3.arb_element3 */
5453#define XSEM_REG_ARB_ELEMENT4 0x280030
5454#define XSEM_REG_ENABLE_IN 0x2800a4
5455#define XSEM_REG_ENABLE_OUT 0x2800a8
5456/* [RW 32] This address space contains all registers and memories that are
5457 placed in SEM_FAST block. The SEM_FAST registers are described in
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07005458 appendix B. In order to access the sem_fast registers the base address
5459 ~fast_memory.fast_memory should be added to eachsem_fast register offset. */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005460#define XSEM_REG_FAST_MEMORY 0x2a0000
5461/* [RW 1] Disables input messages from FIC0 May be updated during run_time
5462 by the microcode */
5463#define XSEM_REG_FIC0_DISABLE 0x280224
5464/* [RW 1] Disables input messages from FIC1 May be updated during run_time
5465 by the microcode */
5466#define XSEM_REG_FIC1_DISABLE 0x280234
5467/* [RW 15] Interrupt table Read and write access to it is not possible in
5468 the middle of the work */
5469#define XSEM_REG_INT_TABLE 0x280400
5470/* [ST 24] Statistics register. The number of messages that entered through
5471 FIC0 */
5472#define XSEM_REG_MSG_NUM_FIC0 0x280000
5473/* [ST 24] Statistics register. The number of messages that entered through
5474 FIC1 */
5475#define XSEM_REG_MSG_NUM_FIC1 0x280004
5476/* [ST 24] Statistics register. The number of messages that were sent to
5477 FOC0 */
5478#define XSEM_REG_MSG_NUM_FOC0 0x280008
5479/* [ST 24] Statistics register. The number of messages that were sent to
5480 FOC1 */
5481#define XSEM_REG_MSG_NUM_FOC1 0x28000c
5482/* [ST 24] Statistics register. The number of messages that were sent to
5483 FOC2 */
5484#define XSEM_REG_MSG_NUM_FOC2 0x280010
5485/* [ST 24] Statistics register. The number of messages that were sent to
5486 FOC3 */
5487#define XSEM_REG_MSG_NUM_FOC3 0x280014
5488/* [RW 1] Disables input messages from the passive buffer May be updated
5489 during run_time by the microcode */
5490#define XSEM_REG_PAS_DISABLE 0x28024c
5491/* [WB 128] Debug only. Passive buffer memory */
5492#define XSEM_REG_PASSIVE_BUFFER 0x282000
5493/* [WB 46] pram memory. B45 is parity; b[44:0] - data. */
5494#define XSEM_REG_PRAM 0x2c0000
5495/* [R 16] Valid sleeping threads indication have bit per thread */
5496#define XSEM_REG_SLEEP_THREADS_VALID 0x28026c
5497/* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */
5498#define XSEM_REG_SLOW_EXT_STORE_EMPTY 0x2802a0
5499/* [RW 16] List of free threads . There is a bit per thread. */
5500#define XSEM_REG_THREADS_LIST 0x2802e4
5501/* [RW 3] The arbitration scheme of time_slot 0 */
5502#define XSEM_REG_TS_0_AS 0x280038
5503/* [RW 3] The arbitration scheme of time_slot 10 */
5504#define XSEM_REG_TS_10_AS 0x280060
5505/* [RW 3] The arbitration scheme of time_slot 11 */
5506#define XSEM_REG_TS_11_AS 0x280064
5507/* [RW 3] The arbitration scheme of time_slot 12 */
5508#define XSEM_REG_TS_12_AS 0x280068
5509/* [RW 3] The arbitration scheme of time_slot 13 */
5510#define XSEM_REG_TS_13_AS 0x28006c
5511/* [RW 3] The arbitration scheme of time_slot 14 */
5512#define XSEM_REG_TS_14_AS 0x280070
5513/* [RW 3] The arbitration scheme of time_slot 15 */
5514#define XSEM_REG_TS_15_AS 0x280074
5515/* [RW 3] The arbitration scheme of time_slot 16 */
5516#define XSEM_REG_TS_16_AS 0x280078
5517/* [RW 3] The arbitration scheme of time_slot 17 */
5518#define XSEM_REG_TS_17_AS 0x28007c
5519/* [RW 3] The arbitration scheme of time_slot 18 */
5520#define XSEM_REG_TS_18_AS 0x280080
5521/* [RW 3] The arbitration scheme of time_slot 1 */
5522#define XSEM_REG_TS_1_AS 0x28003c
5523/* [RW 3] The arbitration scheme of time_slot 2 */
5524#define XSEM_REG_TS_2_AS 0x280040
5525/* [RW 3] The arbitration scheme of time_slot 3 */
5526#define XSEM_REG_TS_3_AS 0x280044
5527/* [RW 3] The arbitration scheme of time_slot 4 */
5528#define XSEM_REG_TS_4_AS 0x280048
5529/* [RW 3] The arbitration scheme of time_slot 5 */
5530#define XSEM_REG_TS_5_AS 0x28004c
5531/* [RW 3] The arbitration scheme of time_slot 6 */
5532#define XSEM_REG_TS_6_AS 0x280050
5533/* [RW 3] The arbitration scheme of time_slot 7 */
5534#define XSEM_REG_TS_7_AS 0x280054
5535/* [RW 3] The arbitration scheme of time_slot 8 */
5536#define XSEM_REG_TS_8_AS 0x280058
5537/* [RW 3] The arbitration scheme of time_slot 9 */
5538#define XSEM_REG_TS_9_AS 0x28005c
Dmitry Kravkovf2e08992010-10-06 03:28:26 +00005539/* [W 7] VF or PF ID for reset error bit. Values 0-63 reset error bit for 64
5540 * VF; values 64-67 reset error for 4 PF; values 68-127 are not valid. */
5541#define XSEM_REG_VFPF_ERR_NUM 0x280380
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005542/* [RW 32] Interrupt mask register #0 read/write */
5543#define XSEM_REG_XSEM_INT_MASK_0 0x280110
5544#define XSEM_REG_XSEM_INT_MASK_1 0x280120
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07005545/* [R 32] Interrupt register #0 read */
5546#define XSEM_REG_XSEM_INT_STS_0 0x280104
5547#define XSEM_REG_XSEM_INT_STS_1 0x280114
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005548/* [RW 32] Parity mask register #0 read/write */
5549#define XSEM_REG_XSEM_PRTY_MASK_0 0x280130
5550#define XSEM_REG_XSEM_PRTY_MASK_1 0x280140
Eliezer Tamirf1410642008-02-28 11:51:50 -08005551/* [R 32] Parity register #0 read */
5552#define XSEM_REG_XSEM_PRTY_STS_0 0x280124
5553#define XSEM_REG_XSEM_PRTY_STS_1 0x280134
Vladislav Zolotarov4a33bc02011-01-09 02:20:04 +00005554/* [RC 32] Parity register #0 read clear */
5555#define XSEM_REG_XSEM_PRTY_STS_CLR_0 0x280128
5556#define XSEM_REG_XSEM_PRTY_STS_CLR_1 0x280138
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005557#define MCPR_NVM_ACCESS_ENABLE_EN (1L<<0)
5558#define MCPR_NVM_ACCESS_ENABLE_WR_EN (1L<<1)
5559#define MCPR_NVM_ADDR_NVM_ADDR_VALUE (0xffffffL<<0)
5560#define MCPR_NVM_CFG4_FLASH_SIZE (0x7L<<0)
5561#define MCPR_NVM_COMMAND_DOIT (1L<<4)
5562#define MCPR_NVM_COMMAND_DONE (1L<<3)
5563#define MCPR_NVM_COMMAND_FIRST (1L<<7)
5564#define MCPR_NVM_COMMAND_LAST (1L<<8)
5565#define MCPR_NVM_COMMAND_WR (1L<<5)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005566#define MCPR_NVM_SW_ARB_ARB_ARB1 (1L<<9)
5567#define MCPR_NVM_SW_ARB_ARB_REQ_CLR1 (1L<<5)
5568#define MCPR_NVM_SW_ARB_ARB_REQ_SET1 (1L<<1)
5569#define BIGMAC_REGISTER_BMAC_CONTROL (0x00<<3)
5570#define BIGMAC_REGISTER_BMAC_XGXS_CONTROL (0x01<<3)
5571#define BIGMAC_REGISTER_CNT_MAX_SIZE (0x05<<3)
5572#define BIGMAC_REGISTER_RX_CONTROL (0x21<<3)
5573#define BIGMAC_REGISTER_RX_LLFC_MSG_FLDS (0x46<<3)
Yaniv Rosner3deb8162011-06-14 01:34:33 +00005574#define BIGMAC_REGISTER_RX_LSS_STATUS (0x43<<3)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005575#define BIGMAC_REGISTER_RX_MAX_SIZE (0x23<<3)
5576#define BIGMAC_REGISTER_RX_STAT_GR64 (0x26<<3)
5577#define BIGMAC_REGISTER_RX_STAT_GRIPJ (0x42<<3)
5578#define BIGMAC_REGISTER_TX_CONTROL (0x07<<3)
5579#define BIGMAC_REGISTER_TX_MAX_SIZE (0x09<<3)
5580#define BIGMAC_REGISTER_TX_PAUSE_THRESHOLD (0x0A<<3)
5581#define BIGMAC_REGISTER_TX_SOURCE_ADDR (0x08<<3)
5582#define BIGMAC_REGISTER_TX_STAT_GTBYT (0x20<<3)
5583#define BIGMAC_REGISTER_TX_STAT_GTPKT (0x0C<<3)
Dmitry Kravkovf2e08992010-10-06 03:28:26 +00005584#define BIGMAC2_REGISTER_BMAC_CONTROL (0x00<<3)
5585#define BIGMAC2_REGISTER_BMAC_XGXS_CONTROL (0x01<<3)
5586#define BIGMAC2_REGISTER_CNT_MAX_SIZE (0x05<<3)
5587#define BIGMAC2_REGISTER_PFC_CONTROL (0x06<<3)
5588#define BIGMAC2_REGISTER_RX_CONTROL (0x3A<<3)
5589#define BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS (0x62<<3)
Yaniv Rosner3deb8162011-06-14 01:34:33 +00005590#define BIGMAC2_REGISTER_RX_LSS_STAT (0x3E<<3)
Dmitry Kravkovf2e08992010-10-06 03:28:26 +00005591#define BIGMAC2_REGISTER_RX_MAX_SIZE (0x3C<<3)
5592#define BIGMAC2_REGISTER_RX_STAT_GR64 (0x40<<3)
5593#define BIGMAC2_REGISTER_RX_STAT_GRIPJ (0x5f<<3)
5594#define BIGMAC2_REGISTER_RX_STAT_GRPP (0x51<<3)
5595#define BIGMAC2_REGISTER_TX_CONTROL (0x1C<<3)
5596#define BIGMAC2_REGISTER_TX_MAX_SIZE (0x1E<<3)
5597#define BIGMAC2_REGISTER_TX_PAUSE_CONTROL (0x20<<3)
5598#define BIGMAC2_REGISTER_TX_SOURCE_ADDR (0x1D<<3)
5599#define BIGMAC2_REGISTER_TX_STAT_GTBYT (0x39<<3)
5600#define BIGMAC2_REGISTER_TX_STAT_GTPOK (0x22<<3)
5601#define BIGMAC2_REGISTER_TX_STAT_GTPP (0x24<<3)
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07005602#define EMAC_LED_1000MB_OVERRIDE (1L<<1)
5603#define EMAC_LED_100MB_OVERRIDE (1L<<2)
5604#define EMAC_LED_10MB_OVERRIDE (1L<<3)
5605#define EMAC_LED_2500MB_OVERRIDE (1L<<12)
5606#define EMAC_LED_OVERRIDE (1L<<0)
5607#define EMAC_LED_TRAFFIC (1L<<6)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005608#define EMAC_MDIO_COMM_COMMAND_ADDRESS (0L<<26)
Yaniv Rosner6583e332011-06-14 01:34:17 +00005609#define EMAC_MDIO_COMM_COMMAND_READ_22 (2L<<26)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005610#define EMAC_MDIO_COMM_COMMAND_READ_45 (3L<<26)
Yaniv Rosner6583e332011-06-14 01:34:17 +00005611#define EMAC_MDIO_COMM_COMMAND_WRITE_22 (1L<<26)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005612#define EMAC_MDIO_COMM_COMMAND_WRITE_45 (1L<<26)
5613#define EMAC_MDIO_COMM_DATA (0xffffL<<0)
5614#define EMAC_MDIO_COMM_START_BUSY (1L<<29)
5615#define EMAC_MDIO_MODE_AUTO_POLL (1L<<4)
5616#define EMAC_MDIO_MODE_CLAUSE_45 (1L<<31)
Eliezer Tamirf1410642008-02-28 11:51:50 -08005617#define EMAC_MDIO_MODE_CLOCK_CNT (0x3fL<<16)
5618#define EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT 16
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005619#define EMAC_MODE_25G_MODE (1L<<5)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005620#define EMAC_MODE_HALF_DUPLEX (1L<<1)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005621#define EMAC_MODE_PORT_GMII (2L<<2)
5622#define EMAC_MODE_PORT_MII (1L<<2)
5623#define EMAC_MODE_PORT_MII_10M (3L<<2)
5624#define EMAC_MODE_RESET (1L<<0)
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07005625#define EMAC_REG_EMAC_LED 0xc
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005626#define EMAC_REG_EMAC_MAC_MATCH 0x10
5627#define EMAC_REG_EMAC_MDIO_COMM 0xac
5628#define EMAC_REG_EMAC_MDIO_MODE 0xb4
5629#define EMAC_REG_EMAC_MODE 0x0
5630#define EMAC_REG_EMAC_RX_MODE 0xc8
5631#define EMAC_REG_EMAC_RX_MTU_SIZE 0x9c
5632#define EMAC_REG_EMAC_RX_STAT_AC 0x180
5633#define EMAC_REG_EMAC_RX_STAT_AC_28 0x1f4
5634#define EMAC_REG_EMAC_RX_STAT_AC_COUNT 23
5635#define EMAC_REG_EMAC_TX_MODE 0xbc
5636#define EMAC_REG_EMAC_TX_STAT_AC 0x280
5637#define EMAC_REG_EMAC_TX_STAT_AC_COUNT 22
Vladislav Zolotarovbcab15c2010-12-13 05:44:25 +00005638#define EMAC_REG_RX_PFC_MODE 0x320
5639#define EMAC_REG_RX_PFC_MODE_PRIORITIES (1L<<2)
5640#define EMAC_REG_RX_PFC_MODE_RX_EN (1L<<1)
5641#define EMAC_REG_RX_PFC_MODE_TX_EN (1L<<0)
5642#define EMAC_REG_RX_PFC_PARAM 0x324
5643#define EMAC_REG_RX_PFC_PARAM_OPCODE_BITSHIFT 0
5644#define EMAC_REG_RX_PFC_PARAM_PRIORITY_EN_BITSHIFT 16
5645#define EMAC_REG_RX_PFC_STATS_XOFF_RCVD 0x328
5646#define EMAC_REG_RX_PFC_STATS_XOFF_RCVD_COUNT (0xffff<<0)
5647#define EMAC_REG_RX_PFC_STATS_XOFF_SENT 0x330
5648#define EMAC_REG_RX_PFC_STATS_XOFF_SENT_COUNT (0xffff<<0)
5649#define EMAC_REG_RX_PFC_STATS_XON_RCVD 0x32c
5650#define EMAC_REG_RX_PFC_STATS_XON_RCVD_COUNT (0xffff<<0)
5651#define EMAC_REG_RX_PFC_STATS_XON_SENT 0x334
5652#define EMAC_REG_RX_PFC_STATS_XON_SENT_COUNT (0xffff<<0)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005653#define EMAC_RX_MODE_FLOW_EN (1L<<2)
Vladislav Zolotarovbcab15c2010-12-13 05:44:25 +00005654#define EMAC_RX_MODE_KEEP_MAC_CONTROL (1L<<3)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005655#define EMAC_RX_MODE_KEEP_VLAN_TAG (1L<<10)
5656#define EMAC_RX_MODE_PROMISCUOUS (1L<<8)
Eilon Greenstein811a2f22009-02-12 08:37:04 +00005657#define EMAC_RX_MODE_RESET (1L<<0)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005658#define EMAC_RX_MTU_SIZE_JUMBO_ENA (1L<<31)
5659#define EMAC_TX_MODE_EXT_PAUSE_EN (1L<<3)
Yaniv Rosner8c99e7b2008-08-13 15:56:17 -07005660#define EMAC_TX_MODE_FLOW_EN (1L<<4)
Eilon Greenstein811a2f22009-02-12 08:37:04 +00005661#define EMAC_TX_MODE_RESET (1L<<0)
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07005662#define MISC_REGISTERS_GPIO_0 0
Eliezer Tamirf1410642008-02-28 11:51:50 -08005663#define MISC_REGISTERS_GPIO_1 1
5664#define MISC_REGISTERS_GPIO_2 2
5665#define MISC_REGISTERS_GPIO_3 3
5666#define MISC_REGISTERS_GPIO_CLR_POS 16
5667#define MISC_REGISTERS_GPIO_FLOAT (0xffL<<24)
5668#define MISC_REGISTERS_GPIO_FLOAT_POS 24
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07005669#define MISC_REGISTERS_GPIO_HIGH 1
Eliezer Tamirf1410642008-02-28 11:51:50 -08005670#define MISC_REGISTERS_GPIO_INPUT_HI_Z 2
Eilon Greenstein4acac6a2009-02-12 08:36:52 +00005671#define MISC_REGISTERS_GPIO_INT_CLR_POS 24
5672#define MISC_REGISTERS_GPIO_INT_OUTPUT_CLR 0
5673#define MISC_REGISTERS_GPIO_INT_OUTPUT_SET 1
5674#define MISC_REGISTERS_GPIO_INT_SET_POS 16
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07005675#define MISC_REGISTERS_GPIO_LOW 0
Eliezer Tamirf1410642008-02-28 11:51:50 -08005676#define MISC_REGISTERS_GPIO_OUTPUT_HIGH 1
5677#define MISC_REGISTERS_GPIO_OUTPUT_LOW 0
5678#define MISC_REGISTERS_GPIO_PORT_SHIFT 4
5679#define MISC_REGISTERS_GPIO_SET_POS 8
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005680#define MISC_REGISTERS_RESET_REG_1_CLEAR 0x588
Vladislav Zolotarov72fd0712010-04-19 01:13:12 +00005681#define MISC_REGISTERS_RESET_REG_1_RST_HC (0x1<<29)
Vladislav Zolotarovda5a6622008-08-13 15:50:00 -07005682#define MISC_REGISTERS_RESET_REG_1_RST_NIG (0x1<<7)
Vladislav Zolotarov72fd0712010-04-19 01:13:12 +00005683#define MISC_REGISTERS_RESET_REG_1_RST_PXP (0x1<<26)
5684#define MISC_REGISTERS_RESET_REG_1_RST_PXPV (0x1<<27)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005685#define MISC_REGISTERS_RESET_REG_1_SET 0x584
5686#define MISC_REGISTERS_RESET_REG_2_CLEAR 0x598
Vlad Zolotarov619c5cb2011-06-14 14:33:44 +03005687#define MISC_REGISTERS_RESET_REG_2_MSTAT0 (0x1<<24)
5688#define MISC_REGISTERS_RESET_REG_2_MSTAT1 (0x1<<25)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005689#define MISC_REGISTERS_RESET_REG_2_RST_BMAC0 (0x1<<0)
5690#define MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE (0x1<<14)
Vladislav Zolotarov72fd0712010-04-19 01:13:12 +00005691#define MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE (0x1<<15)
5692#define MISC_REGISTERS_RESET_REG_2_RST_GRC (0x1<<4)
5693#define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B (0x1<<6)
Vladislav Zolotarovc9ee9202011-06-14 01:33:51 +00005694#define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE (0x1<<8)
5695#define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU (0x1<<7)
Vladislav Zolotarov72fd0712010-04-19 01:13:12 +00005696#define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE (0x1<<5)
5697#define MISC_REGISTERS_RESET_REG_2_RST_MDIO (0x1<<13)
5698#define MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE (0x1<<11)
Vladislav Zolotarovc9ee9202011-06-14 01:33:51 +00005699#define MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO (0x1<<13)
Vladislav Zolotarov72fd0712010-04-19 01:13:12 +00005700#define MISC_REGISTERS_RESET_REG_2_RST_RBCN (0x1<<9)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005701#define MISC_REGISTERS_RESET_REG_2_SET 0x594
Yaniv Rosner9380bb92011-06-14 01:34:07 +00005702#define MISC_REGISTERS_RESET_REG_2_UMAC0 (0x1<<20)
5703#define MISC_REGISTERS_RESET_REG_2_XMAC (0x1<<22)
5704#define MISC_REGISTERS_RESET_REG_2_XMAC_SOFT (0x1<<23)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005705#define MISC_REGISTERS_RESET_REG_3_CLEAR 0x5a8
5706#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ (0x1<<1)
5707#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN (0x1<<2)
5708#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD (0x1<<3)
5709#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW (0x1<<0)
5710#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ (0x1<<5)
5711#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN (0x1<<6)
5712#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD (0x1<<7)
5713#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW (0x1<<4)
5714#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB (0x1<<8)
5715#define MISC_REGISTERS_RESET_REG_3_SET 0x5a4
Eliezer Tamirf1410642008-02-28 11:51:50 -08005716#define MISC_REGISTERS_SPIO_4 4
5717#define MISC_REGISTERS_SPIO_5 5
5718#define MISC_REGISTERS_SPIO_7 7
5719#define MISC_REGISTERS_SPIO_CLR_POS 16
5720#define MISC_REGISTERS_SPIO_FLOAT (0xffL<<24)
Eliezer Tamirf1410642008-02-28 11:51:50 -08005721#define MISC_REGISTERS_SPIO_FLOAT_POS 24
5722#define MISC_REGISTERS_SPIO_INPUT_HI_Z 2
5723#define MISC_REGISTERS_SPIO_INT_OLD_SET_POS 16
5724#define MISC_REGISTERS_SPIO_OUTPUT_HIGH 1
5725#define MISC_REGISTERS_SPIO_OUTPUT_LOW 0
5726#define MISC_REGISTERS_SPIO_SET_POS 8
Vlad Zolotarov619c5cb2011-06-14 14:33:44 +03005727#define HW_LOCK_DRV_FLAGS 10
Eliezer Tamirf1410642008-02-28 11:51:50 -08005728#define HW_LOCK_MAX_RESOURCE_VALUE 31
Eliezer Tamirf1410642008-02-28 11:51:50 -08005729#define HW_LOCK_RESOURCE_GPIO 1
Eilon Greenstein46c6a672009-02-12 08:36:58 +00005730#define HW_LOCK_RESOURCE_MDIO 0
Vladislav Zolotarovc9ee9202011-06-14 01:33:51 +00005731#define HW_LOCK_RESOURCE_PORT0_ATT_MASK 3
5732#define HW_LOCK_RESOURCE_RECOVERY_LEADER_0 8
5733#define HW_LOCK_RESOURCE_RECOVERY_LEADER_1 9
Eliezer Tamirf1410642008-02-28 11:51:50 -08005734#define HW_LOCK_RESOURCE_SPIO 2
Vladislav Zolotarovda5a6622008-08-13 15:50:00 -07005735#define HW_LOCK_RESOURCE_UNDI 5
Vladislav Zolotarovc9ee9202011-06-14 01:33:51 +00005736#define AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT (0x1<<4)
5737#define AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR (0x1<<5)
5738#define AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR (0x1<<18)
5739#define AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT (0x1<<31)
5740#define AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR (0x1<<30)
5741#define AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT (0x1<<9)
5742#define AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR (0x1<<8)
5743#define AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT (0x1<<7)
5744#define AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR (0x1<<6)
5745#define AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT (0x1<<29)
5746#define AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR (0x1<<28)
5747#define AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT (0x1<<1)
5748#define AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR (0x1<<0)
5749#define AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR (0x1<<18)
5750#define AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT (0x1<<11)
5751#define AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR (0x1<<10)
5752#define AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT (0x1<<13)
5753#define AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR (0x1<<12)
5754#define AEU_INPUTS_ATTN_BITS_GPIO0_FUNCTION_0 (0x1<<2)
5755#define AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR (0x1<<12)
5756#define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY (0x1<<28)
5757#define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY (0x1<<31)
5758#define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY (0x1<<29)
5759#define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY (0x1<<30)
5760#define AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT (0x1<<15)
5761#define AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR (0x1<<14)
5762#define AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR (0x1<<14)
5763#define AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR (0x1<<20)
5764#define AEU_INPUTS_ATTN_BITS_PBCLIENT_HW_INTERRUPT (0x1<<31)
5765#define AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR (0x1<<30)
5766#define AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR (0x1<<0)
5767#define AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT (0x1<<2)
5768#define AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR (0x1<<3)
5769#define AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT (0x1<<5)
5770#define AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR (0x1<<4)
5771#define AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT (0x1<<3)
5772#define AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR (0x1<<2)
5773#define AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT (0x1<<3)
5774#define AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR (0x1<<2)
5775#define AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR (0x1<<22)
5776#define AEU_INPUTS_ATTN_BITS_SPIO5 (0x1<<15)
5777#define AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT (0x1<<27)
5778#define AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR (0x1<<26)
5779#define AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT (0x1<<5)
5780#define AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR (0x1<<4)
5781#define AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT (0x1<<25)
5782#define AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR (0x1<<24)
5783#define AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT (0x1<<29)
5784#define AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR (0x1<<28)
5785#define AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT (0x1<<23)
5786#define AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR (0x1<<22)
5787#define AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT (0x1<<27)
5788#define AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR (0x1<<26)
5789#define AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT (0x1<<21)
5790#define AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR (0x1<<20)
5791#define AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT (0x1<<25)
5792#define AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR (0x1<<24)
5793#define AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR (0x1<<16)
5794#define AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT (0x1<<9)
5795#define AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR (0x1<<8)
5796#define AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT (0x1<<7)
5797#define AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR (0x1<<6)
5798#define AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT (0x1<<11)
5799#define AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR (0x1<<10)
5800
5801#define AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_0 (0x1<<5)
5802#define AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_1 (0x1<<9)
5803
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005804#define RESERVED_GENERAL_ATTENTION_BIT_0 0
5805
Vladislav Zolotarovc9ee9202011-06-14 01:33:51 +00005806#define EVEREST_GEN_ATTN_IN_USE_MASK 0x7ffe0
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005807#define EVEREST_LATCHED_ATTN_IN_USE_MASK 0xffe00000
5808
5809#define RESERVED_GENERAL_ATTENTION_BIT_6 6
5810#define RESERVED_GENERAL_ATTENTION_BIT_7 7
5811#define RESERVED_GENERAL_ATTENTION_BIT_8 8
5812#define RESERVED_GENERAL_ATTENTION_BIT_9 9
5813#define RESERVED_GENERAL_ATTENTION_BIT_10 10
5814#define RESERVED_GENERAL_ATTENTION_BIT_11 11
5815#define RESERVED_GENERAL_ATTENTION_BIT_12 12
5816#define RESERVED_GENERAL_ATTENTION_BIT_13 13
5817#define RESERVED_GENERAL_ATTENTION_BIT_14 14
5818#define RESERVED_GENERAL_ATTENTION_BIT_15 15
5819#define RESERVED_GENERAL_ATTENTION_BIT_16 16
5820#define RESERVED_GENERAL_ATTENTION_BIT_17 17
5821#define RESERVED_GENERAL_ATTENTION_BIT_18 18
5822#define RESERVED_GENERAL_ATTENTION_BIT_19 19
5823#define RESERVED_GENERAL_ATTENTION_BIT_20 20
5824#define RESERVED_GENERAL_ATTENTION_BIT_21 21
5825
5826/* storm asserts attention bits */
5827#define TSTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_7
5828#define USTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_8
5829#define CSTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_9
5830#define XSTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_10
5831
5832/* mcp error attention bit */
5833#define MCP_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_11
5834
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07005835/*E1H NIG status sync attention mapped to group 4-7*/
5836#define LINK_SYNC_ATTENTION_BIT_FUNC_0 RESERVED_GENERAL_ATTENTION_BIT_12
5837#define LINK_SYNC_ATTENTION_BIT_FUNC_1 RESERVED_GENERAL_ATTENTION_BIT_13
5838#define LINK_SYNC_ATTENTION_BIT_FUNC_2 RESERVED_GENERAL_ATTENTION_BIT_14
5839#define LINK_SYNC_ATTENTION_BIT_FUNC_3 RESERVED_GENERAL_ATTENTION_BIT_15
5840#define LINK_SYNC_ATTENTION_BIT_FUNC_4 RESERVED_GENERAL_ATTENTION_BIT_16
5841#define LINK_SYNC_ATTENTION_BIT_FUNC_5 RESERVED_GENERAL_ATTENTION_BIT_17
5842#define LINK_SYNC_ATTENTION_BIT_FUNC_6 RESERVED_GENERAL_ATTENTION_BIT_18
5843#define LINK_SYNC_ATTENTION_BIT_FUNC_7 RESERVED_GENERAL_ATTENTION_BIT_19
5844
5845
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005846#define LATCHED_ATTN_RBCR 23
5847#define LATCHED_ATTN_RBCT 24
5848#define LATCHED_ATTN_RBCN 25
5849#define LATCHED_ATTN_RBCU 26
5850#define LATCHED_ATTN_RBCP 27
5851#define LATCHED_ATTN_TIMEOUT_GRC 28
5852#define LATCHED_ATTN_RSVD_GRC 29
5853#define LATCHED_ATTN_ROM_PARITY_MCP 30
5854#define LATCHED_ATTN_UM_RX_PARITY_MCP 31
5855#define LATCHED_ATTN_UM_TX_PARITY_MCP 32
5856#define LATCHED_ATTN_SCPAD_PARITY_MCP 33
5857
5858#define GENERAL_ATTEN_WORD(atten_name) ((94 + atten_name) / 32)
Eilon Greensteinab6ad5a2009-08-12 08:24:29 +00005859#define GENERAL_ATTEN_OFFSET(atten_name)\
5860 (1UL << ((94 + atten_name) % 32))
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005861/*
5862 * This file defines GRC base address for every block.
5863 * This file is included by chipsim, asm microcode and cpp microcode.
5864 * These values are used in Design.xml on regBase attribute
5865 * Use the base with the generated offsets of specific registers.
5866 */
5867
5868#define GRCBASE_PXPCS 0x000000
5869#define GRCBASE_PCICONFIG 0x002000
5870#define GRCBASE_PCIREG 0x002400
5871#define GRCBASE_EMAC0 0x008000
5872#define GRCBASE_EMAC1 0x008400
5873#define GRCBASE_DBU 0x008800
5874#define GRCBASE_MISC 0x00A000
5875#define GRCBASE_DBG 0x00C000
5876#define GRCBASE_NIG 0x010000
5877#define GRCBASE_XCM 0x020000
5878#define GRCBASE_PRS 0x040000
5879#define GRCBASE_SRCH 0x040400
5880#define GRCBASE_TSDM 0x042000
5881#define GRCBASE_TCM 0x050000
5882#define GRCBASE_BRB1 0x060000
5883#define GRCBASE_MCP 0x080000
5884#define GRCBASE_UPB 0x0C1000
5885#define GRCBASE_CSDM 0x0C2000
5886#define GRCBASE_USDM 0x0C4000
5887#define GRCBASE_CCM 0x0D0000
5888#define GRCBASE_UCM 0x0E0000
5889#define GRCBASE_CDU 0x101000
5890#define GRCBASE_DMAE 0x102000
5891#define GRCBASE_PXP 0x103000
5892#define GRCBASE_CFC 0x104000
5893#define GRCBASE_HC 0x108000
5894#define GRCBASE_PXP2 0x120000
5895#define GRCBASE_PBF 0x140000
Yaniv Rosner9380bb92011-06-14 01:34:07 +00005896#define GRCBASE_UMAC0 0x160000
5897#define GRCBASE_UMAC1 0x160400
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005898#define GRCBASE_XPB 0x161000
Vlad Zolotarov619c5cb2011-06-14 14:33:44 +03005899#define GRCBASE_MSTAT0 0x162000
5900#define GRCBASE_MSTAT1 0x162800
Yaniv Rosner9380bb92011-06-14 01:34:07 +00005901#define GRCBASE_XMAC0 0x163000
5902#define GRCBASE_XMAC1 0x163800
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005903#define GRCBASE_TIMERS 0x164000
5904#define GRCBASE_XSDM 0x166000
5905#define GRCBASE_QM 0x168000
5906#define GRCBASE_DQ 0x170000
5907#define GRCBASE_TSEM 0x180000
5908#define GRCBASE_CSEM 0x200000
5909#define GRCBASE_XSEM 0x280000
5910#define GRCBASE_USEM 0x300000
5911#define GRCBASE_MISC_AEU GRCBASE_MISC
5912
5913
Eilon Greenstein5c862842008-08-13 15:51:48 -07005914/* offset of configuration space in the pci core register */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005915#define PCICFG_OFFSET 0x2000
5916#define PCICFG_VENDOR_ID_OFFSET 0x00
5917#define PCICFG_DEVICE_ID_OFFSET 0x02
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07005918#define PCICFG_COMMAND_OFFSET 0x04
Eilon Greenstein5c862842008-08-13 15:51:48 -07005919#define PCICFG_COMMAND_IO_SPACE (1<<0)
5920#define PCICFG_COMMAND_MEM_SPACE (1<<1)
5921#define PCICFG_COMMAND_BUS_MASTER (1<<2)
5922#define PCICFG_COMMAND_SPECIAL_CYCLES (1<<3)
5923#define PCICFG_COMMAND_MWI_CYCLES (1<<4)
5924#define PCICFG_COMMAND_VGA_SNOOP (1<<5)
5925#define PCICFG_COMMAND_PERR_ENA (1<<6)
5926#define PCICFG_COMMAND_STEPPING (1<<7)
5927#define PCICFG_COMMAND_SERR_ENA (1<<8)
5928#define PCICFG_COMMAND_FAST_B2B (1<<9)
5929#define PCICFG_COMMAND_INT_DISABLE (1<<10)
5930#define PCICFG_COMMAND_RESERVED (0x1f<<11)
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07005931#define PCICFG_STATUS_OFFSET 0x06
Eilon Greenstein0d1a8d22009-03-02 07:59:20 +00005932#define PCICFG_REVESION_ID_OFFSET 0x08
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005933#define PCICFG_CACHE_LINE_SIZE 0x0c
5934#define PCICFG_LATENCY_TIMER 0x0d
Eilon Greenstein5c862842008-08-13 15:51:48 -07005935#define PCICFG_BAR_1_LOW 0x10
5936#define PCICFG_BAR_1_HIGH 0x14
5937#define PCICFG_BAR_2_LOW 0x18
5938#define PCICFG_BAR_2_HIGH 0x1c
5939#define PCICFG_SUBSYSTEM_VENDOR_ID_OFFSET 0x2c
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07005940#define PCICFG_SUBSYSTEM_ID_OFFSET 0x2e
Eilon Greenstein5c862842008-08-13 15:51:48 -07005941#define PCICFG_INT_LINE 0x3c
5942#define PCICFG_INT_PIN 0x3d
5943#define PCICFG_PM_CAPABILITY 0x48
5944#define PCICFG_PM_CAPABILITY_VERSION (0x3<<16)
5945#define PCICFG_PM_CAPABILITY_CLOCK (1<<19)
5946#define PCICFG_PM_CAPABILITY_RESERVED (1<<20)
5947#define PCICFG_PM_CAPABILITY_DSI (1<<21)
5948#define PCICFG_PM_CAPABILITY_AUX_CURRENT (0x7<<22)
5949#define PCICFG_PM_CAPABILITY_D1_SUPPORT (1<<25)
5950#define PCICFG_PM_CAPABILITY_D2_SUPPORT (1<<26)
5951#define PCICFG_PM_CAPABILITY_PME_IN_D0 (1<<27)
5952#define PCICFG_PM_CAPABILITY_PME_IN_D1 (1<<28)
5953#define PCICFG_PM_CAPABILITY_PME_IN_D2 (1<<29)
5954#define PCICFG_PM_CAPABILITY_PME_IN_D3_HOT (1<<30)
5955#define PCICFG_PM_CAPABILITY_PME_IN_D3_COLD (1<<31)
5956#define PCICFG_PM_CSR_OFFSET 0x4c
5957#define PCICFG_PM_CSR_STATE (0x3<<0)
5958#define PCICFG_PM_CSR_PME_ENABLE (1<<8)
5959#define PCICFG_PM_CSR_PME_STATUS (1<<15)
Eilon Greenstein0d1a8d22009-03-02 07:59:20 +00005960#define PCICFG_MSI_CAP_ID_OFFSET 0x58
Eilon Greenstein8badd272009-02-12 08:36:15 +00005961#define PCICFG_MSI_CONTROL_ENABLE (0x1<<16)
5962#define PCICFG_MSI_CONTROL_MCAP (0x7<<17)
5963#define PCICFG_MSI_CONTROL_MENA (0x7<<20)
5964#define PCICFG_MSI_CONTROL_64_BIT_ADDR_CAP (0x1<<23)
5965#define PCICFG_MSI_CONTROL_MSI_PVMASK_CAPABLE (0x1<<24)
Eilon Greenstein5c862842008-08-13 15:51:48 -07005966#define PCICFG_GRC_ADDRESS 0x78
5967#define PCICFG_GRC_DATA 0x80
Eilon Greenstein0d1a8d22009-03-02 07:59:20 +00005968#define PCICFG_MSIX_CAP_ID_OFFSET 0xa0
Eilon Greenstein8badd272009-02-12 08:36:15 +00005969#define PCICFG_MSIX_CONTROL_TABLE_SIZE (0x7ff<<16)
5970#define PCICFG_MSIX_CONTROL_RESERVED (0x7<<27)
5971#define PCICFG_MSIX_CONTROL_FUNC_MASK (0x1<<30)
5972#define PCICFG_MSIX_CONTROL_MSIX_ENABLE (0x1<<31)
5973
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005974#define PCICFG_DEVICE_CONTROL 0xb4
Eilon Greenstein8badd272009-02-12 08:36:15 +00005975#define PCICFG_DEVICE_STATUS 0xb6
5976#define PCICFG_DEVICE_STATUS_CORR_ERR_DET (1<<0)
5977#define PCICFG_DEVICE_STATUS_NON_FATAL_ERR_DET (1<<1)
5978#define PCICFG_DEVICE_STATUS_FATAL_ERR_DET (1<<2)
5979#define PCICFG_DEVICE_STATUS_UNSUP_REQ_DET (1<<3)
5980#define PCICFG_DEVICE_STATUS_AUX_PWR_DET (1<<4)
5981#define PCICFG_DEVICE_STATUS_NO_PEND (1<<5)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005982#define PCICFG_LINK_CONTROL 0xbc
5983
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07005984
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005985#define BAR_USTRORM_INTMEM 0x400000
5986#define BAR_CSTRORM_INTMEM 0x410000
5987#define BAR_XSTRORM_INTMEM 0x420000
5988#define BAR_TSTRORM_INTMEM 0x430000
5989
Eilon Greenstein5c862842008-08-13 15:51:48 -07005990/* for accessing the IGU in case of status block ACK */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02005991#define BAR_IGU_INTMEM 0x440000
5992
5993#define BAR_DOORBELL_OFFSET 0x800000
5994
5995#define BAR_ME_REGISTER 0x450000
5996
Eilon Greenstein5c862842008-08-13 15:51:48 -07005997/* config_2 offset */
5998#define GRC_CONFIG_2_SIZE_REG 0x408
5999#define PCI_CONFIG_2_BAR1_SIZE (0xfL<<0)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006000#define PCI_CONFIG_2_BAR1_SIZE_DISABLED (0L<<0)
6001#define PCI_CONFIG_2_BAR1_SIZE_64K (1L<<0)
6002#define PCI_CONFIG_2_BAR1_SIZE_128K (2L<<0)
6003#define PCI_CONFIG_2_BAR1_SIZE_256K (3L<<0)
6004#define PCI_CONFIG_2_BAR1_SIZE_512K (4L<<0)
6005#define PCI_CONFIG_2_BAR1_SIZE_1M (5L<<0)
6006#define PCI_CONFIG_2_BAR1_SIZE_2M (6L<<0)
6007#define PCI_CONFIG_2_BAR1_SIZE_4M (7L<<0)
6008#define PCI_CONFIG_2_BAR1_SIZE_8M (8L<<0)
6009#define PCI_CONFIG_2_BAR1_SIZE_16M (9L<<0)
6010#define PCI_CONFIG_2_BAR1_SIZE_32M (10L<<0)
6011#define PCI_CONFIG_2_BAR1_SIZE_64M (11L<<0)
6012#define PCI_CONFIG_2_BAR1_SIZE_128M (12L<<0)
6013#define PCI_CONFIG_2_BAR1_SIZE_256M (13L<<0)
6014#define PCI_CONFIG_2_BAR1_SIZE_512M (14L<<0)
6015#define PCI_CONFIG_2_BAR1_SIZE_1G (15L<<0)
Eilon Greenstein5c862842008-08-13 15:51:48 -07006016#define PCI_CONFIG_2_BAR1_64ENA (1L<<4)
6017#define PCI_CONFIG_2_EXP_ROM_RETRY (1L<<5)
6018#define PCI_CONFIG_2_CFG_CYCLE_RETRY (1L<<6)
6019#define PCI_CONFIG_2_FIRST_CFG_DONE (1L<<7)
6020#define PCI_CONFIG_2_EXP_ROM_SIZE (0xffL<<8)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006021#define PCI_CONFIG_2_EXP_ROM_SIZE_DISABLED (0L<<8)
6022#define PCI_CONFIG_2_EXP_ROM_SIZE_2K (1L<<8)
6023#define PCI_CONFIG_2_EXP_ROM_SIZE_4K (2L<<8)
6024#define PCI_CONFIG_2_EXP_ROM_SIZE_8K (3L<<8)
6025#define PCI_CONFIG_2_EXP_ROM_SIZE_16K (4L<<8)
6026#define PCI_CONFIG_2_EXP_ROM_SIZE_32K (5L<<8)
6027#define PCI_CONFIG_2_EXP_ROM_SIZE_64K (6L<<8)
6028#define PCI_CONFIG_2_EXP_ROM_SIZE_128K (7L<<8)
6029#define PCI_CONFIG_2_EXP_ROM_SIZE_256K (8L<<8)
6030#define PCI_CONFIG_2_EXP_ROM_SIZE_512K (9L<<8)
6031#define PCI_CONFIG_2_EXP_ROM_SIZE_1M (10L<<8)
6032#define PCI_CONFIG_2_EXP_ROM_SIZE_2M (11L<<8)
6033#define PCI_CONFIG_2_EXP_ROM_SIZE_4M (12L<<8)
6034#define PCI_CONFIG_2_EXP_ROM_SIZE_8M (13L<<8)
6035#define PCI_CONFIG_2_EXP_ROM_SIZE_16M (14L<<8)
6036#define PCI_CONFIG_2_EXP_ROM_SIZE_32M (15L<<8)
Eilon Greenstein5c862842008-08-13 15:51:48 -07006037#define PCI_CONFIG_2_BAR_PREFETCH (1L<<16)
6038#define PCI_CONFIG_2_RESERVED0 (0x7fffL<<17)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006039
6040/* config_3 offset */
Eilon Greenstein5c862842008-08-13 15:51:48 -07006041#define GRC_CONFIG_3_SIZE_REG 0x40c
6042#define PCI_CONFIG_3_STICKY_BYTE (0xffL<<0)
6043#define PCI_CONFIG_3_FORCE_PME (1L<<24)
6044#define PCI_CONFIG_3_PME_STATUS (1L<<25)
6045#define PCI_CONFIG_3_PME_ENABLE (1L<<26)
6046#define PCI_CONFIG_3_PM_STATE (0x3L<<27)
6047#define PCI_CONFIG_3_VAUX_PRESET (1L<<30)
6048#define PCI_CONFIG_3_PCI_POWER (1L<<31)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006049
6050#define GRC_BAR2_CONFIG 0x4e0
Eilon Greenstein5c862842008-08-13 15:51:48 -07006051#define PCI_CONFIG_2_BAR2_SIZE (0xfL<<0)
6052#define PCI_CONFIG_2_BAR2_SIZE_DISABLED (0L<<0)
6053#define PCI_CONFIG_2_BAR2_SIZE_64K (1L<<0)
6054#define PCI_CONFIG_2_BAR2_SIZE_128K (2L<<0)
6055#define PCI_CONFIG_2_BAR2_SIZE_256K (3L<<0)
6056#define PCI_CONFIG_2_BAR2_SIZE_512K (4L<<0)
6057#define PCI_CONFIG_2_BAR2_SIZE_1M (5L<<0)
6058#define PCI_CONFIG_2_BAR2_SIZE_2M (6L<<0)
6059#define PCI_CONFIG_2_BAR2_SIZE_4M (7L<<0)
6060#define PCI_CONFIG_2_BAR2_SIZE_8M (8L<<0)
6061#define PCI_CONFIG_2_BAR2_SIZE_16M (9L<<0)
6062#define PCI_CONFIG_2_BAR2_SIZE_32M (10L<<0)
6063#define PCI_CONFIG_2_BAR2_SIZE_64M (11L<<0)
6064#define PCI_CONFIG_2_BAR2_SIZE_128M (12L<<0)
6065#define PCI_CONFIG_2_BAR2_SIZE_256M (13L<<0)
6066#define PCI_CONFIG_2_BAR2_SIZE_512M (14L<<0)
6067#define PCI_CONFIG_2_BAR2_SIZE_1G (15L<<0)
6068#define PCI_CONFIG_2_BAR2_64ENA (1L<<4)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006069
Eilon Greenstein5c862842008-08-13 15:51:48 -07006070#define PCI_PM_DATA_A 0x410
6071#define PCI_PM_DATA_B 0x414
6072#define PCI_ID_VAL1 0x434
6073#define PCI_ID_VAL2 0x438
6074
Dmitry Kravkovf2e08992010-10-06 03:28:26 +00006075#define PXPCS_TL_CONTROL_5 0x814
6076#define PXPCS_TL_CONTROL_5_UNKNOWNTYPE_ERR_ATTN (1 << 29) /*WC*/
6077#define PXPCS_TL_CONTROL_5_BOUNDARY4K_ERR_ATTN (1 << 28) /*WC*/
6078#define PXPCS_TL_CONTROL_5_MRRS_ERR_ATTN (1 << 27) /*WC*/
6079#define PXPCS_TL_CONTROL_5_MPS_ERR_ATTN (1 << 26) /*WC*/
6080#define PXPCS_TL_CONTROL_5_TTX_BRIDGE_FORWARD_ERR (1 << 25) /*WC*/
6081#define PXPCS_TL_CONTROL_5_TTX_TXINTF_OVERFLOW (1 << 24) /*WC*/
6082#define PXPCS_TL_CONTROL_5_PHY_ERR_ATTN (1 << 23) /*RO*/
6083#define PXPCS_TL_CONTROL_5_DL_ERR_ATTN (1 << 22) /*RO*/
6084#define PXPCS_TL_CONTROL_5_TTX_ERR_NP_TAG_IN_USE (1 << 21) /*WC*/
6085#define PXPCS_TL_CONTROL_5_TRX_ERR_UNEXP_RTAG (1 << 20) /*WC*/
6086#define PXPCS_TL_CONTROL_5_PRI_SIG_TARGET_ABORT1 (1 << 19) /*WC*/
6087#define PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 (1 << 18) /*WC*/
6088#define PXPCS_TL_CONTROL_5_ERR_ECRC1 (1 << 17) /*WC*/
6089#define PXPCS_TL_CONTROL_5_ERR_MALF_TLP1 (1 << 16) /*WC*/
6090#define PXPCS_TL_CONTROL_5_ERR_RX_OFLOW1 (1 << 15) /*WC*/
6091#define PXPCS_TL_CONTROL_5_ERR_UNEXP_CPL1 (1 << 14) /*WC*/
6092#define PXPCS_TL_CONTROL_5_ERR_MASTER_ABRT1 (1 << 13) /*WC*/
6093#define PXPCS_TL_CONTROL_5_ERR_CPL_TIMEOUT1 (1 << 12) /*WC*/
6094#define PXPCS_TL_CONTROL_5_ERR_FC_PRTL1 (1 << 11) /*WC*/
6095#define PXPCS_TL_CONTROL_5_ERR_PSND_TLP1 (1 << 10) /*WC*/
6096#define PXPCS_TL_CONTROL_5_PRI_SIG_TARGET_ABORT (1 << 9) /*WC*/
6097#define PXPCS_TL_CONTROL_5_ERR_UNSPPORT (1 << 8) /*WC*/
6098#define PXPCS_TL_CONTROL_5_ERR_ECRC (1 << 7) /*WC*/
6099#define PXPCS_TL_CONTROL_5_ERR_MALF_TLP (1 << 6) /*WC*/
6100#define PXPCS_TL_CONTROL_5_ERR_RX_OFLOW (1 << 5) /*WC*/
6101#define PXPCS_TL_CONTROL_5_ERR_UNEXP_CPL (1 << 4) /*WC*/
6102#define PXPCS_TL_CONTROL_5_ERR_MASTER_ABRT (1 << 3) /*WC*/
6103#define PXPCS_TL_CONTROL_5_ERR_CPL_TIMEOUT (1 << 2) /*WC*/
6104#define PXPCS_TL_CONTROL_5_ERR_FC_PRTL (1 << 1) /*WC*/
6105#define PXPCS_TL_CONTROL_5_ERR_PSND_TLP (1 << 0) /*WC*/
6106
6107
6108#define PXPCS_TL_FUNC345_STAT 0x854
6109#define PXPCS_TL_FUNC345_STAT_PRI_SIG_TARGET_ABORT4 (1 << 29) /* WC */
6110#define PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4\
6111 (1 << 28) /* Unsupported Request Error Status in function4, if \
6112 set, generate pcie_err_attn output when this error is seen. WC */
6113#define PXPCS_TL_FUNC345_STAT_ERR_ECRC4\
6114 (1 << 27) /* ECRC Error TLP Status Status in function 4, if set, \
6115 generate pcie_err_attn output when this error is seen.. WC */
6116#define PXPCS_TL_FUNC345_STAT_ERR_MALF_TLP4\
6117 (1 << 26) /* Malformed TLP Status Status in function 4, if set, \
6118 generate pcie_err_attn output when this error is seen.. WC */
6119#define PXPCS_TL_FUNC345_STAT_ERR_RX_OFLOW4\
6120 (1 << 25) /* Receiver Overflow Status Status in function 4, if \
6121 set, generate pcie_err_attn output when this error is seen.. WC \
6122 */
6123#define PXPCS_TL_FUNC345_STAT_ERR_UNEXP_CPL4\
6124 (1 << 24) /* Unexpected Completion Status Status in function 4, \
6125 if set, generate pcie_err_attn output when this error is seen. WC \
6126 */
6127#define PXPCS_TL_FUNC345_STAT_ERR_MASTER_ABRT4\
6128 (1 << 23) /* Receive UR Statusin function 4. If set, generate \
6129 pcie_err_attn output when this error is seen. WC */
6130#define PXPCS_TL_FUNC345_STAT_ERR_CPL_TIMEOUT4\
6131 (1 << 22) /* Completer Timeout Status Status in function 4, if \
6132 set, generate pcie_err_attn output when this error is seen. WC */
6133#define PXPCS_TL_FUNC345_STAT_ERR_FC_PRTL4\
6134 (1 << 21) /* Flow Control Protocol Error Status Status in \
6135 function 4, if set, generate pcie_err_attn output when this error \
6136 is seen. WC */
6137#define PXPCS_TL_FUNC345_STAT_ERR_PSND_TLP4\
6138 (1 << 20) /* Poisoned Error Status Status in function 4, if set, \
6139 generate pcie_err_attn output when this error is seen.. WC */
6140#define PXPCS_TL_FUNC345_STAT_PRI_SIG_TARGET_ABORT3 (1 << 19) /* WC */
6141#define PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3\
6142 (1 << 18) /* Unsupported Request Error Status in function3, if \
6143 set, generate pcie_err_attn output when this error is seen. WC */
6144#define PXPCS_TL_FUNC345_STAT_ERR_ECRC3\
6145 (1 << 17) /* ECRC Error TLP Status Status in function 3, if set, \
6146 generate pcie_err_attn output when this error is seen.. WC */
6147#define PXPCS_TL_FUNC345_STAT_ERR_MALF_TLP3\
6148 (1 << 16) /* Malformed TLP Status Status in function 3, if set, \
6149 generate pcie_err_attn output when this error is seen.. WC */
6150#define PXPCS_TL_FUNC345_STAT_ERR_RX_OFLOW3\
6151 (1 << 15) /* Receiver Overflow Status Status in function 3, if \
6152 set, generate pcie_err_attn output when this error is seen.. WC \
6153 */
6154#define PXPCS_TL_FUNC345_STAT_ERR_UNEXP_CPL3\
6155 (1 << 14) /* Unexpected Completion Status Status in function 3, \
6156 if set, generate pcie_err_attn output when this error is seen. WC \
6157 */
6158#define PXPCS_TL_FUNC345_STAT_ERR_MASTER_ABRT3\
6159 (1 << 13) /* Receive UR Statusin function 3. If set, generate \
6160 pcie_err_attn output when this error is seen. WC */
6161#define PXPCS_TL_FUNC345_STAT_ERR_CPL_TIMEOUT3\
6162 (1 << 12) /* Completer Timeout Status Status in function 3, if \
6163 set, generate pcie_err_attn output when this error is seen. WC */
6164#define PXPCS_TL_FUNC345_STAT_ERR_FC_PRTL3\
6165 (1 << 11) /* Flow Control Protocol Error Status Status in \
6166 function 3, if set, generate pcie_err_attn output when this error \
6167 is seen. WC */
6168#define PXPCS_TL_FUNC345_STAT_ERR_PSND_TLP3\
6169 (1 << 10) /* Poisoned Error Status Status in function 3, if set, \
6170 generate pcie_err_attn output when this error is seen.. WC */
6171#define PXPCS_TL_FUNC345_STAT_PRI_SIG_TARGET_ABORT2 (1 << 9) /* WC */
6172#define PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2\
6173 (1 << 8) /* Unsupported Request Error Status for Function 2, if \
6174 set, generate pcie_err_attn output when this error is seen. WC */
6175#define PXPCS_TL_FUNC345_STAT_ERR_ECRC2\
6176 (1 << 7) /* ECRC Error TLP Status Status for Function 2, if set, \
6177 generate pcie_err_attn output when this error is seen.. WC */
6178#define PXPCS_TL_FUNC345_STAT_ERR_MALF_TLP2\
6179 (1 << 6) /* Malformed TLP Status Status for Function 2, if set, \
6180 generate pcie_err_attn output when this error is seen.. WC */
6181#define PXPCS_TL_FUNC345_STAT_ERR_RX_OFLOW2\
6182 (1 << 5) /* Receiver Overflow Status Status for Function 2, if \
6183 set, generate pcie_err_attn output when this error is seen.. WC \
6184 */
6185#define PXPCS_TL_FUNC345_STAT_ERR_UNEXP_CPL2\
6186 (1 << 4) /* Unexpected Completion Status Status for Function 2, \
6187 if set, generate pcie_err_attn output when this error is seen. WC \
6188 */
6189#define PXPCS_TL_FUNC345_STAT_ERR_MASTER_ABRT2\
6190 (1 << 3) /* Receive UR Statusfor Function 2. If set, generate \
6191 pcie_err_attn output when this error is seen. WC */
6192#define PXPCS_TL_FUNC345_STAT_ERR_CPL_TIMEOUT2\
6193 (1 << 2) /* Completer Timeout Status Status for Function 2, if \
6194 set, generate pcie_err_attn output when this error is seen. WC */
6195#define PXPCS_TL_FUNC345_STAT_ERR_FC_PRTL2\
6196 (1 << 1) /* Flow Control Protocol Error Status Status for \
6197 Function 2, if set, generate pcie_err_attn output when this error \
6198 is seen. WC */
6199#define PXPCS_TL_FUNC345_STAT_ERR_PSND_TLP2\
6200 (1 << 0) /* Poisoned Error Status Status for Function 2, if set, \
6201 generate pcie_err_attn output when this error is seen.. WC */
6202
6203
6204#define PXPCS_TL_FUNC678_STAT 0x85C
6205#define PXPCS_TL_FUNC678_STAT_PRI_SIG_TARGET_ABORT7 (1 << 29) /* WC */
6206#define PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7\
6207 (1 << 28) /* Unsupported Request Error Status in function7, if \
6208 set, generate pcie_err_attn output when this error is seen. WC */
6209#define PXPCS_TL_FUNC678_STAT_ERR_ECRC7\
6210 (1 << 27) /* ECRC Error TLP Status Status in function 7, if set, \
6211 generate pcie_err_attn output when this error is seen.. WC */
6212#define PXPCS_TL_FUNC678_STAT_ERR_MALF_TLP7\
6213 (1 << 26) /* Malformed TLP Status Status in function 7, if set, \
6214 generate pcie_err_attn output when this error is seen.. WC */
6215#define PXPCS_TL_FUNC678_STAT_ERR_RX_OFLOW7\
6216 (1 << 25) /* Receiver Overflow Status Status in function 7, if \
6217 set, generate pcie_err_attn output when this error is seen.. WC \
6218 */
6219#define PXPCS_TL_FUNC678_STAT_ERR_UNEXP_CPL7\
6220 (1 << 24) /* Unexpected Completion Status Status in function 7, \
6221 if set, generate pcie_err_attn output when this error is seen. WC \
6222 */
6223#define PXPCS_TL_FUNC678_STAT_ERR_MASTER_ABRT7\
6224 (1 << 23) /* Receive UR Statusin function 7. If set, generate \
6225 pcie_err_attn output when this error is seen. WC */
6226#define PXPCS_TL_FUNC678_STAT_ERR_CPL_TIMEOUT7\
6227 (1 << 22) /* Completer Timeout Status Status in function 7, if \
6228 set, generate pcie_err_attn output when this error is seen. WC */
6229#define PXPCS_TL_FUNC678_STAT_ERR_FC_PRTL7\
6230 (1 << 21) /* Flow Control Protocol Error Status Status in \
6231 function 7, if set, generate pcie_err_attn output when this error \
6232 is seen. WC */
6233#define PXPCS_TL_FUNC678_STAT_ERR_PSND_TLP7\
6234 (1 << 20) /* Poisoned Error Status Status in function 7, if set, \
6235 generate pcie_err_attn output when this error is seen.. WC */
6236#define PXPCS_TL_FUNC678_STAT_PRI_SIG_TARGET_ABORT6 (1 << 19) /* WC */
6237#define PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6\
6238 (1 << 18) /* Unsupported Request Error Status in function6, if \
6239 set, generate pcie_err_attn output when this error is seen. WC */
6240#define PXPCS_TL_FUNC678_STAT_ERR_ECRC6\
6241 (1 << 17) /* ECRC Error TLP Status Status in function 6, if set, \
6242 generate pcie_err_attn output when this error is seen.. WC */
6243#define PXPCS_TL_FUNC678_STAT_ERR_MALF_TLP6\
6244 (1 << 16) /* Malformed TLP Status Status in function 6, if set, \
6245 generate pcie_err_attn output when this error is seen.. WC */
6246#define PXPCS_TL_FUNC678_STAT_ERR_RX_OFLOW6\
6247 (1 << 15) /* Receiver Overflow Status Status in function 6, if \
6248 set, generate pcie_err_attn output when this error is seen.. WC \
6249 */
6250#define PXPCS_TL_FUNC678_STAT_ERR_UNEXP_CPL6\
6251 (1 << 14) /* Unexpected Completion Status Status in function 6, \
6252 if set, generate pcie_err_attn output when this error is seen. WC \
6253 */
6254#define PXPCS_TL_FUNC678_STAT_ERR_MASTER_ABRT6\
6255 (1 << 13) /* Receive UR Statusin function 6. If set, generate \
6256 pcie_err_attn output when this error is seen. WC */
6257#define PXPCS_TL_FUNC678_STAT_ERR_CPL_TIMEOUT6\
6258 (1 << 12) /* Completer Timeout Status Status in function 6, if \
6259 set, generate pcie_err_attn output when this error is seen. WC */
6260#define PXPCS_TL_FUNC678_STAT_ERR_FC_PRTL6\
6261 (1 << 11) /* Flow Control Protocol Error Status Status in \
6262 function 6, if set, generate pcie_err_attn output when this error \
6263 is seen. WC */
6264#define PXPCS_TL_FUNC678_STAT_ERR_PSND_TLP6\
6265 (1 << 10) /* Poisoned Error Status Status in function 6, if set, \
6266 generate pcie_err_attn output when this error is seen.. WC */
6267#define PXPCS_TL_FUNC678_STAT_PRI_SIG_TARGET_ABORT5 (1 << 9) /* WC */
6268#define PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5\
6269 (1 << 8) /* Unsupported Request Error Status for Function 5, if \
6270 set, generate pcie_err_attn output when this error is seen. WC */
6271#define PXPCS_TL_FUNC678_STAT_ERR_ECRC5\
6272 (1 << 7) /* ECRC Error TLP Status Status for Function 5, if set, \
6273 generate pcie_err_attn output when this error is seen.. WC */
6274#define PXPCS_TL_FUNC678_STAT_ERR_MALF_TLP5\
6275 (1 << 6) /* Malformed TLP Status Status for Function 5, if set, \
6276 generate pcie_err_attn output when this error is seen.. WC */
6277#define PXPCS_TL_FUNC678_STAT_ERR_RX_OFLOW5\
6278 (1 << 5) /* Receiver Overflow Status Status for Function 5, if \
6279 set, generate pcie_err_attn output when this error is seen.. WC \
6280 */
6281#define PXPCS_TL_FUNC678_STAT_ERR_UNEXP_CPL5\
6282 (1 << 4) /* Unexpected Completion Status Status for Function 5, \
6283 if set, generate pcie_err_attn output when this error is seen. WC \
6284 */
6285#define PXPCS_TL_FUNC678_STAT_ERR_MASTER_ABRT5\
6286 (1 << 3) /* Receive UR Statusfor Function 5. If set, generate \
6287 pcie_err_attn output when this error is seen. WC */
6288#define PXPCS_TL_FUNC678_STAT_ERR_CPL_TIMEOUT5\
6289 (1 << 2) /* Completer Timeout Status Status for Function 5, if \
6290 set, generate pcie_err_attn output when this error is seen. WC */
6291#define PXPCS_TL_FUNC678_STAT_ERR_FC_PRTL5\
6292 (1 << 1) /* Flow Control Protocol Error Status Status for \
6293 Function 5, if set, generate pcie_err_attn output when this error \
6294 is seen. WC */
6295#define PXPCS_TL_FUNC678_STAT_ERR_PSND_TLP5\
6296 (1 << 0) /* Poisoned Error Status Status for Function 5, if set, \
6297 generate pcie_err_attn output when this error is seen.. WC */
6298
6299
6300#define BAR_USTRORM_INTMEM 0x400000
6301#define BAR_CSTRORM_INTMEM 0x410000
6302#define BAR_XSTRORM_INTMEM 0x420000
6303#define BAR_TSTRORM_INTMEM 0x430000
6304
6305/* for accessing the IGU in case of status block ACK */
6306#define BAR_IGU_INTMEM 0x440000
6307
6308#define BAR_DOORBELL_OFFSET 0x800000
6309
6310#define BAR_ME_REGISTER 0x450000
6311#define ME_REG_PF_NUM_SHIFT 0
6312#define ME_REG_PF_NUM\
6313 (7L<<ME_REG_PF_NUM_SHIFT) /* Relative PF Num */
6314#define ME_REG_VF_VALID (1<<8)
6315#define ME_REG_VF_NUM_SHIFT 9
6316#define ME_REG_VF_NUM_MASK (0x3f<<ME_REG_VF_NUM_SHIFT)
6317#define ME_REG_VF_ERR (0x1<<3)
6318#define ME_REG_ABS_PF_NUM_SHIFT 16
6319#define ME_REG_ABS_PF_NUM\
6320 (7L<<ME_REG_ABS_PF_NUM_SHIFT) /* Absolute PF Num */
6321
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006322
Yaniv Rosner7846e472009-11-05 19:18:07 +02006323#define MDIO_REG_BANK_CL73_IEEEB0 0x0
6324#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL 0x0
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006325#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN 0x0200
6326#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN 0x1000
6327#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_MAIN_RST 0x8000
6328
Yaniv Rosner7846e472009-11-05 19:18:07 +02006329#define MDIO_REG_BANK_CL73_IEEEB1 0x10
6330#define MDIO_CL73_IEEEB1_AN_ADV1 0x00
6331#define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE 0x0400
6332#define MDIO_CL73_IEEEB1_AN_ADV1_ASYMMETRIC 0x0800
6333#define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH 0x0C00
6334#define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK 0x0C00
6335#define MDIO_CL73_IEEEB1_AN_ADV2 0x01
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006336#define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M 0x0000
6337#define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX 0x0020
6338#define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 0x0040
6339#define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR 0x0080
Yaniv Rosner7846e472009-11-05 19:18:07 +02006340#define MDIO_CL73_IEEEB1_AN_LP_ADV1 0x03
6341#define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE 0x0400
6342#define MDIO_CL73_IEEEB1_AN_LP_ADV1_ASYMMETRIC 0x0800
6343#define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_BOTH 0x0C00
6344#define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK 0x0C00
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006345
6346#define MDIO_REG_BANK_RX0 0x80b0
Eilon Greenstein239d6862009-08-12 08:23:04 +00006347#define MDIO_RX0_RX_STATUS 0x10
6348#define MDIO_RX0_RX_STATUS_SIGDET 0x8000
6349#define MDIO_RX0_RX_STATUS_RX_SEQ_DONE 0x1000
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006350#define MDIO_RX0_RX_EQ_BOOST 0x1c
6351#define MDIO_RX0_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
6352#define MDIO_RX0_RX_EQ_BOOST_OFFSET_CTRL 0x10
6353
6354#define MDIO_REG_BANK_RX1 0x80c0
6355#define MDIO_RX1_RX_EQ_BOOST 0x1c
6356#define MDIO_RX1_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
6357#define MDIO_RX1_RX_EQ_BOOST_OFFSET_CTRL 0x10
6358
6359#define MDIO_REG_BANK_RX2 0x80d0
6360#define MDIO_RX2_RX_EQ_BOOST 0x1c
6361#define MDIO_RX2_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
6362#define MDIO_RX2_RX_EQ_BOOST_OFFSET_CTRL 0x10
6363
6364#define MDIO_REG_BANK_RX3 0x80e0
6365#define MDIO_RX3_RX_EQ_BOOST 0x1c
6366#define MDIO_RX3_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
6367#define MDIO_RX3_RX_EQ_BOOST_OFFSET_CTRL 0x10
6368
6369#define MDIO_REG_BANK_RX_ALL 0x80f0
6370#define MDIO_RX_ALL_RX_EQ_BOOST 0x1c
6371#define MDIO_RX_ALL_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07006372#define MDIO_RX_ALL_RX_EQ_BOOST_OFFSET_CTRL 0x10
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006373
6374#define MDIO_REG_BANK_TX0 0x8060
6375#define MDIO_TX0_TX_DRIVER 0x17
6376#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
6377#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
6378#define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
6379#define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8
6380#define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
6381#define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
6382#define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
6383#define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
6384#define MDIO_TX0_TX_DRIVER_ICBUF1T 1
6385
Eilon Greensteinc2c8b032009-02-12 08:37:14 +00006386#define MDIO_REG_BANK_TX1 0x8070
6387#define MDIO_TX1_TX_DRIVER 0x17
6388#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
6389#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
6390#define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
6391#define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8
6392#define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
6393#define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
6394#define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
6395#define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
6396#define MDIO_TX0_TX_DRIVER_ICBUF1T 1
6397
6398#define MDIO_REG_BANK_TX2 0x8080
6399#define MDIO_TX2_TX_DRIVER 0x17
6400#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
6401#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
6402#define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
6403#define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8
6404#define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
6405#define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
6406#define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
6407#define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
6408#define MDIO_TX0_TX_DRIVER_ICBUF1T 1
6409
6410#define MDIO_REG_BANK_TX3 0x8090
6411#define MDIO_TX3_TX_DRIVER 0x17
6412#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
6413#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
6414#define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
6415#define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8
6416#define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
6417#define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
6418#define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
6419#define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
6420#define MDIO_TX0_TX_DRIVER_ICBUF1T 1
6421
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006422#define MDIO_REG_BANK_XGXS_BLOCK0 0x8000
6423#define MDIO_BLOCK0_XGXS_CONTROL 0x10
6424
6425#define MDIO_REG_BANK_XGXS_BLOCK1 0x8010
6426#define MDIO_BLOCK1_LANE_CTRL0 0x15
6427#define MDIO_BLOCK1_LANE_CTRL1 0x16
6428#define MDIO_BLOCK1_LANE_CTRL2 0x17
6429#define MDIO_BLOCK1_LANE_PRBS 0x19
6430
6431#define MDIO_REG_BANK_XGXS_BLOCK2 0x8100
6432#define MDIO_XGXS_BLOCK2_RX_LN_SWAP 0x10
6433#define MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE 0x8000
6434#define MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE 0x4000
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07006435#define MDIO_XGXS_BLOCK2_TX_LN_SWAP 0x11
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006436#define MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE 0x8000
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07006437#define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G 0x14
Eliezer Tamirf1410642008-02-28 11:51:50 -08006438#define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS 0x0001
6439#define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS 0x0010
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07006440#define MDIO_XGXS_BLOCK2_TEST_MODE_LANE 0x15
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006441
6442#define MDIO_REG_BANK_GP_STATUS 0x8120
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07006443#define MDIO_GP_STATUS_TOP_AN_STATUS1 0x1B
6444#define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE 0x0001
6445#define MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE 0x0002
6446#define MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS 0x0004
6447#define MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS 0x0008
6448#define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE 0x0010
6449#define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_LP_NP_BAM_ABLE 0x0020
6450#define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE 0x0040
6451#define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE 0x0080
6452#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK 0x3f00
6453#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M 0x0000
6454#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M 0x0100
6455#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G 0x0200
6456#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G 0x0300
6457#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G 0x0400
6458#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G 0x0500
6459#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG 0x0600
6460#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4 0x0700
6461#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12G_HIG 0x0800
6462#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12_5G 0x0900
6463#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_13G 0x0A00
6464#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_15G 0x0B00
6465#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_16G 0x0C00
6466#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX 0x0D00
6467#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4 0x0E00
Yaniv Rosner3c9ada22011-06-14 01:34:12 +00006468#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KR 0x0F00
6469#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_XFI 0x1B00
6470#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_DXGXS 0x1E00
6471#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_SFI 0x1F00
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006472
6473
6474#define MDIO_REG_BANK_10G_PARALLEL_DETECT 0x8130
Yaniv Rosner15ddd2d2009-11-05 19:18:12 +02006475#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS 0x10
6476#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK 0x8000
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07006477#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL 0x11
6478#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN 0x1
6479#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK 0x13
6480#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT (0xb71<<1)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006481
6482#define MDIO_REG_BANK_SERDES_DIGITAL 0x8300
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07006483#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1 0x10
6484#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE 0x0001
6485#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_TBI_IF 0x0002
6486#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN 0x0004
6487#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT 0x0008
6488#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET 0x0010
6489#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE 0x0020
6490#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2 0x11
6491#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN 0x0001
6492#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_AN_FST_TMR 0x0040
6493#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1 0x14
Yaniv Rosnera22f0782010-09-07 11:41:20 +00006494#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SGMII 0x0001
6495#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_LINK 0x0002
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07006496#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_DUPLEX 0x0004
6497#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_MASK 0x0018
6498#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_SHIFT 3
6499#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_2_5G 0x0018
6500#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_1G 0x0010
6501#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_100M 0x0008
6502#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_10M 0x0000
Yaniv Rosner15ddd2d2009-11-05 19:18:12 +02006503#define MDIO_SERDES_DIGITAL_A_1000X_STATUS2 0x15
6504#define MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED 0x0002
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07006505#define MDIO_SERDES_DIGITAL_MISC1 0x18
6506#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_MASK 0xE000
6507#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_25M 0x0000
6508#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_100M 0x2000
6509#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_125M 0x4000
6510#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M 0x6000
6511#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_187_5M 0x8000
6512#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL 0x0010
6513#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK 0x000f
6514#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_2_5G 0x0000
6515#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_5G 0x0001
6516#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_6G 0x0002
6517#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_HIG 0x0003
6518#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4 0x0004
6519#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12G 0x0005
6520#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12_5G 0x0006
6521#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_13G 0x0007
6522#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_15G 0x0008
6523#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_16G 0x0009
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006524
6525#define MDIO_REG_BANK_OVER_1G 0x8320
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07006526#define MDIO_OVER_1G_DIGCTL_3_4 0x14
6527#define MDIO_OVER_1G_DIGCTL_3_4_MP_ID_MASK 0xffe0
6528#define MDIO_OVER_1G_DIGCTL_3_4_MP_ID_SHIFT 5
6529#define MDIO_OVER_1G_UP1 0x19
6530#define MDIO_OVER_1G_UP1_2_5G 0x0001
6531#define MDIO_OVER_1G_UP1_5G 0x0002
6532#define MDIO_OVER_1G_UP1_6G 0x0004
6533#define MDIO_OVER_1G_UP1_10G 0x0010
6534#define MDIO_OVER_1G_UP1_10GH 0x0008
6535#define MDIO_OVER_1G_UP1_12G 0x0020
6536#define MDIO_OVER_1G_UP1_12_5G 0x0040
6537#define MDIO_OVER_1G_UP1_13G 0x0080
6538#define MDIO_OVER_1G_UP1_15G 0x0100
6539#define MDIO_OVER_1G_UP1_16G 0x0200
6540#define MDIO_OVER_1G_UP2 0x1A
6541#define MDIO_OVER_1G_UP2_IPREDRIVER_MASK 0x0007
6542#define MDIO_OVER_1G_UP2_IDRIVER_MASK 0x0038
6543#define MDIO_OVER_1G_UP2_PREEMPHASIS_MASK 0x03C0
6544#define MDIO_OVER_1G_UP3 0x1B
6545#define MDIO_OVER_1G_UP3_HIGIG2 0x0001
6546#define MDIO_OVER_1G_LP_UP1 0x1C
6547#define MDIO_OVER_1G_LP_UP2 0x1D
6548#define MDIO_OVER_1G_LP_UP2_MR_ADV_OVER_1G_MASK 0x03ff
6549#define MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK 0x0780
6550#define MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT 7
6551#define MDIO_OVER_1G_LP_UP3 0x1E
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006552
Eilon Greenstein239d6862009-08-12 08:23:04 +00006553#define MDIO_REG_BANK_REMOTE_PHY 0x8330
6554#define MDIO_REMOTE_PHY_MISC_RX_STATUS 0x10
6555#define MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG 0x0010
6556#define MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG 0x0600
6557
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006558#define MDIO_REG_BANK_BAM_NEXT_PAGE 0x8350
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07006559#define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL 0x10
6560#define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE 0x0001
6561#define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN 0x0002
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006562
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07006563#define MDIO_REG_BANK_CL73_USERB0 0x8370
Eilon Greenstein239d6862009-08-12 08:23:04 +00006564#define MDIO_CL73_USERB0_CL73_UCTRL 0x10
6565#define MDIO_CL73_USERB0_CL73_UCTRL_USTAT1_MUXSEL 0x0002
6566#define MDIO_CL73_USERB0_CL73_USTAT1 0x11
6567#define MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK 0x0100
6568#define MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37 0x0400
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07006569#define MDIO_CL73_USERB0_CL73_BAM_CTRL1 0x12
6570#define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN 0x8000
6571#define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN 0x4000
6572#define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN 0x2000
6573#define MDIO_CL73_USERB0_CL73_BAM_CTRL3 0x14
6574#define MDIO_CL73_USERB0_CL73_BAM_CTRL3_USE_CL73_HCD_MR 0x0001
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006575
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07006576#define MDIO_REG_BANK_AER_BLOCK 0xFFD0
6577#define MDIO_AER_BLOCK_AER_REG 0x1E
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006578
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07006579#define MDIO_REG_BANK_COMBO_IEEE0 0xFFE0
6580#define MDIO_COMBO_IEEE0_MII_CONTROL 0x10
6581#define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK 0x2040
6582#define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_10 0x0000
6583#define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100 0x2000
6584#define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000 0x0040
6585#define MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX 0x0100
6586#define MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN 0x0200
6587#define MDIO_COMBO_IEEO_MII_CONTROL_AN_EN 0x1000
6588#define MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK 0x4000
6589#define MDIO_COMBO_IEEO_MII_CONTROL_RESET 0x8000
6590#define MDIO_COMBO_IEEE0_MII_STATUS 0x11
6591#define MDIO_COMBO_IEEE0_MII_STATUS_LINK_PASS 0x0004
6592#define MDIO_COMBO_IEEE0_MII_STATUS_AUTONEG_COMPLETE 0x0020
6593#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV 0x14
6594#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX 0x0020
6595#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_HALF_DUPLEX 0x0040
6596#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK 0x0180
6597#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE 0x0000
6598#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC 0x0080
6599#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC 0x0100
6600#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH 0x0180
6601#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_NEXT_PAGE 0x8000
6602#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1 0x15
6603#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_NEXT_PAGE 0x8000
6604#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_ACK 0x4000
6605#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_MASK 0x0180
6606#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_NONE 0x0000
6607#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_BOTH 0x0180
6608#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_HALF_DUP_CAP 0x0040
6609#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_FULL_DUP_CAP 0x0020
6610/*WhenthelinkpartnerisinSGMIImode(bit0=1),then
6611bit15=link,bit12=duplex,bits11:10=speed,bit14=acknowledge.
6612Theotherbitsarereservedandshouldbezero*/
6613#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_SGMII_MODE 0x0001
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006614
6615
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07006616#define MDIO_PMA_DEVAD 0x1
6617/*ieee*/
6618#define MDIO_PMA_REG_CTRL 0x0
6619#define MDIO_PMA_REG_STATUS 0x1
6620#define MDIO_PMA_REG_10G_CTRL2 0x7
6621#define MDIO_PMA_REG_RX_SD 0xa
6622/*bcm*/
6623#define MDIO_PMA_REG_BCM_CTRL 0x0096
6624#define MDIO_PMA_REG_FEC_CTRL 0x00ab
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07006625#define MDIO_PMA_REG_PHY_IDENTIFIER 0xc800
6626#define MDIO_PMA_REG_DIGITAL_CTRL 0xc808
6627#define MDIO_PMA_REG_DIGITAL_STATUS 0xc809
6628#define MDIO_PMA_REG_TX_POWER_DOWN 0xca02
6629#define MDIO_PMA_REG_CMU_PLL_BYPASS 0xca09
6630#define MDIO_PMA_REG_MISC_CTRL 0xca0a
6631#define MDIO_PMA_REG_GEN_CTRL 0xca10
6632#define MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP 0x0188
6633#define MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET 0x018a
Yaniv Rosner57963ed2008-08-13 15:55:28 -07006634#define MDIO_PMA_REG_M8051_MSGIN_REG 0xca12
6635#define MDIO_PMA_REG_M8051_MSGOUT_REG 0xca13
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07006636#define MDIO_PMA_REG_ROM_VER1 0xca19
6637#define MDIO_PMA_REG_ROM_VER2 0xca1a
6638#define MDIO_PMA_REG_EDC_FFE_MAIN 0xca1b
6639#define MDIO_PMA_REG_PLL_BANDWIDTH 0xca1d
Eilon Greenstein4d295db2009-07-21 05:47:47 +00006640#define MDIO_PMA_REG_PLL_CTRL 0xca1e
Eilon Greenstein589abe32009-02-12 08:36:55 +00006641#define MDIO_PMA_REG_MISC_CTRL0 0xca23
6642#define MDIO_PMA_REG_LRM_MODE 0xca3f
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07006643#define MDIO_PMA_REG_CDR_BANDWIDTH 0xca46
6644#define MDIO_PMA_REG_MISC_CTRL1 0xca85
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006645
Eilon Greenstein4d295db2009-07-21 05:47:47 +00006646#define MDIO_PMA_REG_SFP_TWO_WIRE_CTRL 0x8000
6647#define MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK 0x000c
6648#define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE 0x0000
6649#define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE 0x0004
6650#define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IN_PROGRESS 0x0008
6651#define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_FAILED 0x000c
6652#define MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT 0x8002
6653#define MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR 0x8003
Eilon Greenstein589abe32009-02-12 08:36:55 +00006654#define MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF 0xc820
6655#define MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK 0xff
6656#define MDIO_PMA_REG_8726_TX_CTRL1 0xca01
6657#define MDIO_PMA_REG_8726_TX_CTRL2 0xca05
6658
Eilon Greenstein4d295db2009-07-21 05:47:47 +00006659#define MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR 0x8005
6660#define MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF 0x8007
6661#define MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK 0xff
Eilon Greenstein4d295db2009-07-21 05:47:47 +00006662#define MDIO_PMA_REG_8727_TX_CTRL1 0xca02
6663#define MDIO_PMA_REG_8727_TX_CTRL2 0xca05
6664#define MDIO_PMA_REG_8727_PCS_OPT_CTRL 0xc808
6665#define MDIO_PMA_REG_8727_GPIO_CTRL 0xc80e
Yaniv Rosnere10bc842010-09-07 11:40:50 +00006666#define MDIO_PMA_REG_8727_PCS_GP 0xc842
Yaniv Rosnera8db5b42011-01-31 04:22:28 +00006667#define MDIO_PMA_REG_8727_OPT_CFG_REG 0xc8e4
Yaniv Rosnere10bc842010-09-07 11:40:50 +00006668
6669#define MDIO_AN_REG_8727_MISC_CTRL 0x8309
Eilon Greenstein589abe32009-02-12 08:36:55 +00006670
Eilon Greenstein052a38e2009-02-12 08:37:16 +00006671#define MDIO_PMA_REG_8073_CHIP_REV 0xc801
6672#define MDIO_PMA_REG_8073_SPEED_LINK_STATUS 0xc820
6673#define MDIO_PMA_REG_8073_XAUI_WA 0xc841
Yaniv Rosnere10bc842010-09-07 11:40:50 +00006674#define MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL 0xcd08
Eilon Greenstein052a38e2009-02-12 08:37:16 +00006675
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07006676#define MDIO_PMA_REG_7101_RESET 0xc000
6677#define MDIO_PMA_REG_7107_LED_CNTL 0xc007
Yaniv Rosnere10bc842010-09-07 11:40:50 +00006678#define MDIO_PMA_REG_7107_LINK_LED_CNTL 0xc009
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07006679#define MDIO_PMA_REG_7101_VER1 0xc026
6680#define MDIO_PMA_REG_7101_VER2 0xc027
Eliezer Tamirf1410642008-02-28 11:51:50 -08006681
Yaniv Rosner7f02c4a2010-09-07 11:41:23 +00006682#define MDIO_PMA_REG_8481_PMD_SIGNAL 0xa811
6683#define MDIO_PMA_REG_8481_LED1_MASK 0xa82c
6684#define MDIO_PMA_REG_8481_LED2_MASK 0xa82f
6685#define MDIO_PMA_REG_8481_LED3_MASK 0xa832
6686#define MDIO_PMA_REG_8481_LED3_BLINK 0xa834
6687#define MDIO_PMA_REG_8481_LED5_MASK 0xa838
6688#define MDIO_PMA_REG_8481_SIGNAL_MASK 0xa835
6689#define MDIO_PMA_REG_8481_LINK_SIGNAL 0xa83b
6690#define MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK 0x800
6691#define MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT 11
Eilon Greenstein2f904462009-08-12 08:22:16 +00006692
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07006693
6694#define MDIO_WIS_DEVAD 0x2
6695/*bcm*/
6696#define MDIO_WIS_REG_LASI_CNTL 0x9002
6697#define MDIO_WIS_REG_LASI_STATUS 0x9005
6698
6699#define MDIO_PCS_DEVAD 0x3
6700#define MDIO_PCS_REG_STATUS 0x0020
6701#define MDIO_PCS_REG_LASI_STATUS 0x9005
6702#define MDIO_PCS_REG_7101_DSP_ACCESS 0xD000
6703#define MDIO_PCS_REG_7101_SPI_MUX 0xD008
6704#define MDIO_PCS_REG_7101_SPI_CTRL_ADDR 0xE12A
6705#define MDIO_PCS_REG_7101_SPI_RESET_BIT (5)
6706#define MDIO_PCS_REG_7101_SPI_FIFO_ADDR 0xE02A
6707#define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_WRITE_ENABLE_CMD (6)
6708#define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_BULK_ERASE_CMD (0xC7)
6709#define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_PAGE_PROGRAM_CMD (2)
6710#define MDIO_PCS_REG_7101_SPI_BYTES_TO_TRANSFER_ADDR 0xE028
6711
6712
6713#define MDIO_XS_DEVAD 0x4
6714#define MDIO_XS_PLL_SEQUENCER 0x8000
6715#define MDIO_XS_SFX7101_XGXS_TEST1 0xc00a
6716
Eilon Greenstein589abe32009-02-12 08:36:55 +00006717#define MDIO_XS_8706_REG_BANK_RX0 0x80bc
6718#define MDIO_XS_8706_REG_BANK_RX1 0x80cc
6719#define MDIO_XS_8706_REG_BANK_RX2 0x80dc
6720#define MDIO_XS_8706_REG_BANK_RX3 0x80ec
6721#define MDIO_XS_8706_REG_BANK_RXA 0x80fc
6722
Yaniv Rosnera22f0782010-09-07 11:41:20 +00006723#define MDIO_XS_REG_8073_RX_CTRL_PCIE 0x80FA
6724
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07006725#define MDIO_AN_DEVAD 0x7
6726/*ieee*/
6727#define MDIO_AN_REG_CTRL 0x0000
6728#define MDIO_AN_REG_STATUS 0x0001
6729#define MDIO_AN_REG_STATUS_AN_COMPLETE 0x0020
6730#define MDIO_AN_REG_ADV_PAUSE 0x0010
6731#define MDIO_AN_REG_ADV_PAUSE_PAUSE 0x0400
6732#define MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC 0x0800
6733#define MDIO_AN_REG_ADV_PAUSE_BOTH 0x0C00
6734#define MDIO_AN_REG_ADV_PAUSE_MASK 0x0C00
6735#define MDIO_AN_REG_ADV 0x0011
6736#define MDIO_AN_REG_ADV2 0x0012
6737#define MDIO_AN_REG_LP_AUTO_NEG 0x0013
6738#define MDIO_AN_REG_MASTER_STATUS 0x0021
6739/*bcm*/
6740#define MDIO_AN_REG_LINK_STATUS 0x8304
6741#define MDIO_AN_REG_CL37_CL73 0x8370
6742#define MDIO_AN_REG_CL37_AN 0xffe0
Yaniv Rosner8c99e7b2008-08-13 15:56:17 -07006743#define MDIO_AN_REG_CL37_FC_LD 0xffe4
6744#define MDIO_AN_REG_CL37_FC_LP 0xffe5
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07006745
Eilon Greenstein052a38e2009-02-12 08:37:16 +00006746#define MDIO_AN_REG_8073_2_5G 0x8329
Yaniv Rosnere10bc842010-09-07 11:40:50 +00006747#define MDIO_AN_REG_8073_BAM 0x8350
Eilon Greenstein052a38e2009-02-12 08:37:16 +00006748
Yaniv Rosnerac4d9442010-09-01 09:51:25 +00006749#define MDIO_AN_REG_8481_10GBASE_T_AN_CTRL 0x0020
Eilon Greenstein2f904462009-08-12 08:22:16 +00006750#define MDIO_AN_REG_8481_LEGACY_MII_CTRL 0xffe0
Yaniv Rosnere10bc842010-09-07 11:40:50 +00006751#define MDIO_AN_REG_8481_LEGACY_MII_STATUS 0xffe1
Eilon Greenstein2f904462009-08-12 08:22:16 +00006752#define MDIO_AN_REG_8481_LEGACY_AN_ADV 0xffe4
Yaniv Rosnere10bc842010-09-07 11:40:50 +00006753#define MDIO_AN_REG_8481_LEGACY_AN_EXPANSION 0xffe6
Eilon Greenstein2f904462009-08-12 08:22:16 +00006754#define MDIO_AN_REG_8481_1000T_CTRL 0xffe9
6755#define MDIO_AN_REG_8481_EXPANSION_REG_RD_RW 0xfff5
6756#define MDIO_AN_REG_8481_EXPANSION_REG_ACCESS 0xfff7
Yaniv Rosnerac4d9442010-09-01 09:51:25 +00006757#define MDIO_AN_REG_8481_AUX_CTRL 0xfff8
Eilon Greenstein2f904462009-08-12 08:22:16 +00006758#define MDIO_AN_REG_8481_LEGACY_SHADOW 0xfffc
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07006759
Yaniv Rosnera22f0782010-09-07 11:41:20 +00006760/* BCM84823 only */
6761#define MDIO_CTL_DEVAD 0x1e
6762#define MDIO_CTL_REG_84823_MEDIA 0x401a
6763#define MDIO_CTL_REG_84823_MEDIA_MAC_MASK 0x0018
6764 /* These pins configure the BCM84823 interface to MAC after reset. */
6765#define MDIO_CTL_REG_84823_CTRL_MAC_XFI 0x0008
6766#define MDIO_CTL_REG_84823_MEDIA_MAC_XAUI_M 0x0010
6767 /* These pins configure the BCM84823 interface to Line after reset. */
6768#define MDIO_CTL_REG_84823_MEDIA_LINE_MASK 0x0060
6769#define MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L 0x0020
6770#define MDIO_CTL_REG_84823_MEDIA_LINE_XFI 0x0040
6771 /* When this pin is active high during reset, 10GBASE-T core is power
6772 * down, When it is active low the 10GBASE-T is power up
6773 */
6774#define MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN 0x0080
6775#define MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK 0x0100
6776#define MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER 0x0000
6777#define MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER 0x0100
6778#define MDIO_CTL_REG_84823_MEDIA_FIBER_1G 0x1000
Yaniv Rosnerf25b3c82011-01-18 04:33:47 +00006779#define MDIO_CTL_REG_84823_USER_CTRL_REG 0x4005
6780#define MDIO_CTL_REG_84823_USER_CTRL_CMS 0x0080
Yaniv Rosnera22f0782010-09-07 11:41:20 +00006781
Yaniv Rosnerf25b3c82011-01-18 04:33:47 +00006782#define MDIO_PMA_REG_84823_CTL_LED_CTL_1 0xa8e3
6783#define MDIO_PMA_REG_84823_LED3_STRETCH_EN 0x0080
Yaniv Rosnera22f0782010-09-07 11:41:20 +00006784
Yaniv Rosnerbac27bd2011-05-31 21:28:10 +00006785/* BCM84833 only */
6786#define MDIO_84833_TOP_CFG_XGPHY_STRAP1 0x401a
6787#define MDIO_84833_SUPER_ISOLATE 0x8000
6788/* These are mailbox register set used by 84833. */
6789#define MDIO_84833_TOP_CFG_SCRATCH_REG0 0x4005
6790#define MDIO_84833_TOP_CFG_SCRATCH_REG1 0x4006
6791#define MDIO_84833_TOP_CFG_SCRATCH_REG2 0x4007
6792#define MDIO_84833_TOP_CFG_SCRATCH_REG3 0x4008
6793#define MDIO_84833_TOP_CFG_SCRATCH_REG4 0x4009
6794
6795/* Mailbox command set used by 84833. */
6796#define PHY84833_DIAG_CMD_PAIR_SWAP_CHANGE 0x2
6797/* Mailbox status set used by 84833. */
6798#define PHY84833_CMD_RECEIVED 0x0001
6799#define PHY84833_CMD_IN_PROGRESS 0x0002
6800#define PHY84833_CMD_COMPLETE_PASS 0x0004
6801#define PHY84833_CMD_COMPLETE_ERROR 0x0008
6802#define PHY84833_CMD_OPEN_FOR_CMDS 0x0010
6803#define PHY84833_CMD_SYSTEM_BOOT 0x0020
6804#define PHY84833_CMD_NOT_OPEN_FOR_CMDS 0x0040
6805#define PHY84833_CMD_CLEAR_COMPLETE 0x0080
6806#define PHY84833_CMD_OPEN_OVERRIDE 0xa5a5
6807
Yaniv Rosner3c9ada22011-06-14 01:34:12 +00006808/* Warpcore clause 45 addressing */
6809#define MDIO_WC_DEVAD 0x3
6810#define MDIO_WC_REG_IEEE0BLK_MIICNTL 0x0
6811#define MDIO_WC_REG_IEEE0BLK_AUTONEGNP 0x7
6812#define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT0 0x10
6813#define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1 0x11
6814#define MDIO_WC_REG_PMD_IEEE9BLK_TENGBASE_KR_PMD_CONTROL_REGISTER_150 0x96
6815#define MDIO_WC_REG_XGXSBLK0_XGXSCONTROL 0x8000
6816#define MDIO_WC_REG_XGXSBLK0_MISCCONTROL1 0x800e
6817#define MDIO_WC_REG_XGXSBLK1_DESKEW 0x8010
6818#define MDIO_WC_REG_XGXSBLK1_LANECTRL0 0x8015
6819#define MDIO_WC_REG_XGXSBLK1_LANECTRL1 0x8016
6820#define MDIO_WC_REG_XGXSBLK1_LANECTRL2 0x8017
6821#define MDIO_WC_REG_TX0_ANA_CTRL0 0x8061
6822#define MDIO_WC_REG_TX1_ANA_CTRL0 0x8071
6823#define MDIO_WC_REG_TX2_ANA_CTRL0 0x8081
6824#define MDIO_WC_REG_TX3_ANA_CTRL0 0x8091
6825#define MDIO_WC_REG_TX0_TX_DRIVER 0x8067
6826#define MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET 0x04
6827#define MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_MASK 0x00f0
6828#define MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET 0x08
6829#define MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
6830#define MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET 0x0c
6831#define MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_MASK 0x7000
6832#define MDIO_WC_REG_TX1_TX_DRIVER 0x8077
6833#define MDIO_WC_REG_TX2_TX_DRIVER 0x8087
6834#define MDIO_WC_REG_TX3_TX_DRIVER 0x8097
6835#define MDIO_WC_REG_RX0_ANARXCONTROL1G 0x80b9
6836#define MDIO_WC_REG_RX2_ANARXCONTROL1G 0x80d9
6837#define MDIO_WC_REG_RX0_PCI_CTRL 0x80ba
6838#define MDIO_WC_REG_RX1_PCI_CTRL 0x80ca
6839#define MDIO_WC_REG_RX2_PCI_CTRL 0x80da
6840#define MDIO_WC_REG_RX3_PCI_CTRL 0x80ea
6841#define MDIO_WC_REG_XGXSBLK2_UNICORE_MODE_10G 0x8104
6842#define MDIO_WC_REG_XGXS_STATUS3 0x8129
6843#define MDIO_WC_REG_PAR_DET_10G_STATUS 0x8130
6844#define MDIO_WC_REG_PAR_DET_10G_CTRL 0x8131
6845#define MDIO_WC_REG_XGXS_X2_CONTROL2 0x8141
6846#define MDIO_WC_REG_XGXS_RX_LN_SWAP1 0x816B
6847#define MDIO_WC_REG_XGXS_TX_LN_SWAP1 0x8169
6848#define MDIO_WC_REG_GP2_STATUS_GP_2_0 0x81d0
6849#define MDIO_WC_REG_GP2_STATUS_GP_2_1 0x81d1
6850#define MDIO_WC_REG_GP2_STATUS_GP_2_2 0x81d2
6851#define MDIO_WC_REG_GP2_STATUS_GP_2_3 0x81d3
6852#define MDIO_WC_REG_GP2_STATUS_GP_2_4 0x81d4
6853#define MDIO_WC_REG_UC_INFO_B0_DEAD_TRAP 0x81EE
6854#define MDIO_WC_REG_UC_INFO_B1_VERSION 0x81F0
6855#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE 0x81F2
6856#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE0_OFFSET 0x0
6857#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT 0x0
6858#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_OPT_LR 0x1
6859#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_DAC 0x2
6860#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_XLAUI 0x3
6861#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_LONG_CH_6G 0x4
6862#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE1_OFFSET 0x4
6863#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE2_OFFSET 0x8
6864#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE3_OFFSET 0xc
6865#define MDIO_WC_REG_UC_INFO_B1_CRC 0x81FE
6866#define MDIO_WC_REG_DSC_SMC 0x8213
6867#define MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0 0x821e
6868#define MDIO_WC_REG_TX_FIR_TAP 0x82e2
6869#define MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET 0x00
6870#define MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_MASK 0x000f
6871#define MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET 0x04
6872#define MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_MASK 0x03f0
6873#define MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET 0x0a
6874#define MDIO_WC_REG_TX_FIR_TAP_POST_TAP_MASK 0x7c00
6875#define MDIO_WC_REG_TX_FIR_TAP_ENABLE 0x8000
6876#define MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL 0x82e3
6877#define MDIO_WC_REG_CL72_USERB0_CL72_OS_DEF_CTRL 0x82e6
6878#define MDIO_WC_REG_CL72_USERB0_CL72_BR_DEF_CTRL 0x82e7
6879#define MDIO_WC_REG_CL72_USERB0_CL72_2P5_DEF_CTRL 0x82e8
6880#define MDIO_WC_REG_CL72_USERB0_CL72_MISC4_CONTROL 0x82ec
6881#define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1 0x8300
6882#define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2 0x8301
6883#define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3 0x8302
6884#define MDIO_WC_REG_SERDESDIGITAL_STATUS1000X1 0x8304
6885#define MDIO_WC_REG_SERDESDIGITAL_MISC1 0x8308
6886#define MDIO_WC_REG_SERDESDIGITAL_MISC2 0x8309
6887#define MDIO_WC_REG_DIGITAL3_UP1 0x8329
6888#define MDIO_WC_REG_DIGITAL4_MISC3 0x833c
6889#define MDIO_WC_REG_DIGITAL5_MISC6 0x8345
6890#define MDIO_WC_REG_DIGITAL5_MISC7 0x8349
6891#define MDIO_WC_REG_DIGITAL5_ACTUAL_SPEED 0x834e
Yaniv Rosnera34bc962011-07-05 01:06:41 +00006892#define MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL 0x8350
Yaniv Rosner3c9ada22011-06-14 01:34:12 +00006893#define MDIO_WC_REG_CL49_USERB0_CTRL 0x8368
6894#define MDIO_WC_REG_TX66_CONTROL 0x83b0
6895#define MDIO_WC_REG_RX66_CONTROL 0x83c0
6896#define MDIO_WC_REG_RX66_SCW0 0x83c2
6897#define MDIO_WC_REG_RX66_SCW1 0x83c3
6898#define MDIO_WC_REG_RX66_SCW2 0x83c4
6899#define MDIO_WC_REG_RX66_SCW3 0x83c5
6900#define MDIO_WC_REG_RX66_SCW0_MASK 0x83c6
6901#define MDIO_WC_REG_RX66_SCW1_MASK 0x83c7
6902#define MDIO_WC_REG_RX66_SCW2_MASK 0x83c8
6903#define MDIO_WC_REG_RX66_SCW3_MASK 0x83c9
6904#define MDIO_WC_REG_FX100_CTRL1 0x8400
6905#define MDIO_WC_REG_FX100_CTRL3 0x8402
6906
6907#define MDIO_WC_REG_MICROBLK_CMD 0xffc2
6908#define MDIO_WC_REG_MICROBLK_DL_STATUS 0xffc5
6909#define MDIO_WC_REG_MICROBLK_CMD3 0xffcc
6910
6911#define MDIO_WC_REG_AERBLK_AER 0xffde
6912#define MDIO_WC_REG_COMBO_IEEE0_MIICTRL 0xffe0
6913#define MDIO_WC_REG_COMBO_IEEE0_MIIISTAT 0xffe1
6914
6915#define MDIO_WC0_XGXS_BLK2_LANE_RESET 0x810A
6916#define MDIO_WC0_XGXS_BLK2_LANE_RESET_RX_BITSHIFT 0
6917#define MDIO_WC0_XGXS_BLK2_LANE_RESET_TX_BITSHIFT 4
6918
6919#define MDIO_WC0_XGXS_BLK6_XGXS_X2_CONTROL2 0x8141
6920
6921#define DIGITAL5_ACTUAL_SPEED_TX_MASK 0x003f
6922
Yaniv Rosner52c4d6c2011-07-05 01:06:34 +00006923/* 54618se */
6924#define MDIO_REG_GPHY_PHYID_LSB 0x3
6925#define MDIO_REG_GPHY_ID_54618SE 0x5cd5
6926#define MDIO_REG_GPHY_CL45_ADDR_REG 0xd
6927#define MDIO_REG_GPHY_CL45_DATA_REG 0xe
6928#define MDIO_REG_GPHY_EEE_ADV 0x3c
6929#define MDIO_REG_GPHY_EEE_1G (0x1 << 2)
6930#define MDIO_REG_GPHY_EEE_100 (0x1 << 1)
6931#define MDIO_REG_GPHY_EEE_RESOLVED 0x803e
Yaniv Rosner6583e332011-06-14 01:34:17 +00006932#define MDIO_REG_INTR_STATUS 0x1a
6933#define MDIO_REG_INTR_MASK 0x1b
6934#define MDIO_REG_INTR_MASK_LINK_STATUS (0x1 << 1)
6935#define MDIO_REG_GPHY_SHADOW 0x1c
6936#define MDIO_REG_GPHY_SHADOW_LED_SEL2 (0x0e << 10)
6937#define MDIO_REG_GPHY_SHADOW_WR_ENA (0x1 << 15)
6938#define MDIO_REG_GPHY_SHADOW_AUTO_DET_MED (0x1e << 10)
6939#define MDIO_REG_GPHY_SHADOW_INVERT_FIB_SD (0x1 << 8)
6940
Yaniv Rosnerc18487e2008-06-23 20:27:52 -07006941#define IGU_FUNC_BASE 0x0400
6942
6943#define IGU_ADDR_MSIX 0x0000
6944#define IGU_ADDR_INT_ACK 0x0200
6945#define IGU_ADDR_PROD_UPD 0x0201
6946#define IGU_ADDR_ATTN_BITS_UPD 0x0202
6947#define IGU_ADDR_ATTN_BITS_SET 0x0203
6948#define IGU_ADDR_ATTN_BITS_CLR 0x0204
6949#define IGU_ADDR_COALESCE_NOW 0x0205
6950#define IGU_ADDR_SIMD_MASK 0x0206
6951#define IGU_ADDR_SIMD_NOMASK 0x0207
6952#define IGU_ADDR_MSI_CTL 0x0210
6953#define IGU_ADDR_MSI_ADDR_LO 0x0211
6954#define IGU_ADDR_MSI_ADDR_HI 0x0212
6955#define IGU_ADDR_MSI_DATA 0x0213
6956
Dmitry Kravkovf2e08992010-10-06 03:28:26 +00006957#define IGU_USE_REGISTER_ustorm_type_0_sb_cleanup 0
6958#define IGU_USE_REGISTER_ustorm_type_1_sb_cleanup 1
6959#define IGU_USE_REGISTER_cstorm_type_0_sb_cleanup 2
6960#define IGU_USE_REGISTER_cstorm_type_1_sb_cleanup 3
6961
Eilon Greenstein5c862842008-08-13 15:51:48 -07006962#define COMMAND_REG_INT_ACK 0x0
6963#define COMMAND_REG_PROD_UPD 0x4
6964#define COMMAND_REG_ATTN_BITS_UPD 0x8
6965#define COMMAND_REG_ATTN_BITS_SET 0xc
6966#define COMMAND_REG_ATTN_BITS_CLR 0x10
6967#define COMMAND_REG_COALESCE_NOW 0x14
6968#define COMMAND_REG_SIMD_MASK 0x18
6969#define COMMAND_REG_SIMD_NOMASK 0x1c
6970
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02006971
Eilon Greenstein573f2032009-08-12 08:24:14 +00006972#define IGU_MEM_BASE 0x0000
6973
6974#define IGU_MEM_MSIX_BASE 0x0000
6975#define IGU_MEM_MSIX_UPPER 0x007f
6976#define IGU_MEM_MSIX_RESERVED_UPPER 0x01ff
6977
6978#define IGU_MEM_PBA_MSIX_BASE 0x0200
6979#define IGU_MEM_PBA_MSIX_UPPER 0x0200
6980
6981#define IGU_CMD_BACKWARD_COMP_PROD_UPD 0x0201
6982#define IGU_MEM_PBA_MSIX_RESERVED_UPPER 0x03ff
6983
6984#define IGU_CMD_INT_ACK_BASE 0x0400
6985#define IGU_CMD_INT_ACK_UPPER\
6986 (IGU_CMD_INT_ACK_BASE + MAX_SB_PER_PORT * NUM_OF_PORTS_PER_PATH - 1)
6987#define IGU_CMD_INT_ACK_RESERVED_UPPER 0x04ff
6988
6989#define IGU_CMD_E2_PROD_UPD_BASE 0x0500
6990#define IGU_CMD_E2_PROD_UPD_UPPER\
6991 (IGU_CMD_E2_PROD_UPD_BASE + MAX_SB_PER_PORT * NUM_OF_PORTS_PER_PATH - 1)
6992#define IGU_CMD_E2_PROD_UPD_RESERVED_UPPER 0x059f
6993
6994#define IGU_CMD_ATTN_BIT_UPD_UPPER 0x05a0
6995#define IGU_CMD_ATTN_BIT_SET_UPPER 0x05a1
6996#define IGU_CMD_ATTN_BIT_CLR_UPPER 0x05a2
6997
6998#define IGU_REG_SISR_MDPC_WMASK_UPPER 0x05a3
6999#define IGU_REG_SISR_MDPC_WMASK_LSB_UPPER 0x05a4
7000#define IGU_REG_SISR_MDPC_WMASK_MSB_UPPER 0x05a5
7001#define IGU_REG_SISR_MDPC_WOMASK_UPPER 0x05a6
7002
7003#define IGU_REG_RESERVED_UPPER 0x05ff
Dmitry Kravkovf2e08992010-10-06 03:28:26 +00007004/* Fields of IGU PF CONFIGRATION REGISTER */
7005#define IGU_PF_CONF_FUNC_EN (0x1<<0) /* function enable */
7006#define IGU_PF_CONF_MSI_MSIX_EN (0x1<<1) /* MSI/MSIX enable */
7007#define IGU_PF_CONF_INT_LINE_EN (0x1<<2) /* INT enable */
7008#define IGU_PF_CONF_ATTN_BIT_EN (0x1<<3) /* attention enable */
7009#define IGU_PF_CONF_SINGLE_ISR_EN (0x1<<4) /* single ISR mode enable */
7010#define IGU_PF_CONF_SIMD_MODE (0x1<<5) /* simd all ones mode */
7011
7012/* Fields of IGU VF CONFIGRATION REGISTER */
7013#define IGU_VF_CONF_FUNC_EN (0x1<<0) /* function enable */
7014#define IGU_VF_CONF_MSI_MSIX_EN (0x1<<1) /* MSI/MSIX enable */
7015#define IGU_VF_CONF_PARENT_MASK (0x3<<2) /* Parent PF */
7016#define IGU_VF_CONF_PARENT_SHIFT 2 /* Parent PF */
7017#define IGU_VF_CONF_SINGLE_ISR_EN (0x1<<4) /* single ISR mode enable */
7018
7019
7020#define IGU_BC_DSB_NUM_SEGS 5
7021#define IGU_BC_NDSB_NUM_SEGS 2
7022#define IGU_NORM_DSB_NUM_SEGS 2
7023#define IGU_NORM_NDSB_NUM_SEGS 1
7024#define IGU_BC_BASE_DSB_PROD 128
7025#define IGU_NORM_BASE_DSB_PROD 136
7026
Dmitry Kravkovf2e08992010-10-06 03:28:26 +00007027 /* FID (if VF - [6] = 0; [5:0] = VF number; if PF - [6] = 1; \
7028 [5:2] = 0; [1:0] = PF number) */
7029#define IGU_FID_ENCODE_IS_PF (0x1<<6)
7030#define IGU_FID_ENCODE_IS_PF_SHIFT 6
7031#define IGU_FID_VF_NUM_MASK (0x3f)
7032#define IGU_FID_PF_NUM_MASK (0x7)
7033
7034#define IGU_REG_MAPPING_MEMORY_VALID (1<<0)
7035#define IGU_REG_MAPPING_MEMORY_VECTOR_MASK (0x3F<<1)
7036#define IGU_REG_MAPPING_MEMORY_VECTOR_SHIFT 1
7037#define IGU_REG_MAPPING_MEMORY_FID_MASK (0x7F<<7)
7038#define IGU_REG_MAPPING_MEMORY_FID_SHIFT 7
Eilon Greenstein573f2032009-08-12 08:24:14 +00007039
7040
7041#define CDU_REGION_NUMBER_XCM_AG 2
7042#define CDU_REGION_NUMBER_UCM_AG 4
7043
7044
7045/**
7046 * String-to-compress [31:8] = CID (all 24 bits)
7047 * String-to-compress [7:4] = Region
7048 * String-to-compress [3:0] = Type
7049 */
7050#define CDU_VALID_DATA(_cid, _region, _type)\
7051 (((_cid) << 8) | (((_region)&0xf)<<4) | (((_type)&0xf)))
7052#define CDU_CRC8(_cid, _region, _type)\
7053 (calc_crc8(CDU_VALID_DATA(_cid, _region, _type), 0xff))
7054#define CDU_RSRVD_VALUE_TYPE_A(_cid, _region, _type)\
7055 (0x80 | ((CDU_CRC8(_cid, _region, _type)) & 0x7f))
7056#define CDU_RSRVD_VALUE_TYPE_B(_crc, _type)\
7057 (0x80 | ((_type)&0xf << 3) | ((CDU_CRC8(_cid, _region, _type)) & 0x7))
7058#define CDU_RSRVD_INVALIDATE_CONTEXT_VALUE(_val) ((_val) & ~0x80)
7059
7060/******************************************************************************
7061 * Description:
7062 * Calculates crc 8 on a word value: polynomial 0-1-2-8
7063 * Code was translated from Verilog.
7064 * Return:
7065 *****************************************************************************/
7066static inline u8 calc_crc8(u32 data, u8 crc)
7067{
7068 u8 D[32];
7069 u8 NewCRC[8];
7070 u8 C[8];
7071 u8 crc_res;
7072 u8 i;
7073
7074 /* split the data into 31 bits */
7075 for (i = 0; i < 32; i++) {
7076 D[i] = (u8)(data & 1);
7077 data = data >> 1;
7078 }
7079
7080 /* split the crc into 8 bits */
7081 for (i = 0; i < 8; i++) {
7082 C[i] = crc & 1;
7083 crc = crc >> 1;
7084 }
7085
7086 NewCRC[0] = D[31] ^ D[30] ^ D[28] ^ D[23] ^ D[21] ^ D[19] ^ D[18] ^
7087 D[16] ^ D[14] ^ D[12] ^ D[8] ^ D[7] ^ D[6] ^ D[0] ^ C[4] ^
7088 C[6] ^ C[7];
7089 NewCRC[1] = D[30] ^ D[29] ^ D[28] ^ D[24] ^ D[23] ^ D[22] ^ D[21] ^
7090 D[20] ^ D[18] ^ D[17] ^ D[16] ^ D[15] ^ D[14] ^ D[13] ^
7091 D[12] ^ D[9] ^ D[6] ^ D[1] ^ D[0] ^ C[0] ^ C[4] ^ C[5] ^
7092 C[6];
7093 NewCRC[2] = D[29] ^ D[28] ^ D[25] ^ D[24] ^ D[22] ^ D[17] ^ D[15] ^
7094 D[13] ^ D[12] ^ D[10] ^ D[8] ^ D[6] ^ D[2] ^ D[1] ^ D[0] ^
7095 C[0] ^ C[1] ^ C[4] ^ C[5];
7096 NewCRC[3] = D[30] ^ D[29] ^ D[26] ^ D[25] ^ D[23] ^ D[18] ^ D[16] ^
7097 D[14] ^ D[13] ^ D[11] ^ D[9] ^ D[7] ^ D[3] ^ D[2] ^ D[1] ^
7098 C[1] ^ C[2] ^ C[5] ^ C[6];
7099 NewCRC[4] = D[31] ^ D[30] ^ D[27] ^ D[26] ^ D[24] ^ D[19] ^ D[17] ^
7100 D[15] ^ D[14] ^ D[12] ^ D[10] ^ D[8] ^ D[4] ^ D[3] ^ D[2] ^
7101 C[0] ^ C[2] ^ C[3] ^ C[6] ^ C[7];
7102 NewCRC[5] = D[31] ^ D[28] ^ D[27] ^ D[25] ^ D[20] ^ D[18] ^ D[16] ^
7103 D[15] ^ D[13] ^ D[11] ^ D[9] ^ D[5] ^ D[4] ^ D[3] ^ C[1] ^
7104 C[3] ^ C[4] ^ C[7];
7105 NewCRC[6] = D[29] ^ D[28] ^ D[26] ^ D[21] ^ D[19] ^ D[17] ^ D[16] ^
7106 D[14] ^ D[12] ^ D[10] ^ D[6] ^ D[5] ^ D[4] ^ C[2] ^ C[4] ^
7107 C[5];
7108 NewCRC[7] = D[30] ^ D[29] ^ D[27] ^ D[22] ^ D[20] ^ D[18] ^ D[17] ^
7109 D[15] ^ D[13] ^ D[11] ^ D[7] ^ D[6] ^ D[5] ^ C[3] ^ C[5] ^
7110 C[6];
7111
7112 crc_res = 0;
7113 for (i = 0; i < 8; i++)
7114 crc_res |= (NewCRC[i] << i);
7115
7116 return crc_res;
7117}
7118
7119
Vladislav Zolotarov4a33bc02011-01-09 02:20:04 +00007120#endif /* BNX2X_REG_H */