blob: 28bce3f4f81d6aa56840657169c0842461f9f515 [file] [log] [blame]
Mark Rutland8a4da6e2012-11-12 14:33:44 +00001/*
2 * linux/drivers/clocksource/arm_arch_timer.c
3 *
4 * Copyright (C) 2011 ARM Ltd.
5 * All Rights Reserved
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11#include <linux/init.h>
12#include <linux/kernel.h>
13#include <linux/device.h>
14#include <linux/smp.h>
15#include <linux/cpu.h>
Sudeep KarkadaNagesha346e7482013-08-23 15:53:15 +010016#include <linux/cpu_pm.h>
Mark Rutland8a4da6e2012-11-12 14:33:44 +000017#include <linux/clockchips.h>
Richard Cochran7c8f1e72015-01-06 14:26:13 +010018#include <linux/clocksource.h>
Mark Rutland8a4da6e2012-11-12 14:33:44 +000019#include <linux/interrupt.h>
20#include <linux/of_irq.h>
Stephen Boyd22006992013-07-18 16:59:32 -070021#include <linux/of_address.h>
Mark Rutland8a4da6e2012-11-12 14:33:44 +000022#include <linux/io.h>
Stephen Boyd22006992013-07-18 16:59:32 -070023#include <linux/slab.h>
Stephen Boyd65cd4f62013-07-18 16:21:18 -070024#include <linux/sched_clock.h>
Hanjun Guob09ca1e2015-03-24 14:02:50 +000025#include <linux/acpi.h>
Mark Rutland8a4da6e2012-11-12 14:33:44 +000026
27#include <asm/arch_timer.h>
Marc Zyngier82668912013-01-10 11:13:07 +000028#include <asm/virt.h>
Mark Rutland8a4da6e2012-11-12 14:33:44 +000029
30#include <clocksource/arm_arch_timer.h>
31
Stephen Boyd22006992013-07-18 16:59:32 -070032#define CNTTIDR 0x08
33#define CNTTIDR_VIRT(n) (BIT(1) << ((n) * 4))
34
Robin Murphye392d602016-02-01 12:00:48 +000035#define CNTACR(n) (0x40 + ((n) * 4))
36#define CNTACR_RPCT BIT(0)
37#define CNTACR_RVCT BIT(1)
38#define CNTACR_RFRQ BIT(2)
39#define CNTACR_RVOFF BIT(3)
40#define CNTACR_RWVT BIT(4)
41#define CNTACR_RWPT BIT(5)
42
Stephen Boyd22006992013-07-18 16:59:32 -070043#define CNTVCT_LO 0x08
44#define CNTVCT_HI 0x0c
45#define CNTFRQ 0x10
46#define CNTP_TVAL 0x28
47#define CNTP_CTL 0x2c
48#define CNTV_TVAL 0x38
49#define CNTV_CTL 0x3c
50
51#define ARCH_CP15_TIMER BIT(0)
52#define ARCH_MEM_TIMER BIT(1)
53static unsigned arch_timers_present __initdata;
54
55static void __iomem *arch_counter_base;
56
57struct arch_timer {
58 void __iomem *base;
59 struct clock_event_device evt;
60};
61
62#define to_arch_timer(e) container_of(e, struct arch_timer, evt)
63
Mark Rutland8a4da6e2012-11-12 14:33:44 +000064static u32 arch_timer_rate;
65
66enum ppi_nr {
67 PHYS_SECURE_PPI,
68 PHYS_NONSECURE_PPI,
69 VIRT_PPI,
70 HYP_PPI,
71 MAX_TIMER_PPI
72};
73
74static int arch_timer_ppi[MAX_TIMER_PPI];
75
76static struct clock_event_device __percpu *arch_timer_evt;
77
Marc Zyngierf81f03f2014-02-20 15:21:23 +000078static enum ppi_nr arch_timer_uses_ppi = VIRT_PPI;
Lorenzo Pieralisi82a561942014-04-08 10:04:32 +010079static bool arch_timer_c3stop;
Stephen Boyd22006992013-07-18 16:59:32 -070080static bool arch_timer_mem_use_virtual;
Mark Rutland8a4da6e2012-11-12 14:33:44 +000081
Will Deacon46fd5c62016-06-27 17:30:13 +010082static bool evtstrm_enable = IS_ENABLED(CONFIG_ARM_ARCH_TIMER_EVTSTREAM);
83
84static int __init early_evtstrm_cfg(char *buf)
85{
86 return strtobool(buf, &evtstrm_enable);
87}
88early_param("clocksource.arm_arch_timer.evtstrm", early_evtstrm_cfg);
89
Mark Rutland8a4da6e2012-11-12 14:33:44 +000090/*
91 * Architected system timer support.
92 */
93
Stephen Boyd60faddf2013-07-18 16:59:31 -070094static __always_inline
95void arch_timer_reg_write(int access, enum arch_timer_reg reg, u32 val,
Thomas Gleixnercfb6d652013-08-21 14:59:23 +020096 struct clock_event_device *clk)
Stephen Boyd60faddf2013-07-18 16:59:31 -070097{
Stephen Boyd22006992013-07-18 16:59:32 -070098 if (access == ARCH_TIMER_MEM_PHYS_ACCESS) {
99 struct arch_timer *timer = to_arch_timer(clk);
100 switch (reg) {
101 case ARCH_TIMER_REG_CTRL:
102 writel_relaxed(val, timer->base + CNTP_CTL);
103 break;
104 case ARCH_TIMER_REG_TVAL:
105 writel_relaxed(val, timer->base + CNTP_TVAL);
106 break;
107 }
108 } else if (access == ARCH_TIMER_MEM_VIRT_ACCESS) {
109 struct arch_timer *timer = to_arch_timer(clk);
110 switch (reg) {
111 case ARCH_TIMER_REG_CTRL:
112 writel_relaxed(val, timer->base + CNTV_CTL);
113 break;
114 case ARCH_TIMER_REG_TVAL:
115 writel_relaxed(val, timer->base + CNTV_TVAL);
116 break;
117 }
118 } else {
119 arch_timer_reg_write_cp15(access, reg, val);
120 }
Stephen Boyd60faddf2013-07-18 16:59:31 -0700121}
122
123static __always_inline
124u32 arch_timer_reg_read(int access, enum arch_timer_reg reg,
Thomas Gleixnercfb6d652013-08-21 14:59:23 +0200125 struct clock_event_device *clk)
Stephen Boyd60faddf2013-07-18 16:59:31 -0700126{
Stephen Boyd22006992013-07-18 16:59:32 -0700127 u32 val;
128
129 if (access == ARCH_TIMER_MEM_PHYS_ACCESS) {
130 struct arch_timer *timer = to_arch_timer(clk);
131 switch (reg) {
132 case ARCH_TIMER_REG_CTRL:
133 val = readl_relaxed(timer->base + CNTP_CTL);
134 break;
135 case ARCH_TIMER_REG_TVAL:
136 val = readl_relaxed(timer->base + CNTP_TVAL);
137 break;
138 }
139 } else if (access == ARCH_TIMER_MEM_VIRT_ACCESS) {
140 struct arch_timer *timer = to_arch_timer(clk);
141 switch (reg) {
142 case ARCH_TIMER_REG_CTRL:
143 val = readl_relaxed(timer->base + CNTV_CTL);
144 break;
145 case ARCH_TIMER_REG_TVAL:
146 val = readl_relaxed(timer->base + CNTV_TVAL);
147 break;
148 }
149 } else {
150 val = arch_timer_reg_read_cp15(access, reg);
151 }
152
153 return val;
Stephen Boyd60faddf2013-07-18 16:59:31 -0700154}
155
Stephen Boyde09f3cc2013-07-18 16:59:28 -0700156static __always_inline irqreturn_t timer_handler(const int access,
Mark Rutland8a4da6e2012-11-12 14:33:44 +0000157 struct clock_event_device *evt)
158{
159 unsigned long ctrl;
Thomas Gleixnercfb6d652013-08-21 14:59:23 +0200160
Stephen Boyd60faddf2013-07-18 16:59:31 -0700161 ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, evt);
Mark Rutland8a4da6e2012-11-12 14:33:44 +0000162 if (ctrl & ARCH_TIMER_CTRL_IT_STAT) {
163 ctrl |= ARCH_TIMER_CTRL_IT_MASK;
Stephen Boyd60faddf2013-07-18 16:59:31 -0700164 arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, evt);
Mark Rutland8a4da6e2012-11-12 14:33:44 +0000165 evt->event_handler(evt);
166 return IRQ_HANDLED;
167 }
168
169 return IRQ_NONE;
170}
171
172static irqreturn_t arch_timer_handler_virt(int irq, void *dev_id)
173{
174 struct clock_event_device *evt = dev_id;
175
176 return timer_handler(ARCH_TIMER_VIRT_ACCESS, evt);
177}
178
179static irqreturn_t arch_timer_handler_phys(int irq, void *dev_id)
180{
181 struct clock_event_device *evt = dev_id;
182
183 return timer_handler(ARCH_TIMER_PHYS_ACCESS, evt);
184}
185
Stephen Boyd22006992013-07-18 16:59:32 -0700186static irqreturn_t arch_timer_handler_phys_mem(int irq, void *dev_id)
187{
188 struct clock_event_device *evt = dev_id;
189
190 return timer_handler(ARCH_TIMER_MEM_PHYS_ACCESS, evt);
191}
192
193static irqreturn_t arch_timer_handler_virt_mem(int irq, void *dev_id)
194{
195 struct clock_event_device *evt = dev_id;
196
197 return timer_handler(ARCH_TIMER_MEM_VIRT_ACCESS, evt);
198}
199
Viresh Kumar46c5bfd2015-06-12 13:30:12 +0530200static __always_inline int timer_shutdown(const int access,
201 struct clock_event_device *clk)
Mark Rutland8a4da6e2012-11-12 14:33:44 +0000202{
203 unsigned long ctrl;
Viresh Kumar46c5bfd2015-06-12 13:30:12 +0530204
205 ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, clk);
206 ctrl &= ~ARCH_TIMER_CTRL_ENABLE;
207 arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk);
208
209 return 0;
Mark Rutland8a4da6e2012-11-12 14:33:44 +0000210}
211
Viresh Kumar46c5bfd2015-06-12 13:30:12 +0530212static int arch_timer_shutdown_virt(struct clock_event_device *clk)
Mark Rutland8a4da6e2012-11-12 14:33:44 +0000213{
Viresh Kumar46c5bfd2015-06-12 13:30:12 +0530214 return timer_shutdown(ARCH_TIMER_VIRT_ACCESS, clk);
Mark Rutland8a4da6e2012-11-12 14:33:44 +0000215}
216
Viresh Kumar46c5bfd2015-06-12 13:30:12 +0530217static int arch_timer_shutdown_phys(struct clock_event_device *clk)
Mark Rutland8a4da6e2012-11-12 14:33:44 +0000218{
Viresh Kumar46c5bfd2015-06-12 13:30:12 +0530219 return timer_shutdown(ARCH_TIMER_PHYS_ACCESS, clk);
Mark Rutland8a4da6e2012-11-12 14:33:44 +0000220}
221
Viresh Kumar46c5bfd2015-06-12 13:30:12 +0530222static int arch_timer_shutdown_virt_mem(struct clock_event_device *clk)
Stephen Boyd22006992013-07-18 16:59:32 -0700223{
Viresh Kumar46c5bfd2015-06-12 13:30:12 +0530224 return timer_shutdown(ARCH_TIMER_MEM_VIRT_ACCESS, clk);
Stephen Boyd22006992013-07-18 16:59:32 -0700225}
226
Viresh Kumar46c5bfd2015-06-12 13:30:12 +0530227static int arch_timer_shutdown_phys_mem(struct clock_event_device *clk)
Stephen Boyd22006992013-07-18 16:59:32 -0700228{
Viresh Kumar46c5bfd2015-06-12 13:30:12 +0530229 return timer_shutdown(ARCH_TIMER_MEM_PHYS_ACCESS, clk);
Stephen Boyd22006992013-07-18 16:59:32 -0700230}
231
Stephen Boyd60faddf2013-07-18 16:59:31 -0700232static __always_inline void set_next_event(const int access, unsigned long evt,
Thomas Gleixnercfb6d652013-08-21 14:59:23 +0200233 struct clock_event_device *clk)
Mark Rutland8a4da6e2012-11-12 14:33:44 +0000234{
235 unsigned long ctrl;
Stephen Boyd60faddf2013-07-18 16:59:31 -0700236 ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, clk);
Mark Rutland8a4da6e2012-11-12 14:33:44 +0000237 ctrl |= ARCH_TIMER_CTRL_ENABLE;
238 ctrl &= ~ARCH_TIMER_CTRL_IT_MASK;
Stephen Boyd60faddf2013-07-18 16:59:31 -0700239 arch_timer_reg_write(access, ARCH_TIMER_REG_TVAL, evt, clk);
240 arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk);
Mark Rutland8a4da6e2012-11-12 14:33:44 +0000241}
242
243static int arch_timer_set_next_event_virt(unsigned long evt,
Stephen Boyd60faddf2013-07-18 16:59:31 -0700244 struct clock_event_device *clk)
Mark Rutland8a4da6e2012-11-12 14:33:44 +0000245{
Stephen Boyd60faddf2013-07-18 16:59:31 -0700246 set_next_event(ARCH_TIMER_VIRT_ACCESS, evt, clk);
Mark Rutland8a4da6e2012-11-12 14:33:44 +0000247 return 0;
248}
249
250static int arch_timer_set_next_event_phys(unsigned long evt,
Stephen Boyd60faddf2013-07-18 16:59:31 -0700251 struct clock_event_device *clk)
Mark Rutland8a4da6e2012-11-12 14:33:44 +0000252{
Stephen Boyd60faddf2013-07-18 16:59:31 -0700253 set_next_event(ARCH_TIMER_PHYS_ACCESS, evt, clk);
Mark Rutland8a4da6e2012-11-12 14:33:44 +0000254 return 0;
255}
256
Stephen Boyd22006992013-07-18 16:59:32 -0700257static int arch_timer_set_next_event_virt_mem(unsigned long evt,
258 struct clock_event_device *clk)
Mark Rutland8a4da6e2012-11-12 14:33:44 +0000259{
Stephen Boyd22006992013-07-18 16:59:32 -0700260 set_next_event(ARCH_TIMER_MEM_VIRT_ACCESS, evt, clk);
261 return 0;
262}
Mark Rutland8a4da6e2012-11-12 14:33:44 +0000263
Stephen Boyd22006992013-07-18 16:59:32 -0700264static int arch_timer_set_next_event_phys_mem(unsigned long evt,
265 struct clock_event_device *clk)
266{
267 set_next_event(ARCH_TIMER_MEM_PHYS_ACCESS, evt, clk);
268 return 0;
269}
270
Thomas Gleixnercfb6d652013-08-21 14:59:23 +0200271static void __arch_timer_setup(unsigned type,
272 struct clock_event_device *clk)
Stephen Boyd22006992013-07-18 16:59:32 -0700273{
274 clk->features = CLOCK_EVT_FEAT_ONESHOT;
275
276 if (type == ARCH_CP15_TIMER) {
Lorenzo Pieralisi82a561942014-04-08 10:04:32 +0100277 if (arch_timer_c3stop)
278 clk->features |= CLOCK_EVT_FEAT_C3STOP;
Stephen Boyd22006992013-07-18 16:59:32 -0700279 clk->name = "arch_sys_timer";
280 clk->rating = 450;
281 clk->cpumask = cpumask_of(smp_processor_id());
Marc Zyngierf81f03f2014-02-20 15:21:23 +0000282 clk->irq = arch_timer_ppi[arch_timer_uses_ppi];
283 switch (arch_timer_uses_ppi) {
284 case VIRT_PPI:
Viresh Kumar46c5bfd2015-06-12 13:30:12 +0530285 clk->set_state_shutdown = arch_timer_shutdown_virt;
Viresh Kumarcf8c5002015-12-23 16:59:12 +0530286 clk->set_state_oneshot_stopped = arch_timer_shutdown_virt;
Stephen Boyd22006992013-07-18 16:59:32 -0700287 clk->set_next_event = arch_timer_set_next_event_virt;
Marc Zyngierf81f03f2014-02-20 15:21:23 +0000288 break;
289 case PHYS_SECURE_PPI:
290 case PHYS_NONSECURE_PPI:
291 case HYP_PPI:
Viresh Kumar46c5bfd2015-06-12 13:30:12 +0530292 clk->set_state_shutdown = arch_timer_shutdown_phys;
Viresh Kumarcf8c5002015-12-23 16:59:12 +0530293 clk->set_state_oneshot_stopped = arch_timer_shutdown_phys;
Stephen Boyd22006992013-07-18 16:59:32 -0700294 clk->set_next_event = arch_timer_set_next_event_phys;
Marc Zyngierf81f03f2014-02-20 15:21:23 +0000295 break;
296 default:
297 BUG();
Stephen Boyd22006992013-07-18 16:59:32 -0700298 }
299 } else {
Stephen Boyd7b52ad22014-01-06 14:56:17 -0800300 clk->features |= CLOCK_EVT_FEAT_DYNIRQ;
Stephen Boyd22006992013-07-18 16:59:32 -0700301 clk->name = "arch_mem_timer";
302 clk->rating = 400;
303 clk->cpumask = cpu_all_mask;
304 if (arch_timer_mem_use_virtual) {
Viresh Kumar46c5bfd2015-06-12 13:30:12 +0530305 clk->set_state_shutdown = arch_timer_shutdown_virt_mem;
Viresh Kumarcf8c5002015-12-23 16:59:12 +0530306 clk->set_state_oneshot_stopped = arch_timer_shutdown_virt_mem;
Stephen Boyd22006992013-07-18 16:59:32 -0700307 clk->set_next_event =
308 arch_timer_set_next_event_virt_mem;
309 } else {
Viresh Kumar46c5bfd2015-06-12 13:30:12 +0530310 clk->set_state_shutdown = arch_timer_shutdown_phys_mem;
Viresh Kumarcf8c5002015-12-23 16:59:12 +0530311 clk->set_state_oneshot_stopped = arch_timer_shutdown_phys_mem;
Stephen Boyd22006992013-07-18 16:59:32 -0700312 clk->set_next_event =
313 arch_timer_set_next_event_phys_mem;
314 }
315 }
Mark Rutland8a4da6e2012-11-12 14:33:44 +0000316
Viresh Kumar46c5bfd2015-06-12 13:30:12 +0530317 clk->set_state_shutdown(clk);
Mark Rutland8a4da6e2012-11-12 14:33:44 +0000318
Stephen Boyd22006992013-07-18 16:59:32 -0700319 clockevents_config_and_register(clk, arch_timer_rate, 0xf, 0x7fffffff);
320}
321
Nathan Lynche1ce5c72014-09-29 01:50:06 +0200322static void arch_timer_evtstrm_enable(int divider)
323{
324 u32 cntkctl = arch_timer_get_cntkctl();
325
326 cntkctl &= ~ARCH_TIMER_EVT_TRIGGER_MASK;
327 /* Set the divider and enable virtual event stream */
328 cntkctl |= (divider << ARCH_TIMER_EVT_TRIGGER_SHIFT)
329 | ARCH_TIMER_VIRT_EVT_EN;
330 arch_timer_set_cntkctl(cntkctl);
331 elf_hwcap |= HWCAP_EVTSTRM;
332#ifdef CONFIG_COMPAT
333 compat_elf_hwcap |= COMPAT_HWCAP_EVTSTRM;
334#endif
335}
336
Will Deacon037f6372013-08-23 15:32:29 +0100337static void arch_timer_configure_evtstream(void)
338{
339 int evt_stream_div, pos;
340
341 /* Find the closest power of two to the divisor */
342 evt_stream_div = arch_timer_rate / ARCH_TIMER_EVT_STREAM_FREQ;
343 pos = fls(evt_stream_div);
344 if (pos > 1 && !(evt_stream_div & (1 << (pos - 2))))
345 pos--;
346 /* enable event stream */
347 arch_timer_evtstrm_enable(min(pos, 15));
348}
349
Nathan Lynch8b8dde02014-09-29 01:50:06 +0200350static void arch_counter_set_user_access(void)
351{
352 u32 cntkctl = arch_timer_get_cntkctl();
353
354 /* Disable user access to the timers and the physical counter */
355 /* Also disable virtual event stream */
356 cntkctl &= ~(ARCH_TIMER_USR_PT_ACCESS_EN
357 | ARCH_TIMER_USR_VT_ACCESS_EN
358 | ARCH_TIMER_VIRT_EVT_EN
359 | ARCH_TIMER_USR_PCT_ACCESS_EN);
360
361 /* Enable user access to the virtual counter */
362 cntkctl |= ARCH_TIMER_USR_VCT_ACCESS_EN;
363
364 arch_timer_set_cntkctl(cntkctl);
365}
366
Marc Zyngierf81f03f2014-02-20 15:21:23 +0000367static bool arch_timer_has_nonsecure_ppi(void)
368{
369 return (arch_timer_uses_ppi == PHYS_SECURE_PPI &&
370 arch_timer_ppi[PHYS_NONSECURE_PPI]);
371}
372
Richard Cochran7e86e8b2016-07-13 17:16:39 +0000373static int arch_timer_starting_cpu(unsigned int cpu)
Mark Rutland8a4da6e2012-11-12 14:33:44 +0000374{
Richard Cochran7e86e8b2016-07-13 17:16:39 +0000375 struct clock_event_device *clk = this_cpu_ptr(arch_timer_evt);
376
Stephen Boyd22006992013-07-18 16:59:32 -0700377 __arch_timer_setup(ARCH_CP15_TIMER, clk);
Mark Rutland8a4da6e2012-11-12 14:33:44 +0000378
Marc Zyngierf81f03f2014-02-20 15:21:23 +0000379 enable_percpu_irq(arch_timer_ppi[arch_timer_uses_ppi], 0);
380
381 if (arch_timer_has_nonsecure_ppi())
382 enable_percpu_irq(arch_timer_ppi[PHYS_NONSECURE_PPI], 0);
Mark Rutland8a4da6e2012-11-12 14:33:44 +0000383
384 arch_counter_set_user_access();
Will Deacon46fd5c62016-06-27 17:30:13 +0100385 if (evtstrm_enable)
Will Deacon037f6372013-08-23 15:32:29 +0100386 arch_timer_configure_evtstream();
Mark Rutland8a4da6e2012-11-12 14:33:44 +0000387
388 return 0;
389}
390
Stephen Boyd22006992013-07-18 16:59:32 -0700391static void
392arch_timer_detect_rate(void __iomem *cntbase, struct device_node *np)
Mark Rutland8a4da6e2012-11-12 14:33:44 +0000393{
Stephen Boyd22006992013-07-18 16:59:32 -0700394 /* Who has more than one independent system counter? */
395 if (arch_timer_rate)
396 return;
Mark Rutland8a4da6e2012-11-12 14:33:44 +0000397
Hanjun Guob09ca1e2015-03-24 14:02:50 +0000398 /*
399 * Try to determine the frequency from the device tree or CNTFRQ,
400 * if ACPI is enabled, get the frequency from CNTFRQ ONLY.
401 */
402 if (!acpi_disabled ||
403 of_property_read_u32(np, "clock-frequency", &arch_timer_rate)) {
Stephen Boyd22006992013-07-18 16:59:32 -0700404 if (cntbase)
405 arch_timer_rate = readl_relaxed(cntbase + CNTFRQ);
406 else
407 arch_timer_rate = arch_timer_get_cntfrq();
Mark Rutland8a4da6e2012-11-12 14:33:44 +0000408 }
409
Stephen Boyd22006992013-07-18 16:59:32 -0700410 /* Check the timer frequency. */
411 if (arch_timer_rate == 0)
412 pr_warn("Architected timer frequency not available\n");
413}
414
415static void arch_timer_banner(unsigned type)
416{
417 pr_info("Architected %s%s%s timer(s) running at %lu.%02luMHz (%s%s%s).\n",
418 type & ARCH_CP15_TIMER ? "cp15" : "",
419 type == (ARCH_CP15_TIMER | ARCH_MEM_TIMER) ? " and " : "",
420 type & ARCH_MEM_TIMER ? "mmio" : "",
Mark Rutland8a4da6e2012-11-12 14:33:44 +0000421 (unsigned long)arch_timer_rate / 1000000,
422 (unsigned long)(arch_timer_rate / 10000) % 100,
Stephen Boyd22006992013-07-18 16:59:32 -0700423 type & ARCH_CP15_TIMER ?
Marc Zyngierf81f03f2014-02-20 15:21:23 +0000424 (arch_timer_uses_ppi == VIRT_PPI) ? "virt" : "phys" :
Stephen Boyd22006992013-07-18 16:59:32 -0700425 "",
426 type == (ARCH_CP15_TIMER | ARCH_MEM_TIMER) ? "/" : "",
427 type & ARCH_MEM_TIMER ?
428 arch_timer_mem_use_virtual ? "virt" : "phys" :
429 "");
Mark Rutland8a4da6e2012-11-12 14:33:44 +0000430}
431
432u32 arch_timer_get_rate(void)
433{
434 return arch_timer_rate;
435}
436
Stephen Boyd22006992013-07-18 16:59:32 -0700437static u64 arch_counter_get_cntvct_mem(void)
Mark Rutland8a4da6e2012-11-12 14:33:44 +0000438{
Stephen Boyd22006992013-07-18 16:59:32 -0700439 u32 vct_lo, vct_hi, tmp_hi;
440
441 do {
442 vct_hi = readl_relaxed(arch_counter_base + CNTVCT_HI);
443 vct_lo = readl_relaxed(arch_counter_base + CNTVCT_LO);
444 tmp_hi = readl_relaxed(arch_counter_base + CNTVCT_HI);
445 } while (vct_hi != tmp_hi);
446
447 return ((u64) vct_hi << 32) | vct_lo;
Mark Rutland8a4da6e2012-11-12 14:33:44 +0000448}
449
Stephen Boyd22006992013-07-18 16:59:32 -0700450/*
451 * Default to cp15 based access because arm64 uses this function for
452 * sched_clock() before DT is probed and the cp15 method is guaranteed
453 * to exist on arm64. arm doesn't use this before DT is probed so even
454 * if we don't have the cp15 accessors we won't have a problem.
455 */
456u64 (*arch_timer_read_counter)(void) = arch_counter_get_cntvct;
457
Mark Rutland8a4da6e2012-11-12 14:33:44 +0000458static cycle_t arch_counter_read(struct clocksource *cs)
459{
Stephen Boyd22006992013-07-18 16:59:32 -0700460 return arch_timer_read_counter();
Mark Rutland8a4da6e2012-11-12 14:33:44 +0000461}
462
463static cycle_t arch_counter_read_cc(const struct cyclecounter *cc)
464{
Stephen Boyd22006992013-07-18 16:59:32 -0700465 return arch_timer_read_counter();
Mark Rutland8a4da6e2012-11-12 14:33:44 +0000466}
467
468static struct clocksource clocksource_counter = {
469 .name = "arch_sys_counter",
470 .rating = 400,
471 .read = arch_counter_read,
472 .mask = CLOCKSOURCE_MASK(56),
Stephen Boyd4fbcdc82013-09-27 13:13:12 -0700473 .flags = CLOCK_SOURCE_IS_CONTINUOUS | CLOCK_SOURCE_SUSPEND_NONSTOP,
Mark Rutland8a4da6e2012-11-12 14:33:44 +0000474};
475
476static struct cyclecounter cyclecounter = {
477 .read = arch_counter_read_cc,
478 .mask = CLOCKSOURCE_MASK(56),
479};
480
Julien Grallb4d6ce92016-04-11 16:32:51 +0100481static struct arch_timer_kvm_info arch_timer_kvm_info;
482
483struct arch_timer_kvm_info *arch_timer_get_kvm_info(void)
484{
485 return &arch_timer_kvm_info;
486}
Mark Rutland8a4da6e2012-11-12 14:33:44 +0000487
Stephen Boyd22006992013-07-18 16:59:32 -0700488static void __init arch_counter_register(unsigned type)
489{
490 u64 start_count;
491
492 /* Register the CP15 based counter if we have one */
Nathan Lynch423bd692014-09-29 01:50:06 +0200493 if (type & ARCH_CP15_TIMER) {
Marc Zyngierf81f03f2014-02-20 15:21:23 +0000494 if (IS_ENABLED(CONFIG_ARM64) || arch_timer_uses_ppi == VIRT_PPI)
Sonny Rao0b46b8a2014-11-23 23:02:44 -0800495 arch_timer_read_counter = arch_counter_get_cntvct;
496 else
497 arch_timer_read_counter = arch_counter_get_cntpct;
Nathan Lynch423bd692014-09-29 01:50:06 +0200498 } else {
Stephen Boyd22006992013-07-18 16:59:32 -0700499 arch_timer_read_counter = arch_counter_get_cntvct_mem;
500
Nathan Lynch423bd692014-09-29 01:50:06 +0200501 /* If the clocksource name is "arch_sys_counter" the
502 * VDSO will attempt to read the CP15-based counter.
503 * Ensure this does not happen when CP15-based
504 * counter is not available.
505 */
506 clocksource_counter.name = "arch_mem_counter";
507 }
508
Stephen Boyd22006992013-07-18 16:59:32 -0700509 start_count = arch_timer_read_counter();
510 clocksource_register_hz(&clocksource_counter, arch_timer_rate);
511 cyclecounter.mult = clocksource_counter.mult;
512 cyclecounter.shift = clocksource_counter.shift;
Julien Grallb4d6ce92016-04-11 16:32:51 +0100513 timecounter_init(&arch_timer_kvm_info.timecounter,
514 &cyclecounter, start_count);
Thierry Reding4a7d3e82013-10-15 15:31:51 +0200515
516 /* 56 bits minimum, so we assume worst case rollover */
517 sched_clock_register(arch_timer_read_counter, 56, arch_timer_rate);
Stephen Boyd22006992013-07-18 16:59:32 -0700518}
519
Paul Gortmaker8c37bb32013-06-19 11:32:08 -0400520static void arch_timer_stop(struct clock_event_device *clk)
Mark Rutland8a4da6e2012-11-12 14:33:44 +0000521{
522 pr_debug("arch_timer_teardown disable IRQ%d cpu #%d\n",
523 clk->irq, smp_processor_id());
524
Marc Zyngierf81f03f2014-02-20 15:21:23 +0000525 disable_percpu_irq(arch_timer_ppi[arch_timer_uses_ppi]);
526 if (arch_timer_has_nonsecure_ppi())
527 disable_percpu_irq(arch_timer_ppi[PHYS_NONSECURE_PPI]);
Mark Rutland8a4da6e2012-11-12 14:33:44 +0000528
Viresh Kumar46c5bfd2015-06-12 13:30:12 +0530529 clk->set_state_shutdown(clk);
Mark Rutland8a4da6e2012-11-12 14:33:44 +0000530}
531
Richard Cochran7e86e8b2016-07-13 17:16:39 +0000532static int arch_timer_dying_cpu(unsigned int cpu)
Mark Rutland8a4da6e2012-11-12 14:33:44 +0000533{
Richard Cochran7e86e8b2016-07-13 17:16:39 +0000534 struct clock_event_device *clk = this_cpu_ptr(arch_timer_evt);
Mark Rutland8a4da6e2012-11-12 14:33:44 +0000535
Richard Cochran7e86e8b2016-07-13 17:16:39 +0000536 arch_timer_stop(clk);
537 return 0;
Mark Rutland8a4da6e2012-11-12 14:33:44 +0000538}
539
Sudeep KarkadaNagesha346e7482013-08-23 15:53:15 +0100540#ifdef CONFIG_CPU_PM
541static unsigned int saved_cntkctl;
542static int arch_timer_cpu_pm_notify(struct notifier_block *self,
543 unsigned long action, void *hcpu)
544{
545 if (action == CPU_PM_ENTER)
546 saved_cntkctl = arch_timer_get_cntkctl();
547 else if (action == CPU_PM_ENTER_FAILED || action == CPU_PM_EXIT)
548 arch_timer_set_cntkctl(saved_cntkctl);
549 return NOTIFY_OK;
550}
551
552static struct notifier_block arch_timer_cpu_pm_notifier = {
553 .notifier_call = arch_timer_cpu_pm_notify,
554};
555
556static int __init arch_timer_cpu_pm_init(void)
557{
558 return cpu_pm_register_notifier(&arch_timer_cpu_pm_notifier);
559}
Richard Cochran7e86e8b2016-07-13 17:16:39 +0000560
561static void __init arch_timer_cpu_pm_deinit(void)
562{
563 WARN_ON(cpu_pm_unregister_notifier(&arch_timer_cpu_pm_notifier));
564}
565
Sudeep KarkadaNagesha346e7482013-08-23 15:53:15 +0100566#else
567static int __init arch_timer_cpu_pm_init(void)
568{
569 return 0;
570}
Richard Cochran7e86e8b2016-07-13 17:16:39 +0000571
572static void __init arch_timer_cpu_pm_deinit(void)
573{
574}
Sudeep KarkadaNagesha346e7482013-08-23 15:53:15 +0100575#endif
576
Mark Rutland8a4da6e2012-11-12 14:33:44 +0000577static int __init arch_timer_register(void)
578{
579 int err;
580 int ppi;
581
Mark Rutland8a4da6e2012-11-12 14:33:44 +0000582 arch_timer_evt = alloc_percpu(struct clock_event_device);
583 if (!arch_timer_evt) {
584 err = -ENOMEM;
585 goto out;
586 }
587
Marc Zyngierf81f03f2014-02-20 15:21:23 +0000588 ppi = arch_timer_ppi[arch_timer_uses_ppi];
589 switch (arch_timer_uses_ppi) {
590 case VIRT_PPI:
Mark Rutland8a4da6e2012-11-12 14:33:44 +0000591 err = request_percpu_irq(ppi, arch_timer_handler_virt,
592 "arch_timer", arch_timer_evt);
Marc Zyngierf81f03f2014-02-20 15:21:23 +0000593 break;
594 case PHYS_SECURE_PPI:
595 case PHYS_NONSECURE_PPI:
Mark Rutland8a4da6e2012-11-12 14:33:44 +0000596 err = request_percpu_irq(ppi, arch_timer_handler_phys,
597 "arch_timer", arch_timer_evt);
598 if (!err && arch_timer_ppi[PHYS_NONSECURE_PPI]) {
599 ppi = arch_timer_ppi[PHYS_NONSECURE_PPI];
600 err = request_percpu_irq(ppi, arch_timer_handler_phys,
601 "arch_timer", arch_timer_evt);
602 if (err)
603 free_percpu_irq(arch_timer_ppi[PHYS_SECURE_PPI],
604 arch_timer_evt);
605 }
Marc Zyngierf81f03f2014-02-20 15:21:23 +0000606 break;
607 case HYP_PPI:
608 err = request_percpu_irq(ppi, arch_timer_handler_phys,
609 "arch_timer", arch_timer_evt);
610 break;
611 default:
612 BUG();
Mark Rutland8a4da6e2012-11-12 14:33:44 +0000613 }
614
615 if (err) {
616 pr_err("arch_timer: can't register interrupt %d (%d)\n",
617 ppi, err);
618 goto out_free;
619 }
620
Sudeep KarkadaNagesha346e7482013-08-23 15:53:15 +0100621 err = arch_timer_cpu_pm_init();
622 if (err)
623 goto out_unreg_notify;
624
Mark Rutland8a4da6e2012-11-12 14:33:44 +0000625
Richard Cochran7e86e8b2016-07-13 17:16:39 +0000626 /* Register and immediately configure the timer on the boot CPU */
627 err = cpuhp_setup_state(CPUHP_AP_ARM_ARCH_TIMER_STARTING,
628 "AP_ARM_ARCH_TIMER_STARTING",
629 arch_timer_starting_cpu, arch_timer_dying_cpu);
630 if (err)
631 goto out_unreg_cpupm;
Mark Rutland8a4da6e2012-11-12 14:33:44 +0000632 return 0;
633
Richard Cochran7e86e8b2016-07-13 17:16:39 +0000634out_unreg_cpupm:
635 arch_timer_cpu_pm_deinit();
636
Sudeep KarkadaNagesha346e7482013-08-23 15:53:15 +0100637out_unreg_notify:
Marc Zyngierf81f03f2014-02-20 15:21:23 +0000638 free_percpu_irq(arch_timer_ppi[arch_timer_uses_ppi], arch_timer_evt);
639 if (arch_timer_has_nonsecure_ppi())
640 free_percpu_irq(arch_timer_ppi[PHYS_NONSECURE_PPI],
Mark Rutland8a4da6e2012-11-12 14:33:44 +0000641 arch_timer_evt);
Mark Rutland8a4da6e2012-11-12 14:33:44 +0000642
643out_free:
644 free_percpu(arch_timer_evt);
645out:
646 return err;
647}
648
Stephen Boyd22006992013-07-18 16:59:32 -0700649static int __init arch_timer_mem_register(void __iomem *base, unsigned int irq)
650{
651 int ret;
652 irq_handler_t func;
653 struct arch_timer *t;
654
655 t = kzalloc(sizeof(*t), GFP_KERNEL);
656 if (!t)
657 return -ENOMEM;
658
659 t->base = base;
660 t->evt.irq = irq;
661 __arch_timer_setup(ARCH_MEM_TIMER, &t->evt);
662
663 if (arch_timer_mem_use_virtual)
664 func = arch_timer_handler_virt_mem;
665 else
666 func = arch_timer_handler_phys_mem;
667
668 ret = request_irq(irq, func, IRQF_TIMER, "arch_mem_timer", &t->evt);
669 if (ret) {
670 pr_err("arch_timer: Failed to request mem timer irq\n");
671 kfree(t);
672 }
673
674 return ret;
675}
676
677static const struct of_device_id arch_timer_of_match[] __initconst = {
678 { .compatible = "arm,armv7-timer", },
679 { .compatible = "arm,armv8-timer", },
680 {},
681};
682
683static const struct of_device_id arch_timer_mem_of_match[] __initconst = {
684 { .compatible = "arm,armv7-timer-mem", },
685 {},
686};
687
Sudeep Hollac387f072014-09-29 01:50:05 +0200688static bool __init
Laurent Pinchart566e6df2015-03-31 12:12:22 +0200689arch_timer_needs_probing(int type, const struct of_device_id *matches)
Sudeep Hollac387f072014-09-29 01:50:05 +0200690{
691 struct device_node *dn;
Laurent Pinchart566e6df2015-03-31 12:12:22 +0200692 bool needs_probing = false;
Sudeep Hollac387f072014-09-29 01:50:05 +0200693
694 dn = of_find_matching_node(NULL, matches);
Marc Zyngier59aa8962014-10-15 16:06:20 +0100695 if (dn && of_device_is_available(dn) && !(arch_timers_present & type))
Laurent Pinchart566e6df2015-03-31 12:12:22 +0200696 needs_probing = true;
Sudeep Hollac387f072014-09-29 01:50:05 +0200697 of_node_put(dn);
698
Laurent Pinchart566e6df2015-03-31 12:12:22 +0200699 return needs_probing;
Sudeep Hollac387f072014-09-29 01:50:05 +0200700}
701
Daniel Lezcano3c0731d2016-06-06 17:55:40 +0200702static int __init arch_timer_common_init(void)
Stephen Boyd22006992013-07-18 16:59:32 -0700703{
704 unsigned mask = ARCH_CP15_TIMER | ARCH_MEM_TIMER;
705
706 /* Wait until both nodes are probed if we have two timers */
707 if ((arch_timers_present & mask) != mask) {
Laurent Pinchart566e6df2015-03-31 12:12:22 +0200708 if (arch_timer_needs_probing(ARCH_MEM_TIMER, arch_timer_mem_of_match))
Daniel Lezcano3c0731d2016-06-06 17:55:40 +0200709 return 0;
Laurent Pinchart566e6df2015-03-31 12:12:22 +0200710 if (arch_timer_needs_probing(ARCH_CP15_TIMER, arch_timer_of_match))
Daniel Lezcano3c0731d2016-06-06 17:55:40 +0200711 return 0;
Stephen Boyd22006992013-07-18 16:59:32 -0700712 }
713
714 arch_timer_banner(arch_timers_present);
715 arch_counter_register(arch_timers_present);
Daniel Lezcano3c0731d2016-06-06 17:55:40 +0200716 return arch_timer_arch_init();
Stephen Boyd22006992013-07-18 16:59:32 -0700717}
718
Daniel Lezcano3c0731d2016-06-06 17:55:40 +0200719static int __init arch_timer_init(void)
Mark Rutland8a4da6e2012-11-12 14:33:44 +0000720{
Daniel Lezcano3c0731d2016-06-06 17:55:40 +0200721 int ret;
Doug Anderson65b57322014-10-08 00:33:47 -0700722 /*
Marc Zyngier82668912013-01-10 11:13:07 +0000723 * If HYP mode is available, we know that the physical timer
724 * has been configured to be accessible from PL1. Use it, so
725 * that a guest can use the virtual timer instead.
726 *
Mark Rutland8a4da6e2012-11-12 14:33:44 +0000727 * If no interrupt provided for virtual timer, we'll have to
728 * stick to the physical timer. It'd better be accessible...
Marc Zyngierf81f03f2014-02-20 15:21:23 +0000729 *
730 * On ARMv8.1 with VH extensions, the kernel runs in HYP. VHE
731 * accesses to CNTP_*_EL1 registers are silently redirected to
732 * their CNTHP_*_EL2 counterparts, and use a different PPI
733 * number.
Mark Rutland8a4da6e2012-11-12 14:33:44 +0000734 */
Marc Zyngier82668912013-01-10 11:13:07 +0000735 if (is_hyp_mode_available() || !arch_timer_ppi[VIRT_PPI]) {
Marc Zyngierf81f03f2014-02-20 15:21:23 +0000736 bool has_ppi;
Mark Rutland8a4da6e2012-11-12 14:33:44 +0000737
Marc Zyngierf81f03f2014-02-20 15:21:23 +0000738 if (is_kernel_in_hyp_mode()) {
739 arch_timer_uses_ppi = HYP_PPI;
740 has_ppi = !!arch_timer_ppi[HYP_PPI];
741 } else {
742 arch_timer_uses_ppi = PHYS_SECURE_PPI;
743 has_ppi = (!!arch_timer_ppi[PHYS_SECURE_PPI] ||
744 !!arch_timer_ppi[PHYS_NONSECURE_PPI]);
745 }
746
747 if (!has_ppi) {
Mark Rutland8a4da6e2012-11-12 14:33:44 +0000748 pr_warn("arch_timer: No interrupt available, giving up\n");
Daniel Lezcano3c0731d2016-06-06 17:55:40 +0200749 return -EINVAL;
Mark Rutland8a4da6e2012-11-12 14:33:44 +0000750 }
751 }
752
Daniel Lezcano3c0731d2016-06-06 17:55:40 +0200753 ret = arch_timer_register();
754 if (ret)
755 return ret;
756
757 ret = arch_timer_common_init();
758 if (ret)
759 return ret;
Julien Gralld9b5e412016-04-11 16:32:52 +0100760
761 arch_timer_kvm_info.virtual_irq = arch_timer_ppi[VIRT_PPI];
Daniel Lezcano3c0731d2016-06-06 17:55:40 +0200762
763 return 0;
Mark Rutland8a4da6e2012-11-12 14:33:44 +0000764}
Hanjun Guob09ca1e2015-03-24 14:02:50 +0000765
Daniel Lezcano3c0731d2016-06-06 17:55:40 +0200766static int __init arch_timer_of_init(struct device_node *np)
Hanjun Guob09ca1e2015-03-24 14:02:50 +0000767{
768 int i;
769
770 if (arch_timers_present & ARCH_CP15_TIMER) {
771 pr_warn("arch_timer: multiple nodes in dt, skipping\n");
Daniel Lezcano3c0731d2016-06-06 17:55:40 +0200772 return 0;
Hanjun Guob09ca1e2015-03-24 14:02:50 +0000773 }
774
775 arch_timers_present |= ARCH_CP15_TIMER;
776 for (i = PHYS_SECURE_PPI; i < MAX_TIMER_PPI; i++)
777 arch_timer_ppi[i] = irq_of_parse_and_map(np, i);
778
779 arch_timer_detect_rate(NULL, np);
780
781 arch_timer_c3stop = !of_property_read_bool(np, "always-on");
782
783 /*
784 * If we cannot rely on firmware initializing the timer registers then
785 * we should use the physical timers instead.
786 */
787 if (IS_ENABLED(CONFIG_ARM) &&
788 of_property_read_bool(np, "arm,cpu-registers-not-fw-configured"))
Marc Zyngierf81f03f2014-02-20 15:21:23 +0000789 arch_timer_uses_ppi = PHYS_SECURE_PPI;
Hanjun Guob09ca1e2015-03-24 14:02:50 +0000790
Daniel Lezcano3c0731d2016-06-06 17:55:40 +0200791 return arch_timer_init();
Hanjun Guob09ca1e2015-03-24 14:02:50 +0000792}
Daniel Lezcano177cf6e2016-06-07 00:27:44 +0200793CLOCKSOURCE_OF_DECLARE(armv7_arch_timer, "arm,armv7-timer", arch_timer_of_init);
794CLOCKSOURCE_OF_DECLARE(armv8_arch_timer, "arm,armv8-timer", arch_timer_of_init);
Stephen Boyd22006992013-07-18 16:59:32 -0700795
Daniel Lezcano3c0731d2016-06-06 17:55:40 +0200796static int __init arch_timer_mem_init(struct device_node *np)
Stephen Boyd22006992013-07-18 16:59:32 -0700797{
798 struct device_node *frame, *best_frame = NULL;
799 void __iomem *cntctlbase, *base;
Daniel Lezcano3c0731d2016-06-06 17:55:40 +0200800 unsigned int irq, ret = -EINVAL;
Stephen Boyd22006992013-07-18 16:59:32 -0700801 u32 cnttidr;
802
803 arch_timers_present |= ARCH_MEM_TIMER;
804 cntctlbase = of_iomap(np, 0);
805 if (!cntctlbase) {
806 pr_err("arch_timer: Can't find CNTCTLBase\n");
Daniel Lezcano3c0731d2016-06-06 17:55:40 +0200807 return -ENXIO;
Stephen Boyd22006992013-07-18 16:59:32 -0700808 }
809
810 cnttidr = readl_relaxed(cntctlbase + CNTTIDR);
Stephen Boyd22006992013-07-18 16:59:32 -0700811
812 /*
813 * Try to find a virtual capable frame. Otherwise fall back to a
814 * physical capable frame.
815 */
816 for_each_available_child_of_node(np, frame) {
817 int n;
Robin Murphye392d602016-02-01 12:00:48 +0000818 u32 cntacr;
Stephen Boyd22006992013-07-18 16:59:32 -0700819
820 if (of_property_read_u32(frame, "frame-number", &n)) {
821 pr_err("arch_timer: Missing frame-number\n");
Stephen Boyd22006992013-07-18 16:59:32 -0700822 of_node_put(frame);
Robin Murphye392d602016-02-01 12:00:48 +0000823 goto out;
Stephen Boyd22006992013-07-18 16:59:32 -0700824 }
825
Robin Murphye392d602016-02-01 12:00:48 +0000826 /* Try enabling everything, and see what sticks */
827 cntacr = CNTACR_RFRQ | CNTACR_RWPT | CNTACR_RPCT |
828 CNTACR_RWVT | CNTACR_RVOFF | CNTACR_RVCT;
829 writel_relaxed(cntacr, cntctlbase + CNTACR(n));
830 cntacr = readl_relaxed(cntctlbase + CNTACR(n));
831
832 if ((cnttidr & CNTTIDR_VIRT(n)) &&
833 !(~cntacr & (CNTACR_RWVT | CNTACR_RVCT))) {
Stephen Boyd22006992013-07-18 16:59:32 -0700834 of_node_put(best_frame);
835 best_frame = frame;
836 arch_timer_mem_use_virtual = true;
837 break;
838 }
Robin Murphye392d602016-02-01 12:00:48 +0000839
840 if (~cntacr & (CNTACR_RWPT | CNTACR_RPCT))
841 continue;
842
Stephen Boyd22006992013-07-18 16:59:32 -0700843 of_node_put(best_frame);
844 best_frame = of_node_get(frame);
845 }
846
Daniel Lezcano3c0731d2016-06-06 17:55:40 +0200847 ret= -ENXIO;
Stephen Boyd22006992013-07-18 16:59:32 -0700848 base = arch_counter_base = of_iomap(best_frame, 0);
849 if (!base) {
850 pr_err("arch_timer: Can't map frame's registers\n");
Robin Murphye392d602016-02-01 12:00:48 +0000851 goto out;
Stephen Boyd22006992013-07-18 16:59:32 -0700852 }
853
854 if (arch_timer_mem_use_virtual)
855 irq = irq_of_parse_and_map(best_frame, 1);
856 else
857 irq = irq_of_parse_and_map(best_frame, 0);
Robin Murphye392d602016-02-01 12:00:48 +0000858
Daniel Lezcano3c0731d2016-06-06 17:55:40 +0200859 ret = -EINVAL;
Stephen Boyd22006992013-07-18 16:59:32 -0700860 if (!irq) {
861 pr_err("arch_timer: Frame missing %s irq",
Thomas Gleixnercfb6d652013-08-21 14:59:23 +0200862 arch_timer_mem_use_virtual ? "virt" : "phys");
Robin Murphye392d602016-02-01 12:00:48 +0000863 goto out;
Stephen Boyd22006992013-07-18 16:59:32 -0700864 }
865
866 arch_timer_detect_rate(base, np);
Daniel Lezcano3c0731d2016-06-06 17:55:40 +0200867 ret = arch_timer_mem_register(base, irq);
868 if (ret)
869 goto out;
870
871 return arch_timer_common_init();
Robin Murphye392d602016-02-01 12:00:48 +0000872out:
873 iounmap(cntctlbase);
874 of_node_put(best_frame);
Daniel Lezcano3c0731d2016-06-06 17:55:40 +0200875 return ret;
Stephen Boyd22006992013-07-18 16:59:32 -0700876}
Daniel Lezcano177cf6e2016-06-07 00:27:44 +0200877CLOCKSOURCE_OF_DECLARE(armv7_arch_timer_mem, "arm,armv7-timer-mem",
Stephen Boyd22006992013-07-18 16:59:32 -0700878 arch_timer_mem_init);
Hanjun Guob09ca1e2015-03-24 14:02:50 +0000879
880#ifdef CONFIG_ACPI
881static int __init map_generic_timer_interrupt(u32 interrupt, u32 flags)
882{
883 int trigger, polarity;
884
885 if (!interrupt)
886 return 0;
887
888 trigger = (flags & ACPI_GTDT_INTERRUPT_MODE) ? ACPI_EDGE_SENSITIVE
889 : ACPI_LEVEL_SENSITIVE;
890
891 polarity = (flags & ACPI_GTDT_INTERRUPT_POLARITY) ? ACPI_ACTIVE_LOW
892 : ACPI_ACTIVE_HIGH;
893
894 return acpi_register_gsi(NULL, interrupt, trigger, polarity);
895}
896
897/* Initialize per-processor generic timer */
898static int __init arch_timer_acpi_init(struct acpi_table_header *table)
899{
900 struct acpi_table_gtdt *gtdt;
901
902 if (arch_timers_present & ARCH_CP15_TIMER) {
903 pr_warn("arch_timer: already initialized, skipping\n");
904 return -EINVAL;
905 }
906
907 gtdt = container_of(table, struct acpi_table_gtdt, header);
908
909 arch_timers_present |= ARCH_CP15_TIMER;
910
911 arch_timer_ppi[PHYS_SECURE_PPI] =
912 map_generic_timer_interrupt(gtdt->secure_el1_interrupt,
913 gtdt->secure_el1_flags);
914
915 arch_timer_ppi[PHYS_NONSECURE_PPI] =
916 map_generic_timer_interrupt(gtdt->non_secure_el1_interrupt,
917 gtdt->non_secure_el1_flags);
918
919 arch_timer_ppi[VIRT_PPI] =
920 map_generic_timer_interrupt(gtdt->virtual_timer_interrupt,
921 gtdt->virtual_timer_flags);
922
923 arch_timer_ppi[HYP_PPI] =
924 map_generic_timer_interrupt(gtdt->non_secure_el2_interrupt,
925 gtdt->non_secure_el2_flags);
926
927 /* Get the frequency from CNTFRQ */
928 arch_timer_detect_rate(NULL, NULL);
929
930 /* Always-on capability */
931 arch_timer_c3stop = !(gtdt->non_secure_el1_flags & ACPI_GTDT_ALWAYS_ON);
932
933 arch_timer_init();
934 return 0;
935}
Marc Zyngierae281cb2015-09-28 15:49:17 +0100936CLOCKSOURCE_ACPI_DECLARE(arch_timer, ACPI_SIG_GTDT, arch_timer_acpi_init);
Hanjun Guob09ca1e2015-03-24 14:02:50 +0000937#endif