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gerrit-public.fairphone.software / kernel / msm-4.9 / a38c9cb7cb46ad2d7124c20e033e047d8829128e / . / drivers / pinctrl / sunxi / pinctrl-sun5i-a10s.c
blob: f9a3f8f446f76afe28177d5f9dcb8b8376b0310b [file] [log] [blame]
Maxime Ripard0a127c12014-04-18 20:12:50 +0200[diff] [blame]1/*
2 * Allwinner A10s SoCs pinctrl driver.
3 *
4 * Copyright (C) 2014 Maxime Ripard
5 *
6 * Maxime Ripard <maxime.ripard@free-electrons.com>
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 */
12
13#include <linux/module.h>
14#include <linux/platform_device.h>
15#include <linux/of.h>
16#include <linux/of_device.h>
17#include <linux/pinctrl/pinctrl.h>
18
19#include "pinctrl-sunxi.h"
20
21static const struct sunxi_desc_pin sun5i_a10s_pins[] = {
22 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 0),
23 SUNXI_FUNCTION(0x0, "gpio_in"),
24 SUNXI_FUNCTION(0x1, "gpio_out"),
25 SUNXI_FUNCTION(0x2, "emac"), /* ERXD3 */
26 SUNXI_FUNCTION(0x3, "ts0"), /* CLK */
27 SUNXI_FUNCTION(0x5, "keypad")), /* IN0 */
28 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 1),
29 SUNXI_FUNCTION(0x0, "gpio_in"),
30 SUNXI_FUNCTION(0x1, "gpio_out"),
31 SUNXI_FUNCTION(0x2, "emac"), /* ERXD2 */
32 SUNXI_FUNCTION(0x3, "ts0"), /* ERR */
33 SUNXI_FUNCTION(0x5, "keypad")), /* IN1 */
34 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 2),
35 SUNXI_FUNCTION(0x0, "gpio_in"),
36 SUNXI_FUNCTION(0x1, "gpio_out"),
37 SUNXI_FUNCTION(0x2, "emac"), /* ERXD1 */
38 SUNXI_FUNCTION(0x3, "ts0"), /* SYNC */
39 SUNXI_FUNCTION(0x5, "keypad")), /* IN2 */
40 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3),
41 SUNXI_FUNCTION(0x0, "gpio_in"),
42 SUNXI_FUNCTION(0x1, "gpio_out"),
43 SUNXI_FUNCTION(0x2, "emac"), /* ERXD0 */
44 SUNXI_FUNCTION(0x3, "ts0"), /* DLVD */
45 SUNXI_FUNCTION(0x5, "keypad")), /* IN3 */
46 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 4),
47 SUNXI_FUNCTION(0x0, "gpio_in"),
48 SUNXI_FUNCTION(0x1, "gpio_out"),
49 SUNXI_FUNCTION(0x2, "emac"), /* ETXD3 */
50 SUNXI_FUNCTION(0x3, "ts0"), /* D0 */
51 SUNXI_FUNCTION(0x5, "keypad")), /* IN4 */
52 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 5),
53 SUNXI_FUNCTION(0x0, "gpio_in"),
54 SUNXI_FUNCTION(0x1, "gpio_out"),
55 SUNXI_FUNCTION(0x2, "emac"), /* ETXD2 */
56 SUNXI_FUNCTION(0x3, "ts0"), /* D1 */
57 SUNXI_FUNCTION(0x5, "keypad")), /* IN5 */
58 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 6),
59 SUNXI_FUNCTION(0x0, "gpio_in"),
60 SUNXI_FUNCTION(0x1, "gpio_out"),
61 SUNXI_FUNCTION(0x2, "emac"), /* ETXD1 */
62 SUNXI_FUNCTION(0x3, "ts0"), /* D2 */
63 SUNXI_FUNCTION(0x5, "keypad")), /* IN6 */
64 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 7),
65 SUNXI_FUNCTION(0x0, "gpio_in"),
66 SUNXI_FUNCTION(0x1, "gpio_out"),
67 SUNXI_FUNCTION(0x2, "emac"), /* ETXD0 */
68 SUNXI_FUNCTION(0x3, "ts0"), /* D3 */
69 SUNXI_FUNCTION(0x5, "keypad")), /* IN7 */
70 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 8),
71 SUNXI_FUNCTION(0x0, "gpio_in"),
72 SUNXI_FUNCTION(0x1, "gpio_out"),
73 SUNXI_FUNCTION(0x2, "emac"), /* ERXCK */
74 SUNXI_FUNCTION(0x3, "ts0"), /* D4 */
75 SUNXI_FUNCTION(0x4, "uart1"), /* DTR */
76 SUNXI_FUNCTION(0x5, "keypad")), /* OUT0 */
77 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 9),
78 SUNXI_FUNCTION(0x0, "gpio_in"),
79 SUNXI_FUNCTION(0x1, "gpio_out"),
80 SUNXI_FUNCTION(0x2, "emac"), /* ERXERR */
81 SUNXI_FUNCTION(0x3, "ts0"), /* D5 */
82 SUNXI_FUNCTION(0x4, "uart1"), /* DSR */
83 SUNXI_FUNCTION(0x5, "keypad")), /* OUT1 */
84 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 10),
85 SUNXI_FUNCTION(0x0, "gpio_in"),
86 SUNXI_FUNCTION(0x1, "gpio_out"),
87 SUNXI_FUNCTION(0x2, "emac"), /* ERXDV */
88 SUNXI_FUNCTION(0x3, "ts0"), /* D6 */
89 SUNXI_FUNCTION(0x4, "uart1"), /* DCD */
90 SUNXI_FUNCTION(0x5, "keypad")), /* OUT2 */
91 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 11),
92 SUNXI_FUNCTION(0x0, "gpio_in"),
93 SUNXI_FUNCTION(0x1, "gpio_out"),
94 SUNXI_FUNCTION(0x2, "emac"), /* EMDC */
95 SUNXI_FUNCTION(0x3, "ts0"), /* D7 */
96 SUNXI_FUNCTION(0x4, "uart1"), /* RING */
97 SUNXI_FUNCTION(0x5, "keypad")), /* OUT3 */
98 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 12),
99 SUNXI_FUNCTION(0x0, "gpio_in"),
100 SUNXI_FUNCTION(0x1, "gpio_out"),
101 SUNXI_FUNCTION(0x2, "emac"), /* EMDIO */
102 SUNXI_FUNCTION(0x3, "uart1"), /* TX */
103 SUNXI_FUNCTION(0x5, "keypad")), /* OUT4 */
104 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 13),
105 SUNXI_FUNCTION(0x0, "gpio_in"),
106 SUNXI_FUNCTION(0x1, "gpio_out"),
107 SUNXI_FUNCTION(0x2, "emac"), /* ETXEN */
108 SUNXI_FUNCTION(0x3, "uart1"), /* RX */
109 SUNXI_FUNCTION(0x5, "keypad")), /* OUT5 */
110 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 14),
111 SUNXI_FUNCTION(0x0, "gpio_in"),
112 SUNXI_FUNCTION(0x1, "gpio_out"),
113 SUNXI_FUNCTION(0x2, "emac"), /* ETXCK */
114 SUNXI_FUNCTION(0x3, "uart1"), /* CTS */
115 SUNXI_FUNCTION(0x4, "uart3"), /* TX */
116 SUNXI_FUNCTION(0x5, "keypad")), /* OUT6 */
117 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 15),
118 SUNXI_FUNCTION(0x0, "gpio_in"),
119 SUNXI_FUNCTION(0x1, "gpio_out"),
120 SUNXI_FUNCTION(0x2, "emac"), /* ECRS */
121 SUNXI_FUNCTION(0x3, "uart1"), /* RTS */
122 SUNXI_FUNCTION(0x4, "uart3"), /* RX */
123 SUNXI_FUNCTION(0x5, "keypad")), /* OUT7 */
124 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 16),
125 SUNXI_FUNCTION(0x0, "gpio_in"),
126 SUNXI_FUNCTION(0x1, "gpio_out"),
127 SUNXI_FUNCTION(0x2, "emac"), /* ECOL */
128 SUNXI_FUNCTION(0x3, "uart2")), /* TX */
129 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 17),
130 SUNXI_FUNCTION(0x0, "gpio_in"),
131 SUNXI_FUNCTION(0x1, "gpio_out"),
132 SUNXI_FUNCTION(0x2, "emac"), /* ETXERR */
133 SUNXI_FUNCTION(0x3, "uart2"), /* RX */
134 SUNXI_FUNCTION_IRQ(0x6, 31)), /* EINT31 */
135 /* Hole */
136 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0),
137 SUNXI_FUNCTION(0x0, "gpio_in"),
138 SUNXI_FUNCTION(0x1, "gpio_out"),
139 SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */
140 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1),
141 SUNXI_FUNCTION(0x0, "gpio_in"),
142 SUNXI_FUNCTION(0x1, "gpio_out"),
143 SUNXI_FUNCTION(0x2, "i2c0")), /* SDA */
144 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2),
145 SUNXI_FUNCTION(0x0, "gpio_in"),
146 SUNXI_FUNCTION(0x1, "gpio_out"),
147 SUNXI_FUNCTION(0x2, "pwm"), /* PWM0 */
148 SUNXI_FUNCTION_IRQ(0x6, 16)), /* EINT16 */
149 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3),
150 SUNXI_FUNCTION(0x0, "gpio_in"),
151 SUNXI_FUNCTION(0x1, "gpio_out"),
152 SUNXI_FUNCTION(0x2, "ir0"), /* TX */
153 SUNXI_FUNCTION_IRQ(0x6, 17)), /* EINT17 */
154 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4),
155 SUNXI_FUNCTION(0x0, "gpio_in"),
156 SUNXI_FUNCTION(0x1, "gpio_out"),
157 SUNXI_FUNCTION(0x2, "ir0"), /* RX */
158 SUNXI_FUNCTION_IRQ(0x6, 18)), /* EINT18 */
159 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5),
160 SUNXI_FUNCTION(0x0, "gpio_in"),
161 SUNXI_FUNCTION(0x1, "gpio_out"),
162 SUNXI_FUNCTION(0x2, "i2s"), /* MCLK */
163 SUNXI_FUNCTION_IRQ(0x6, 19)), /* EINT19 */
164 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6),
165 SUNXI_FUNCTION(0x0, "gpio_in"),
166 SUNXI_FUNCTION(0x1, "gpio_out"),
167 SUNXI_FUNCTION(0x2, "i2s"), /* BCLK */
168 SUNXI_FUNCTION_IRQ(0x6, 20)), /* EINT20 */
169 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7),
170 SUNXI_FUNCTION(0x0, "gpio_in"),
171 SUNXI_FUNCTION(0x1, "gpio_out"),
172 SUNXI_FUNCTION(0x2, "i2s"), /* LRCK */
173 SUNXI_FUNCTION_IRQ(0x6, 21)), /* EINT21 */
174 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 8),
175 SUNXI_FUNCTION(0x0, "gpio_in"),
176 SUNXI_FUNCTION(0x1, "gpio_out"),
177 SUNXI_FUNCTION(0x2, "i2s"), /* DO */
178 SUNXI_FUNCTION_IRQ(0x6, 22)), /* EINT22 */
179 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 9),
180 SUNXI_FUNCTION(0x0, "gpio_in"),
181 SUNXI_FUNCTION(0x1, "gpio_out"),
182 SUNXI_FUNCTION(0x2, "i2s"), /* DI */
183 SUNXI_FUNCTION_IRQ(0x6, 23)), /* EINT23 */
184 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 10),
185 SUNXI_FUNCTION(0x0, "gpio_in"),
186 SUNXI_FUNCTION(0x1, "gpio_out"),
187 SUNXI_FUNCTION(0x2, "spi2"), /* CS1 */
188 SUNXI_FUNCTION_IRQ(0x6, 24)), /* EINT24 */
189 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 11),
190 SUNXI_FUNCTION(0x0, "gpio_in"),
191 SUNXI_FUNCTION(0x1, "gpio_out"),
192 SUNXI_FUNCTION(0x2, "spi2"), /* CS0 */
193 SUNXI_FUNCTION(0x3, "jtag"), /* MS0 */
194 SUNXI_FUNCTION_IRQ(0x6, 25)), /* EINT25 */
195 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 12),
196 SUNXI_FUNCTION(0x0, "gpio_in"),
197 SUNXI_FUNCTION(0x1, "gpio_out"),
198 SUNXI_FUNCTION(0x2, "spi2"), /* CLK */
199 SUNXI_FUNCTION(0x3, "jtag"), /* CK0 */
200 SUNXI_FUNCTION_IRQ(0x6, 26)), /* EINT26 */
201 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 13),
202 SUNXI_FUNCTION(0x0, "gpio_in"),
203 SUNXI_FUNCTION(0x1, "gpio_out"),
204 SUNXI_FUNCTION(0x2, "spi2"), /* MOSI */
205 SUNXI_FUNCTION(0x3, "jtag"), /* DO0 */
206 SUNXI_FUNCTION_IRQ(0x6, 27)), /* EINT27 */
207 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 14),
208 SUNXI_FUNCTION(0x0, "gpio_in"),
209 SUNXI_FUNCTION(0x1, "gpio_out"),
210 SUNXI_FUNCTION(0x2, "spi2"), /* MISO */
211 SUNXI_FUNCTION(0x3, "jtag"), /* DI0 */
212 SUNXI_FUNCTION_IRQ(0x6, 28)), /* EINT28 */
213 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 15),
214 SUNXI_FUNCTION(0x0, "gpio_in"),
215 SUNXI_FUNCTION(0x1, "gpio_out"),
216 SUNXI_FUNCTION(0x2, "i2c1")), /* SCK */
217 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 16),
218 SUNXI_FUNCTION(0x0, "gpio_in"),
219 SUNXI_FUNCTION(0x1, "gpio_out"),
220 SUNXI_FUNCTION(0x2, "i2c1")), /* SDA */
221 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 17),
222 SUNXI_FUNCTION(0x0, "gpio_in"),
223 SUNXI_FUNCTION(0x1, "gpio_out"),
224 SUNXI_FUNCTION(0x2, "i2c2")), /* SCK */
225 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 18),
226 SUNXI_FUNCTION(0x0, "gpio_in"),
227 SUNXI_FUNCTION(0x1, "gpio_out"),
228 SUNXI_FUNCTION(0x2, "i2c2")), /* SDA */
229 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 19),
230 SUNXI_FUNCTION(0x0, "gpio_in"),
231 SUNXI_FUNCTION(0x1, "gpio_out"),
232 SUNXI_FUNCTION(0x2, "uart0"), /* TX */
233 SUNXI_FUNCTION_IRQ(0x6, 29)), /* EINT29 */
234 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 20),
235 SUNXI_FUNCTION(0x0, "gpio_in"),
236 SUNXI_FUNCTION(0x1, "gpio_out"),
237 SUNXI_FUNCTION(0x2, "uart0"), /* RX */
238 SUNXI_FUNCTION_IRQ(0x6, 30)), /* EINT30 */
239 /* Hole */
240 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),
241 SUNXI_FUNCTION(0x0, "gpio_in"),
242 SUNXI_FUNCTION(0x1, "gpio_out"),
243 SUNXI_FUNCTION(0x2, "nand0"), /* NWE */
244 SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */
245 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1),
246 SUNXI_FUNCTION(0x0, "gpio_in"),
247 SUNXI_FUNCTION(0x1, "gpio_out"),
248 SUNXI_FUNCTION(0x2, "nand0"), /* NALE */
249 SUNXI_FUNCTION(0x3, "spi0")), /* MISO */
250 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2),
251 SUNXI_FUNCTION(0x0, "gpio_in"),
252 SUNXI_FUNCTION(0x1, "gpio_out"),
253 SUNXI_FUNCTION(0x2, "nand0"), /* NCLE */
254 SUNXI_FUNCTION(0x3, "spi0")), /* SCK */
255 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3),
256 SUNXI_FUNCTION(0x0, "gpio_in"),
257 SUNXI_FUNCTION(0x1, "gpio_out"),
258 SUNXI_FUNCTION(0x2, "nand0"), /* NCE1 */
259 SUNXI_FUNCTION(0x3, "spi0")), /* CS0 */
260 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4),
261 SUNXI_FUNCTION(0x0, "gpio_in"),
262 SUNXI_FUNCTION(0x1, "gpio_out"),
263 SUNXI_FUNCTION(0x2, "nand0")), /* NCE0 */
264 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5),
265 SUNXI_FUNCTION(0x0, "gpio_in"),
266 SUNXI_FUNCTION(0x1, "gpio_out"),
267 SUNXI_FUNCTION(0x2, "nand0")), /* NRE */
268 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6),
269 SUNXI_FUNCTION(0x0, "gpio_in"),
270 SUNXI_FUNCTION(0x1, "gpio_out"),
271 SUNXI_FUNCTION(0x2, "nand0"), /* NRB0 */
272 SUNXI_FUNCTION(0x3, "mmc2")), /* CMD */
273 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7),
274 SUNXI_FUNCTION(0x0, "gpio_in"),
275 SUNXI_FUNCTION(0x1, "gpio_out"),
276 SUNXI_FUNCTION(0x2, "nand0"), /* NRB1 */
277 SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */
278 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8),
279 SUNXI_FUNCTION(0x0, "gpio_in"),
280 SUNXI_FUNCTION(0x1, "gpio_out"),
281 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ0 */
282 SUNXI_FUNCTION(0x3, "mmc2")), /* D0 */
283 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9),
284 SUNXI_FUNCTION(0x0, "gpio_in"),
285 SUNXI_FUNCTION(0x1, "gpio_out"),
286 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ1 */
287 SUNXI_FUNCTION(0x3, "mmc2")), /* D1 */
288 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10),
289 SUNXI_FUNCTION(0x0, "gpio_in"),
290 SUNXI_FUNCTION(0x1, "gpio_out"),
291 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ2 */
292 SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */
293 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11),
294 SUNXI_FUNCTION(0x0, "gpio_in"),
295 SUNXI_FUNCTION(0x1, "gpio_out"),
296 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ3 */
297 SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */
298 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12),
299 SUNXI_FUNCTION(0x0, "gpio_in"),
300 SUNXI_FUNCTION(0x1, "gpio_out"),
301 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ4 */
302 SUNXI_FUNCTION(0x3, "mmc2")), /* D4 */
303 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13),
304 SUNXI_FUNCTION(0x0, "gpio_in"),
305 SUNXI_FUNCTION(0x1, "gpio_out"),
306 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ5 */
307 SUNXI_FUNCTION(0x3, "mmc2")), /* D5 */
308 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14),
309 SUNXI_FUNCTION(0x0, "gpio_in"),
310 SUNXI_FUNCTION(0x1, "gpio_out"),
311 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ6 */
312 SUNXI_FUNCTION(0x3, "mmc2")), /* D6 */
313 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15),
314 SUNXI_FUNCTION(0x0, "gpio_in"),
315 SUNXI_FUNCTION(0x1, "gpio_out"),
316 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ7 */
317 SUNXI_FUNCTION(0x3, "mmc2")), /* D7 */
318 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16),
319 SUNXI_FUNCTION(0x0, "gpio_in"),
320 SUNXI_FUNCTION(0x1, "gpio_out"),
321 SUNXI_FUNCTION(0x2, "nand0"), /* NWP */
322 SUNXI_FUNCTION(0x4, "uart3")), /* TX */
323 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 17),
324 SUNXI_FUNCTION(0x0, "gpio_in"),
325 SUNXI_FUNCTION(0x1, "gpio_out"),
326 SUNXI_FUNCTION(0x2, "nand0"), /* NCE2 */
327 SUNXI_FUNCTION(0x4, "uart3")), /* RX */
328 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 18),
329 SUNXI_FUNCTION(0x0, "gpio_in"),
330 SUNXI_FUNCTION(0x1, "gpio_out"),
331 SUNXI_FUNCTION(0x2, "nand0"), /* NCE3 */
332 SUNXI_FUNCTION(0x3, "uart2"), /* TX */
333 SUNXI_FUNCTION(0x4, "uart3")), /* CTS */
334 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 19),
335 SUNXI_FUNCTION(0x0, "gpio_in"),
336 SUNXI_FUNCTION(0x1, "gpio_out"),
337 SUNXI_FUNCTION(0x2, "nand0"), /* NCE4 */
338 SUNXI_FUNCTION(0x3, "uart2"), /* RX */
339 SUNXI_FUNCTION(0x4, "uart3")), /* RTS */
340 /* Hole */
341 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 0),
342 SUNXI_FUNCTION(0x0, "gpio_in"),
343 SUNXI_FUNCTION(0x1, "gpio_out"),
344 SUNXI_FUNCTION(0x2, "lcd0")), /* D0 */
345 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 1),
346 SUNXI_FUNCTION(0x0, "gpio_in"),
347 SUNXI_FUNCTION(0x1, "gpio_out"),
348 SUNXI_FUNCTION(0x2, "lcd0")), /* D1 */
349 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2),
350 SUNXI_FUNCTION(0x0, "gpio_in"),
351 SUNXI_FUNCTION(0x1, "gpio_out"),
352 SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */
353 SUNXI_FUNCTION(0x3, "uart2")), /* TX */
354 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3),
355 SUNXI_FUNCTION(0x0, "gpio_in"),
356 SUNXI_FUNCTION(0x1, "gpio_out"),
357 SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */
358 SUNXI_FUNCTION(0x3, "uart2")), /* RX */
359 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4),
360 SUNXI_FUNCTION(0x0, "gpio_in"),
361 SUNXI_FUNCTION(0x1, "gpio_out"),
362 SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */
363 SUNXI_FUNCTION(0x3, "uart2")), /* CTS */
364 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5),
365 SUNXI_FUNCTION(0x0, "gpio_in"),
366 SUNXI_FUNCTION(0x1, "gpio_out"),
367 SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */
368 SUNXI_FUNCTION(0x3, "uart2")), /* RTS */
369 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6),
370 SUNXI_FUNCTION(0x0, "gpio_in"),
371 SUNXI_FUNCTION(0x1, "gpio_out"),
372 SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */
373 SUNXI_FUNCTION(0x3, "emac")), /* ECRS */
374 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7),
375 SUNXI_FUNCTION(0x0, "gpio_in"),
376 SUNXI_FUNCTION(0x1, "gpio_out"),
377 SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */
378 SUNXI_FUNCTION(0x3, "emac")), /* ECOL */
379 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 8),
380 SUNXI_FUNCTION(0x0, "gpio_in"),
381 SUNXI_FUNCTION(0x1, "gpio_out"),
382 SUNXI_FUNCTION(0x2, "lcd0")), /* D8 */
383 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9),
384 SUNXI_FUNCTION(0x0, "gpio_in"),
385 SUNXI_FUNCTION(0x1, "gpio_out"),
386 SUNXI_FUNCTION(0x2, "lcd0")), /* D9 */
387 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10),
388 SUNXI_FUNCTION(0x0, "gpio_in"),
389 SUNXI_FUNCTION(0x1, "gpio_out"),
390 SUNXI_FUNCTION(0x2, "lcd0"), /* D10 */
391 SUNXI_FUNCTION(0x3, "emac")), /* ERXD0 */
392 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11),
393 SUNXI_FUNCTION(0x0, "gpio_in"),
394 SUNXI_FUNCTION(0x1, "gpio_out"),
395 SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */
396 SUNXI_FUNCTION(0x3, "emac")), /* ERXD1 */
397 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12),
398 SUNXI_FUNCTION(0x0, "gpio_in"),
399 SUNXI_FUNCTION(0x1, "gpio_out"),
400 SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */
401 SUNXI_FUNCTION(0x3, "emac")), /* ERXD2 */
402 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13),
403 SUNXI_FUNCTION(0x0, "gpio_in"),
404 SUNXI_FUNCTION(0x1, "gpio_out"),
405 SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */
406 SUNXI_FUNCTION(0x3, "emac")), /* ERXD3 */
407 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14),
408 SUNXI_FUNCTION(0x0, "gpio_in"),
409 SUNXI_FUNCTION(0x1, "gpio_out"),
410 SUNXI_FUNCTION(0x2, "lcd0"), /* D14 */
411 SUNXI_FUNCTION(0x3, "emac")), /* ERXCK */
412 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15),
413 SUNXI_FUNCTION(0x0, "gpio_in"),
414 SUNXI_FUNCTION(0x1, "gpio_out"),
415 SUNXI_FUNCTION(0x2, "lcd0"), /* D15 */
416 SUNXI_FUNCTION(0x3, "emac")), /* ERXERR */
417 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16),
418 SUNXI_FUNCTION(0x0, "gpio_in"),
419 SUNXI_FUNCTION(0x1, "gpio_out"),
420 SUNXI_FUNCTION(0x2, "lcd0")), /* D16 */
421 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17),
422 SUNXI_FUNCTION(0x0, "gpio_in"),
423 SUNXI_FUNCTION(0x1, "gpio_out"),
424 SUNXI_FUNCTION(0x2, "lcd0")), /* D17 */
425 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18),
426 SUNXI_FUNCTION(0x0, "gpio_in"),
427 SUNXI_FUNCTION(0x1, "gpio_out"),
428 SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */
429 SUNXI_FUNCTION(0x3, "emac")), /* ERXDV */
430 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19),
431 SUNXI_FUNCTION(0x0, "gpio_in"),
432 SUNXI_FUNCTION(0x1, "gpio_out"),
433 SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */
434 SUNXI_FUNCTION(0x3, "emac")), /* ETXD0 */
435 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20),
436 SUNXI_FUNCTION(0x0, "gpio_in"),
437 SUNXI_FUNCTION(0x1, "gpio_out"),
438 SUNXI_FUNCTION(0x2, "lcd0"), /* D20 */
439 SUNXI_FUNCTION(0x3, "emac")), /* ETXD1 */
440 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21),
441 SUNXI_FUNCTION(0x0, "gpio_in"),
442 SUNXI_FUNCTION(0x1, "gpio_out"),
443 SUNXI_FUNCTION(0x2, "lcd0"), /* D21 */
444 SUNXI_FUNCTION(0x3, "emac")), /* ETXD2 */
445 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22),
446 SUNXI_FUNCTION(0x0, "gpio_in"),
447 SUNXI_FUNCTION(0x1, "gpio_out"),
448 SUNXI_FUNCTION(0x2, "lcd0"), /* D22 */
449 SUNXI_FUNCTION(0x3, "emac")), /* ETXD3 */
450 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 23),
451 SUNXI_FUNCTION(0x0, "gpio_in"),
452 SUNXI_FUNCTION(0x1, "gpio_out"),
453 SUNXI_FUNCTION(0x2, "lcd0"), /* D23 */
454 SUNXI_FUNCTION(0x3, "emac")), /* ETXEN */
455 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 24),
456 SUNXI_FUNCTION(0x0, "gpio_in"),
457 SUNXI_FUNCTION(0x1, "gpio_out"),
458 SUNXI_FUNCTION(0x2, "lcd0"), /* CLK */
459 SUNXI_FUNCTION(0x3, "emac")), /* ETXCK */
460 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 25),
461 SUNXI_FUNCTION(0x0, "gpio_in"),
462 SUNXI_FUNCTION(0x1, "gpio_out"),
463 SUNXI_FUNCTION(0x2, "lcd0"), /* DE */
464 SUNXI_FUNCTION(0x3, "emac")), /* ETXERR */
465 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 26),
466 SUNXI_FUNCTION(0x0, "gpio_in"),
467 SUNXI_FUNCTION(0x1, "gpio_out"),
468 SUNXI_FUNCTION(0x2, "lcd0"), /* HSYNC */
469 SUNXI_FUNCTION(0x3, "emac")), /* EMDC */
470 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 27),
471 SUNXI_FUNCTION(0x0, "gpio_in"),
472 SUNXI_FUNCTION(0x1, "gpio_out"),
473 SUNXI_FUNCTION(0x2, "lcd0"), /* VSYNC */
474 SUNXI_FUNCTION(0x3, "emac")), /* EMDIO */
475 /* Hole */
476 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0),
477 SUNXI_FUNCTION(0x0, "gpio_in"),
478 SUNXI_FUNCTION(0x2, "ts0"), /* CLK */
479 SUNXI_FUNCTION(0x3, "csi0"), /* PCK */
480 SUNXI_FUNCTION(0x4, "spi2"), /* CS0 */
481 SUNXI_FUNCTION_IRQ(0x6, 14)), /* EINT14 */
482 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1),
483 SUNXI_FUNCTION(0x0, "gpio_in"),
484 SUNXI_FUNCTION(0x2, "ts0"), /* ERR */
485 SUNXI_FUNCTION(0x3, "csi0"), /* CK */
486 SUNXI_FUNCTION(0x4, "spi2"), /* CLK */
487 SUNXI_FUNCTION_IRQ(0x6, 15)), /* EINT15 */
488 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2),
489 SUNXI_FUNCTION(0x0, "gpio_in"),
490 SUNXI_FUNCTION(0x2, "ts0"), /* SYNC */
491 SUNXI_FUNCTION(0x3, "csi0"), /* HSYNC */
492 SUNXI_FUNCTION(0x4, "spi2")), /* MOSI */
493 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3),
494 SUNXI_FUNCTION(0x0, "gpio_in"),
495 SUNXI_FUNCTION(0x1, "gpio_out"),
496 SUNXI_FUNCTION(0x2, "ts0"), /* DVLD */
497 SUNXI_FUNCTION(0x3, "csi0"), /* VSYNC */
498 SUNXI_FUNCTION(0x4, "spi2")), /* MISO */
499 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4),
500 SUNXI_FUNCTION(0x0, "gpio_in"),
501 SUNXI_FUNCTION(0x1, "gpio_out"),
502 SUNXI_FUNCTION(0x2, "ts0"), /* D0 */
503 SUNXI_FUNCTION(0x3, "csi0"), /* D0 */
504 SUNXI_FUNCTION(0x4, "mmc2")), /* D0 */
505 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5),
506 SUNXI_FUNCTION(0x0, "gpio_in"),
507 SUNXI_FUNCTION(0x1, "gpio_out"),
508 SUNXI_FUNCTION(0x2, "ts0"), /* D1 */
509 SUNXI_FUNCTION(0x3, "csi0"), /* D1 */
510 SUNXI_FUNCTION(0x4, "mmc2")), /* D1 */
511 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6),
512 SUNXI_FUNCTION(0x0, "gpio_in"),
513 SUNXI_FUNCTION(0x1, "gpio_out"),
514 SUNXI_FUNCTION(0x2, "ts0"), /* D2 */
515 SUNXI_FUNCTION(0x3, "csi0"), /* D2 */
516 SUNXI_FUNCTION(0x4, "mmc2")), /* D2 */
517 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7),
518 SUNXI_FUNCTION(0x0, "gpio_in"),
519 SUNXI_FUNCTION(0x1, "gpio_out"),
520 SUNXI_FUNCTION(0x2, "ts0"), /* D3 */
521 SUNXI_FUNCTION(0x3, "csi0"), /* D3 */
522 SUNXI_FUNCTION(0x4, "mmc2")), /* D3 */
523 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8),
524 SUNXI_FUNCTION(0x0, "gpio_in"),
525 SUNXI_FUNCTION(0x1, "gpio_out"),
526 SUNXI_FUNCTION(0x2, "ts0"), /* D4 */
527 SUNXI_FUNCTION(0x3, "csi0"), /* D4 */
528 SUNXI_FUNCTION(0x4, "mmc2")), /* CMD */
529 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9),
530 SUNXI_FUNCTION(0x0, "gpio_in"),
531 SUNXI_FUNCTION(0x1, "gpio_out"),
532 SUNXI_FUNCTION(0x2, "ts0"), /* D5 */
533 SUNXI_FUNCTION(0x3, "csi0"), /* D5 */
534 SUNXI_FUNCTION(0x4, "mmc2")), /* CLK */
535 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10),
536 SUNXI_FUNCTION(0x0, "gpio_in"),
537 SUNXI_FUNCTION(0x1, "gpio_out"),
538 SUNXI_FUNCTION(0x2, "ts0"), /* D6 */
539 SUNXI_FUNCTION(0x3, "csi0"), /* D6 */
540 SUNXI_FUNCTION(0x4, "uart1")), /* TX */
541 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11),
542 SUNXI_FUNCTION(0x0, "gpio_in"),
543 SUNXI_FUNCTION(0x1, "gpio_out"),
544 SUNXI_FUNCTION(0x2, "ts0"), /* D7 */
545 SUNXI_FUNCTION(0x3, "csi0"), /* D7 */
546 SUNXI_FUNCTION(0x4, "uart1")), /* RX */
547 /* Hole */
548 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
549 SUNXI_FUNCTION(0x0, "gpio_in"),
550 SUNXI_FUNCTION(0x1, "gpio_out"),
551 SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */
552 SUNXI_FUNCTION(0x4, "jtag")), /* MS1 */
553 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1),
554 SUNXI_FUNCTION(0x0, "gpio_in"),
555 SUNXI_FUNCTION(0x1, "gpio_out"),
556 SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */
557 SUNXI_FUNCTION(0x4, "jtag")), /* DI1 */
558 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2),
559 SUNXI_FUNCTION(0x0, "gpio_in"),
560 SUNXI_FUNCTION(0x1, "gpio_out"),
561 SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */
562 SUNXI_FUNCTION(0x4, "uart0")), /* TX */
563 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3),
564 SUNXI_FUNCTION(0x0, "gpio_in"),
565 SUNXI_FUNCTION(0x1, "gpio_out"),
566 SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */
567 SUNXI_FUNCTION(0x4, "jtag")), /* DO1 */
568 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4),
569 SUNXI_FUNCTION(0x0, "gpio_in"),
570 SUNXI_FUNCTION(0x1, "gpio_out"),
571 SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */
572 SUNXI_FUNCTION(0x4, "uart0")), /* RX */
573 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
574 SUNXI_FUNCTION(0x0, "gpio_in"),
575 SUNXI_FUNCTION(0x1, "gpio_out"),
576 SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */
577 SUNXI_FUNCTION(0x4, "jtag")), /* CK1 */
578 /* Hole */
579 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0),
580 SUNXI_FUNCTION(0x0, "gpio_in"),
581 SUNXI_FUNCTION(0x2, "gps"), /* CLK */
582 SUNXI_FUNCTION_IRQ(0x6, 0)), /* EINT0 */
583 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1),
584 SUNXI_FUNCTION(0x0, "gpio_in"),
585 SUNXI_FUNCTION(0x2, "gps"), /* SIGN */
586 SUNXI_FUNCTION_IRQ(0x6, 1)), /* EINT1 */
587 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2),
588 SUNXI_FUNCTION(0x0, "gpio_in"),
589 SUNXI_FUNCTION(0x2, "gps"), /* MAG */
590 SUNXI_FUNCTION_IRQ(0x6, 2)), /* EINT2 */
591 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3),
592 SUNXI_FUNCTION(0x0, "gpio_in"),
593 SUNXI_FUNCTION(0x1, "gpio_out"),
594 SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */
595 SUNXI_FUNCTION(0x4, "uart1"), /* TX */
596 SUNXI_FUNCTION_IRQ(0x6, 3)), /* EINT3 */
597 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4),
598 SUNXI_FUNCTION(0x0, "gpio_in"),
599 SUNXI_FUNCTION(0x1, "gpio_out"),
600 SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */
601 SUNXI_FUNCTION(0x4, "uart1"), /* RX */
602 SUNXI_FUNCTION_IRQ(0x6, 4)), /* EINT4 */
603 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5),
604 SUNXI_FUNCTION(0x0, "gpio_in"),
605 SUNXI_FUNCTION(0x1, "gpio_out"),
606 SUNXI_FUNCTION(0x2, "mmc1"), /* DO */
607 SUNXI_FUNCTION(0x4, "uart1"), /* CTS */
608 SUNXI_FUNCTION_IRQ(0x6, 5)), /* EINT5 */
609 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6),
610 SUNXI_FUNCTION(0x0, "gpio_in"),
611 SUNXI_FUNCTION(0x1, "gpio_out"),
612 SUNXI_FUNCTION(0x2, "mmc1"), /* D1 */
613 SUNXI_FUNCTION(0x4, "uart1"), /* RTS */
614 SUNXI_FUNCTION(0x5, "uart2"), /* RTS */
615 SUNXI_FUNCTION_IRQ(0x6, 6)), /* EINT6 */
616 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7),
617 SUNXI_FUNCTION(0x0, "gpio_in"),
618 SUNXI_FUNCTION(0x1, "gpio_out"),
619 SUNXI_FUNCTION(0x2, "mmc1"), /* D2 */
620 SUNXI_FUNCTION(0x5, "uart2"), /* TX */
621 SUNXI_FUNCTION_IRQ(0x6, 7)), /* EINT7 */
622 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8),
623 SUNXI_FUNCTION(0x0, "gpio_in"),
624 SUNXI_FUNCTION(0x1, "gpio_out"),
625 SUNXI_FUNCTION(0x2, "mmc1"), /* D3 */
626 SUNXI_FUNCTION(0x5, "uart2"), /* RX */
627 SUNXI_FUNCTION_IRQ(0x6, 8)), /* EINT8 */
628 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9),
629 SUNXI_FUNCTION(0x0, "gpio_in"),
630 SUNXI_FUNCTION(0x1, "gpio_out"),
631 SUNXI_FUNCTION(0x2, "spi1"), /* CS0 */
632 SUNXI_FUNCTION(0x3, "uart3"), /* TX */
633 SUNXI_FUNCTION_IRQ(0x6, 9)), /* EINT9 */
634 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10),
635 SUNXI_FUNCTION(0x0, "gpio_in"),
636 SUNXI_FUNCTION(0x1, "gpio_out"),
637 SUNXI_FUNCTION(0x2, "spi1"), /* CLK */
638 SUNXI_FUNCTION(0x3, "uart3"), /* RX */
639 SUNXI_FUNCTION_IRQ(0x6, 10)), /* EINT10 */
640 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11),
641 SUNXI_FUNCTION(0x0, "gpio_in"),
642 SUNXI_FUNCTION(0x1, "gpio_out"),
643 SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */
644 SUNXI_FUNCTION(0x3, "uart3"), /* CTS */
645 SUNXI_FUNCTION_IRQ(0x6, 11)), /* EINT11 */
646 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12),
647 SUNXI_FUNCTION(0x0, "gpio_in"),
648 SUNXI_FUNCTION(0x1, "gpio_out"),
649 SUNXI_FUNCTION(0x2, "spi1"), /* MISO */
650 SUNXI_FUNCTION(0x3, "uart3"), /* RTS */
651 SUNXI_FUNCTION_IRQ(0x6, 12)), /* EINT12 */
652 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13),
653 SUNXI_FUNCTION(0x0, "gpio_in"),
654 SUNXI_FUNCTION(0x1, "gpio_out"),
655 SUNXI_FUNCTION(0x2, "spi1"), /* CS1 */
Hans de Goeded50a9e12015-09-19 17:56:44 -0400[diff] [blame]656 SUNXI_FUNCTION(0x3, "pwm"), /* PWM1 */
Maxime Ripard0a127c12014-04-18 20:12:50 +0200[diff] [blame]657 SUNXI_FUNCTION(0x5, "uart2"), /* CTS */
658 SUNXI_FUNCTION_IRQ(0x6, 13)), /* EINT13 */
659};
660
661static const struct sunxi_pinctrl_desc sun5i_a10s_pinctrl_data = {
662 .pins = sun5i_a10s_pins,
663 .npins = ARRAY_SIZE(sun5i_a10s_pins),
Maxime Ripard8966ada2014-06-05 15:26:02 +0200[diff] [blame]664 .irq_banks = 1,
Maxime Ripard0a127c12014-04-18 20:12:50 +0200[diff] [blame]665};
666
667static int sun5i_a10s_pinctrl_probe(struct platform_device *pdev)
668{
669 return sunxi_pinctrl_init(pdev,
670 &sun5i_a10s_pinctrl_data);
671}
672
Fabian Frederickbaa9946e2015-03-16 20:59:09 +0100[diff] [blame]673static const struct of_device_id sun5i_a10s_pinctrl_match[] = {
Maxime Ripard0a127c12014-04-18 20:12:50 +0200[diff] [blame]674 { .compatible = "allwinner,sun5i-a10s-pinctrl", },
675 {}
676};
677MODULE_DEVICE_TABLE(of, sun5i_a10s_pinctrl_match);
678
679static struct platform_driver sun5i_a10s_pinctrl_driver = {
680 .probe = sun5i_a10s_pinctrl_probe,
681 .driver = {
682 .name = "sun5i-a10s-pinctrl",
Maxime Ripard0a127c12014-04-18 20:12:50 +0200[diff] [blame]683 .of_match_table = sun5i_a10s_pinctrl_match,
684 },
685};
686module_platform_driver(sun5i_a10s_pinctrl_driver);
687
688MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com");
689MODULE_DESCRIPTION("Allwinner A10s pinctrl driver");
690MODULE_LICENSE("GPL");