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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * linux/arch/arm/mach-pxa/pxa25x.c
3 *
4 * Author: Nicolas Pitre
5 * Created: Jun 15, 2001
6 * Copyright: MontaVista Software Inc.
7 *
8 * Code specific to PXA21x/25x/26x variants.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 *
14 * Since this file should be linked before any other machine specific file,
15 * the __initcall() here will be executed first. This serves as default
16 * initialization stuff for PXA machines which can be overridden later if
17 * need be.
18 */
19#include <linux/module.h>
20#include <linux/kernel.h>
21#include <linux/init.h>
Russell King34f32312007-05-15 10:39:49 +010022#include <linux/platform_device.h>
Rafael J. Wysocki95d9ffb2007-10-18 03:04:39 -070023#include <linux/suspend.h>
eric miaoc01655042008-01-28 23:00:02 +000024#include <linux/sysdev.h>
Lennert Buytenheka3f4c922010-11-29 11:18:26 +010025#include <linux/irq.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070026
Marek Vasut851982c2010-10-11 02:20:19 +020027#include <asm/mach/map.h>
Russell Kinga09e64f2008-08-05 16:14:15 +010028#include <mach/hardware.h>
29#include <mach/irqs.h>
Eric Miaoa58fbcd2009-01-06 17:37:37 +080030#include <mach/gpio.h>
Eric Miao51c62982009-01-02 23:17:22 +080031#include <mach/pxa25x.h>
Russell Kingafd2fc02008-08-07 11:05:25 +010032#include <mach/reset.h>
Russell Kinga09e64f2008-08-05 16:14:15 +010033#include <mach/pm.h>
34#include <mach/dma.h>
Marek Vasutad68bb92010-11-03 16:29:35 +010035#include <mach/smemc.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070036
37#include "generic.h"
Russell King46c41e62007-05-15 15:39:36 +010038#include "devices.h"
Russell Kinga6dba202007-08-20 10:18:02 +010039#include "clock.h"
Linus Torvalds1da177e2005-04-16 15:20:36 -070040
41/*
42 * Various clock factors driven by the CCCR register.
43 */
44
45/* Crystal Frequency to Memory Frequency Multiplier (L) */
46static unsigned char L_clk_mult[32] = { 0, 27, 32, 36, 40, 45, 0, };
47
48/* Memory Frequency to Run Mode Frequency Multiplier (M) */
49static unsigned char M_clk_mult[4] = { 0, 1, 2, 4 };
50
51/* Run Mode Frequency to Turbo Mode Frequency Multiplier (N) */
52/* Note: we store the value N * 2 here. */
53static unsigned char N2_clk_mult[8] = { 0, 0, 2, 3, 4, 0, 6, 0 };
54
55/* Crystal clock */
56#define BASE_CLK 3686400
57
58/*
59 * Get the clock frequency as reflected by CCCR and the turbo flag.
60 * We assume these values have been applied via a fcs.
61 * If info is not 0 we also display the current settings.
62 */
Russell King15a40332007-08-20 10:07:44 +010063unsigned int pxa25x_get_clk_frequency_khz(int info)
Linus Torvalds1da177e2005-04-16 15:20:36 -070064{
65 unsigned long cccr, turbo;
66 unsigned int l, L, m, M, n2, N;
67
68 cccr = CCCR;
69 asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (turbo) );
70
71 l = L_clk_mult[(cccr >> 0) & 0x1f];
72 m = M_clk_mult[(cccr >> 5) & 0x03];
73 n2 = N2_clk_mult[(cccr >> 7) & 0x07];
74
75 L = l * BASE_CLK;
76 M = m * L;
77 N = n2 * M / 2;
78
79 if(info)
80 {
81 L += 5000;
82 printk( KERN_INFO "Memory clock: %d.%02dMHz (*%d)\n",
83 L / 1000000, (L % 1000000) / 10000, l );
84 M += 5000;
85 printk( KERN_INFO "Run Mode clock: %d.%02dMHz (*%d)\n",
86 M / 1000000, (M % 1000000) / 10000, m );
87 N += 5000;
88 printk( KERN_INFO "Turbo Mode clock: %d.%02dMHz (*%d.%d, %sactive)\n",
89 N / 1000000, (N % 1000000) / 10000, n2 / 2, (n2 % 2) * 5,
90 (turbo & 1) ? "" : "in" );
91 }
92
93 return (turbo & 1) ? (N/1000) : (M/1000);
94}
95
Eric Miao2a125dd2010-11-22 22:48:49 +080096static unsigned long clk_pxa25x_mem_getrate(struct clk *clk)
Linus Torvalds1da177e2005-04-16 15:20:36 -070097{
Eric Miao2a125dd2010-11-22 22:48:49 +080098 return L_clk_mult[(CCCR >> 0) & 0x1f] * BASE_CLK;
Linus Torvalds1da177e2005-04-16 15:20:36 -070099}
100
Eric Miao2a125dd2010-11-22 22:48:49 +0800101static const struct clkops clk_pxa25x_mem_ops = {
102 .enable = clk_dummy_enable,
103 .disable = clk_dummy_disable,
104 .getrate = clk_pxa25x_mem_getrate,
105};
Russell Kinga6dba202007-08-20 10:18:02 +0100106
107static const struct clkops clk_pxa25x_lcd_ops = {
Eric Miao40298132010-11-22 10:49:55 +0800108 .enable = clk_pxa2xx_cken_enable,
109 .disable = clk_pxa2xx_cken_disable,
Eric Miao2a125dd2010-11-22 22:48:49 +0800110 .getrate = clk_pxa25x_mem_getrate,
Russell Kinga6dba202007-08-20 10:18:02 +0100111};
112
Ian Moltoned847782008-07-08 10:32:08 +0100113static unsigned long gpio12_config_32k[] = {
114 GPIO12_32KHz,
115};
116
117static unsigned long gpio12_config_gpio[] = {
118 GPIO12_GPIO,
119};
120
121static void clk_gpio12_enable(struct clk *clk)
122{
123 pxa2xx_mfp_config(gpio12_config_32k, 1);
124}
125
126static void clk_gpio12_disable(struct clk *clk)
127{
128 pxa2xx_mfp_config(gpio12_config_gpio, 1);
129}
130
131static const struct clkops clk_pxa25x_gpio12_ops = {
132 .enable = clk_gpio12_enable,
133 .disable = clk_gpio12_disable,
134};
135
Ian Molton13f75582008-07-08 10:32:50 +0100136static unsigned long gpio11_config_3m6[] = {
137 GPIO11_3_6MHz,
138};
139
140static unsigned long gpio11_config_gpio[] = {
141 GPIO11_GPIO,
142};
143
144static void clk_gpio11_enable(struct clk *clk)
145{
146 pxa2xx_mfp_config(gpio11_config_3m6, 1);
147}
148
149static void clk_gpio11_disable(struct clk *clk)
150{
151 pxa2xx_mfp_config(gpio11_config_gpio, 1);
152}
153
154static const struct clkops clk_pxa25x_gpio11_ops = {
155 .enable = clk_gpio11_enable,
156 .disable = clk_gpio11_disable,
157};
158
Russell Kinga6dba202007-08-20 10:18:02 +0100159/*
160 * 3.6864MHz -> OST, GPIO, SSP, PWM, PLLs (95.842MHz, 147.456MHz)
161 * 95.842MHz -> MMC 19.169MHz, I2C 31.949MHz, FICP 47.923MHz, USB 47.923MHz
162 * 147.456MHz -> UART 14.7456MHz, AC97 12.288MHz, I2S 5.672MHz (allegedly)
163 */
Dmitry Baryshkove01dbdb2008-01-27 23:11:48 +0100164
Russell Kingbdb08cb2008-06-30 19:47:59 +0100165/*
Ian Moltonc1ed4062008-07-26 00:52:36 +0100166 * PXA 2xx clock declarations.
Russell Kingbdb08cb2008-06-30 19:47:59 +0100167 */
Eric Miao40298132010-11-22 10:49:55 +0800168static DEFINE_PXA2_CKEN(pxa25x_hwuart, HWUART, 14745600, 1);
169static DEFINE_PXA2_CKEN(pxa25x_ffuart, FFUART, 14745600, 1);
170static DEFINE_PXA2_CKEN(pxa25x_btuart, BTUART, 14745600, 1);
171static DEFINE_PXA2_CKEN(pxa25x_stuart, STUART, 14745600, 1);
172static DEFINE_PXA2_CKEN(pxa25x_usb, USB, 47923000, 5);
173static DEFINE_PXA2_CKEN(pxa25x_mmc, MMC, 19169000, 0);
174static DEFINE_PXA2_CKEN(pxa25x_i2c, I2C, 31949000, 0);
175static DEFINE_PXA2_CKEN(pxa25x_ssp, SSP, 3686400, 0);
176static DEFINE_PXA2_CKEN(pxa25x_nssp, NSSP, 3686400, 0);
177static DEFINE_PXA2_CKEN(pxa25x_assp, ASSP, 3686400, 0);
178static DEFINE_PXA2_CKEN(pxa25x_pwm0, PWM0, 3686400, 0);
179static DEFINE_PXA2_CKEN(pxa25x_pwm1, PWM1, 3686400, 0);
180static DEFINE_PXA2_CKEN(pxa25x_ac97, AC97, 24576000, 0);
181static DEFINE_PXA2_CKEN(pxa25x_i2s, I2S, 14745600, 0);
182static DEFINE_PXA2_CKEN(pxa25x_ficp, FICP, 47923000, 0);
183
Russell King8c3abc72008-11-08 20:25:21 +0000184static DEFINE_CK(pxa25x_lcd, LCD, &clk_pxa25x_lcd_ops);
Russell King8c3abc72008-11-08 20:25:21 +0000185static DEFINE_CLK(pxa25x_gpio11, &clk_pxa25x_gpio11_ops, 3686400, 0);
186static DEFINE_CLK(pxa25x_gpio12, &clk_pxa25x_gpio12_ops, 32768, 0);
Eric Miao2a125dd2010-11-22 22:48:49 +0800187static DEFINE_CLK(pxa25x_mem, &clk_pxa25x_mem_ops, 0, 0);
eric miaod8e0db12007-12-10 17:54:36 +0800188
Russell King8c3abc72008-11-08 20:25:21 +0000189static struct clk_lookup pxa25x_clkregs[] = {
190 INIT_CLKREG(&clk_pxa25x_lcd, "pxa2xx-fb", NULL),
191 INIT_CLKREG(&clk_pxa25x_ffuart, "pxa2xx-uart.0", NULL),
192 INIT_CLKREG(&clk_pxa25x_btuart, "pxa2xx-uart.1", NULL),
193 INIT_CLKREG(&clk_pxa25x_stuart, "pxa2xx-uart.2", NULL),
194 INIT_CLKREG(&clk_pxa25x_usb, "pxa25x-udc", NULL),
195 INIT_CLKREG(&clk_pxa25x_mmc, "pxa2xx-mci.0", NULL),
196 INIT_CLKREG(&clk_pxa25x_i2c, "pxa2xx-i2c.0", NULL),
197 INIT_CLKREG(&clk_pxa25x_ssp, "pxa25x-ssp.0", NULL),
198 INIT_CLKREG(&clk_pxa25x_nssp, "pxa25x-nssp.1", NULL),
199 INIT_CLKREG(&clk_pxa25x_assp, "pxa25x-nssp.2", NULL),
200 INIT_CLKREG(&clk_pxa25x_pwm0, "pxa25x-pwm.0", NULL),
201 INIT_CLKREG(&clk_pxa25x_pwm1, "pxa25x-pwm.1", NULL),
202 INIT_CLKREG(&clk_pxa25x_i2s, "pxa2xx-i2s", NULL),
203 INIT_CLKREG(&clk_pxa25x_stuart, "pxa2xx-ir", "UARTCLK"),
204 INIT_CLKREG(&clk_pxa25x_ficp, "pxa2xx-ir", "FICPCLK"),
205 INIT_CLKREG(&clk_pxa25x_ac97, NULL, "AC97CLK"),
206 INIT_CLKREG(&clk_pxa25x_gpio11, NULL, "GPIO11_CLK"),
207 INIT_CLKREG(&clk_pxa25x_gpio12, NULL, "GPIO12_CLK"),
Eric Miao2a125dd2010-11-22 22:48:49 +0800208 INIT_CLKREG(&clk_pxa25x_mem, "pxa2xx-pcmcia", NULL),
Russell Kinga6dba202007-08-20 10:18:02 +0100209};
210
Eric Miao40298132010-11-22 10:49:55 +0800211static struct clk_lookup pxa25x_hwuart_clkreg =
212 INIT_CLKREG(&clk_pxa25x_hwuart, "pxa2xx-uart.3", NULL);
213
Nicolas Pitrea8fa3f02005-06-13 22:35:41 +0100214#ifdef CONFIG_PM
Todd Poynor87754202005-06-03 20:52:27 +0100215
Eric Miao711be5c2007-07-18 11:38:45 +0100216#define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x
217#define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x]
218
Eric Miao711be5c2007-07-18 11:38:45 +0100219/*
220 * List of global PXA peripheral registers to preserve.
221 * More ones like CP and general purpose register values are preserved
222 * with the stack pointer in sleep.S.
223 */
Eric Miao5a3d9652008-09-03 18:06:34 +0800224enum {
Eric Miao711be5c2007-07-18 11:38:45 +0100225 SLEEP_SAVE_PSTR,
Robert Jarzmik649de512008-05-02 21:17:06 +0100226 SLEEP_SAVE_COUNT
Eric Miao711be5c2007-07-18 11:38:45 +0100227};
228
229
230static void pxa25x_cpu_pm_save(unsigned long *sleep_save)
231{
Eric Miao711be5c2007-07-18 11:38:45 +0100232 SAVE(PSTR);
233}
234
235static void pxa25x_cpu_pm_restore(unsigned long *sleep_save)
236{
Eric Miao711be5c2007-07-18 11:38:45 +0100237 RESTORE(PSTR);
238}
239
240static void pxa25x_cpu_pm_enter(suspend_state_t state)
Todd Poynor87754202005-06-03 20:52:27 +0100241{
Russell Kingdc38e2a2008-05-08 16:50:39 +0100242 /* Clear reset status */
243 RCSR = RCSR_HWR | RCSR_WDR | RCSR_SMR | RCSR_GPR;
244
Todd Poynor87754202005-06-03 20:52:27 +0100245 switch (state) {
246 case PM_SUSPEND_MEM:
Eric Miaob750a092007-07-18 11:40:13 +0100247 pxa25x_cpu_suspend(PWRMODE_SLEEP);
Todd Poynor87754202005-06-03 20:52:27 +0100248 break;
249 }
250}
Nicolas Pitrea8fa3f02005-06-13 22:35:41 +0100251
Russell King41049802008-08-27 12:55:04 +0100252static int pxa25x_cpu_pm_prepare(void)
253{
254 /* set resume return address */
255 PSPR = virt_to_phys(pxa_cpu_resume);
256 return 0;
257}
258
259static void pxa25x_cpu_pm_finish(void)
260{
261 /* ensure not to come back here if it wasn't intended */
262 PSPR = 0;
263}
264
Eric Miao711be5c2007-07-18 11:38:45 +0100265static struct pxa_cpu_pm_fns pxa25x_cpu_pm_fns = {
Robert Jarzmik649de512008-05-02 21:17:06 +0100266 .save_count = SLEEP_SAVE_COUNT,
Rafael J. Wysocki26398a72007-10-18 03:04:40 -0700267 .valid = suspend_valid_only_mem,
Eric Miao711be5c2007-07-18 11:38:45 +0100268 .save = pxa25x_cpu_pm_save,
269 .restore = pxa25x_cpu_pm_restore,
270 .enter = pxa25x_cpu_pm_enter,
Russell King41049802008-08-27 12:55:04 +0100271 .prepare = pxa25x_cpu_pm_prepare,
272 .finish = pxa25x_cpu_pm_finish,
Russell Kinge176bb02007-05-15 11:16:10 +0100273};
Eric Miao711be5c2007-07-18 11:38:45 +0100274
275static void __init pxa25x_init_pm(void)
276{
277 pxa_cpu_pm_fns = &pxa25x_cpu_pm_fns;
278}
eric miaof79299c2008-01-02 08:24:49 +0800279#else
280static inline void pxa25x_init_pm(void) {}
Nicolas Pitrea8fa3f02005-06-13 22:35:41 +0100281#endif
Russell Kinge176bb02007-05-15 11:16:10 +0100282
eric miaoc95530c2007-08-29 10:22:17 +0100283/* PXA25x: supports wakeup from GPIO0..GPIO15 and RTC alarm
284 */
285
Lennert Buytenheka3f4c922010-11-29 11:18:26 +0100286static int pxa25x_set_wake(struct irq_data *d, unsigned int on)
eric miaoc95530c2007-08-29 10:22:17 +0100287{
Lennert Buytenheka3f4c922010-11-29 11:18:26 +0100288 int gpio = IRQ_TO_GPIO(d->irq);
eric miaoc0a596d2008-03-11 09:46:28 +0800289 uint32_t mask = 0;
eric miaoc95530c2007-08-29 10:22:17 +0100290
eric miaoc0a596d2008-03-11 09:46:28 +0800291 if (gpio >= 0 && gpio < 85)
292 return gpio_set_wake(gpio, on);
eric miaoc95530c2007-08-29 10:22:17 +0100293
Lennert Buytenheka3f4c922010-11-29 11:18:26 +0100294 if (d->irq == IRQ_RTCAlrm) {
eric miaoc95530c2007-08-29 10:22:17 +0100295 mask = PWER_RTC;
296 goto set_pwer;
297 }
298
299 return -EINVAL;
300
301set_pwer:
302 if (on)
303 PWER |= mask;
304 else
305 PWER &=~mask;
306
307 return 0;
308}
309
Eric Miaocd491042007-06-22 04:14:09 +0100310void __init pxa25x_init_irq(void)
311{
eric miaob9e25ac2008-03-04 14:19:58 +0800312 pxa_init_irq(32, pxa25x_set_wake);
Eric Miaoa58fbcd2009-01-06 17:37:37 +0800313 pxa_init_gpio(IRQ_GPIO_2_x, 2, 84, pxa25x_set_wake);
Eric Miaocd491042007-06-22 04:14:09 +0100314}
315
Eric Miao067455a2008-11-26 18:12:04 +0800316#ifdef CONFIG_CPU_PXA26x
317void __init pxa26x_init_irq(void)
318{
319 pxa_init_irq(32, pxa25x_set_wake);
Eric Miaoa58fbcd2009-01-06 17:37:37 +0800320 pxa_init_gpio(IRQ_GPIO_2_x, 2, 89, pxa25x_set_wake);
Eric Miao067455a2008-11-26 18:12:04 +0800321}
322#endif
323
Marek Vasut851982c2010-10-11 02:20:19 +0200324static struct map_desc pxa25x_io_desc[] __initdata = {
325 { /* Mem Ctl */
Marek Vasutad68bb92010-11-03 16:29:35 +0100326 .virtual = SMEMC_VIRT,
327 .pfn = __phys_to_pfn(PXA2XX_SMEMC_BASE),
Marek Vasut851982c2010-10-11 02:20:19 +0200328 .length = 0x00200000,
329 .type = MT_DEVICE
330 },
331};
332
333void __init pxa25x_map_io(void)
334{
335 pxa_map_io();
336 iotable_init(ARRAY_AND_SIZE(pxa25x_io_desc));
337 pxa25x_get_clk_frequency_khz(1);
338}
339
Russell King34f32312007-05-15 10:39:49 +0100340static struct platform_device *pxa25x_devices[] __initdata = {
Philipp Zabel7a857622008-06-22 23:36:39 +0100341 &pxa25x_device_udc,
Eric Miao09a53582010-06-14 00:43:00 +0800342 &pxa_device_pmu,
Eric Miaoe09d02e2007-07-17 10:45:58 +0100343 &pxa_device_i2s,
Robert Jarzmik72493142008-11-13 23:50:56 +0100344 &sa1100_device_rtc,
eric miaod8e0db12007-12-10 17:54:36 +0800345 &pxa25x_device_ssp,
346 &pxa25x_device_nssp,
347 &pxa25x_device_assp,
eric miao75540c12008-04-13 21:44:04 +0100348 &pxa25x_device_pwm0,
349 &pxa25x_device_pwm1,
Russell King34f32312007-05-15 10:39:49 +0100350};
351
eric miaoc01655042008-01-28 23:00:02 +0000352static struct sys_device pxa25x_sysdev[] = {
353 {
354 .cls = &pxa_irq_sysclass,
eric miao16dfdbf2008-01-28 23:00:02 +0000355 }, {
Eric Miao5a3d9652008-09-03 18:06:34 +0800356 .cls = &pxa2xx_mfp_sysclass,
357 }, {
eric miao16dfdbf2008-01-28 23:00:02 +0000358 .cls = &pxa_gpio_sysclass,
Eric Miaof113fe42010-11-23 17:00:03 +0800359 }, {
360 .cls = &pxa2xx_clock_sysclass,
361 }
eric miaoc01655042008-01-28 23:00:02 +0000362};
363
Russell Kinge176bb02007-05-15 11:16:10 +0100364static int __init pxa25x_init(void)
365{
eric miaoc01655042008-01-28 23:00:02 +0000366 int i, ret = 0;
Eric Miaof53f0662007-06-22 05:40:17 +0100367
Eric Miao0ffcbfd2008-09-11 10:27:30 +0800368 if (cpu_is_pxa25x()) {
Eric Miao04fef222008-07-29 14:26:00 +0800369
370 reset_status = RCSR;
371
Russell King0a0300d2010-01-12 12:28:00 +0000372 clkdev_add_table(pxa25x_clkregs, ARRAY_SIZE(pxa25x_clkregs));
Russell Kinga6dba202007-08-20 10:18:02 +0100373
Eric Miaofef1f992009-01-02 16:26:33 +0800374 if ((ret = pxa_init_dma(IRQ_DMA, 16)))
Eric Miaof53f0662007-06-22 05:40:17 +0100375 return ret;
eric miaof79299c2008-01-02 08:24:49 +0800376
Eric Miao711be5c2007-07-18 11:38:45 +0100377 pxa25x_init_pm();
eric miaof79299c2008-01-02 08:24:49 +0800378
eric miaoc01655042008-01-28 23:00:02 +0000379 for (i = 0; i < ARRAY_SIZE(pxa25x_sysdev); i++) {
380 ret = sysdev_register(&pxa25x_sysdev[i]);
381 if (ret)
382 pr_err("failed to register sysdev[%d]\n", i);
383 }
384
Russell King34f32312007-05-15 10:39:49 +0100385 ret = platform_add_devices(pxa25x_devices,
386 ARRAY_SIZE(pxa25x_devices));
eric miaoc01655042008-01-28 23:00:02 +0000387 if (ret)
388 return ret;
Russell Kinge176bb02007-05-15 11:16:10 +0100389 }
eric miaoc01655042008-01-28 23:00:02 +0000390
Eric Miao2b127972008-09-11 10:25:59 +0800391 /* Only add HWUART for PXA255/26x; PXA210/250 do not have it. */
Russell Kingcc155c62009-11-09 13:34:08 +0800392 if (cpu_is_pxa255())
Russell King0a0300d2010-01-12 12:28:00 +0000393 clkdev_add(&pxa25x_hwuart_clkreg);
Russell King34f32312007-05-15 10:39:49 +0100394
395 return ret;
Russell Kinge176bb02007-05-15 11:16:10 +0100396}
397
Russell King1c104e02008-04-19 10:59:24 +0100398postcore_initcall(pxa25x_init);