| Kevin Wells | 437db59 | 2010-02-26 15:53:38 -0800 | [diff] [blame] | 1 | /* |
| 2 | * arch/arm/mach-lpc32xx/include/mach/platform.h |
| 3 | * |
| 4 | * Author: Kevin Wells <kevin.wells@nxp.com> |
| 5 | * |
| 6 | * Copyright (C) 2010 NXP Semiconductors |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; either version 2 of the License, or |
| 11 | * (at your option) any later version. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | */ |
| 18 | |
| 19 | #ifndef __ASM_ARCH_PLATFORM_H |
| 20 | #define __ASM_ARCH_PLATFORM_H |
| 21 | |
| 22 | #define _SBF(f, v) ((v) << (f)) |
| 23 | #define _BIT(n) _SBF(n, 1) |
| 24 | |
| 25 | /* |
| 26 | * AHB 0 physical base addresses |
| 27 | */ |
| 28 | #define LPC32XX_SLC_BASE 0x20020000 |
| 29 | #define LPC32XX_SSP0_BASE 0x20084000 |
| 30 | #define LPC32XX_SPI1_BASE 0x20088000 |
| 31 | #define LPC32XX_SSP1_BASE 0x2008C000 |
| 32 | #define LPC32XX_SPI2_BASE 0x20090000 |
| 33 | #define LPC32XX_I2S0_BASE 0x20094000 |
| 34 | #define LPC32XX_SD_BASE 0x20098000 |
| 35 | #define LPC32XX_I2S1_BASE 0x2009C000 |
| 36 | #define LPC32XX_MLC_BASE 0x200A8000 |
| 37 | #define LPC32XX_AHB0_START LPC32XX_SLC_BASE |
| 38 | #define LPC32XX_AHB0_SIZE 0x00089000 |
| 39 | |
| 40 | /* |
| 41 | * AHB 1 physical base addresses |
| 42 | */ |
| 43 | #define LPC32XX_DMA_BASE 0x31000000 |
| 44 | #define LPC32XX_USB_BASE 0x31020000 |
| 45 | #define LPC32XX_USBH_BASE 0x31020000 |
| 46 | #define LPC32XX_USB_OTG_BASE 0x31020000 |
| 47 | #define LPC32XX_OTG_I2C_BASE 0x31020300 |
| 48 | #define LPC32XX_LCD_BASE 0x31040000 |
| 49 | #define LPC32XX_ETHERNET_BASE 0x31060000 |
| 50 | #define LPC32XX_EMC_BASE 0x31080000 |
| 51 | #define LPC32XX_ETB_CFG_BASE 0x310C0000 |
| 52 | #define LPC32XX_ETB_DATA_BASE 0x310E0000 |
| 53 | #define LPC32XX_AHB1_START LPC32XX_DMA_BASE |
| 54 | #define LPC32XX_AHB1_SIZE 0x000E1000 |
| 55 | |
| 56 | /* |
| 57 | * FAB physical base addresses |
| 58 | */ |
| 59 | #define LPC32XX_CLK_PM_BASE 0x40004000 |
| 60 | #define LPC32XX_MIC_BASE 0x40008000 |
| 61 | #define LPC32XX_SIC1_BASE 0x4000C000 |
| 62 | #define LPC32XX_SIC2_BASE 0x40010000 |
| 63 | #define LPC32XX_HS_UART1_BASE 0x40014000 |
| 64 | #define LPC32XX_HS_UART2_BASE 0x40018000 |
| 65 | #define LPC32XX_HS_UART7_BASE 0x4001C000 |
| 66 | #define LPC32XX_RTC_BASE 0x40024000 |
| 67 | #define LPC32XX_RTC_RAM_BASE 0x40024080 |
| 68 | #define LPC32XX_GPIO_BASE 0x40028000 |
| 69 | #define LPC32XX_PWM3_BASE 0x4002C000 |
| 70 | #define LPC32XX_PWM4_BASE 0x40030000 |
| 71 | #define LPC32XX_MSTIM_BASE 0x40034000 |
| 72 | #define LPC32XX_HSTIM_BASE 0x40038000 |
| 73 | #define LPC32XX_WDTIM_BASE 0x4003C000 |
| 74 | #define LPC32XX_DEBUG_CTRL_BASE 0x40040000 |
| 75 | #define LPC32XX_TIMER0_BASE 0x40044000 |
| 76 | #define LPC32XX_ADC_BASE 0x40048000 |
| 77 | #define LPC32XX_TIMER1_BASE 0x4004C000 |
| 78 | #define LPC32XX_KSCAN_BASE 0x40050000 |
| 79 | #define LPC32XX_UART_CTRL_BASE 0x40054000 |
| 80 | #define LPC32XX_TIMER2_BASE 0x40058000 |
| 81 | #define LPC32XX_PWM1_BASE 0x4005C000 |
| 82 | #define LPC32XX_PWM2_BASE 0x4005C004 |
| 83 | #define LPC32XX_TIMER3_BASE 0x40060000 |
| 84 | |
| 85 | /* |
| 86 | * APB physical base addresses |
| 87 | */ |
| 88 | #define LPC32XX_UART3_BASE 0x40080000 |
| 89 | #define LPC32XX_UART4_BASE 0x40088000 |
| 90 | #define LPC32XX_UART5_BASE 0x40090000 |
| 91 | #define LPC32XX_UART6_BASE 0x40098000 |
| 92 | #define LPC32XX_I2C1_BASE 0x400A0000 |
| 93 | #define LPC32XX_I2C2_BASE 0x400A8000 |
| 94 | |
| 95 | /* |
| 96 | * FAB and APB base and sizing |
| 97 | */ |
| 98 | #define LPC32XX_FABAPB_START LPC32XX_CLK_PM_BASE |
| 99 | #define LPC32XX_FABAPB_SIZE 0x000A5000 |
| 100 | |
| 101 | /* |
| 102 | * Internal memory bases and sizes |
| 103 | */ |
| 104 | #define LPC32XX_IRAM_BASE 0x08000000 |
| 105 | #define LPC32XX_IROM_BASE 0x0C000000 |
| 106 | |
| 107 | /* |
| 108 | * External Static Memory Bank Address Space Bases |
| 109 | */ |
| 110 | #define LPC32XX_EMC_CS0_BASE 0xE0000000 |
| 111 | #define LPC32XX_EMC_CS1_BASE 0xE1000000 |
| 112 | #define LPC32XX_EMC_CS2_BASE 0xE2000000 |
| 113 | #define LPC32XX_EMC_CS3_BASE 0xE3000000 |
| 114 | |
| 115 | /* |
| 116 | * External SDRAM Memory Bank Address Space Bases |
| 117 | */ |
| 118 | #define LPC32XX_EMC_DYCS0_BASE 0x80000000 |
| 119 | #define LPC32XX_EMC_DYCS1_BASE 0xA0000000 |
| 120 | |
| 121 | /* |
| 122 | * Clock and crystal information |
| 123 | */ |
| 124 | #define LPC32XX_MAIN_OSC_FREQ 13000000 |
| 125 | #define LPC32XX_CLOCK_OSC_FREQ 32768 |
| 126 | |
| 127 | /* |
| 128 | * Clock and Power control register offsets |
| 129 | */ |
| 130 | #define _PMREG(x) io_p2v(LPC32XX_CLK_PM_BASE +\ |
| 131 | (x)) |
| 132 | #define LPC32XX_CLKPWR_DEBUG_CTRL _PMREG(0x000) |
| 133 | #define LPC32XX_CLKPWR_BOOTMAP _PMREG(0x014) |
| 134 | #define LPC32XX_CLKPWR_P01_ER _PMREG(0x018) |
| 135 | #define LPC32XX_CLKPWR_USBCLK_PDIV _PMREG(0x01C) |
| 136 | #define LPC32XX_CLKPWR_INT_ER _PMREG(0x020) |
| 137 | #define LPC32XX_CLKPWR_INT_RS _PMREG(0x024) |
| 138 | #define LPC32XX_CLKPWR_INT_SR _PMREG(0x028) |
| 139 | #define LPC32XX_CLKPWR_INT_AP _PMREG(0x02C) |
| 140 | #define LPC32XX_CLKPWR_PIN_ER _PMREG(0x030) |
| 141 | #define LPC32XX_CLKPWR_PIN_RS _PMREG(0x034) |
| 142 | #define LPC32XX_CLKPWR_PIN_SR _PMREG(0x038) |
| 143 | #define LPC32XX_CLKPWR_PIN_AP _PMREG(0x03C) |
| 144 | #define LPC32XX_CLKPWR_HCLK_DIV _PMREG(0x040) |
| 145 | #define LPC32XX_CLKPWR_PWR_CTRL _PMREG(0x044) |
| 146 | #define LPC32XX_CLKPWR_PLL397_CTRL _PMREG(0x048) |
| 147 | #define LPC32XX_CLKPWR_MAIN_OSC_CTRL _PMREG(0x04C) |
| 148 | #define LPC32XX_CLKPWR_SYSCLK_CTRL _PMREG(0x050) |
| 149 | #define LPC32XX_CLKPWR_LCDCLK_CTRL _PMREG(0x054) |
| 150 | #define LPC32XX_CLKPWR_HCLKPLL_CTRL _PMREG(0x058) |
| 151 | #define LPC32XX_CLKPWR_ADC_CLK_CTRL_1 _PMREG(0x060) |
| 152 | #define LPC32XX_CLKPWR_USB_CTRL _PMREG(0x064) |
| 153 | #define LPC32XX_CLKPWR_SDRAMCLK_CTRL _PMREG(0x068) |
| 154 | #define LPC32XX_CLKPWR_DDR_LAP_NOM _PMREG(0x06C) |
| 155 | #define LPC32XX_CLKPWR_DDR_LAP_COUNT _PMREG(0x070) |
| 156 | #define LPC32XX_CLKPWR_DDR_LAP_DELAY _PMREG(0x074) |
| 157 | #define LPC32XX_CLKPWR_SSP_CLK_CTRL _PMREG(0x078) |
| 158 | #define LPC32XX_CLKPWR_I2S_CLK_CTRL _PMREG(0x07C) |
| 159 | #define LPC32XX_CLKPWR_MS_CTRL _PMREG(0x080) |
| 160 | #define LPC32XX_CLKPWR_MACCLK_CTRL _PMREG(0x090) |
| 161 | #define LPC32XX_CLKPWR_TEST_CLK_SEL _PMREG(0x0A4) |
| 162 | #define LPC32XX_CLKPWR_SFW_INT _PMREG(0x0A8) |
| 163 | #define LPC32XX_CLKPWR_I2C_CLK_CTRL _PMREG(0x0AC) |
| 164 | #define LPC32XX_CLKPWR_KEY_CLK_CTRL _PMREG(0x0B0) |
| 165 | #define LPC32XX_CLKPWR_ADC_CLK_CTRL _PMREG(0x0B4) |
| 166 | #define LPC32XX_CLKPWR_PWM_CLK_CTRL _PMREG(0x0B8) |
| 167 | #define LPC32XX_CLKPWR_TIMER_CLK_CTRL _PMREG(0x0BC) |
| 168 | #define LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1 _PMREG(0x0C0) |
| 169 | #define LPC32XX_CLKPWR_SPI_CLK_CTRL _PMREG(0x0C4) |
| 170 | #define LPC32XX_CLKPWR_NAND_CLK_CTRL _PMREG(0x0C8) |
| 171 | #define LPC32XX_CLKPWR_UART3_CLK_CTRL _PMREG(0x0D0) |
| 172 | #define LPC32XX_CLKPWR_UART4_CLK_CTRL _PMREG(0x0D4) |
| 173 | #define LPC32XX_CLKPWR_UART5_CLK_CTRL _PMREG(0x0D8) |
| 174 | #define LPC32XX_CLKPWR_UART6_CLK_CTRL _PMREG(0x0DC) |
| 175 | #define LPC32XX_CLKPWR_IRDA_CLK_CTRL _PMREG(0x0E0) |
| 176 | #define LPC32XX_CLKPWR_UART_CLK_CTRL _PMREG(0x0E4) |
| 177 | #define LPC32XX_CLKPWR_DMA_CLK_CTRL _PMREG(0x0E8) |
| 178 | #define LPC32XX_CLKPWR_AUTOCLOCK _PMREG(0x0EC) |
| 179 | #define LPC32XX_CLKPWR_DEVID(x) _PMREG(0x130 + (x)) |
| 180 | |
| 181 | /* |
| 182 | * clkpwr_debug_ctrl register definitions |
| 183 | */ |
| 184 | #define LPC32XX_CLKPWR_VFP_CLOCK_ENABLE_BIT _BIT(4) |
| 185 | |
| 186 | /* |
| 187 | * clkpwr_bootmap register definitions |
| 188 | */ |
| 189 | #define LPC32XX_CLKPWR_BOOTMAP_SEL_BIT _BIT(1) |
| 190 | |
| 191 | /* |
| 192 | * clkpwr_start_gpio register bit definitions |
| 193 | */ |
| 194 | #define LPC32XX_CLKPWR_GPIOSRC_P1IO23_BIT _BIT(31) |
| 195 | #define LPC32XX_CLKPWR_GPIOSRC_P1IO22_BIT _BIT(30) |
| 196 | #define LPC32XX_CLKPWR_GPIOSRC_P1IO21_BIT _BIT(29) |
| 197 | #define LPC32XX_CLKPWR_GPIOSRC_P1IO20_BIT _BIT(28) |
| 198 | #define LPC32XX_CLKPWR_GPIOSRC_P1IO19_BIT _BIT(27) |
| 199 | #define LPC32XX_CLKPWR_GPIOSRC_P1IO18_BIT _BIT(26) |
| 200 | #define LPC32XX_CLKPWR_GPIOSRC_P1IO17_BIT _BIT(25) |
| 201 | #define LPC32XX_CLKPWR_GPIOSRC_P1IO16_BIT _BIT(24) |
| 202 | #define LPC32XX_CLKPWR_GPIOSRC_P1IO15_BIT _BIT(23) |
| 203 | #define LPC32XX_CLKPWR_GPIOSRC_P1IO14_BIT _BIT(22) |
| 204 | #define LPC32XX_CLKPWR_GPIOSRC_P1IO13_BIT _BIT(21) |
| 205 | #define LPC32XX_CLKPWR_GPIOSRC_P1IO12_BIT _BIT(20) |
| 206 | #define LPC32XX_CLKPWR_GPIOSRC_P1IO11_BIT _BIT(19) |
| 207 | #define LPC32XX_CLKPWR_GPIOSRC_P1IO10_BIT _BIT(18) |
| 208 | #define LPC32XX_CLKPWR_GPIOSRC_P1IO9_BIT _BIT(17) |
| 209 | #define LPC32XX_CLKPWR_GPIOSRC_P1IO8_BIT _BIT(16) |
| 210 | #define LPC32XX_CLKPWR_GPIOSRC_P1IO7_BIT _BIT(15) |
| 211 | #define LPC32XX_CLKPWR_GPIOSRC_P1IO6_BIT _BIT(14) |
| 212 | #define LPC32XX_CLKPWR_GPIOSRC_P1IO5_BIT _BIT(13) |
| 213 | #define LPC32XX_CLKPWR_GPIOSRC_P1IO4_BIT _BIT(12) |
| 214 | #define LPC32XX_CLKPWR_GPIOSRC_P1IO3_BIT _BIT(11) |
| 215 | #define LPC32XX_CLKPWR_GPIOSRC_P1IO2_BIT _BIT(10) |
| 216 | #define LPC32XX_CLKPWR_GPIOSRC_P1IO1_BIT _BIT(9) |
| 217 | #define LPC32XX_CLKPWR_GPIOSRC_P1IO0_BIT _BIT(8) |
| 218 | #define LPC32XX_CLKPWR_GPIOSRC_P0IO7_BIT _BIT(7) |
| 219 | #define LPC32XX_CLKPWR_GPIOSRC_P0IO6_BIT _BIT(6) |
| 220 | #define LPC32XX_CLKPWR_GPIOSRC_P0IO5_BIT _BIT(5) |
| 221 | #define LPC32XX_CLKPWR_GPIOSRC_P0IO4_BIT _BIT(4) |
| 222 | #define LPC32XX_CLKPWR_GPIOSRC_P0IO3_BIT _BIT(3) |
| 223 | #define LPC32XX_CLKPWR_GPIOSRC_P0IO2_BIT _BIT(2) |
| 224 | #define LPC32XX_CLKPWR_GPIOSRC_P0IO1_BIT _BIT(1) |
| 225 | #define LPC32XX_CLKPWR_GPIOSRC_P0IO0_BIT _BIT(0) |
| 226 | |
| 227 | /* |
| 228 | * clkpwr_usbclk_pdiv register definitions |
| 229 | */ |
| 230 | #define LPC32XX_CLKPWR_USBPDIV_PLL_MASK 0xF |
| 231 | |
| 232 | /* |
| 233 | * clkpwr_start_int, clkpwr_start_raw_sts_int, clkpwr_start_sts_int, |
| 234 | * clkpwr_start_pol_int, register bit definitions |
| 235 | */ |
| 236 | #define LPC32XX_CLKPWR_INTSRC_ADC_BIT _BIT(31) |
| 237 | #define LPC32XX_CLKPWR_INTSRC_TS_P_BIT _BIT(30) |
| 238 | #define LPC32XX_CLKPWR_INTSRC_TS_AUX_BIT _BIT(29) |
| 239 | #define LPC32XX_CLKPWR_INTSRC_USBAHNEEDCLK_BIT _BIT(26) |
| 240 | #define LPC32XX_CLKPWR_INTSRC_MSTIMER_BIT _BIT(25) |
| 241 | #define LPC32XX_CLKPWR_INTSRC_RTC_BIT _BIT(24) |
| 242 | #define LPC32XX_CLKPWR_INTSRC_USBNEEDCLK_BIT _BIT(23) |
| 243 | #define LPC32XX_CLKPWR_INTSRC_USB_BIT _BIT(22) |
| 244 | #define LPC32XX_CLKPWR_INTSRC_I2C_BIT _BIT(21) |
| 245 | #define LPC32XX_CLKPWR_INTSRC_USBOTGTIMER_BIT _BIT(20) |
| 246 | #define LPC32XX_CLKPWR_INTSRC_USBATXINT_BIT _BIT(19) |
| 247 | #define LPC32XX_CLKPWR_INTSRC_KEY_BIT _BIT(16) |
| 248 | #define LPC32XX_CLKPWR_INTSRC_MAC_BIT _BIT(7) |
| 249 | #define LPC32XX_CLKPWR_INTSRC_P0P1_BIT _BIT(6) |
| 250 | #define LPC32XX_CLKPWR_INTSRC_GPIO_05_BIT _BIT(5) |
| 251 | #define LPC32XX_CLKPWR_INTSRC_GPIO_04_BIT _BIT(4) |
| 252 | #define LPC32XX_CLKPWR_INTSRC_GPIO_03_BIT _BIT(3) |
| 253 | #define LPC32XX_CLKPWR_INTSRC_GPIO_02_BIT _BIT(2) |
| 254 | #define LPC32XX_CLKPWR_INTSRC_GPIO_01_BIT _BIT(1) |
| 255 | #define LPC32XX_CLKPWR_INTSRC_GPIO_00_BIT _BIT(0) |
| 256 | |
| 257 | /* |
| 258 | * clkpwr_start_pin, clkpwr_start_raw_sts_pin, clkpwr_start_sts_pin, |
| 259 | * clkpwr_start_pol_pin register bit definitions |
| 260 | */ |
| 261 | #define LPC32XX_CLKPWR_EXTSRC_U7_RX_BIT _BIT(31) |
| 262 | #define LPC32XX_CLKPWR_EXTSRC_U7_HCTS_BIT _BIT(30) |
| 263 | #define LPC32XX_CLKPWR_EXTSRC_U6_IRRX_BIT _BIT(28) |
| 264 | #define LPC32XX_CLKPWR_EXTSRC_U5_RX_BIT _BIT(26) |
| 265 | #define LPC32XX_CLKPWR_EXTSRC_GPI_28_BIT _BIT(25) |
| 266 | #define LPC32XX_CLKPWR_EXTSRC_U3_RX_BIT _BIT(24) |
| 267 | #define LPC32XX_CLKPWR_EXTSRC_U2_HCTS_BIT _BIT(23) |
| 268 | #define LPC32XX_CLKPWR_EXTSRC_U2_RX_BIT _BIT(22) |
| 269 | #define LPC32XX_CLKPWR_EXTSRC_U1_RX_BIT _BIT(21) |
| 270 | #define LPC32XX_CLKPWR_EXTSRC_MSDIO_INT_BIT _BIT(18) |
| 271 | #define LPC32XX_CLKPWR_EXTSRC_MSDIO_SRT_BIT _BIT(17) |
| 272 | #define LPC32XX_CLKPWR_EXTSRC_GPI_06_BIT _BIT(16) |
| 273 | #define LPC32XX_CLKPWR_EXTSRC_GPI_05_BIT _BIT(15) |
| 274 | #define LPC32XX_CLKPWR_EXTSRC_GPI_04_BIT _BIT(14) |
| 275 | #define LPC32XX_CLKPWR_EXTSRC_GPI_03_BIT _BIT(13) |
| 276 | #define LPC32XX_CLKPWR_EXTSRC_GPI_02_BIT _BIT(12) |
| 277 | #define LPC32XX_CLKPWR_EXTSRC_GPI_01_BIT _BIT(11) |
| 278 | #define LPC32XX_CLKPWR_EXTSRC_GPI_00_BIT _BIT(10) |
| 279 | #define LPC32XX_CLKPWR_EXTSRC_SYSCLKEN_BIT _BIT(9) |
| 280 | #define LPC32XX_CLKPWR_EXTSRC_SPI1_DATIN_BIT _BIT(8) |
| 281 | #define LPC32XX_CLKPWR_EXTSRC_GPI_07_BIT _BIT(7) |
| 282 | #define LPC32XX_CLKPWR_EXTSRC_SPI2_DATIN_BIT _BIT(6) |
| 283 | #define LPC32XX_CLKPWR_EXTSRC_GPI_19_BIT _BIT(5) |
| 284 | #define LPC32XX_CLKPWR_EXTSRC_GPI_09_BIT _BIT(4) |
| 285 | #define LPC32XX_CLKPWR_EXTSRC_GPI_08_BIT _BIT(3) |
| 286 | |
| 287 | /* |
| 288 | * clkpwr_hclk_div register definitions |
| 289 | */ |
| 290 | #define LPC32XX_CLKPWR_HCLKDIV_DDRCLK_STOP (0x0 << 7) |
| 291 | #define LPC32XX_CLKPWR_HCLKDIV_DDRCLK_NORM (0x1 << 7) |
| 292 | #define LPC32XX_CLKPWR_HCLKDIV_DDRCLK_HALF (0x2 << 7) |
| 293 | #define LPC32XX_CLKPWR_HCLKDIV_PCLK_DIV(n) (((n) & 0x1F) << 2) |
| 294 | #define LPC32XX_CLKPWR_HCLKDIV_DIV_2POW(n) ((n) & 0x3) |
| 295 | |
| 296 | /* |
| 297 | * clkpwr_pwr_ctrl register definitions |
| 298 | */ |
| 299 | #define LPC32XX_CLKPWR_CTRL_FORCE_PCLK _BIT(10) |
| 300 | #define LPC32XX_CLKPWR_SDRAM_SELF_RFSH _BIT(9) |
| 301 | #define LPC32XX_CLKPWR_UPD_SDRAM_SELF_RFSH _BIT(8) |
| 302 | #define LPC32XX_CLKPWR_AUTO_SDRAM_SELF_RFSH _BIT(7) |
| 303 | #define LPC32XX_CLKPWR_HIGHCORE_STATE_BIT _BIT(5) |
| 304 | #define LPC32XX_CLKPWR_SYSCLKEN_STATE_BIT _BIT(4) |
| 305 | #define LPC32XX_CLKPWR_SYSCLKEN_GPIO_EN _BIT(3) |
| 306 | #define LPC32XX_CLKPWR_SELECT_RUN_MODE _BIT(2) |
| 307 | #define LPC32XX_CLKPWR_HIGHCORE_GPIO_EN _BIT(1) |
| 308 | #define LPC32XX_CLKPWR_STOP_MODE_CTRL _BIT(0) |
| 309 | |
| 310 | /* |
| 311 | * clkpwr_pll397_ctrl register definitions |
| 312 | */ |
| 313 | #define LPC32XX_CLKPWR_PLL397_MSLOCK_STS _BIT(10) |
| 314 | #define LPC32XX_CLKPWR_PLL397_BYPASS _BIT(9) |
| 315 | #define LPC32XX_CLKPWR_PLL397_BIAS_NORM 0x000 |
| 316 | #define LPC32XX_CLKPWR_PLL397_BIAS_N12_5 0x040 |
| 317 | #define LPC32XX_CLKPWR_PLL397_BIAS_N25 0x080 |
| 318 | #define LPC32XX_CLKPWR_PLL397_BIAS_N37_5 0x0C0 |
| 319 | #define LPC32XX_CLKPWR_PLL397_BIAS_P12_5 0x100 |
| 320 | #define LPC32XX_CLKPWR_PLL397_BIAS_P25 0x140 |
| 321 | #define LPC32XX_CLKPWR_PLL397_BIAS_P37_5 0x180 |
| 322 | #define LPC32XX_CLKPWR_PLL397_BIAS_P50 0x1C0 |
| 323 | #define LPC32XX_CLKPWR_PLL397_BIAS_MASK 0x1C0 |
| 324 | #define LPC32XX_CLKPWR_SYSCTRL_PLL397_DIS _BIT(1) |
| 325 | #define LPC32XX_CLKPWR_SYSCTRL_PLL397_STS _BIT(0) |
| 326 | |
| 327 | /* |
| 328 | * clkpwr_main_osc_ctrl register definitions |
| 329 | */ |
| 330 | #define LPC32XX_CLKPWR_MOSC_ADD_CAP(n) (((n) & 0x7F) << 2) |
| 331 | #define LPC32XX_CLKPWR_MOSC_CAP_MASK (0x7F << 2) |
| 332 | #define LPC32XX_CLKPWR_TEST_MODE _BIT(1) |
| 333 | #define LPC32XX_CLKPWR_MOSC_DISABLE _BIT(0) |
| 334 | |
| 335 | /* |
| 336 | * clkpwr_sysclk_ctrl register definitions |
| 337 | */ |
| 338 | #define LPC32XX_CLKPWR_SYSCTRL_BP_TRIG(n) (((n) & 0x3FF) << 2) |
| 339 | #define LPC32XX_CLKPWR_SYSCTRL_BP_MASK (0x3FF << 2) |
| 340 | #define LPC32XX_CLKPWR_SYSCTRL_USEPLL397 _BIT(1) |
| 341 | #define LPC32XX_CLKPWR_SYSCTRL_SYSCLKMUX _BIT(0) |
| 342 | |
| 343 | /* |
| 344 | * clkpwr_lcdclk_ctrl register definitions |
| 345 | */ |
| 346 | #define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_TFT12 0x000 |
| 347 | #define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_TFT16 0x040 |
| 348 | #define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_TFT15 0x080 |
| 349 | #define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_TFT24 0x0C0 |
| 350 | #define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_STN4M 0x100 |
| 351 | #define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_STN8C 0x140 |
| 352 | #define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_DSTN4M 0x180 |
| 353 | #define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_DSTN8C 0x1C0 |
| 354 | #define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_MSK 0x01C0 |
| 355 | #define LPC32XX_CLKPWR_LCDCTRL_CLK_EN 0x020 |
| 356 | #define LPC32XX_CLKPWR_LCDCTRL_SET_PSCALE(n) ((n - 1) & 0x1F) |
| 357 | #define LPC32XX_CLKPWR_LCDCTRL_PSCALE_MSK 0x001F |
| 358 | |
| 359 | /* |
| 360 | * clkpwr_hclkpll_ctrl register definitions |
| 361 | */ |
| 362 | #define LPC32XX_CLKPWR_HCLKPLL_POWER_UP _BIT(16) |
| 363 | #define LPC32XX_CLKPWR_HCLKPLL_CCO_BYPASS _BIT(15) |
| 364 | #define LPC32XX_CLKPWR_HCLKPLL_POSTDIV_BYPASS _BIT(14) |
| 365 | #define LPC32XX_CLKPWR_HCLKPLL_FDBK_SEL_FCLK _BIT(13) |
| 366 | #define LPC32XX_CLKPWR_HCLKPLL_POSTDIV_2POW(n) (((n) & 0x3) << 11) |
| 367 | #define LPC32XX_CLKPWR_HCLKPLL_PREDIV_PLUS1(n) (((n) & 0x3) << 9) |
| 368 | #define LPC32XX_CLKPWR_HCLKPLL_PLLM(n) (((n) & 0xFF) << 1) |
| 369 | #define LPC32XX_CLKPWR_HCLKPLL_PLL_STS _BIT(0) |
| 370 | |
| 371 | /* |
| 372 | * clkpwr_adc_clk_ctrl_1 register definitions |
| 373 | */ |
| 374 | #define LPC32XX_CLKPWR_ADCCTRL1_RTDIV(n) (((n) & 0xFF) << 0) |
| 375 | #define LPC32XX_CLKPWR_ADCCTRL1_PCLK_SEL _BIT(8) |
| 376 | |
| 377 | /* |
| 378 | * clkpwr_usb_ctrl register definitions |
| 379 | */ |
| 380 | #define LPC32XX_CLKPWR_USBCTRL_HCLK_EN _BIT(24) |
| 381 | #define LPC32XX_CLKPWR_USBCTRL_USBI2C_EN _BIT(23) |
| 382 | #define LPC32XX_CLKPWR_USBCTRL_USBDVND_EN _BIT(22) |
| 383 | #define LPC32XX_CLKPWR_USBCTRL_USBHSTND_EN _BIT(21) |
| 384 | #define LPC32XX_CLKPWR_USBCTRL_PU_ADD (0x0 << 19) |
| 385 | #define LPC32XX_CLKPWR_USBCTRL_BUS_KEEPER (0x1 << 19) |
| 386 | #define LPC32XX_CLKPWR_USBCTRL_PD_ADD (0x3 << 19) |
| 387 | #define LPC32XX_CLKPWR_USBCTRL_CLK_EN2 _BIT(18) |
| 388 | #define LPC32XX_CLKPWR_USBCTRL_CLK_EN1 _BIT(17) |
| 389 | #define LPC32XX_CLKPWR_USBCTRL_PLL_PWRUP _BIT(16) |
| 390 | #define LPC32XX_CLKPWR_USBCTRL_CCO_BYPASS _BIT(15) |
| 391 | #define LPC32XX_CLKPWR_USBCTRL_POSTDIV_BYPASS _BIT(14) |
| 392 | #define LPC32XX_CLKPWR_USBCTRL_FDBK_SEL_FCLK _BIT(13) |
| 393 | #define LPC32XX_CLKPWR_USBCTRL_POSTDIV_2POW(n) (((n) & 0x3) << 11) |
| 394 | #define LPC32XX_CLKPWR_USBCTRL_PREDIV_PLUS1(n) (((n) & 0x3) << 9) |
| 395 | #define LPC32XX_CLKPWR_USBCTRL_FDBK_PLUS1(n) (((n) & 0xFF) << 1) |
| 396 | #define LPC32XX_CLKPWR_USBCTRL_PLL_STS _BIT(0) |
| 397 | |
| 398 | /* |
| 399 | * clkpwr_sdramclk_ctrl register definitions |
| 400 | */ |
| 401 | #define LPC32XX_CLKPWR_SDRCLK_FASTSLEW_CLK _BIT(22) |
| 402 | #define LPC32XX_CLKPWR_SDRCLK_FASTSLEW _BIT(21) |
| 403 | #define LPC32XX_CLKPWR_SDRCLK_FASTSLEW_DAT _BIT(20) |
| 404 | #define LPC32XX_CLKPWR_SDRCLK_SW_DDR_RESET _BIT(19) |
| 405 | #define LPC32XX_CLKPWR_SDRCLK_HCLK_DLY(n) (((n) & 0x1F) << 14) |
| 406 | #define LPC32XX_CLKPWR_SDRCLK_DLY_ADDR_STS _BIT(13) |
| 407 | #define LPC32XX_CLKPWR_SDRCLK_SENS_FACT(n) (((n) & 0x7) << 10) |
| 408 | #define LPC32XX_CLKPWR_SDRCLK_USE_CAL _BIT(9) |
| 409 | #define LPC32XX_CLKPWR_SDRCLK_DO_CAL _BIT(8) |
| 410 | #define LPC32XX_CLKPWR_SDRCLK_CAL_ON_RTC _BIT(7) |
| 411 | #define LPC32XX_CLKPWR_SDRCLK_DQS_DLY(n) (((n) & 0x1F) << 2) |
| 412 | #define LPC32XX_CLKPWR_SDRCLK_USE_DDR _BIT(1) |
| 413 | #define LPC32XX_CLKPWR_SDRCLK_CLK_DIS _BIT(0) |
| 414 | |
| 415 | /* |
| 416 | * clkpwr_ssp_blk_ctrl register definitions |
| 417 | */ |
| 418 | #define LPC32XX_CLKPWR_SSPCTRL_DMA_SSP1RX _BIT(5) |
| 419 | #define LPC32XX_CLKPWR_SSPCTRL_DMA_SSP1TX _BIT(4) |
| 420 | #define LPC32XX_CLKPWR_SSPCTRL_DMA_SSP0RX _BIT(3) |
| 421 | #define LPC32XX_CLKPWR_SSPCTRL_DMA_SSP0TX _BIT(2) |
| 422 | #define LPC32XX_CLKPWR_SSPCTRL_SSPCLK1_EN _BIT(1) |
| 423 | #define LPC32XX_CLKPWR_SSPCTRL_SSPCLK0_EN _BIT(0) |
| 424 | |
| 425 | /* |
| 426 | * clkpwr_i2s_clk_ctrl register definitions |
| 427 | */ |
| 428 | #define LPC32XX_CLKPWR_I2SCTRL_I2S1_RX_FOR_TX _BIT(6) |
| 429 | #define LPC32XX_CLKPWR_I2SCTRL_I2S1_TX_FOR_RX _BIT(5) |
| 430 | #define LPC32XX_CLKPWR_I2SCTRL_I2S1_USE_DMA _BIT(4) |
| 431 | #define LPC32XX_CLKPWR_I2SCTRL_I2S0_RX_FOR_TX _BIT(3) |
| 432 | #define LPC32XX_CLKPWR_I2SCTRL_I2S0_TX_FOR_RX _BIT(2) |
| 433 | #define LPC32XX_CLKPWR_I2SCTRL_I2SCLK1_EN _BIT(1) |
| 434 | #define LPC32XX_CLKPWR_I2SCTRL_I2SCLK0_EN _BIT(0) |
| 435 | |
| 436 | /* |
| 437 | * clkpwr_ms_ctrl register definitions |
| 438 | */ |
| 439 | #define LPC32XX_CLKPWR_MSCARD_MSDIO_PIN_DIS _BIT(10) |
| 440 | #define LPC32XX_CLKPWR_MSCARD_MSDIO_PU_EN _BIT(9) |
| 441 | #define LPC32XX_CLKPWR_MSCARD_MSDIO23_DIS _BIT(8) |
| 442 | #define LPC32XX_CLKPWR_MSCARD_MSDIO1_DIS _BIT(7) |
| 443 | #define LPC32XX_CLKPWR_MSCARD_MSDIO0_DIS _BIT(6) |
| 444 | #define LPC32XX_CLKPWR_MSCARD_SDCARD_EN _BIT(5) |
| 445 | #define LPC32XX_CLKPWR_MSCARD_SDCARD_DIV(n) ((n) & 0xF) |
| 446 | |
| 447 | /* |
| 448 | * clkpwr_macclk_ctrl register definitions |
| 449 | */ |
| 450 | #define LPC32XX_CLKPWR_MACCTRL_NO_ENET_PIS 0x00 |
| 451 | #define LPC32XX_CLKPWR_MACCTRL_USE_MII_PINS 0x08 |
| 452 | #define LPC32XX_CLKPWR_MACCTRL_USE_RMII_PINS 0x18 |
| 453 | #define LPC32XX_CLKPWR_MACCTRL_PINS_MSK 0x18 |
| 454 | #define LPC32XX_CLKPWR_MACCTRL_DMACLK_EN _BIT(2) |
| 455 | #define LPC32XX_CLKPWR_MACCTRL_MMIOCLK_EN _BIT(1) |
| 456 | #define LPC32XX_CLKPWR_MACCTRL_HRCCLK_EN _BIT(0) |
| 457 | |
| 458 | /* |
| 459 | * clkpwr_test_clk_sel register definitions |
| 460 | */ |
| 461 | #define LPC32XX_CLKPWR_TESTCLK1_SEL_PERCLK (0x0 << 5) |
| 462 | #define LPC32XX_CLKPWR_TESTCLK1_SEL_RTC (0x1 << 5) |
| 463 | #define LPC32XX_CLKPWR_TESTCLK1_SEL_MOSC (0x2 << 5) |
| 464 | #define LPC32XX_CLKPWR_TESTCLK1_SEL_MASK (0x3 << 5) |
| 465 | #define LPC32XX_CLKPWR_TESTCLK_TESTCLK1_EN _BIT(4) |
| 466 | #define LPC32XX_CLKPWR_TESTCLK2_SEL_HCLK (0x0 << 1) |
| 467 | #define LPC32XX_CLKPWR_TESTCLK2_SEL_PERCLK (0x1 << 1) |
| 468 | #define LPC32XX_CLKPWR_TESTCLK2_SEL_USBCLK (0x2 << 1) |
| 469 | #define LPC32XX_CLKPWR_TESTCLK2_SEL_MOSC (0x5 << 1) |
| 470 | #define LPC32XX_CLKPWR_TESTCLK2_SEL_PLL397 (0x7 << 1) |
| 471 | #define LPC32XX_CLKPWR_TESTCLK2_SEL_MASK (0x7 << 1) |
| 472 | #define LPC32XX_CLKPWR_TESTCLK_TESTCLK2_EN _BIT(0) |
| 473 | |
| 474 | /* |
| 475 | * clkpwr_sw_int register definitions |
| 476 | */ |
| 477 | #define LPC32XX_CLKPWR_SW_INT(n) (_BIT(0) | (((n) & 0x7F) << 1)) |
| 478 | #define LPC32XX_CLKPWR_SW_GET_ARG(n) (((n) & 0xFE) >> 1) |
| 479 | |
| 480 | /* |
| 481 | * clkpwr_i2c_clk_ctrl register definitions |
| 482 | */ |
| 483 | #define LPC32XX_CLKPWR_I2CCLK_USBI2CHI_DRIVE _BIT(4) |
| 484 | #define LPC32XX_CLKPWR_I2CCLK_I2C2HI_DRIVE _BIT(3) |
| 485 | #define LPC32XX_CLKPWR_I2CCLK_I2C1HI_DRIVE _BIT(2) |
| 486 | #define LPC32XX_CLKPWR_I2CCLK_I2C2CLK_EN _BIT(1) |
| 487 | #define LPC32XX_CLKPWR_I2CCLK_I2C1CLK_EN _BIT(0) |
| 488 | |
| 489 | /* |
| 490 | * clkpwr_key_clk_ctrl register definitions |
| 491 | */ |
| 492 | #define LPC32XX_CLKPWR_KEYCLKCTRL_CLK_EN 0x1 |
| 493 | |
| 494 | /* |
| 495 | * clkpwr_adc_clk_ctrl register definitions |
| 496 | */ |
| 497 | #define LPC32XX_CLKPWR_ADC32CLKCTRL_CLK_EN 0x1 |
| 498 | |
| 499 | /* |
| 500 | * clkpwr_pwm_clk_ctrl register definitions |
| 501 | */ |
| 502 | #define LPC32XX_CLKPWR_PWMCLK_PWM2_DIV(n) (((n) & 0xF) << 8) |
| 503 | #define LPC32XX_CLKPWR_PWMCLK_PWM1_DIV(n) (((n) & 0xF) << 4) |
| 504 | #define LPC32XX_CLKPWR_PWMCLK_PWM2SEL_PCLK 0x8 |
| 505 | #define LPC32XX_CLKPWR_PWMCLK_PWM2CLK_EN 0x4 |
| 506 | #define LPC32XX_CLKPWR_PWMCLK_PWM1SEL_PCLK 0x2 |
| 507 | #define LPC32XX_CLKPWR_PWMCLK_PWM1CLK_EN 0x1 |
| 508 | |
| 509 | /* |
| 510 | * clkpwr_timer_clk_ctrl register definitions |
| 511 | */ |
| 512 | #define LPC32XX_CLKPWR_PWMCLK_HSTIMER_EN 0x2 |
| 513 | #define LPC32XX_CLKPWR_PWMCLK_WDOG_EN 0x1 |
| 514 | |
| 515 | /* |
| 516 | * clkpwr_timers_pwms_clk_ctrl_1 register definitions |
| 517 | */ |
| 518 | #define LPC32XX_CLKPWR_TMRPWMCLK_TIMER3_EN 0x20 |
| 519 | #define LPC32XX_CLKPWR_TMRPWMCLK_TIMER2_EN 0x10 |
| 520 | #define LPC32XX_CLKPWR_TMRPWMCLK_TIMER1_EN 0x08 |
| 521 | #define LPC32XX_CLKPWR_TMRPWMCLK_TIMER0_EN 0x04 |
| 522 | #define LPC32XX_CLKPWR_TMRPWMCLK_PWM4_EN 0x02 |
| 523 | #define LPC32XX_CLKPWR_TMRPWMCLK_PWM3_EN 0x01 |
| 524 | |
| 525 | /* |
| 526 | * clkpwr_spi_clk_ctrl register definitions |
| 527 | */ |
| 528 | #define LPC32XX_CLKPWR_SPICLK_SET_SPI2DATIO 0x80 |
| 529 | #define LPC32XX_CLKPWR_SPICLK_SET_SPI2CLK 0x40 |
| 530 | #define LPC32XX_CLKPWR_SPICLK_USE_SPI2 0x20 |
| 531 | #define LPC32XX_CLKPWR_SPICLK_SPI2CLK_EN 0x10 |
| 532 | #define LPC32XX_CLKPWR_SPICLK_SET_SPI1DATIO 0x08 |
| 533 | #define LPC32XX_CLKPWR_SPICLK_SET_SPI1CLK 0x04 |
| 534 | #define LPC32XX_CLKPWR_SPICLK_USE_SPI1 0x02 |
| 535 | #define LPC32XX_CLKPWR_SPICLK_SPI1CLK_EN 0x01 |
| 536 | |
| 537 | /* |
| 538 | * clkpwr_nand_clk_ctrl register definitions |
| 539 | */ |
| 540 | #define LPC32XX_CLKPWR_NANDCLK_INTSEL_MLC 0x20 |
| 541 | #define LPC32XX_CLKPWR_NANDCLK_DMA_RNB 0x10 |
| 542 | #define LPC32XX_CLKPWR_NANDCLK_DMA_INT 0x08 |
| 543 | #define LPC32XX_CLKPWR_NANDCLK_SEL_SLC 0x04 |
| 544 | #define LPC32XX_CLKPWR_NANDCLK_MLCCLK_EN 0x02 |
| 545 | #define LPC32XX_CLKPWR_NANDCLK_SLCCLK_EN 0x01 |
| 546 | |
| 547 | /* |
| 548 | * clkpwr_uart3_clk_ctrl, clkpwr_uart4_clk_ctrl, clkpwr_uart5_clk_ctrl |
| 549 | * and clkpwr_uart6_clk_ctrl register definitions |
| 550 | */ |
| 551 | #define LPC32XX_CLKPWR_UART_Y_DIV(y) ((y) & 0xFF) |
| 552 | #define LPC32XX_CLKPWR_UART_X_DIV(x) (((x) & 0xFF) << 8) |
| 553 | #define LPC32XX_CLKPWR_UART_USE_HCLK _BIT(16) |
| 554 | |
| 555 | /* |
| 556 | * clkpwr_irda_clk_ctrl register definitions |
| 557 | */ |
| 558 | #define LPC32XX_CLKPWR_IRDA_Y_DIV(y) ((y) & 0xFF) |
| 559 | #define LPC32XX_CLKPWR_IRDA_X_DIV(x) (((x) & 0xFF) << 8) |
| 560 | |
| 561 | /* |
| 562 | * clkpwr_uart_clk_ctrl register definitions |
| 563 | */ |
| 564 | #define LPC32XX_CLKPWR_UARTCLKCTRL_UART6_EN _BIT(3) |
| 565 | #define LPC32XX_CLKPWR_UARTCLKCTRL_UART5_EN _BIT(2) |
| 566 | #define LPC32XX_CLKPWR_UARTCLKCTRL_UART4_EN _BIT(1) |
| 567 | #define LPC32XX_CLKPWR_UARTCLKCTRL_UART3_EN _BIT(0) |
| 568 | |
| 569 | /* |
| 570 | * clkpwr_dmaclk_ctrl register definitions |
| 571 | */ |
| 572 | #define LPC32XX_CLKPWR_DMACLKCTRL_CLK_EN 0x1 |
| 573 | |
| 574 | /* |
| 575 | * clkpwr_autoclock register definitions |
| 576 | */ |
| 577 | #define LPC32XX_CLKPWR_AUTOCLK_USB_EN 0x40 |
| 578 | #define LPC32XX_CLKPWR_AUTOCLK_IRAM_EN 0x02 |
| 579 | #define LPC32XX_CLKPWR_AUTOCLK_IROM_EN 0x01 |
| 580 | |
| 581 | /* |
| 582 | * Interrupt controller register offsets |
| 583 | */ |
| 584 | #define LPC32XX_INTC_MASK(x) io_p2v((x) + 0x00) |
| 585 | #define LPC32XX_INTC_RAW_STAT(x) io_p2v((x) + 0x04) |
| 586 | #define LPC32XX_INTC_STAT(x) io_p2v((x) + 0x08) |
| 587 | #define LPC32XX_INTC_POLAR(x) io_p2v((x) + 0x0C) |
| 588 | #define LPC32XX_INTC_ACT_TYPE(x) io_p2v((x) + 0x10) |
| 589 | #define LPC32XX_INTC_TYPE(x) io_p2v((x) + 0x14) |
| 590 | |
| 591 | /* |
| 592 | * Timer/counter register offsets |
| 593 | */ |
| Roland Stigge | cfac337 | 2012-02-27 17:31:24 +0100 | [diff] [blame] | 594 | #define LPC32XX_TIMER_IR(x) io_p2v((x) + 0x00) |
| 595 | #define LPC32XX_TIMER_TCR(x) io_p2v((x) + 0x04) |
| 596 | #define LPC32XX_TIMER_TC(x) io_p2v((x) + 0x08) |
| 597 | #define LPC32XX_TIMER_PR(x) io_p2v((x) + 0x0C) |
| 598 | #define LPC32XX_TIMER_PC(x) io_p2v((x) + 0x10) |
| 599 | #define LPC32XX_TIMER_MCR(x) io_p2v((x) + 0x14) |
| 600 | #define LPC32XX_TIMER_MR0(x) io_p2v((x) + 0x18) |
| 601 | #define LPC32XX_TIMER_MR1(x) io_p2v((x) + 0x1C) |
| 602 | #define LPC32XX_TIMER_MR2(x) io_p2v((x) + 0x20) |
| 603 | #define LPC32XX_TIMER_MR3(x) io_p2v((x) + 0x24) |
| 604 | #define LPC32XX_TIMER_CCR(x) io_p2v((x) + 0x28) |
| 605 | #define LPC32XX_TIMER_CR0(x) io_p2v((x) + 0x2C) |
| 606 | #define LPC32XX_TIMER_CR1(x) io_p2v((x) + 0x30) |
| 607 | #define LPC32XX_TIMER_CR2(x) io_p2v((x) + 0x34) |
| 608 | #define LPC32XX_TIMER_CR3(x) io_p2v((x) + 0x38) |
| 609 | #define LPC32XX_TIMER_EMR(x) io_p2v((x) + 0x3C) |
| 610 | #define LPC32XX_TIMER_CTCR(x) io_p2v((x) + 0x70) |
| Kevin Wells | 437db59 | 2010-02-26 15:53:38 -0800 | [diff] [blame] | 611 | |
| 612 | /* |
| 613 | * ir register definitions |
| 614 | */ |
| Roland Stigge | cfac337 | 2012-02-27 17:31:24 +0100 | [diff] [blame] | 615 | #define LPC32XX_TIMER_CNTR_MTCH_BIT(n) (1 << ((n) & 0x3)) |
| 616 | #define LPC32XX_TIMER_CNTR_CAPT_BIT(n) (1 << (4 + ((n) & 0x3))) |
| Kevin Wells | 437db59 | 2010-02-26 15:53:38 -0800 | [diff] [blame] | 617 | |
| 618 | /* |
| 619 | * tcr register definitions |
| 620 | */ |
| Roland Stigge | cfac337 | 2012-02-27 17:31:24 +0100 | [diff] [blame] | 621 | #define LPC32XX_TIMER_CNTR_TCR_EN 0x1 |
| 622 | #define LPC32XX_TIMER_CNTR_TCR_RESET 0x2 |
| Kevin Wells | 437db59 | 2010-02-26 15:53:38 -0800 | [diff] [blame] | 623 | |
| 624 | /* |
| 625 | * mcr register definitions |
| 626 | */ |
| Roland Stigge | cfac337 | 2012-02-27 17:31:24 +0100 | [diff] [blame] | 627 | #define LPC32XX_TIMER_CNTR_MCR_MTCH(n) (0x1 << ((n) * 3)) |
| 628 | #define LPC32XX_TIMER_CNTR_MCR_RESET(n) (0x1 << (((n) * 3) + 1)) |
| 629 | #define LPC32XX_TIMER_CNTR_MCR_STOP(n) (0x1 << (((n) * 3) + 2)) |
| Kevin Wells | 437db59 | 2010-02-26 15:53:38 -0800 | [diff] [blame] | 630 | |
| 631 | /* |
| 632 | * Standard UART register offsets |
| 633 | */ |
| 634 | #define LPC32XX_UART_DLL_FIFO(x) io_p2v((x) + 0x00) |
| 635 | #define LPC32XX_UART_DLM_IER(x) io_p2v((x) + 0x04) |
| 636 | #define LPC32XX_UART_IIR_FCR(x) io_p2v((x) + 0x08) |
| 637 | #define LPC32XX_UART_LCR(x) io_p2v((x) + 0x0C) |
| 638 | #define LPC32XX_UART_MODEM_CTRL(x) io_p2v((x) + 0x10) |
| 639 | #define LPC32XX_UART_LSR(x) io_p2v((x) + 0x14) |
| 640 | #define LPC32XX_UART_MODEM_STATUS(x) io_p2v((x) + 0x18) |
| 641 | #define LPC32XX_UART_RXLEV(x) io_p2v((x) + 0x1C) |
| 642 | |
| 643 | /* |
| 644 | * UART control structure offsets |
| 645 | */ |
| 646 | #define _UCREG(x) io_p2v(\ |
| 647 | LPC32XX_UART_CTRL_BASE + (x)) |
| 648 | #define LPC32XX_UARTCTL_CTRL _UCREG(0x00) |
| 649 | #define LPC32XX_UARTCTL_CLKMODE _UCREG(0x04) |
| 650 | #define LPC32XX_UARTCTL_CLOOP _UCREG(0x08) |
| 651 | |
| 652 | /* |
| 653 | * ctrl register definitions |
| 654 | */ |
| 655 | #define LPC32XX_UART_U3_MD_CTRL_EN _BIT(11) |
| 656 | #define LPC32XX_UART_IRRX6_INV_EN _BIT(10) |
| 657 | #define LPC32XX_UART_HDPX_EN _BIT(9) |
| 658 | #define LPC32XX_UART_UART6_IRDAMOD_BYPASS _BIT(5) |
| 659 | #define LPC32XX_RT_IRTX6_INV_EN _BIT(4) |
| 660 | #define LPC32XX_RT_IRTX6_INV_MIR_EN _BIT(3) |
| 661 | #define LPC32XX_RT_RX_IRPULSE_3_16_115K _BIT(2) |
| 662 | #define LPC32XX_RT_TX_IRPULSE_3_16_115K _BIT(1) |
| 663 | #define LPC32XX_UART_U5_ROUTE_TO_USB _BIT(0) |
| 664 | |
| 665 | /* |
| 666 | * clkmode register definitions |
| 667 | */ |
| 668 | #define LPC32XX_UART_ENABLED_CLOCKS(n) (((n) >> 16) & 0x7F) |
| 669 | #define LPC32XX_UART_ENABLED_CLOCK(n, u) (((n) >> (16 + (u))) & 0x1) |
| 670 | #define LPC32XX_UART_ENABLED_CLKS_ANY _BIT(14) |
| 671 | #define LPC32XX_UART_CLKMODE_OFF 0x0 |
| 672 | #define LPC32XX_UART_CLKMODE_ON 0x1 |
| 673 | #define LPC32XX_UART_CLKMODE_AUTO 0x2 |
| 674 | #define LPC32XX_UART_CLKMODE_MASK(u) (0x3 << ((((u) - 3) * 2) + 4)) |
| 675 | #define LPC32XX_UART_CLKMODE_LOAD(m, u) ((m) << ((((u) - 3) * 2) + 4)) |
| 676 | |
| 677 | /* |
| 678 | * GPIO Module Register offsets |
| 679 | */ |
| 680 | #define _GPREG(x) io_p2v(LPC32XX_GPIO_BASE + (x)) |
| 681 | #define LPC32XX_GPIO_P_MUX_SET _GPREG(0x100) |
| 682 | #define LPC32XX_GPIO_P_MUX_CLR _GPREG(0x104) |
| 683 | #define LPC32XX_GPIO_P_MUX_STATE _GPREG(0x108) |
| 684 | #define LPC32XX_GPIO_P3_MUX_SET _GPREG(0x110) |
| 685 | #define LPC32XX_GPIO_P3_MUX_CLR _GPREG(0x114) |
| 686 | #define LPC32XX_GPIO_P3_MUX_STATE _GPREG(0x118) |
| 687 | #define LPC32XX_GPIO_P0_MUX_SET _GPREG(0x120) |
| 688 | #define LPC32XX_GPIO_P0_MUX_CLR _GPREG(0x124) |
| 689 | #define LPC32XX_GPIO_P0_MUX_STATE _GPREG(0x128) |
| 690 | #define LPC32XX_GPIO_P1_MUX_SET _GPREG(0x130) |
| 691 | #define LPC32XX_GPIO_P1_MUX_CLR _GPREG(0x134) |
| 692 | #define LPC32XX_GPIO_P1_MUX_STATE _GPREG(0x138) |
| Roland Stigge | cfac337 | 2012-02-27 17:31:24 +0100 | [diff] [blame] | 693 | #define LPC32XX_GPIO_P2_MUX_SET _GPREG(0x028) |
| 694 | #define LPC32XX_GPIO_P2_MUX_CLR _GPREG(0x02C) |
| 695 | #define LPC32XX_GPIO_P2_MUX_STATE _GPREG(0x030) |
| Kevin Wells | 437db59 | 2010-02-26 15:53:38 -0800 | [diff] [blame] | 696 | |
| Alexandre Pereira da Silva | a408e8f | 2012-07-01 21:06:45 +0200 | [diff] [blame^] | 697 | /* |
| 698 | * USB Otg Registers |
| 699 | */ |
| 700 | #define _OTGREG(x) io_p2v(LPC32XX_USB_OTG_BASE + (x)) |
| 701 | #define LPC32XX_USB_OTG_CLK_CTRL _OTGREG(0xFF4) |
| 702 | #define LPC32XX_USB_OTG_CLK_STAT _OTGREG(0xFF8) |
| 703 | |
| 704 | /* USB OTG CLK CTRL bit defines */ |
| 705 | #define LPC32XX_USB_OTG_AHB_M_CLOCK_ON _BIT(4) |
| 706 | #define LPC32XX_USB_OTG_OTG_CLOCK_ON _BIT(3) |
| 707 | #define LPC32XX_USB_OTG_I2C_CLOCK_ON _BIT(2) |
| 708 | #define LPC32XX_USB_OTG_DEV_CLOCK_ON _BIT(1) |
| 709 | #define LPC32XX_USB_OTG_HOST_CLOCK_ON _BIT(0) |
| 710 | |
| Kevin Wells | 437db59 | 2010-02-26 15:53:38 -0800 | [diff] [blame] | 711 | #endif |